Semiconductor equipment
The semiconductor device addresses device characteristic deterioration in RB-IGBTs by optimizing the separation diffusion region width and impurity concentrations to prevent depletion layer reach-through, ensuring reliable operation under reverse bias.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- FUJI ELECTRIC CO LTD
- Filing Date
- 2022-07-14
- Publication Date
- 2026-06-23
AI Technical Summary
In conventional RB-IGBTs, the p-type isolation diffusion region forms a low impurity concentration near the collector region, leading to wider depletion layers that can reach the outer peripheral surface, causing device characteristic deterioration under reverse bias.
A semiconductor device design with a separation diffusion region that has a wider upper width than lower width, ensuring the depletion layer does not reach the chip's side surface by setting the width of the separation diffusion region to be at least 1 to 2 times the substrate thickness, and optimizing impurity concentrations to control depletion layer expansion.
Prevents device characteristic deterioration by suppressing depletion layer reach-through, reducing the inactive pressure-resistant structure area, and maintaining chip size, thus enhancing reliability.
Smart Images
Figure 0007877903000001 
Figure 0007877903000002 
Figure 0007877903000003
Abstract
Description
[Technical Field]
[0001] This invention relates to a semiconductor device. [Background technology]
[0002] In reverse-blocking insulated-gate bipolar transistors (RB-IGBTs), when the wafer is processed and then diced to become a chip, n is present on the side of the chip. - To prevent the mold region from being exposed, p-type impurities are ion-implanted into the dicing line at the beginning of the wafer process, and diffusion is performed at high temperature for a long time to form a p-type separation and diffusion region (separation layer). Then, a MOS structure and a breakdown structure are formed on the surface side of the substrate, and the substrate is ground from the back side to the thickness necessary to maintain the breakdown. A collector region is formed on the back side of the substrate, and a collector electrode is formed on the back side of the collector region, completing the wafer process. Subsequently, in the dicing process, the inside of the separation and diffusion region is cut with a diamond cutter or the like to create a chip. The separation and diffusion region is exposed on the side of the chip.
[0003] Patent Document 1 discloses a configuration in an RB-IGBT in which, in order to prevent cracks on the wafer side surface, the width of the portion in which the p-type isolation layer connects to the p-type collector layer on the back side is set to 60 to 300 μm in the direction parallel to the substrate surface. Patent Document 2 discloses a configuration in an RB-IGBT in which the impurity concentration near the surface of the p-type isolation layer is 1 × 10⁻¹⁶ 17 ~5×10 18 / cm 3 Therefore, the impurity concentration near the back surface is 2 × 10 14 ~2×10 15 / cm 3 It is disclosed that... [Prior art documents] [Patent Documents]
[0004] [Patent Document 1] Japanese Patent Publication No. 2013-012652 [Patent Document 2] Patent No. 6467882 specification
Summary of the Invention
Problems to be Solved by the Invention
[0005] In a conventional RB-IGBT, the p-type isolation diffusion region is formed by ion-implanting p-type impurities on the surface side of the substrate and then performing thermal diffusion. Therefore, in the region close to the collector layer on the back side of the substrate, the p-type impurity concentration becomes low. When a reverse bias is applied, depletion layers progress not only from the pn junctions between the collector region, the isolation diffusion region, and the n - -type region to the n - -type region side, but also to the collector region and the isolation diffusion region sides. Since the p-type impurity concentration in the collector region is usually sufficiently high, the depletion layer does not reach (reach through) the back surface of the collector region.
[0006] On the other hand, since the p-type impurity concentration becomes low in the vicinity of the collector region below the isolation diffusion region, the depletion layer width in the vicinity of the collector region below the isolation diffusion region becomes wider than the depletion layer width in the vicinity of the emitter region above the isolation diffusion region. Therefore, in the vicinity of the collector region below the isolation diffusion region, the depletion layer may reach (reach through) the exposed outer peripheral surface of the isolation diffusion region, resulting in deterioration of the device characteristics.
[0007] An object of the present invention is to provide a semiconductor device capable of preventing deterioration of device characteristics when a reverse bias is applied.
Means for Solving the Problems
[0008] To achieve the above object, one aspect of the present invention provides a semiconductor device comprising: (a) a drift layer of a first conductivity type; (b) an insulated gate electrode structure provided on the upper surface side of the drift layer; (c) a base region of a second conductivity type provided on the upper part of the drift layer; (d) a first main electrode region of the first conductivity type provided on the upper part of the base region; (e) a second main electrode region of the second conductivity type provided on the lower surface side of the drift layer; and (f) a separation diffusion region of the second conductivity type which is in contact with the upper surface of the second main electrode region and is annularly provided so as to surround the side surface of the drift layer, and has a wider upper width than the lower width, wherein the width of the portion of the separation diffusion region in contact with the second main electrode region is not less than 1 times and not more than 2 times the thickness from the upper surface of the drift layer to the lower surface of the second main electrode region.
Advantages of the Invention
[0009] According to the present invention, it is possible to provide a semiconductor device capable of preventing deterioration of element characteristics when a reverse bias is applied.
Brief Description of the Drawings
[0010] [Figure 1] It is a plan view showing an example of a semiconductor device according to an embodiment. [Figure 2] It is a cross-sectional view obtained by enlarging region A in FIG. 1. [Figure 3A] It is a graph showing the impurity concentration profile of the separation diffusion region. [Figure 3B] It is another graph showing the impurity concentration profile of the separation diffusion region. [Figure 4] It is a graph showing the correlation between the impurity concentration and the depletion layer width of the separation diffusion region. [Figure 5] It is a cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 6] It is a cross-sectional view following FIG. 5 for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 7] It is a cross-sectional view following FIG. 6 for explaining an example of a method for manufacturing a semiconductor device according to an embodiment. [Figure 8]This is a cross-sectional view following Figure 7 illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 9] This is a cross-sectional view following Figure 8, illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 10] This is a cross-sectional view following Figure 9, illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 11] This is a cross-sectional view following Figure 10 illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Figure 12] This is a cross-sectional view following Figure 11 illustrating an example of a method for manufacturing a semiconductor device according to the embodiment. [Modes for carrying out the invention]
[0011] Embodiments of the present invention will be described below with reference to the drawings. In the drawings referred to in the following description, identical or similar parts are denoted by the same or similar reference numerals. However, it should be noted that the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from reality. Therefore, specific thicknesses and dimensions should be determined by referring to the following description. Furthermore, it goes without saying that there are parts where the relationships and ratios of dimensions differ between drawings.
[0012] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of the present invention. For example, it is obvious that if an object is rotated 90° and observed, up and down will be converted to left and right and read accordingly, and if it is rotated 180° and observed, up and down will be inverted and read accordingly.
[0013] Furthermore, the following explanation uses the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. However, it is also acceptable to choose the conductivity types in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. The + and - attached to n and p indicate semiconductor regions with relatively higher or lower impurity concentrations compared to semiconductor regions without + and - markings. However, even if two semiconductor regions are marked with the same n, this does not mean that the impurity concentrations in each semiconductor region are exactly the same.
[0014] (Embodiment) <Structure of a semiconductor device> As shown in Figure 1, the RB-IGBT semiconductor device according to the embodiment comprises a first conductivity type (n-type) semiconductor substrate 100. The semiconductor substrate 100 is made of, for example, a single-crystal silicon (Si) substrate. The thickness D of the semiconductor substrate 100 is, for example, about 110 μm or more and 120 μm or less for a 700 V withstand voltage device, and about 180 μm or more and 190 μm or less for a 1200 V withstand voltage device. A portion of the semiconductor substrate 100 constitutes an n-type drift layer 1.
[0015] The semiconductor device according to this embodiment includes an active region 101 and a pressure-resistant structure 102 provided in an annular shape surrounding the active region 101. In the active region 101 located in the center of the semiconductor substrate 100, as shown on the right side of Figure 1, a base region 3 of the second conductivity type (p-type) is provided above the drift layer 1, in contact with the drift layer 1. Above the base region 3, in contact with the base region 3, + A first main electrode region (emitter region) 4 of the type is provided.
[0016] Multiple trenches 6 are spaced apart from each other in the depth direction from the upper surface of the semiconductor substrate 100. The trenches 6 penetrate the emitter region 4 and the base region 3 and reach the drift layer 1. The sides (side walls) of the trenches 6 are in contact with the sides of the emitter region 4 and the base region 3. In the parallel direction of the trenches 6, a mesa portion, which is formed from the upper part of the semiconductor substrate 100, is provided between adjacent trenches 6. The upper part of the drift layer 1, the base region 3 and the emitter region 4 are provided in the mesa portion.
[0017] A gate insulating film 7 is provided so as to cover the bottom and sides of the trench 6. As the gate insulating film 7, one single layer film of any of the following can be used: silicon dioxide film (SiO2 film), silicon oxynitride (SiON) film, strontium oxide (SrO) film, silicon nitride (Si3N4) film, aluminum oxide (Al2O3) film, magnesium oxide (MgO) film, yttrium oxide (Y2O3) film, hafnium oxide (HfO2) film, zirconium oxide (ZrO2) film, tantalum oxide (Ta2O5) film, or bismuth oxide (Bi2O3) film, or a composite film made by stacking multiple of these.
[0018] Inside the trench 6, a gate electrode 8 is embedded via a gate insulating film 7. As the material for the gate electrode 8, for example, a polysilicon film (doped polysilicon film) with high impurity concentrations of phosphorus (P) or boron (B) can be used. The gate insulating film 7 and the gate electrode 8 constitute an insulated gate type electrode structure (MOS gate structure) (7,8).
[0019] An interlayer insulating film 9 is provided on the upper surface of the semiconductor substrate 100. The interlayer insulating film 9 is composed of single-layer films such as undoped silicon oxide films (SiO2 films) that do not contain phosphorus (P) or boron (B), referred to as "NSG," phosphorus-doped silicon oxide films (PSG films), boron-doped silicon oxide films (BSG films), boron and phosphorus-doped silicon oxide films (BPSG films), silicon nitride films (Si3N4 films), and high-temperature oxide films (HTO), or multilayer films of these.
[0020] An emitter electrode 10 is provided on the interlayer insulating film 9. The emitter electrode 10 is electrically connected to the emitter region 4 and the base region 3 via a contact plug provided in a contact hole that penetrates the interlayer insulating film 9. The emitter electrode 10 can be made of metals such as aluminum (Al), Al alloys, or copper (Cu). Examples of Al alloys include Al-silicon (Si), Al-copper (Cu)-Si, and Al-Cu.
[0021] On the lower surface side of drift layer 1, in contact with drift layer 1, p + A type second main electrode region (collector region) 12 is provided. The thickness of the collector region 12 is, for example, 0.2 μm or more and 1.0 μm or less. The impurity concentration of the collector region 12 is, for example, 2 × 10⁻⁶ 16 cm -3 The above is 2 x 10 18 cm -3 The following is an example. The thickness D of the semiconductor substrate 100 is defined as the thickness from the top surface of the drift layer 1, base region 3, and emitter region 4 to the bottom surface of the collector region 12.
[0022] A collector electrode 13 is provided on the lower surface of the collector region 12. The collector electrode 13 can be made of, for example, a single layer of gold (Au) or a metal film stacked in the order of titanium (Ti), nickel (Ni), and gold (Au).
[0023] As shown on the left side of Figure 1, the pressure-resistant structure 102 located on the outer periphery of the semiconductor substrate 100 contains p + Multiple field limiting ring (FLR) layers 5 are arranged in an annular shape. Field plate layers 11 are connected to the FLR layers 5 via contact plugs provided in contact holes that penetrate the interlayer insulating film 9.
[0024] The outer periphery of the pressure-resistant structure 102 is surrounded by the drift layer 1, p +A ring-shaped separation and diffusion region 2 is provided. The separation and diffusion region 2 is exposed on the dicing surface, which is the side surface 100a of the semiconductor substrate 100. The separation and diffusion region 2 extends from the top surface of the semiconductor substrate 100 to the top surface of the collector region 12. The lower surface of the separation and diffusion region 2 is in contact with the top surface of the collector region 12.
[0025] The separation and diffusion region 2 is formed by ion implantation and heat treatment from the upper surface of the semiconductor substrate 100. The upper width of the separation and diffusion region 2 is greater than the lower width of the separation and diffusion region 2. The impurity concentration in the separation and diffusion region 2 has a peak concentration at the upper side. The impurity concentration at the lower side of the separation and diffusion region 2 is lower than the impurity concentration at the upper side of the separation and diffusion region 2. For example, the impurity concentration at the upper side of the separation and diffusion region 2, near the upper surface of the semiconductor substrate 100, is, for example, 1 × 10⁻⁶. 17 cm -3 The above 5 x 10 18 cm -3 The following is an example of the impurity concentration in the vicinity of the collector region 12 below the separation and diffusion region 2, i.e., the portion in contact with the upper surface of the collector region 12: 16 cm -3 The above is 2 x 10 18 cm -3 It is approximately as follows.
[0026] Figure 2 shows a magnified view of the area A enclosed by the dashed line, which is below the separation and diffusion region 2 and the collector region 12 in Figure 1. In Figure 2, the extension of the depletion layers d1 and d2 from the pn junction, consisting of the separation and diffusion region 2 and the drift layer 1, is schematically shown by the dashed line when a reverse bias is applied, and the direction in which the depletion layers d1 and d2 extend is schematically shown by the arrow. When a reverse bias is applied, p + Type separation and diffusion regions 2 and p + A depletion layer d1 extends from the pn junction between the n-type collector region 12 and the n-type drift layer 1 toward the drift layer 1.
[0027] Furthermore, the depletion layer d2 extends from the pn junction between the separation-diffusion region 2 and the collector region 12 towards the separation-diffusion region 2 and the collector region 12 towards the drift layer 1. Since the collector region 12 has a high impurity concentration, the extension of the depletion layer d2 towards the collector region 12 is slight. On the other hand, near the collector region 12 of the separation-diffusion region 2, the impurity concentration of the separation-diffusion region 2 decreases, making it easier for the depletion layer d2 to extend. When the depletion layer d2 reaches the side surface 100a of the semiconductor substrate 100 (reach-through), leakage current is generated and the breakdown voltage deteriorates.
[0028] Therefore, in the semiconductor device according to this embodiment, the width Wp of the separation and diffusion region 2 near the collector region 12 shown in Figure 2, that is, the portion of the separation and diffusion region 2 that is in contact with the upper surface of the collector region 12, is set to be at least 1 times the thickness D of the semiconductor substrate 100 shown in Figure 1 (Wp / D≧1). By setting the width Wp of the separation and diffusion region 2 to be at least 1 times the thickness D of the semiconductor substrate 100, a wide width Wp of the separation and diffusion region 2 can be secured, and the depletion layer d2 can be prevented from reaching the side surface 100a of the semiconductor substrate 100.
[0029] Furthermore, it is preferable that the width Wp of the separation and diffusion region 2 is set to 1.2 times or more the thickness D of the semiconductor substrate 100 (Wp / D ≥ 1.2). By setting the width Wp of the separation and diffusion region 2 to 1.2 times or more the thickness D of the semiconductor substrate 100, it is possible to more reliably suppress the depletion layer d2 from reaching the side surface 100a of the semiconductor substrate 100.
[0030] Furthermore, the width Wp of the separation and diffusion region 2 is set to be less than or equal to twice the thickness D of the semiconductor substrate 100 (Wp / D ≤ 2). By setting the width Wp of the separation and diffusion region 2 to be less than or equal to twice the thickness D of the semiconductor substrate 100, the area of the withstand voltage structure portion 102, which is an inactive region that does not contribute to the performance of the device, can be reduced, and the area of the active region 101 that contributes to the performance of the device can be secured, thereby suppressing an increase in chip size.
[0031] Furthermore, it is preferable that the width Wp of the separation and diffusion region 2 is set to 1.8 times or less the thickness D of the semiconductor substrate 100 (Wp / D ≤ 1.8). By setting the width Wp of the separation and diffusion region 2 to 1.8 times or less the thickness D of the semiconductor substrate 100, the area of the pressure-resistant structure 102 can be further reduced, and the area of the active region 101 can be further secured, thereby further suppressing the increase in chip size.
[0032] Furthermore, it is preferable that the width Wp of the separation and diffusion region 2 is set to approximately 300 μm or less. By setting the width Wp of the separation and diffusion region 2 to approximately 300 μm or less, the area of the pressure-resistant structure 102 can be reduced, the area of the active region 101 can be secured, and an increase in chip size can be suppressed.
[0033] For example, in a 700V withstand voltage device, the thickness D of the semiconductor substrate 100 is approximately 110μm or more and 120μm or less, and the width Wp of the separation and diffusion region 2 is approximately 110μm or more and 240μm or less. In a 1200V withstand voltage device, the thickness D of the semiconductor substrate 100 is approximately 180μm or more and 190μm or less, and the width Wp of the separation and diffusion region 2 is approximately 180μm or more and 380μm or less, more preferably 180μm or more and 300μm or less.
[0034] The solid line in Figure 3A shows the profile of the impurity concentration in the separated diffusion region 2 and the semiconductor substrate 100 after the separated diffusion region 2 is formed on the n-type semiconductor substrate 100 in the manufacturing process of the semiconductor device according to the embodiment, and before the back surface grinding of the semiconductor substrate 100. The vertical axis in Figure 3A shows the impurity concentration in the separated diffusion region 2 and the semiconductor substrate 100. The horizontal axis in Figure 3A shows the distance from the top surface (surface of the emitter region 4) of the semiconductor substrate 100 at the position of a hypothetical straight line L1 passing through positions P1 and P2 shown in Figure 1.
[0035] The positions P1 and P2 on the solid line in Figure 3A correspond to the positions P1 and P2 shown in Figure 1. Position P1 shown in Figure 1 corresponds to the position of the edge of the opening of the mask used for ion implantation to form the separation and diffusion region 2 on the surface of the semiconductor substrate 100. Position P2 is a position perpendicularly lowered from position P1 at the depth of the pn junction interface between the collector region 12 and the drift layer 1. As shown in Figure 2, the edge of the depletion layer d2 is outside of position P2. That is, the edge of the depletion layer d2 is outside of the edge of the opening of the mask used for ion implantation to form the separation and diffusion region 2.
[0036] As shown by the solid line in Figure 3A, the p-type impurity concentration in the separation and diffusion region 2 has a peak concentration on the upper surface side of the semiconductor substrate 100, and the p-type impurity concentration in the separation and diffusion region 2 decreases as the depth increases. On the other hand, the n-type impurity concentration of the semiconductor substrate 100 is a constant impurity concentration Nd. Since a portion of the semiconductor substrate 100 constitutes the drift layer 1, the impurity concentration of the drift layer 1 is also Nd.
[0037] The dashed line in Figure 3B shows the profile of the p-type impurity concentration near the collector region 12 of the separation and diffusion region 2 in the semiconductor device according to the embodiment. The vertical axis in Figure 3B shows the impurity concentration of the separation and diffusion region 2 and the semiconductor substrate 100. The horizontal axis in Figure 3B shows the position in the direction from the side surface to the inside of the semiconductor device at the depth near the collector region 12 of the separation and diffusion region 2 and near the collector region 12 of the drift layer 1. Positions P2, P3, and P4 on the dashed line in Figure 3B correspond to positions P2, P3, and P4 shown in Figure 1. Position P4 shown in Figure 1 is a position exposed on the dicing surface, which is the side surface 100a of the semiconductor substrate 100. Position P3 is a position in contact with the drift layer 1 on the inner circumferential surface of the separation and diffusion region 2.
[0038] As shown by the dashed line in Figure 3B, the impurity concentration in the separation and diffusion region 2 is constant, Na, from position P4, which is exposed to the dicing surface (side surface 100a) of the semiconductor substrate 100, to position P2, which is vertically lowered from position P1, the edge of the opening of the mask used for ion implantation to form the separation and diffusion region 2. The impurity concentration Na in the separation and diffusion region 2 can be defined as the impurity concentration at position P4, which is exposed to the dicing surface (side surface 100a) of the semiconductor substrate 100.
[0039] In the semiconductor device according to the embodiment, it is preferable that the width Wp of the separation and diffusion region 2 shown in Figure 2 is set to be greater than or equal to the width Wd of the depletion layer d2. The width Wd of the depletion layer d2 is the width of the depletion layer that extends from the pn junction of the separation and diffusion region 2 and the drift layer 1 toward the separation and diffusion region 2 in the portion of the separation and diffusion region 2 that is in contact with the collector region 12 when a reverse bias is applied. By setting the width Wp of the separation and diffusion region 2 to be greater than or equal to the width Wd of the depletion layer d2, it is possible to suppress the depletion layer d2 from reaching the side surface 100a of the semiconductor substrate 100 when a reverse bias is applied.
[0040] Impurity concentration Na in separation and diffusion region 2, reverse voltage V when reverse bias is applied. R Regarding the width Wd of the depletion layer d2, the following equation (1) generally holds true.
[0041] Wd=(2ε s V R / qNa) 1 / 2 …(1)
[0042] Here, ε s V is the dielectric constant of the semiconductor, and q is the elementary charge of the electron. Reverse voltage V R This is, for example, the rated reverse voltage or maximum reverse voltage when reverse bias is applied, and can be set appropriately depending on the breakdown voltage class, etc. The width Wd of the depletion layer d2 can be set appropriately depending on the breakdown voltage class, the impurity concentration in the separation and diffusion region 2, etc.
[0043] Furthermore, in the semiconductor device according to the embodiment, it is preferable that the width Wp of the separation and diffusion region 2 is set to be equal to or greater than the sum of the width Wd of the depletion layer d2 and 50 μm. That is, it is preferable to set the width Wp of the separation and diffusion region 2 to satisfy the following formula (2).
[0044] Wp ≥ Wd + 50 μm …(2)
[0045] In the manufacturing process of the semiconductor device according to this embodiment, cracks or fractures may occur on the dicing surface, which is the side surface 100a of the semiconductor substrate 100, due to vibrations or other shocks during the dicing process or during transport after the dicing process. The cracks or fractures on the dicing surface, which is the side surface 100a of the semiconductor substrate 100, are up to about 50 μm in size. Therefore, by setting the width Wp of the separation and diffusion region 2 to satisfy equation (2), even if cracks or fractures occur on the dicing surface, which is the side surface 100a of the semiconductor substrate 100, it is possible to suppress the depletion layer d2 from reaching the area of the separation and diffusion region 2 where the cracks or fractures have occurred. Thus, the deterioration of the device characteristics when a reverse voltage is applied can be suppressed more reliably, and a highly reliable device can be realized.
[0046] Furthermore, in the semiconductor device according to the embodiment, it is preferable to set the p-type impurity concentration Na of the separation and diffusion region 2 to twice or more the n-type impurity concentration Nd of the drift layer 1. By setting the impurity concentration Na of the separation and diffusion region 2 to twice or more the impurity concentration Nd of the drift layer 1, the width Wd of the depletion layer d2 can be narrowed, and the width Wp of the separation and diffusion region 2, which is an ineffective region that does not contribute to the performance of the device, can be narrowed.
[0047] Furthermore, it is preferable to set the p-type impurity concentration Na in the separation and diffusion region 2 to 10 times or less the n-type impurity concentration Nd in the drift layer 1. By setting the impurity concentration Na in the separation and diffusion region 2 to 10 times or less the impurity concentration Nd in the drift layer 1, the time and burden of the ion implantation and heat treatment processes when forming the separation and diffusion region 2 can be suppressed.
[0048] Figure 4 shows the reverse voltage V when reverse bias is applied. R This shows the correlation between the impurity concentration Na in the separation and diffusion region 2 and the width Wd of the depletion layer d2 when the voltage is 1200V. As shown in Figure 4, the higher the impurity concentration Na, the narrower the width Wd of the depletion layer d2 becomes. For example, impurity concentration Na = 1 × 10⁻⁶ 14 cm -2 In this case, the width of the depletion layer d2 is Wd = 125 μm, and in order to satisfy equation (2), the width of the separation and diffusion region 2 must be Wp = 125 μm + 50 μm = 175 μm. In contrast, the impurity concentration Na is doubled (Na = 2 × 10⁻¹⁰). 14 cm -2 By doing so, in order to satisfy equation (2), the width of the separation and diffusion region 2 Wp becomes Wp = 90 μm + 50 μm = 140 μm, and the width of the separation and diffusion region 2 Wp can be narrowed.
[0049] According to the semiconductor device of this embodiment, the width Wp of the separation and diffusion region 2 is set by focusing on the fact that when a reverse bias is applied, the depletion layer d2 tends to expand in the portion of the separation and diffusion region 2 near the collector region 12 where the impurity concentration is low. This ensures that a sufficient width Wp of the separation and diffusion region 2 can be secured to withstand the expansion of the depletion layer d2. Therefore, degradation of the device characteristics can be prevented, and a highly reliable device can be realized.
[0050] <Manufacturing method for semiconductor devices> Next, an example of a semiconductor device according to the embodiment will be described. It should be noted that the semiconductor device described below is merely an example, and it is of course possible to realize it through various other manufacturing methods, including this modification, within the scope of the claims.
[0051] First, as shown in Figure 5, an n-type semiconductor substrate 100, which is a single-crystal silicon (Si) wafer, is prepared. Next, an insulating film 21, such as an oxide film, is deposited by thermal oxidation or chemical vapor deposition (CVD), and an opening 21a is formed in the insulating film 21 using photolithography technology. Using the insulating film 21 as a mask, p-type impurities such as boron (B) are ion-implanted to form an ion-implanted layer 2a. The width W1 of the opening 21a in the insulating film 21 is, for example, about 200 μm or more and 250 μm or less. In Figure 5, the trimming allowance 22 for the dicing process, which will be described later, is schematically shown by a dashed line. The width W2 of the trimming allowance 22 is, for example, about 50 μm or more and 70 μm or less.
[0052] Next, the p-type impurities in the ion-implanted layer 2a are activated and diffused by high-temperature, long-duration heat treatment (drive diffusion heat treatment). As a result, as shown in Figure 6, a separated diffusion region 2 is formed deep within the semiconductor substrate 100. In Figure 6, the position of the bottom surface of the semiconductor substrate 100 after grinding from the bottom side by back grinding, which will be described later, is schematically shown by the dashed line L2. Also, the edge position of the opening 21a of the insulating film 21 is position P1, and the position near the dashed line L2, which is drawn vertically downward from position P1, is position P2. After that, the insulating film 21 is removed.
[0053] Next, a portion of the drift layer 1 is selectively removed from the upper surface of the semiconductor substrate 100 using photolithography and dry etching techniques, etc., to form multiple trenches 6 on the upper surface of the semiconductor substrate 100 (see Figure 1).
[0054] Next, a gate insulating film 7 is formed on the bottom and sides of the trench 6 by thermal oxidation or CVD (see Figure 1). Then, a polysilicon film (doped polysilicon film) with high concentrations of impurities such as phosphorus (P) and boron (B) is deposited on the inside of the trench 6 via the gate insulating film 7 by CVD or the like. Subsequently, the polysilicon film and the gate insulating film 7 on the semiconductor substrate 100 are selectively removed by photolithography and dry etching. As a result, an insulated gate electrode structure (7,8) consisting of the gate insulating film 7 and the gate electrode 8 of the polysilicon film is formed inside the trench 6 (see Figure 1).
[0055] Next, p-type and n-type impurities are sequentially ion-implanted from the upper surface of the semiconductor substrate 100 by repeatedly performing photolithography and ion implantation processes. Then, the p-type and n-type impurities implanted in the semiconductor substrate 100 are activated by heat treatment. As a result, as shown in Figure 7, in the activated region, a p-type base region 3 and n-type impurities are formed in the upper part of the semiconductor substrate 100. + A type emitter region 4 is formed. In addition, in the pressure-resistant structure, p + A type FLR layer 5 is formed.
[0056] Next, an interlayer insulating film 9 is deposited on the upper surface of the semiconductor substrate 100 by CVD or the like (see Figure 1). Then, contact holes are opened in the interlayer insulating film 9 by photolithography and dry etching or the like. Next, an emitter electrode 10 is formed on the upper surface of the interlayer insulating film 9 by sputtering or vapor deposition and dry etching or the like, as shown in Figure 8.
[0057] Next, a lifetime killer is introduced into the drift layer 1 by irradiating the semiconductor substrate 100 with an electron beam from the top or bottom side. Alternatively, a lifetime control region may be formed inside the drift layer 1 by irradiating the semiconductor substrate 100 with a light element such as helium (He) or proton (H) from the top or bottom side. After that, the desired lifetime is achieved by heat treatment (annealing). Note that irradiation with an electron beam or light element to control the lifetime is not necessarily required.
[0058] Next, the semiconductor substrate 100 is ground from the bottom side by chemical mechanical polishing (CMP) or the like, as shown in Figure 9, to adjust the semiconductor substrate 100 to the product thickness D. As a result, the bottom surface of the separation and diffusion region 2 is exposed.
[0059] Next, p-type impurities such as boron (B) are ion-implanted across the entire underside of the semiconductor substrate 100. Then, the impurity ions implanted in the semiconductor substrate 100 are activated by heat treatment such as laser irradiation. As a result, as shown in Figure 10, p-type impurities are present on the underside of the semiconductor substrate 100. + A collector region 12 of a certain type is formed, and the collector region 12 is connected to the separation and diffusion region 2.
[0060] Next, a collector electrode 13 made of gold (Au) or the like is formed on the entire lower surface of the semiconductor substrate 100 by sputtering or vapor deposition, as shown in Figure 11.
[0061] Next, the dicing blade is rotated at high speed to cut (dice) the central part of the separation and diffusion region 2, as shown in Figure 12, and a chip is cut out from the wafer. The separation and diffusion region 2 is exposed on the side surface of the chip. In this way, the semiconductor device according to the embodiment shown in Figure 1 is completed.
[0062] (Other embodiments) Although embodiments have been described above, the descriptions and drawings that constitute part of this disclosure should not be understood as limiting the present invention. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.
[0063] For example, in the semiconductor device according to the embodiment, a trench-gate type IGBT having an insulated-gate electrode structure (MOS gate structure) (7,8) in which a gate electrode 8 is embedded inside a trench 6 via a gate insulating film 7 was exemplified. However, a planar-type IGBT having an insulated-gate electrode structure (MOS gate structure) in which a gate electrode is provided on the upper surface of the semiconductor substrate 100 via a gate insulating film may also be provided.
[0064] Furthermore, the configurations disclosed in the embodiments can be combined as appropriate, within a non-contradictory scope. Thus, it goes without saying that the present invention includes various embodiments not described herein. Therefore, the technical scope of the present invention is determined solely by the inventive features relating to the claims that are reasonable based on the above description. [Explanation of Symbols]
[0065] 1…Drift layer 2…Separation diffusion region 2a...Ion implantation layer 3…Base area 4…Emitter region 5...FLR layer 6…Trench 7…Gate insulating film 8… Gate gate 9…Interlayer insulating film 10…Emitter electrode 11…Field plate layer 12...Collector area 13...Collector electrode 21… Insulating film 21a...Opening 22...removeable area 100... Semiconductor substrate 101...Active region 102...Pressure-resistant structural part d1,d2…depletion layer Positions P1, P2, P3, P4… Wd… Empty Layers Wp…separation and dispersion domain amplitude
Claims
1. A first conductive drift layer, An insulated gate type electrode structure provided on the upper surface side of the drift layer, A second conductive base region is provided on the upper part of the drift layer, A first main electrode region of the first conductivity type is provided on the upper part of the base region, A second main electrode region of the second conductivity type is provided on the lower surface side of the drift layer, A second conductivity type separation and diffusion region is provided in an annular shape, in contact with the upper surface of the second main electrode region and surrounding the side surface of the drift layer, with the upper width being wider than the lower width, Equipped with, The width of the portion of the separation and diffusion region that is in contact with the second main electrode region is one to two times the thickness from the upper surface of the drift layer to the lower surface of the second main electrode region. A semiconductor device characterized in that, in the portion of the separation and diffusion region in contact with the second main electrode region, the impurity concentration on the outer surface of the separation and diffusion region is set to be at least twice and no more than ten times the impurity concentration of the drift layer.
2. The semiconductor device according to claim 1, characterized in that the width of the portion of the separation-diffusion region that is in contact with the second main electrode region is greater than or equal to the width of the depletion layer extending from the pn junction between the separation-diffusion region and the drift layer toward the separation-diffusion region in the portion of the separation-diffusion region that is in contact with the second main electrode region when a reverse bias is applied.
3. Let Wp be the width of the portion of the separation-diffusion region that is in contact with the second main electrode region, and let Wd be the width of the depletion layer extending from the pn junction between the separation-diffusion region and the drift layer toward the separation-diffusion region in the portion of the separation-diffusion region that is in contact with the second main electrode region when a reverse bias is applied. Wp≧Wd+50 [μm] The semiconductor device according to claim 1, characterized in that it satisfies the requirements.
4. The semiconductor device according to claim 1 or 2, characterized in that the impurity concentration in the upper part of the separation and diffusion region is higher than the impurity concentration in the lower part of the separation and diffusion region.
5. The semiconductor device according to claim 1 or 2, characterized in that a lifetime killer is introduced inside the drift layer.
6. The semiconductor device according to claim 1 or 2, characterized in that the impurity concentration on the upper surface of the separation and diffusion region is 1 × 10¹⁷ cm⁻³ or more and 5 × 10¹⁸ cm⁻³ or less.
7. The semiconductor device according to claim 1 or 2, characterized in that the impurity concentration in the portion of the separation and diffusion region in contact with the second main electrode region is 2 × 10¹⁶ cm⁻³ or more and 2 × 10¹⁸ cm⁻³ or less.