Semiconductor device and method for manufacturing a semiconductor device

Abstract

To provide a semiconductor device capable of suppressing damage to a surface of a regrown nitride semiconductor layer, and the manufacturing method thereof.SOLUTION: A method for manufacturing a semiconductor device includes the steps of: forming an insulation layer 121 on a surface 210A of a nitride semiconductor layer 210; forming a mask including a mask opening through which a part of a first insulation layer is exposed on the insulation layer; forming openings 121S and 121D through which a part of the nitride semiconductor layer is exposed on the insulation layer; forming nitride semiconductor layers 231S and 231D on the nitride semiconductor layer inside the openings; forming insulation layers 122S and 122D covering the boundary line between the nitride semiconductor layers 231S and 231D and the insulation layer; removing the mask; forming an opening 123S through which a part of the nitride semiconductor layer 231S is exposed on the insulation layer 122S and an opening 123D through which a part of the nitride semiconductor layer 231D is exposed on the insulation layer 122D; forming an electrode 132S in contact with the nitride semiconductor layer 231S on the insulation layer 122S and an electrode 132D in contact with the nitride semiconductor layer 231D on the insulation layer 122D; and forming a gate electrode 141 separated from the insulation layers 122S and 122D above the nitride semiconductor layer 210.SELECTED DRAWING: Figure 26

Description

Technical Field

[0001] The present disclosure relates to a semiconductor device and a method for manufacturing the semiconductor device.

Background Art

[0002] A structure in which a nitride semiconductor layer containing impurities at a high concentration is regrown has been proposed for reducing the on-resistance in a semiconductor device using a nitride semiconductor.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Summary of the Invention

Problems to be Solved by the Invention

[0004] In a conventional semiconductor device, the surface of the regrown nitride semiconductor layer may be damaged during manufacturing.

[0005] An object of the present disclosure is to provide a semiconductor device and a method for manufacturing the semiconductor device that can suppress damage to the surface of the regrown nitride semiconductor layer.

Means for Solving the Problems

[0006] A method for manufacturing a semiconductor device according to the present disclosure includes the steps of: forming a first insulating layer on a first nitride semiconductor layer having a first main surface; forming a mask on the first insulating layer having a first mask opening through which a part of the first insulating layer is exposed; forming a first opening through the first mask opening through which a part of the first nitride semiconductor layer is exposed in the first insulating layer; forming a second nitride semiconductor layer on the first nitride semiconductor layer inside the first opening through the first mask opening; forming a second insulating layer through the first mask opening that covers the boundary between the second nitride semiconductor layer and the first insulating layer; removing the mask after the step of forming the second insulating layer; forming a second opening in the second insulating layer through which a part of the second nitride semiconductor layer is exposed; forming a first electrode on the second insulating layer that contacts the second nitride semiconductor layer through the second opening; and forming a gate electrode above the first nitride semiconductor layer, away from the second insulating layer in a plan view perpendicular to the first main surface. [Effects of the Invention]

[0007] According to this disclosure, damage to the surface of the regrowthed nitride semiconductor layer can be suppressed. [Brief explanation of the drawing]

[0008] [Figure 1] Figure 1 is a cross-sectional view showing a semiconductor device according to the first embodiment. [Figure 2] Figure 2 is a cross-sectional view (part 1) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 3] Figure 3 is a cross-sectional view (part 2) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 4] Figure 4 is a cross-sectional view (part 3) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 5] Figure 5 is a cross-sectional view (part 4) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 6] Figure 6 is a cross-sectional view (part 5) showing a method for manufacturing a semiconductor device according to the first embodiment. [Figure 7] FIG. 7 is a cross-sectional view (part 6) showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 8] FIG. 8 is a cross-sectional view (part 7) showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 9] FIG. 9 is a cross-sectional view (part 8) showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 10] FIG. 10 is a cross-sectional view (part 9) showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 11] FIG. 11 is a cross-sectional view (part 10) showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 12] FIG. 12 is a cross-sectional view (part 11) showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 13] FIG. 13 is a cross-sectional view (part 12) showing a method of manufacturing a semiconductor device according to the first embodiment. [Figure 14] FIG. 14 is a cross-sectional view showing a semiconductor device according to the second embodiment. [Figure 15] FIG. 15 is a cross-sectional view (part 1) showing a method of manufacturing a semiconductor device according to the second embodiment. [Figure 16] FIG. 16 is a cross-sectional view (part 2) showing a method of manufacturing a semiconductor device according to the second embodiment. [Figure 17] FIG. 17 is a cross-sectional view (part 3) showing a method of manufacturing a semiconductor device according to the second embodiment. [Figure 18] FIG. 18 is a cross-sectional view (part 4) showing a method of manufacturing a semiconductor device according to the second embodiment. [Figure 19] FIG. 19 is a cross-sectional view (part 5) showing a method of manufacturing a semiconductor device according to the second embodiment. [Figure 20] FIG. 20 is a cross-sectional view (part 6) showing a method of manufacturing a semiconductor device according to the second embodiment. [Figure 21] FIG. 21 is a cross-sectional view (part 7) showing a method of manufacturing a semiconductor device according to the second embodiment. [Figure 22]FIG. 22 is a cross-sectional view (Part 8) showing a method of manufacturing a semiconductor device according to the second embodiment. [Figure 23] FIG. 23 is a cross-sectional view (Part 9) showing a method of manufacturing a semiconductor device according to the second embodiment. [Figure 24] FIG. 24 is a cross-sectional view (Part 10) showing a method of manufacturing a semiconductor device according to the second embodiment. [Figure 25] FIG. 25 is a cross-sectional view (Part 11) showing a method of manufacturing a semiconductor device according to the second embodiment. [Figure 26] FIG. 26 is a cross-sectional view (Part 12) showing a method of manufacturing a semiconductor device according to the second embodiment.

Embodiments for Carrying Out the Invention

[0009] [Description of Embodiments of the Present Disclosure] First, embodiments of the present disclosure will be listed and described.

[0010] 〔1〕 A method of manufacturing a semiconductor device according to one aspect of the present disclosure includes a step of forming a first insulating layer on a first nitride semiconductor layer having a first main surface, a step of forming a mask having a first mask opening through which a part of the first insulating layer is exposed on the first insulating layer, a step of forming a first opening through the first mask opening in the first insulating layer through which a part of the first nitride semiconductor layer is exposed, a step of forming a second nitride semiconductor layer on the first nitride semiconductor layer inside the first opening through the first mask opening, a step of forming a second insulating layer covering a boundary line between the second nitride semiconductor layer and the first insulating layer through the first mask opening, a step of removing the mask after the step of forming the second insulating layer, a step of forming a second opening in the second insulating layer through which a part of the second nitride semiconductor layer is exposed, a step of forming a first electrode contacting the second nitride semiconductor layer through the second opening on the second insulating layer, and a step of forming a gate electrode above the first nitride semiconductor layer and separated from the second insulating layer in a plan view perpendicular to the first main surface.

[0011] Before mask removal, the second nitride semiconductor layer is covered by the second insulating layer. The second insulating layer covers the boundary between the second nitride semiconductor layer and the first insulating layer. Therefore, the surface of the second nitride semiconductor layer is protected from the chemicals used to remove the mask, and damage to the surface of the second nitride semiconductor layer can be suppressed. In addition, the gate electrode is formed away from the second insulating layer in a plan view. Therefore, the distance between the gate electrode and the first nitride semiconductor layer is less affected by the second insulating layer. Thus, changes in gate controllability from a structure without the second insulating layer can be suppressed.

[0012] [2] In [1], the mask may have a second mask opening through which another part of the first insulating layer is exposed, and the process may include: simultaneously forming the first opening, a third opening through the second mask opening through which another part of the first nitride semiconductor layer is exposed in the first insulating layer; simultaneously forming the second nitride semiconductor layer, a third nitride semiconductor layer on the first nitride semiconductor layer inside the third opening through the second mask opening; simultaneously forming the second insulating layer, a third insulating layer covering the boundary between the third nitride semiconductor layer and the first insulating layer through the second mask opening; simultaneously forming the second opening, a fourth opening through the third insulating layer through which a part of the third nitride semiconductor layer is exposed; and simultaneously forming the first electrode, a second electrode on the third insulating layer that contacts the third nitride semiconductor layer through the fourth opening. In this case, the first electrode and the second electrode can be used as the source electrode and drain electrode of a field-effect transistor.

[0013] [3] In [2], in the plan view, the gate electrode may be formed between the second insulating layer and the third insulating layer. In this case, the distance between the gate electrode and the first nitride semiconductor layer is less affected by the third insulating layer.

[0014] [4] In [2] or [3], between the step of forming the first electrode and the step of forming the gate electrode, there is a step of forming a fourth insulating layer covering the first electrode on the first insulating layer, and the gate electrode may be formed on the fourth insulating layer. In this case, a so-called MIS (metal insulator semiconductor) structure can be formed.

[0015] [5] In [4], the upper surface of the second nitride semiconductor layer may be an N-polarity surface. In this case, it is easier to achieve low resistance.

[0016] [6] In [4], between the step of forming the fourth insulating layer and the step of forming the gate electrode, there may be a step of forming a fifth opening in the fourth insulating layer and the first insulating layer, and the gate electrode may be formed to contact the first nitride semiconductor layer through the fifth opening. In this case, a so-called MES (metal insulator) structure can be formed.

[0017] [7] In [6], the upper surface of the second nitride semiconductor layer may be a Ga polarity surface. In this case, good etching resistance can be easily obtained on the upper surface of the second nitride semiconductor layer.

[0018] [8] A semiconductor device according to another aspect of the present disclosure includes: a first nitride semiconductor layer having a first main surface; a first insulating layer provided on the first nitride semiconductor layer and having a first opening through which a part of the first nitride semiconductor layer is exposed; a second nitride semiconductor layer provided on the first nitride semiconductor layer inside the first opening; a second insulating layer covering the boundary between the second nitride semiconductor layer and the first insulating layer and having a second opening through which a part of the second nitride semiconductor layer is exposed; an electrode provided on the second insulating layer and in contact with the second nitride semiconductor layer through the second opening; and a gate electrode provided above the first nitride semiconductor layer and away from the second insulating layer in a plan view perpendicular to the first main surface. In this case, the second insulating layer can suppress damage to the surface of the second nitride semiconductor layer. Furthermore, the distance between the gate electrode and the first nitride semiconductor layer is less affected by the second insulating layer, and changes in gate controllability from a structure without the second insulating layer can be suppressed.

[0019] [Details of the embodiments of this disclosure] The embodiments of this disclosure will be described in detail below, but this disclosure is not limited to these embodiments. In this specification and drawings, components having substantially the same functional configuration may be denoted by the same reference numerals to avoid redundant descriptions.

[0020] (First Embodiment) First, the first embodiment will be described. The first embodiment relates to a semiconductor device including a GaN-based high electron mobility transistor (HEMT). Figure 1 is a cross-sectional view showing the semiconductor device according to the first embodiment.

[0021] As shown in Figure 1, the semiconductor device 100 according to the first embodiment mainly comprises a substrate 101, a nitride semiconductor layer 110, an insulating layer 121, an insulating layer 122S, an insulating layer 122D, an n-type GaN layer 131S, an n-type GaN layer 131D, a gate electrode 141, a source electrode 132S, a drain electrode 132D, and an insulating layer 142.

[0022] The substrate 101 is, for example, a growth substrate for GaN-based semiconductors, and in one example, a semi-insulating SiC substrate. When the substrate 101 is a SiC substrate, the surface of the substrate 101 is a carbon (C) polar surface. When the surface of the substrate 101 is a C polar surface, the nitride semiconductor layer 110 can be grown using the nitrogen (N) polar surface as the growth surface. A sapphire substrate may also be used as the growth substrate for GaN-based semiconductors. Furthermore, the substrate 101 does not have to be a substrate for crystal growth; in that case, the substrate may be removed from the buffer layer 111, barrier layer 112, and channel layer 113 grown on another substrate, and the substrate 101 may be bonded to the buffer layer 111, barrier layer 112, and channel layer 113. In that case, various semi-insulating substrates of different materials can be used as the substrate 101, such as a sapphire substrate, Si substrate, SiC substrate, AlN substrate, sintered body, etc.

[0023] The nitride semiconductor layer 110 has a buffer layer 111, a barrier layer 112, and a channel layer 113. The nitride semiconductor layer 110 is an example of a first nitride semiconductor layer.

[0024] The buffer layer 111 is, for example, an AlN layer. The thickness of the AlN layer is, for example, 5 nm or more and 100 nm or less. The buffer layer 111 may also have an AlN layer and a GaN layer or AlGaN layer on top of the AlN layer. The thickness of the GaN layer or AlGaN layer is, for example, 300 nm or more and 2000 nm or less.

[0025] The barrier layer 112 is, for example, an AlGaN layer. The band gap of the barrier layer 112 is larger than the band gap of the channel layer 113, which will be described later. The thickness of the barrier layer 112 is, for example, in the range of 5 nm or more and 50 nm or less, and in one embodiment it is 30 nm. x Ga 1-x In the case of an N layer, its Al composition x is, for example, 0.15 to 0.55, and in one embodiment it is 0.35. The conductivity type of the barrier layer 112 is, for example, n-type or undoped (i-type). An InAlN layer or an InAlGaN layer may be used instead of the AlGaN layer.

[0026] The channel layer 113 is, for example, a GaN layer. The band gap of the channel layer 113 is smaller than the band gap of the barrier layer 112. The thickness of the channel layer 113 is, for example, in the range of 5 nm or more and 30 nm or less, and in one embodiment it is 9 nm. Due to the difference in their lattice constants, strain is generated between the channel layer 113 and the barrier layer 112, and this strain induces a piezoelectric charge at the interface between them. As a result, a two-dimensional electron gas (2DEG) is generated in the region of the channel layer 113 on the barrier layer 112 side, and the channel region 113c is formed. The conductivity type of the channel layer 113 is, for example, n-type or undoped (i-type). The surface of the channel layer 113 constitutes the surface 110A of the nitride semiconductor layer 110. Alternatively, a spacer layer may be formed between the barrier layer 112 and the channel layer 113. The spacer layer is, for example, an AlN layer. The thickness of the spacer layer is, for example, in the range of 0.5 nm or more and 3.0 nm or less, and in one embodiment it is 1.0 nm. Surface 110A is an example of the first main surface.

[0027] On the C-polarity surface of the SiC substrate, the buffer layer 111, barrier layer 112, and channel layer 113 undergo crystal growth with the N-polarity surface as the growth surface. Therefore, the front surfaces of the buffer layer 111, barrier layer 112, and channel layer 113 become N-polarity surfaces, and the back surfaces of each become gallium (Ga) polarity surfaces.

[0028] The insulating layer 121 is in contact with the surface 110A of the nitride semiconductor layer 110. The insulating layer 121 is, for example, a silicon nitride (SiN) layer. The thickness of the insulating layer 121 is, for example, 20 nm to 80 nm. Openings 121S and 121D are formed in the insulating layer 121. A portion of the nitride semiconductor layer 110 is exposed through opening 121S, and another portion of the nitride semiconductor layer 110 is exposed through opening 121D. The insulating layer 121 is an example of a first insulating layer. Openings 121S and 121D are examples of a first or third opening.

[0029] The n-type GaN layer 131S is formed on the nitride semiconductor layer 110 within the opening 121S. The n-type GaN layer 131D is formed on the nitride semiconductor layer 110 within the opening 121D. The n-type GaN layers 131S and 131D contain Ge or Si as n-type impurities. The n-type GaN layers 131S and 131D are examples of a second nitride semiconductor layer or a third nitride semiconductor layer.

[0030] The insulating layer 122S is formed on the n-type GaN layer 131S and the insulating layer 121. The insulating layer 122S is, for example, a silicon nitride (SiN) layer. The thickness of the insulating layer 122S is, for example, 20 nm to 50 nm. The insulating layer 122S is in contact with the boundary line 124S between the n-type GaN layer 131S and the insulating layer 121, and covers the boundary line 124S between the n-type GaN layer 131S and the insulating layer 121. The boundary line 124S is a line that constitutes the interface between the n-type GaN layer 131S and the insulating layer 121, and is located at the end of the interface that is away from the nitride semiconductor layer 110. The insulating layer 122S has an opening 123S in which a part of the n-type GaN layer 131S is exposed.

[0031] The insulating layer 122D is formed on the n-type GaN layer 131D and the insulating layer 121. The insulating layer 122D is, for example, a silicon nitride (SiN) layer. The thickness of the insulating layer 122D is, for example, 20 nm to 50 nm. The insulating layer 122D is separated from the insulating layer 122S. The insulating layer 122D is in contact with the boundary line 124D between the n-type GaN layer 131D and the insulating layer 121, and covers the boundary line 124D between the n-type GaN layer 131D and the insulating layer 121. The boundary line 124D is a line that constitutes the interface between the n-type GaN layer 131D and the insulating layer 121, and is located at the end of the interface that is away from the nitride semiconductor layer 110. The insulating layer 122D has an opening 123D in which a part of the n-type GaN layer 131D is exposed. The insulating layers 122S and 122D are examples of a second insulating layer or a third insulating layer. Openings 123S and 123D are examples of the second or fourth opening.

[0032] The source electrode 132S is formed on the insulating layer 122S, and the drain electrode 132D is formed on the insulating layer 122D. The source electrode 132S contacts the n-type GaN layer 131S through the opening 123S, and the drain electrode 132D contacts the n-type GaN layer 131D through the opening 123D. The source electrode 132S makes ohmic contact with the n-type GaN layer 131S, and the drain electrode 132D makes ohmic contact with the n-type GaN layer 131D. The source electrode 132S and the drain electrode 132D include, for example, a laminate of sequentially stacked Ta film, Al film, and Ta film. The source electrode 132S and the drain electrode 132D may also include, for example, a laminate of sequentially stacked Ti film, Al film, and Ti film. The source electrode 132S and the drain electrode 132D are examples of first or second electrodes.

[0033] The insulating layer 142 is formed on the insulating layer 121. The insulating layer 142 is, for example, a silicon nitride (SiN) layer. The insulating layer 142 covers the insulating layer 122S, the source electrode 132S, the insulating layer 122D, and the drain electrode 132D. The gate electrode 141 is formed on the insulating layer 142. In a plan view, the gate electrode 141 is located between the insulating layer 122S and the insulating layer 122D. The gate electrode 141 includes, for example, a laminate of sequentially stacked Ni, Pd, and Au films. The insulating layer 142 is an example of a fourth insulating layer.

[0034] Next, a method for manufacturing the semiconductor device 100 according to the first embodiment will be described. Figures 2 to 13 are cross-sectional views showing the method for manufacturing the semiconductor device according to the first embodiment.

[0035] First, as shown in Figure 2, a nitride semiconductor layer 110 is formed on the substrate 101, for example, by metal-organic chemical vapor deposition (MOCVD). In forming the nitride semiconductor layer 110, a buffer layer 111, a barrier layer 112, and a channel layer 113 are formed in order. Due to the difference in lattice constants between the channel layer 113 and the barrier layer 112, strain is generated, and this strain induces a piezoelectric charge at the interface between the two. As a result, a 2DEG is generated in the region of the channel layer 113 on the barrier layer 112 side, and the channel region 113c is formed.

[0036] Next, an insulating layer 121 is formed in contact with the surface 110A of the nitride semiconductor layer 110. The insulating layer 121 can be formed, for example, by a low-pressure CVD (LPCVD) method. The insulating layer 121 may also be formed continuously with the buffer layer 111, barrier layer 112, and channel layer 113, for example by a MOCVD method, without exposing the surface of the channel layer 113 to the atmosphere.

[0037] Next, as shown in Figure 3, a zinc oxide (ZnO) layer 151 is formed on the insulating layer 121. The ZnO layer 151 can be formed, for example, by sputtering. The ZnO layer 151 may also be formed by the sol-gel method, MOCVD method, or molecular beam epitaxy (MBE) method. Next, an aluminum oxide (Al2O3) layer 152 is formed on the ZnO layer 151. The Al2O3 layer 152 can be formed, for example, by plasma-enhanced CVD (PECVD) method. Next, a resist pattern 160 is formed on the Al2O3 layer 152. The resist pattern 160 has an opening 160S for the source and an opening 160D for the drain.

[0038] Next, as shown in Figure 4, the resist pattern 160 is used as a mask to etch the Al2O3 layer 152, the ZnO layer 151, and the insulating layer 121. This etching is reactive ion etching (RIE) using, for example, a fluorine-based gas or a chlorine-based gas. As a result, below the opening 160S, openings 152S, 151S, and 121S are formed in the Al2O3 layer 152, the ZnO layer 151, and the insulating layer 121, respectively. Also, below the opening 160D, openings 152D, 151D, and 121D are formed in the Al2O3 layer 152, the ZnO layer 151, and the insulating layer 121, respectively. Parts of the nitride semiconductor layer 110 are exposed through openings 152S, 151S, and 121S, and other parts of the nitride semiconductor layer 110 are exposed through openings 152D, 151D, and 121D.

[0039] Next, as shown in Figure 5, the resist pattern 160 is removed using a chemical solution to widen the openings 151S and 151D. As a result, the sidewall surface of opening 151S is recessed compared to the sidewall surfaces of openings 121S and 152S, and the sidewall surface of opening 151D is recessed compared to the sidewall surfaces of openings 121D and 152D.

[0040] Furthermore, the Al2O3 layer 152 on which openings 152S and 152D are formed, and the ZnO layer 151 on which openings 151S and 151D are formed, can function as masks during etching of the insulating layer 121. Therefore, the resist pattern 160 may be removed before etching of the Al2O3 layer 152. The Al2O3 layer 152 on which openings 152S and 152D are formed, and the ZnO layer 151 on which openings 151S and 151D are formed, are examples of masks. The combination of openings 151S and 152S and the combination of openings 151D and 152D are examples of first mask openings or second mask openings.

[0041] Next, as shown in Figure 6, an n-type GaN layer 131 is formed on the surfaces exposed from the openings 152S, 151S, and 121S of the nitride semiconductor layer 110, and on the surfaces exposed from the openings 152D, 151D, and 121D. The upper surface of the n-type GaN layer 131 may or may not be flush with the upper surface of the insulating layer 121. The n-type GaN layer 131 can be formed by, for example, sputtering, MOCVD, or MBE. In this case, the n-type GaN layer 131 is deposited not only on the nitride semiconductor layer 110 but also on the Al2O3 layer 152. For example, the concentration of the n-type dopant is 1 × 10⁻⁶. 17 cm -3 The above is the case, and the n-type dopant is either Si or Ge.

[0042] On the N-polarity surface of the nitride semiconductor layer 110, the n-type GaN layer 131 undergoes crystal growth using the N-polarity surface as the growth plane. Therefore, on the N-polarity surface of the nitride semiconductor layer 110, the surface of the n-type GaN layer 131 becomes the N-polarity surface, and the back surface becomes the Ga-polarity surface.

[0043] Next, as shown in Figure 7, an insulating layer 122 is formed on the surfaces exposed from the openings 152S, 151S, and 121S of the insulating layer 121 and the n-type GaN layer 131, and on the surfaces exposed from the openings 152D, 151D, and 121D. The insulating layer 122 is, for example, a silicon nitride (SiN) layer. The thickness of the insulating layer 122 is, for example, 20 nm to 50 nm. The insulating layer 122 is formed to cover the boundary line 124S between the n-type GaN layer 131S and the insulating layer 121, and the boundary line 124D between the n-type GaN layer 131D and the insulating layer 121. The insulating layer 122 can be formed, for example, by CVD or sputtering. At this time, the insulating layer 122 is also deposited on the n-type GaN layer 131 on top of the Al2O3 layer 152.

[0044] The n-type GaN layer 131 and the insulating layer 122 may be formed continuously using the same film deposition apparatus.

[0045] Next, as shown in Figure 8, the ZnO layer 151 is removed using an acidic solution. The acidic solution includes, for example, hydrochloric acid (HCl) or phosphoric acid (H3PO4). Along with the removal of the ZnO layer 151, the Al2O3 layer 152, the n-type GaN layer 131, and the insulating layer 122 on top of the ZnO layer 151 are also removed. As a result, the n-type GaN layer 131 remains in the openings 121S and 121D, the n-type GaN layer 131S is formed in the opening 121S, and the n-type GaN layer 131D is formed in the opening 121D. In addition, the insulating layer 122 remains on the insulating layer 121 and the n-type GaN layer 131S, and the insulating layer 122S is formed on the insulating layer 121 and the n-type GaN layer 131S, and the insulating layer 122D is formed on the insulating layer 121 and the n-type GaN layer 131D.

[0046] Next, as shown in Figure 9, photoresist 153 and photoresist 154 are applied in this order on insulating layer 121, insulating layer 122S, and insulating layer 122D. For example, the material of photoresist 153 is polymethylglutarimide (PMGI), and photoresist 154 is an i-line resist. Next, a source opening 154S and a drain opening 154D are formed in photoresist 154 by photolithography, and a source opening 153S and a drain opening 153D are formed in photoresist 153. Part of insulating layer 122S is exposed through openings 154S and 153S, and part of insulating layer 122D is exposed through openings 154D and 153D. For example, the lower end of opening 153S is in contact with the upper surface of insulating layer 122S, and the lower end of opening 153D is in contact with the upper surface of insulating layer 122D.

[0047] Next, as shown in Figure 10, source openings 123S are formed in the insulating layer 122S and drain openings 123D are formed in the insulating layer 122D by etching using photoresists 153 and 154 as masks. This etching is, for example, RIE using a fluorine-based gas. A portion of the n-type GaN layer 131S is exposed through opening 123S, and a portion of the n-type GaN layer 131D is exposed through opening 123D.

[0048] Next, as shown in Figure 11, a metal layer 132 is formed on the surfaces exposed from the openings 154S and 153S of the insulating layer 122S and the n-type GaN layer 131S, and on the surfaces exposed from the openings 154D and 153D of the insulating layer 122D and the n-type GaN layer 131D. The metal layer 132 can be formed by, for example, a vapor deposition method. In this case, the metal layer 132 is deposited not only on the insulating layer 122S, the n-type GaN layer 131S, the insulating layer 122D, and the n-type GaN layer 131D, but also on the photoresist 154. The metal layer 132 may include, for example, a laminate of sequentially stacked Ta films, Al films, and Ta films. The metal layer 132 may also include, for example, a laminate of sequentially stacked Ti films, Al films, and Ti films.

[0049] Next, as shown in Figure 12, photoresists 153 and 154 are removed. With the removal of photoresist 154, the metal layer 132 on top of the photoresist 154 is also removed. As a result, the metal layer 132 remains within the openings 153S and 153D. In other words, lift-off occurs. Subsequently, the metal layer 132 is alloyed by heat treatment. As a result, a source electrode 132S, which contacts the n-type GaN layer 131S through opening 123S, is formed on the insulating layer 122S, and a drain electrode 132D, which contacts the n-type GaN layer 131D through opening 123D, is formed on the insulating layer 122D. The source electrode 132S makes ohmic contact with the n-type GaN layer 131S, and the drain electrode 132D makes ohmic contact with the n-type GaN layer 131D.

[0050] Next, as shown in Figure 13, an insulating layer 142 covering the insulating layer 122S, source electrode 132S, insulating layer 122D, and drain electrode 132D is formed on the insulating layer 121. The insulating layer 142 can be formed by, for example, plasma CVD. Next, a gate electrode 141 is formed on the insulating layer 142. The gate electrode 141 is formed between the insulating layer 122S and the insulating layer 122D in a plan view. The gate electrode 141 includes, for example, a laminate of Ni film, Pd film, and Au film stacked in order. When forming the gate electrode 141, for example, a metal layer is deposited using a growth mask (not shown) with an opening formed in the region where the gate electrode 141 is to be formed, and then the growth mask is removed together with the metal layer (not shown) formed on it. In other words, lift-off is performed.

[0051] In this way, the semiconductor device 100 can be manufactured.

[0052] In the first embodiment, the n-type GaN layers 131S and 131D are covered with an insulating layer 122 before the removal of the mask ZnO layer 151 and Al2O3 layer 152. The portion of the insulating layer 122 that becomes insulating layer 122S is in contact with the boundary line 124S between the n-type GaN layer 131S and insulating layer 121, and covers the boundary line 124S between the n-type GaN layer 131S and insulating layer 121. The portion of the insulating layer 122 that becomes insulating layer 122D is in contact with the boundary line 124D between the n-type GaN layer 131D and insulating layer 121, and covers the boundary line 124D between the n-type GaN layer 131D and insulating layer 121. Therefore, the surfaces of the n-type GaN layers 131S and 131D are protected from the chemicals used to remove the ZnO layer 151 and Al2O3 layer 152, and damage to the surfaces of the n-type GaN layers 131S and 131D can be suppressed.

[0053] Furthermore, the insulating layers 122S and 122D are located away from the gate electrode 141 in a plan view perpendicular to the first main surface. For example, the gate electrode 141 is located between the insulating layer 122S and the insulating layer 122D in a plan view. Therefore, the distance between the gate electrode 141 and the nitride semiconductor layer 110 is less affected by the insulating layers 122S and 122D. Consequently, changes in gate controllability from a structure without insulating layers 122S and 122D can be suppressed.

[0054] In the first embodiment, the upper surfaces of the n-type GaN layers 131S and 131D are N-polarity surfaces, and the channel layer 113 is above the barrier layer 112. Therefore, the distance between the channel region 113c and the source electrode 132S and drain electrode 132D can be easily shortened, making it easier to achieve low resistance.

[0055] Furthermore, the gate electrode 141 is formed on the insulating layer 142 and is not in contact with the nitride semiconductor layer 110. Therefore, a so-called MIS structure can be formed.

[0056] (Second Embodiment) Next, a second embodiment will be described. The second embodiment relates to a semiconductor device including a GaN-based HEMT. Figure 14 is a cross-sectional view showing a semiconductor device according to the second embodiment.

[0057] As shown in Figure 14, the semiconductor device 200 according to the second embodiment mainly comprises a substrate 201, a nitride semiconductor layer 210, an insulating layer 121, an insulating layer 122S, an insulating layer 122D, an n-type GaN layer 231S, an n-type GaN layer 231D, a gate electrode 141, a source electrode 132S, a drain electrode 132D, and an insulating layer 142.

[0058] The substrate 201 is, for example, a growth substrate for GaN-based semiconductors, and in one example, a semi-insulating SiC substrate. When the substrate 201 is a SiC substrate, the surface of the substrate 201 is a silicon (Si) polar surface. When the surface of the substrate 201 is a Si polar surface, the nitride semiconductor layer 210 can be grown using the Ga polar surface as the growth surface.

[0059] The nitride semiconductor layer 210 has a channel layer 211, a barrier layer 212, and a cap layer 213. The nitride semiconductor layer 210 is an example of a first nitride semiconductor layer.

[0060] The channel layer 211 is, for example, a GaN layer. The thickness of the channel layer 211 is, for example, in the range of 200 nm or more and 2000 nm or less, and in one embodiment it is 1000 nm. A buffer layer may be present between the channel layer 211 and the substrate 201.

[0061] The barrier layer 212 is, for example, an AlGaN layer. The band gap of the barrier layer 212 is larger than the band gap of the channel layer 211. The thickness of the barrier layer 212 is, for example, in the range of 5 nm or more and 30 nm or less, and in one embodiment it is 15 nm. x Ga 1-x In the case of an N layer, its Al composition x is, for example, 0.15 to 0.35, and in one embodiment, it is 0.25. Due to the difference in their lattice constants, strain is generated between the channel layer 211 and the barrier layer 212, and this strain induces a piezoelectric charge at the interface between them. As a result, a 2DEG is generated in the region of the channel layer 211 on the barrier layer 212 side, and the channel region 211c is formed. Instead of the AlGaN layer, an InAlN layer or an InAlGaN layer may be used. Also, a spacer layer may be present between the channel layer 211 and the barrier layer 212. The spacer layer is, for example, an AlN layer. The thickness of the spacer layer is, for example, in the range of 0.5 nm to 3.0 nm, and in one embodiment, it is 1.0 nm.

[0062] The cap layer 213 is, for example, a GaN layer. The thickness of the cap layer 213 is, for example, in the range of 0 nm or more and 5 nm or less, and in one embodiment it is 2 nm. The surface of the cap layer 213 constitutes the surface 210A of the nitride semiconductor layer 210. Surface 210A is an example of a first main surface.

[0063] On the Si polar surface of the SiC substrate, the channel layer 211, barrier layer 212, and cap layer 213 undergo crystal growth with the Ga polar surface as the growth surface. Therefore, the front surfaces of the channel layer 211, barrier layer 212, and cap layer 213 become Ga polar surfaces, and the back surfaces of each become N polar surfaces.

[0064] Recesses 210S and 210D are formed in the nitride semiconductor layer 210. Recesses 210S and 210D are formed to a depth that penetrates the channel region 211c. In other words, with respect to the surface 210A of the nitride semiconductor layer 210, the depth of recesses 210S and 210D is greater than the depth of the channel region 211c. The bottom surfaces of recesses 210S and 210D may be located within the barrier layer 212.

[0065] The insulating layer 121 is in contact with the surface 210A of the nitride semiconductor layer 210. Openings 121S and 121D are formed in the insulating layer 121. Opening 121S is connected to recess 210S, and opening 121D is connected to recess 210D.

[0066] The n-type GaN layer 231S is formed on the nitride semiconductor layer 210 within the recess 210S and the opening 121S. The n-type GaN layer 231D is formed on the nitride semiconductor layer 210 within the recess 210D and the opening 121D. The n-type GaN layers 231S and 231D contain Ge or Si as n-type impurities. The n-type GaN layers 231S and 231D are examples of a second nitride semiconductor layer or a third nitride semiconductor layer.

[0067] The insulating layer 122S is formed on the n-type GaN layer 231S and the insulating layer 121. The insulating layer 122S is in contact with the boundary line 224S between the n-type GaN layer 231S and the insulating layer 121, and covers the boundary line 224S between the n-type GaN layer 231S and the insulating layer 121. The boundary line 224S is a line that constitutes the interface between the n-type GaN layer 231S and the insulating layer 121, and is located at the end of the interface that is away from the nitride semiconductor layer 210. The insulating layer 122S has an opening 123S in which a part of the n-type GaN layer 231S is exposed.

[0068] The insulating layer 122D is formed on the n-type GaN layer 231D and the insulating layer 121. The insulating layer 122D is separated from the insulating layer 122S. The insulating layer 122D is in contact with the boundary line 224D between the n-type GaN layer 231D and the insulating layer 121, and covers the boundary line 224D between the n-type GaN layer 231D and the insulating layer 121. The boundary line 224D is a line that constitutes the interface between the n-type GaN layer 231D and the insulating layer 121, and is located at the end of the interface that is away from the nitride semiconductor layer 210. The insulating layer 122D has an opening 123D in which a part of the n-type GaN layer 231D is exposed.

[0069] The source electrode 132S is formed on the insulating layer 122S, and the drain electrode 132D is formed on the insulating layer 122D. The source electrode 132S is in contact with the n-type GaN layer 231S through the opening 123S, and the drain electrode 132D is in contact with the n-type GaN layer 231D through the opening 123D. The source electrode 132S is in ohmic contact with the n-type GaN layer 231S, and the drain electrode 132D is in ohmic contact with the n-type GaN layer 231D.

[0070] The insulating layer 142 is formed on the insulating layer 121. The insulating layer 142 covers the insulating layer 122S, the source electrode 132S, the insulating layer 122D, and the drain electrode 132D. In a plan view, an opening 121G is formed in the insulating layers 142 and 121 between the insulating layer 122S and the insulating layer 122D. A portion of the nitride semiconductor layer 210 is exposed through the opening 121G. The gate electrode 141 is formed on the insulating layer 142 so as to be in contact with the nitride semiconductor layer 210 through the opening 121G. The gate electrode 141 makes Schottky contact with the nitride semiconductor layer 210. The opening 121G is an example of a fifth opening.

[0071] The other configurations are the same as in the first embodiment.

[0072] Next, a method for manufacturing the semiconductor device 200 according to the second embodiment will be described. Figures 15 to 26 are cross-sectional views showing the method for manufacturing the semiconductor device according to the second embodiment.

[0073] First, as shown in Figure 15, a nitride semiconductor layer 210 is formed on the substrate 201, for example, by the MOCVD method. In the formation of the nitride semiconductor layer 210, a channel layer 211, a barrier layer 212, and a cap layer 213 are formed in order. Due to the difference in lattice constants between the channel layer 211 and the barrier layer 212, strain is generated, and this strain induces a piezoelectric charge at the interface between the two. As a result, a 2DEG is generated in the region of the channel layer 211 on the barrier layer 212 side, and the channel region 211c is formed.

[0074] Next, an insulating layer 121 is formed in contact with the surface 210A of the nitride semiconductor layer 210. The insulating layer 121 can be formed, for example, by a reduced-pressure CVD method. The insulating layer 121 may also be formed continuously with the channel layer 211, barrier layer 212 and cap layer 213, for example by a MOCVD method, without exposing the surface of the cap layer 213 to the atmosphere.

[0075] Next, as shown in Figure 16, a zinc oxide (ZnO) layer 151 is formed on the insulating layer 121. Then, an Al2O3 layer 152 is formed on the ZnO layer 151. Next, a resist pattern 160 is formed on the Al2O3 layer 152. The resist pattern 160 has an opening 160S for the source and an opening 160D for the drain.

[0076] Next, as shown in Figure 17, the resist pattern 160 is used as a mask to etch the Al2O3 layer 152, the ZnO layer 151, and the insulating layer 121. As a result, below the opening 160S, openings 152S, 151S, and 121S are formed in the Al2O3 layer 152, the ZnO layer 151, and the insulating layer 121, respectively. Also, below the opening 160D, openings 152D, 151D, and 121D are formed in the Al2O3 layer 152, the ZnO layer 151, and the insulating layer 121, respectively. Parts of the nitride semiconductor layer 210 are exposed through openings 152S, 151S, and 121S, and other parts of the nitride semiconductor layer 210 are exposed through openings 152D, 151D, and 121D.

[0077] Next, the nitride semiconductor layer 210 is etched using the resist pattern 160 as a mask to form recesses 210S connected to openings 152S, 151S, and 121S, and recesses 210D connected to openings 152D, 151D, and 121D in the nitride semiconductor layer 210. This etching is performed, for example, by RIE using a chlorine-based gas. This etching may also be performed in a mixed atmosphere containing hydrogen (H2) and ammonia (NH3). For example, the recesses 210S and 210D are formed to a depth that penetrates the channel region 211c. The recesses 210S and 210D may also be formed to a depth that does not reach the channel region 211c.

[0078] Similar to the first embodiment, the Al2O3 layer 152 with openings 152S and 152D and the ZnO layer 151 with openings 151S and 151D can function as masks during etching of the insulating layer 121. Therefore, the resist pattern 160 may be removed before etching the Al2O3 layer 152. The Al2O3 layer 152 with openings 152S and 152D and the ZnO layer 151 with openings 151S and 151D are examples of masks. The combination of openings 151S and 152S and the combination of openings 151D and 152D are examples of first mask openings or second mask openings.

[0079] Next, as shown in Figure 18, the resist pattern 160 is removed using a chemical solution, similar to the first embodiment, and the openings 151S and 152D are widened.

[0080] Next, as shown in Figure 19, an n-type GaN layer 231 is formed on the surfaces exposed from the openings 152S, 151S, and 121S of the nitride semiconductor layer 210, and on the surfaces exposed from the openings 152D, 151D, and 121D. The upper surface of the n-type GaN layer 231 may or may not be flush with the upper surface of the insulating layer 121. The n-type GaN layer 231 can be formed by, for example, sputtering, MOCVD, or MBE. In this case, the n-type GaN layer 231 is deposited not only on the nitride semiconductor layer 210 but also on the Al2O3 layer 152. For example, the concentration of the n-type dopant is 1 × 10⁻⁶. 17 cm -3The above is the case, and the n-type dopant is either Si or Ge.

[0081] On the Ga polarity surface of the nitride semiconductor layer 210, the n-type GaN layer 231 undergoes crystal growth using the Ga polarity surface as the growth plane. Therefore, on the Ga polarity surface of the nitride semiconductor layer 210, the surface of the n-type GaN layer 231 becomes the Ga polarity surface, and the back surface becomes the N polarity surface.

[0082] Next, as shown in Figure 20, an insulating layer 122 is formed on the surfaces exposed from the openings 152S, 151S, and 121S of the insulating layer 121 and the n-type GaN layer 231, and on the surfaces exposed from the openings 152D, 151D, and 121D. The insulating layer 122 is formed to cover the boundary line 224S between the n-type GaN layer 231S and the insulating layer 121, and the boundary line 224D between the n-type GaN layer 231D and the insulating layer 121. At this time, the insulating layer 122 is also deposited on the n-type GaN layer 131 on top of the Al2O3 layer 152.

[0083] The n-type GaN layer 231 and the insulating layer 122 may be formed continuously using the same film deposition apparatus.

[0084] Next, as shown in Figure 21, the ZnO layer 151 is removed using an acidic solution. Along with the removal of the ZnO layer 151, the Al2O3 layer 152, the n-type GaN layer 231, and the insulating layer 122 on top of the ZnO layer 151 are also removed. As a result, the n-type GaN layer 231 remains in the opening 121S, the recess 210S, the opening 121D, and the recess 210D, the n-type GaN layer 231S is formed in the opening 121S and the recess 210S, and the n-type GaN layer 231D is formed in the opening 121D and the recess 210D. In addition, the insulating layer 122 remains on the insulating layer 121 and the n-type GaN layer 231S, and the insulating layer 122S is formed on the insulating layer 121 and the n-type GaN layer 231S, and the insulating layer 122D is formed on the insulating layer 121 and the n-type GaN layer 231D.

[0085] Next, as shown in Figure 22, photoresist 153 and photoresist 154 are applied in the same order as in the first embodiment, on insulating layer 121, insulating layer 122S, and insulating layer 122D. Next, source opening 154S and drain opening 154D are formed in photoresist 154, and source opening 153S and drain opening 153D are formed in photoresist 153.

[0086] Next, as shown in Figure 23, source openings 123S are formed in the insulating layer 122S and drain openings 123D are formed in the insulating layer 122D by etching using photoresists 153 and 154 as masks. This etching is, for example, RIE using a fluorine-based gas. A portion of the n-type GaN layer 231S is exposed through opening 123S, and a portion of the n-type GaN layer 231D is exposed through opening 123D.

[0087] Next, as shown in Figure 24, similar to the first embodiment, a metal layer 132 is formed on the surfaces exposed from the openings 154S and 153S of the insulating layer 122S and the n-type GaN layer 131S, and on the surfaces exposed from the openings 154D and 153D of the insulating layer 122D and the n-type GaN layer 131D. At this time, the metal layer 132 is deposited not only on the insulating layer 122S, the n-type GaN layer 131S, the insulating layer 122D, and the n-type GaN layer 131D, but also on the photoresist 154.

[0088] Next, as shown in Figure 25, photoresists 153 and 154 are removed. With the removal of photoresist 154, the metal layer 132 on top of the photoresist 154 is also removed. As a result, the metal layer 132 remains within the openings 153S and 153D. In other words, lift-off occurs. Subsequently, the metal layer 132 is alloyed by heat treatment. As a result, a source electrode 132S, which contacts the n-type GaN layer 231S through opening 123S, is formed on the insulating layer 122S, and a drain electrode 132D, which contacts the n-type GaN layer 231D through opening 123D, is formed on the insulating layer 122D. The source electrode 132S makes ohmic contact with the n-type GaN layer 231S, and the drain electrode 132D makes ohmic contact with the n-type GaN layer 231D.

[0089] Next, as shown in Figure 26, an insulating layer 142 is formed on the insulating layer 121, similar to the first embodiment. Then, an opening 121G is formed in the insulating layers 142 and 121 between the insulating layer 122S and the insulating layer 122D in a plan view. A portion of the nitride semiconductor layer 210 is exposed through the opening 121G. Next, a gate electrode 141 is formed that contacts the nitride semiconductor layer 210 through the opening 121G. The gate electrode 141 can be formed in the same manner as in the first embodiment.

[0090] In this way, the semiconductor device 200 can be manufactured.

[0091] In the semiconductor device 200 according to the second embodiment, the n-type GaN layers 231S and 231D are covered by the insulating layer 122 before the removal of the mask ZnO layer 151 and Al2O3 layer 152. The portion of the insulating layer 122 that becomes insulating layer 122S is in contact with the boundary line 224S between the n-type GaN layer 231S and insulating layer 121, and covers the boundary line 224S between the n-type GaN layer 231S and insulating layer 121. The portion of the insulating layer 122 that becomes insulating layer 122D is in contact with the boundary line 224D between the n-type GaN layer 231D and insulating layer 121, and covers the boundary line 224D between the n-type GaN layer 231D and insulating layer 121. Therefore, the surfaces of the n-type GaN layers 231S and 231D are protected from the chemicals used to remove the ZnO layer 151 and Al2O3 layer 152, and damage to the surfaces of the n-type GaN layers 231S and 231D can be suppressed.

[0092] Furthermore, similar to the first embodiment, the distance between the gate electrode 141 and the nitride semiconductor layer 210 is less affected by the insulating layers 122S and 122D. Therefore, changes in gate controllability from a structure without insulating layers 122S and 122D can be suppressed.

[0093] In the second embodiment, the upper surfaces of the n-type GaN layers 231S and 231D are Ga polarity surfaces. Therefore, good etching resistance can be easily obtained on the upper surfaces of the n-type GaN layers 231S and 231D.

[0094] Furthermore, the gate electrode 141 is in contact with the nitride semiconductor layer 210 through the opening 121G. Therefore, a so-called MES structure can be formed.

[0095] Although embodiments have been described in detail above, the invention is not limited to any particular embodiment, and various modifications and changes are possible within the scope described in the claims. [Explanation of symbols]

[0096] 100, 200: Semiconductor equipment 101, 201: Circuit board 110, 210: Nitride semiconductor layer 110A, 210A: Surface 111: Buffer layer 112, 212: Barrier layer 113, 211: Channel layer 113c, 211c: Channel region 121, 122, 122D, 122S, 142: Insulating layer 121D, 121G, 121S, 123D, 123S, 151D, 151S, 152D, 152S, 153D, 153S, 154D, 154S, 160D, 160S: Aperture 124D, 124S, 224D, 224S: Border 131, 131D, 131S, 231, 231D, 231S: n-type GaN layer 132: Metal layer 132D: Drain electrode 132S: Source electrode 141: Gate Shutdown 151: ZnO layer 152:Al2O3 layer 153, 154: Photoresist 160: Resist Pattern 210D, 210S: Recess 213: Cap layer

Claims

1. A step of forming a first insulating layer on a first nitride semiconductor layer having a first main surface, A step of forming a mask having a first mask opening on the first insulating layer in which a part of the first insulating layer is exposed, A step of forming a first opening through the first mask opening in which a portion of the first nitride semiconductor layer is exposed in the first insulating layer, A step of forming a second nitride semiconductor layer on the first nitride semiconductor layer inside the first opening through the first mask opening, A step of forming a second insulating layer that covers the boundary between the second nitride semiconductor layer and the first insulating layer through the first mask opening, The process of removing the mask after the process of forming the second insulating layer, A step of forming a second opening in the second insulating layer in which a portion of the second nitride semiconductor layer is exposed, A step of forming a first electrode on the second insulating layer that contacts the second nitride semiconductor layer through the second opening, A step of forming a gate electrode above the first nitride semiconductor layer, which is separated from the second insulating layer in a plan view perpendicular to the first main surface, A method for manufacturing a semiconductor device having [a certain feature].

2. The mask includes a second mask opening in which another portion of the first insulating layer is exposed. Simultaneously with the step of forming the first opening, a third opening is formed through the second mask opening, in which another portion of the first nitride semiconductor layer is exposed in the first insulating layer. Simultaneously with the step of forming the second nitride semiconductor layer, a step of forming a third nitride semiconductor layer on the first nitride semiconductor layer inside the third opening through the second mask opening, Simultaneously with the step of forming the second insulating layer, a third insulating layer is formed through the second mask opening to cover the boundary between the third nitride semiconductor layer and the first insulating layer. Simultaneously with the step of forming the second opening, a step is made to form a fourth opening in which a portion of the third nitride semiconductor layer is exposed in the third insulating layer, Simultaneously with the step of forming the first electrode, a step of forming a second electrode on the third insulating layer that contacts the third nitride semiconductor layer through the fourth opening, A method for manufacturing a semiconductor device according to claim 1, having the following characteristics:

3. The method for manufacturing a semiconductor device according to claim 2, wherein, in the plan view, the gate electrode is formed between the second insulating layer and the third insulating layer.

4. Between the step of forming the first electrode and the step of forming the gate electrode, there is a step of forming a fourth insulating layer covering the first electrode on the first insulating layer, The method for manufacturing a semiconductor device according to claim 2 or 3, wherein the gate electrode is formed on the fourth insulating layer.

5. The method for manufacturing a semiconductor device according to claim 4, wherein the upper surface of the second nitride semiconductor layer is an N-polarity surface.

6. Between the step of forming the fourth insulating layer and the step of forming the gate electrode, there is a step of forming a fifth opening in the fourth insulating layer and the first insulating layer. The method for manufacturing a semiconductor device according to claim 4, wherein the gate electrode is formed to contact the first nitride semiconductor layer through the fifth opening.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the upper surface of the second nitride semiconductor layer is a Ga polarity surface.

8. A first nitride semiconductor layer having a first main surface, A first insulating layer provided on the first nitride semiconductor layer, having a first opening in which a part of the first nitride semiconductor layer is exposed, A second nitride semiconductor layer is provided on the first nitride semiconductor layer inside the first opening, A second insulating layer that covers the boundary between the second nitride semiconductor layer and the first insulating layer, and has a second opening through which a part of the second nitride semiconductor layer is exposed, An electrode provided on the second insulating layer and in contact with the second nitride semiconductor layer through the second opening, A gate electrode is provided above the first nitride semiconductor layer and, in a plan view perpendicular to the first main surface, is separated from the second insulating layer, Semiconductor device.

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