Semiconductor device and method for manufacturing the same

Abstract

To provide a semiconductor device that can have a gate resistance easily built in.SOLUTION: A semiconductor device comprises: a drift layer 2 of a first conductivity type; base regions 3a to 3d of a second conductivity type which are provided on a top-surface side of the drift layer 2; main regions 4a to 4d of the first conductivity type which are provided on the top-surface side of the drift layer 2; a gate electrode 7b which is provided on the top-surface side of the drift layer 2, and embedded in a gate trench 10b extending in one direction over both ends of an active part 101 with a gate insulation film 6 interposed; a gate runner 21 which is provided on an outer-periphery side of the active part 101 and electrically connected to the gate electrode 7b; a gate pad 20 which is provided inside the gate runner 21; and resistance layers 7d to 7g which are provided on the top-surface side of the drift layer 2, embedded in the trenches 10d to 10g extending in the one direction over both ends of the active part 101 with the insulation film 6 interposed, and electrically connected between a gate pad 20 and gate runner 21.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] This disclosure relates to semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device having an IGBT element with a trench-type gate electrode and a trench-type built-in gate resistor which is a resistive element, wherein the resistance value is changed by connecting multiple built-in gate resistors in parallel and adjusting their length. Patent Document 2 discloses a double trench structure in which the source trench is deeper than the gate trench. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2008-294301 [Patent Document 2] Japanese Patent Publication No. 2019-161200 [Overview of the project] [Problems that the invention aims to solve]

[0004] In trench gate type semiconductor devices, forming a gate resistor on the upper surface of the substrate via an insulating film increases the number of steps required, making it difficult to incorporate the gate resistor internally.

[0005] In view of the above-mentioned problems, this disclosure aims to provide a semiconductor device and a method for manufacturing the same that can easily incorporate a gate resistor. [Means for solving the problem]

[0006] To achieve the above objective, one aspect of the present disclosure is a semiconductor device comprising: an active portion and a first conductivity type drift layer provided at the terminal portion surrounding the active portion; a second conductivity type base region provided on the upper side of the drift layer of the active portion; a first conductivity type main region provided on the upper side of the drift layer of the active portion in contact with the base region; a gate electrode embedded via a gate insulating film in a gate trench provided on the upper side of the drift layer of the active portion and extending in one direction across both ends of the active portion; a gate runner provided on the outer periphery of the active portion and electrically connected to the gate electrode; a gate pad provided inside the gate runner of the active portion; and a resistance layer provided on the upper side of the drift layer of the active portion and embedded via an insulating film in a resistance trench extending in one direction across both ends of the active portion, and electrically connected between the gate pad and the gate runner.

[0007] Another aspect of this disclosure is a method for manufacturing a semiconductor device, comprising the steps of: forming a drift layer of a first conductivity type on an active portion and on the terminal portion surrounding the active portion; forming a base region of a second conductivity type on the upper side of the drift layer of the active portion; forming a main region of a first conductivity type on the upper side of the drift layer of the active portion, in contact with the base region; forming a gate trench on the upper side of the drift layer of the active portion, extending in one direction across both ends of the active portion; embedding a gate electrode in the gate trench via a gate insulating film; forming a gate runner on the outer periphery of the active portion, electrically connected to the gate electrode; forming a gate pad inside the gate runner of the active portion; forming a resistive trench on the upper side of the drift layer of the active portion, extending in one direction across both ends of the active portion; and embedding a resistive layer in the resistive trench via an insulating film, electrically connected between the gate pad and the gate runner. [Effects of the Invention]

[0008] According to this disclosure, it is possible to provide a semiconductor device and a method for manufacturing the same that can easily incorporate a gate resistor. [Brief explanation of the drawing]

[0009] [Figure 1] It is a schematic plan view showing an example of a semiconductor device according to the first embodiment. [Figure 2] It is a schematic plan view obtained by enlarging the region A in FIG. 1. [Figure 3] It is a schematic cross-sectional view taken along the line A-A' in FIG. 2. [Figure 4] It is a schematic cross-sectional view taken along the line B-B' in FIG. 2. [Figure 5] It is a schematic cross-sectional view taken along the line C-C' in FIG. 2. [Figure 6] It is a schematic view showing an example of a semiconductor module according to the first embodiment. [Figure 7] It is a schematic plan view showing a semiconductor device according to a comparative example. [Figure 8] It is a schematic cross-sectional view for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 9] It is a cross-sectional schematic view following FIG. 8 for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 10] It is a cross-sectional schematic view following FIG. 9 for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 11] It is a cross-sectional schematic view following FIG. 10 for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 12] It is a cross-sectional schematic view following FIG. 11 for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 13] It is a cross-sectional schematic view following FIG. 12 for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 14] It is a cross-sectional schematic view following FIG. 13 for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 15] It is a cross-sectional schematic view following FIG. 14 for explaining an example of a method for manufacturing a semiconductor device according to the first embodiment. [Figure 16] It is a schematic cross-sectional view showing an example of a semiconductor device according to the second embodiment. [Figure 17]This is a schematic cross-sectional view showing an example of a semiconductor device according to the third embodiment. [Figure 18] This is a schematic cross-sectional view showing an example of a semiconductor device according to the fourth embodiment. [Figure 19] This is a schematic cross-sectional view showing an example of a semiconductor device according to the fifth embodiment. [Figure 20] This is a schematic cross-sectional view showing an example of a semiconductor device according to the sixth embodiment. [Figure 21] This is a schematic cross-sectional view showing an example of a semiconductor device according to the seventh embodiment. [Figure 22] This is a schematic cross-sectional view showing an example of a semiconductor device according to the 8th embodiment. [Figure 23] This is a schematic plan view showing an example of a semiconductor device according to the ninth embodiment. [Figure 24] This is a schematic plan view showing an example of a semiconductor device according to the 10th embodiment. [Modes for carrying out the invention]

[0010] The first to tenth embodiments of this disclosure will be described below with reference to the drawings. In the drawings, identical or similar parts are denoted by the same or similar reference numerals, and redundant explanations are omitted. However, the drawings are schematic, and the relationship between thickness and planar dimensions, the ratio of the thickness of each layer, etc., may differ from the actual ones. Furthermore, there may be parts where the dimensional relationships and ratios differ between drawings. In addition, the first to tenth embodiments shown below are illustrative examples of devices and methods for realizing the technical concept of this disclosure, and the technical concept of this disclosure does not specify the materials, shapes, structures, arrangements, etc. of the components as described below.

[0011] In this specification, the source region of a MOS transistor, such as a metal-oxide-semiconductor field-effect transistor (MOSFET), is "one main region (first main region)" that can be selected as the emitter region of an insulated-gate bipolar transistor (IGBT). In a thyristor, such as a MOS-controlled electrostatic induction thyristor (SI thyristor), "one main region" can be selected as the cathode region. The drain region of a MOS transistor is "the other main region (second main region)" of the semiconductor device, which can be selected as the collector region in the case of an IGBT, or as the anode region in the case of a thyristor. In this specification, when simply referred to as "main region," it means either the first main region or the second main region, which is reasonable according to the common technical knowledge of those skilled in the art.

[0012] Furthermore, the definitions of directions such as up and down in the following explanation are merely for explanatory convenience and do not limit the technical concept of this disclosure. For example, if an object is rotated 90° and observed, up and down will be converted to left and right, and if it is rotated 180° and observed, up and down will be inverted and read. Also, "top surface" may be read as "front surface," and "bottom surface" may be read as "back surface."

[0013] Furthermore, the following explanation uses the case where the first conductivity type is n-type and the second conductivity type is p-type as an example. However, it is also acceptable to choose the conductivity types in the reverse relationship, with the first conductivity type being p-type and the second conductivity type being n-type. The + and - attached to n and p indicate semiconductor regions with relatively higher or lower impurity concentrations compared to semiconductor regions without + and - markings. However, even if two semiconductor regions are marked with the same n, this does not mean that the impurity concentrations in each semiconductor region are exactly the same.

[0014] (First Embodiment) <Structure of a semiconductor device> As shown in Figure 1, the semiconductor device (semiconductor chip) according to the first embodiment includes an active portion 101 containing an active element and a termination portion 102 provided around the active portion 101 and having a voltage-resistant structure. The active portion 101 has a rectangular planar pattern. On the outer periphery of the active portion 101 are gate runners (「 Gate finger It is also called A gate runner 21 is provided. The gate runner 21 has a frame-shaped planar pattern. The gate runner 21 is electrically connected to the gate electrode of the active element included in the active part 101.

[0015] A gate pad 20 is provided in part of the active section 101. A bonding wire can be connected to the gate pad 20, and a gate drive circuit is connected via the bonding wire. An internal resistor 100 is provided between the gate pad 20 and the gate runner 21. The gate pad 20 and the gate runner 21 are electrically connected via the internal resistor 100.

[0016] Figure 2 shows an enlarged schematic plan view of region A surrounding the built-in resistor 100 shown in Figure 1. In Figure 2, the trenches 10a to 10i included in the semiconductor device according to the first embodiment are schematically shown with dashed lines. The trenches 10a to 10i have a stripe-like planar pattern that extends in one direction (left-right direction in Figure 2) across both ends of the active portion 101, parallel to each other. The widths of the trenches 10a to 10i are approximately the same, and the spacing between the trenches 10a to 10i is approximately the same. The positions of both ends of the trenches 10a to 10i in the longitudinal direction coincide with the positions of the ends of the outer circumference of the active portion 101. The semiconductor device according to the first embodiment includes a number of trenches similar to the trenches 10a to 10i across the entire area of ​​the active portion 101.

[0017] Figure 3 shows a schematic cross-sectional view of line AA' in Figure 2. As shown in Figure 3, the semiconductor device according to the first embodiment has a first conductivity type (n) provided across the active portion 101 and the terminal portion 102. - It comprises a drift layer 2 of type (type). The drift layer 2 is composed of an epitaxial growth layer made of silicon carbide (SiC).

[0018] Figure 3 illustrates a case where the active section 101 includes a trench-gate metal-oxide-semiconductor field-effect transistor (MOSFET) as the active element. In the active section 101, second conductivity type (p-type) base regions 3a to 3d are selectively provided on the upper part of the drift layer 2. On the upper surface side of the base regions 3a to 3d, n is provided in contact with the base regions 3a to 3d. + The first main domain (source domain) 4a to 4d of the type is selectively provided.

[0019] Trenches (source trenches) 10a and 10c, and a trench (gate trench) 10b sandwiched between the source trenches 10a and 10c are provided extending from the upper surface of the drift layer 2 in the depth direction which is the normal direction to the upper surface of the drift layer 2. That is, the semiconductor device according to the first embodiment has a double trench structure having a gate trench 10b and source trenches 10a and 10c. It is also possible to have a trench-gate type structure that has a gate trench 10b but no source trenches 10a and 10c. In Figure 3, only a part of the active part 101 is shown, but in the active part 101, the same unit structure is repeatedly provided with source trenches 10a and gate trenches 10b as the unit structure.

[0020] The depth d1 of source trenches 10a and 10c is deeper than the depth d2 of gate trench 10b. The depth d1 of source trenches 10a and 10c may be approximately the same as the depth d2 of gate trench 10b. The width w1 of source trenches 10a and 10c is approximately the same as the width w2 of gate trench 10b. The width w1 of source trenches 10a and 10c may be different from the width w2 of gate trench 10b. Source trenches 10a and 10c are spaced apart from gate trench 10b by a distance s1.

[0021] Source region 4a and base region 3a are located in the mesa on the left side of source trench 10a. Here, "mesa" is defined as the portion of drift layer 2 sandwiched between adjacent trenches and above the bottom surface of the trench. Source region 4b and base region 3b are located in the mesa between source trench 10a and gate trench 10b. Source region 4c and base region 3c are located in the mesa between gate trench 10b and source trench 10c. Source region 4d and base region 3d are located in the mesa on the right side of source trench 10c.

[0022] The source region 4b and base region 3b are in contact with the left side of the gate trench 10b. The source region 4c and base region 3c are in contact with the right side of the gate trench 10b. An insulating film 6, which is a gate insulating film, is provided along the bottom surface and both sides of the gate trench 10b. A gate electrode 7b is embedded inside the gate trench 10b via the insulating film 6. The insulating film 6 and gate electrode 7b embedded in the gate trench 10b constitute an insulated gate electrode structure (6,7b). The insulated gate electrode structure (6,7b) controls the surface potential of the base regions 3b and 3c in contact with the sides of the gate trench 10b.

[0023] As the insulating film 6, in addition to silicon oxide film (SiO2 film), any single layer film of any one of the following films can be used: silicon oxynitride film (SiON film), strontium oxide film (SrO film), silicon nitride (Si3N4 film), aluminum oxide film (Al2O3 film), magnesium oxide film (MgO film), yttrium oxide film (Y2O3 film), hafnium oxide film (HfO2 film), zirconium oxide film (ZrO2 film), tantalum oxide film (Ta2O5 film), or bismuth oxide film (Bi2O3 film), or a composite film made by stacking multiple of these films.

[0024] As the material for the gate electrode 7b, for example, a polysilicon layer (doped polysilicon layer) with high impurity concentrations of n-type impurities such as phosphorus (P) or p-type impurities such as boron (B), or a high-melting-point metal such as titanium (Ti) or tungsten (W) can be used. When the gate electrode 7b is made of a p-type polysilicon layer, the gate threshold voltage can be increased. When the gate electrode 7b is made of an n-type polysilicon layer, the switching operation can be made faster.

[0025] In the cross-sectional view of Figure 3, the entire circumference of the gate electrode 7b, including its bottom surface, both sides, and top surface, is covered with an insulating film 6. An interlayer insulating film 8 is provided on the top side of the gate electrode 7b via the insulating film 6. The gate electrode 7b is electrically connected to the gate runner 21 via contact holes (gate contact holes) provided in the insulating film 6 and the interlayer insulating film 8 on the near or far side of the page in Figure 3.

[0026] As the interlayer insulating film 8, for example, a silicon oxide film doped with boron (B) and phosphorus (P) (BPSG film) can be used. The interlayer insulating film 8 may also be a silicon oxide film doped with phosphorus (P) (PSG film), an undoped silicon oxide film that does not contain phosphorus (P) or boron (B) and is called "NSG", a silicon oxide film doped with boron (B) (BSG film), a silicon nitride film (Si3N4 film), etc., and a multilayer film of these may also be used.

[0027] In the drift layer 2, p is placed in contact with the lower and side surfaces of source trenches 10a and 10c. + A type of electric field relaxation region 5a, 5b is provided. The impurity concentration in the electric field relaxation regions 5a, 5b is higher than the impurity concentration in the base regions 3a to 3d. The electric field relaxation regions 5a, 5b have the function of mitigating electric field concentration in the gate insulating film 6 at the bottom of the gate trench 10b and protecting the gate insulating film 6 at the bottom of the gate trench 10b. The electric field relaxation regions 5a, 5b can be formed on the side and bottom surfaces of the source trenches 10a, 10c by ion implantation after the source trenches 10a, 10c have been formed.

[0028] The source region 4a and base region 3a are in contact with the left side of source trench 10a via the field relaxation region 5a. The source region 4b and base region 3b are in contact with the right side of source trench 10a via the field relaxation region 5a. The source region 4c and base region 3c are in contact with the left side of source trench 10c via the field relaxation region 5b. The source region 4d and base region 3d are in contact with the right side of source trench 10b via the field relaxation region 5b.

[0029] An insulating film 6 is provided along the bottom surface and both sides of the source trenches 10a and 10c. Conductive layers 7a and 7c are embedded inside the source trenches 10a and 10c via the insulating film 6. The conductive layers 7a and 7c are made of the same material as the gate electrode 7b, and are formed of polysilicon layers with high impurity concentrations of n-type or p-type impurities. The entire circumference of the conductive layers 7a and 7c, including the bottom surface, both sides, and top surface, may be covered with the insulating film 6. In this case, the conductive layers 7a and 7c will be at a floating potential. Alternatively, contact holes may be provided in the insulating film 6 to connect the conductive layers 7a and 7c to the source electrode 28. In this case, the conductive layers 7a and 7c will be at the same potential as the source electrode 28.

[0030] A first main electrode (source electrode) 28 is provided on the upper surface of the conductive layers 7a and 7c via an insulating film 6. The source electrode 28 is connected to the source regions 4a to 4d and the electric field relaxation regions 5a and 5b via contact holes (source contact holes) in the interlayer insulating film 8. The source electrode 28 can be made of, for example, an aluminum (Al) film or an aluminum-silicon (Al-Si) film. Between the upper surface of the source regions 4a to 4d and the electric field relaxation regions 5a and 5b and the source electrode 28, nickel silicide (NiSi) is provided to make ohmic contact with the source regions 4a to 4d and the electric field relaxation regions 5a and 5b. x A silicide layer made of the like, or a barrier metal layer made of titanium nitride (TiN) or titanium (Ti), may be provided.

[0031] On the lower side of drift layer 2, n has a higher impurity concentration than drift layer 2.+ A second main region (drain region) 1 of the type is provided. The drain region 1 is made of a semiconductor substrate made of SiC.

[0032] A second main electrode (drain electrode) 11 is provided on the lower side of the drain region 1. For the drain electrode 11, a single layer of gold (Au), or a metal film laminated in the order of titanium (Ti), nickel (Ni), and Au can be used, and a metal film of molybdenum (Mo), tungsten (W), etc. may be laminated as the bottom layer. Furthermore, nickel silicide (NiSi) may be placed between the drain region 1 and the drain electrode 11. x A silicide layer consisting of the following may be provided.

[0033] On the outer periphery of the source trench 10c of the active section 101, multiple trenches (resistive trenches) 10d to 10g are provided on the upper part of the drift layer 2. The resistive trenches 10d to 10g do not function as active elements, and a portion of the resistive trenches 10d to 10g constitutes the built-in resistive section 100 shown in Figure 2. Although Figure 3 illustrates the case where four resistive trenches 10d to 10g are provided, the number of resistive trenches is not limited, and there may be one to three resistive trenches, or five or more resistive trenches.

[0034] The depth d3 of the resistive trenches 10d to 10g is deeper than the depth d2 of the gate trench 10b and approximately the same as the depth d1 of the source trenches 10a and 10c. However, the depth d3 of the resistive trenches 10d to 10g may differ from the depth d1 of the source trenches 10a and 10c. Also, the depth d3 of the resistive trenches 10d to 10g may be shallower than the depth d1 of the source trenches 10a and 10c and approximately the same as the depth d2 of the gate trench 10b.

[0035] The width w3 of the resistive trenches 10d to 10g is approximately the same as the width w1 of the source trenches 10a and 10c and the width w2 of the gate trench 10b. However, the width w3 of the resistive trenches 10d to 10g may differ from the width w1 of the source trenches 10a and 10c and the width w2 of the gate trench 10b. The spacing s2 between the resistive trenches 10d to 10g is approximately the same as the spacing s1 between the source trenches 10a and 10c and the gate trench 10b. However, the spacing s2 between the resistive trenches 10d to 10g may differ from the spacing s1 between the source trenches 10a and 10c and the gate trench 10b.

[0036] On the upper part of the drift layer 2, so as to be in contact with the lower surface and both sides of the resistive trenches 10d to 10g, p + A type of electric field relaxation region 5c is provided. In the cross-sectional view of Figure 3, the electric field relaxation region 5c has a meandering cross-sectional shape extending from the left side of the resistive trench 10d to the right side of the resistive trench 10g.

[0037] Resistive layers 7d to 7g are embedded in the resistive trenches 10d to 10g via an insulating film 6. The resistive layers 7d to 7g are made of the same material as the gate electrode 7b and conductive layers 7a and 7c, and are formed of polysilicon layers with high impurity concentrations of n-type or p-type impurities, for example. The entire circumference of the resistive layers 7d to 7g, including the bottom surface, both sides, and top surface, is covered with the insulating film 6. The position of the upper end of the resistive layers 7d to 7g embedded in the resistive trenches 10d to 10g is approximately the same as the position of the upper end of the conductive layers 7a and 7c embedded in the source trenches 10a and 10c and the gate electrode 7b embedded in the gate trench 10b. An interlayer insulating film 8 is provided on the upper surface side of the resistive layers 7d to 7g via the insulating film 6.

[0038] On the outer periphery of the resistive trench 10g of the active section 101, multiple trenches (outer periphery trenches) 10h and 10i are provided on the upper part of the drift layer 2. While Figure 3 illustrates a case with two outer periphery trenches 10h and 10i, the number of outer periphery trenches is not limited. It may include 1 to 3 outer periphery trenches, or 5 or more outer periphery trenches.

[0039] The depths d4 of the outer peripheral side trenches 10h and 10i are deeper than the depth d2 of the gate trench 10b, and are substantially the same as the depths d1 of the source trenches 10a and 10c and the depths d3 of the resistance trenches 10d to 10g. The widths w4 of the outer peripheral side trenches 10h and 10i are substantially the same as the widths w1 of the source trenches 10a and 10c, the width w2 of the gate trench 10b, and the widths w3 of the resistance trenches 10d to 10g. The interval s3 between the outer peripheral side trenches 10h and 10i is substantially the same as the interval s1 between the source trenches 10a and 10c and the gate trench 10b, and the interval s2 between the resistance trenches 10d to 10g.

[0040] Conductive layers 7h and 7i are embedded in the outer peripheral side trenches 10h and 10i via an insulating film 6. The conductive layers 7h and 7i are made of the same material as the gate electrode 7b, the conductive layers 7a and 7c, and the resistance layers 7d to 7g, and are formed of, for example, a polysilicon layer doped with an n-type impurity or a p-type impurity at a high impurity concentration. The entire circumference, which is the lower surface, both side surfaces, and upper surface of the conductive layers 7h and 7i, is covered with the insulating film 6. A gate runner 21 is provided on the upper surface side of the conductive layers 7h and 7i via the insulating film 6.

[0041] A step portion 10j is provided in a termination portion 102 provided on the outer peripheral side of the active portion 101. The depth d5 of the step portion 10j is substantially the same as the depth d1 of the source trenches 10a and 10c, the depth d3 of the resistance trenches 10d to 10g, and the depth d4 of the outer peripheral side trenches 10h and 10i. A p + -type electric field relaxation region 5c is provided continuously from the active portion 101 side. On the outer peripheral side of the end portion of the electric field relaxation region 5c, at least one of a p-type region constituting a junction termination extension (JTE) structure, a guard ring, a field plate, a RESURF, or the like may be provided. In this example, a plurality of p + -type guard rings 5d to 5f are provided. The guard rings 5d to 5f are provided concentrically in a ring shape while being spaced apart from each other. A wiring layer 29 is provided on the surface of the side wall portion of the step portion 10j.

[0042] Figure 4 shows a schematic cross-sectional view of the line BB' parallel to the line AA' in Figure 2. As shown in Figure 4, source trenches 10a, 10c, gate trench 10b, resistance trenches 10d to 10g, and outer trenches 10h, 10i are provided on the upper part of the drift layer 2. Above the source trenches 10a, 10c and gate trench 10b, a gate pad 20 is provided, spaced apart from the source electrode 28 shown in Figure 3, and in the same layer as the source electrode 28. In the built-in resistor 100, contact holes (resistive contact holes) are provided in the insulating film 6 and interlayer insulating film 8 on the upper surface side of the resistive layers 7e, 7f embedded in the resistive trenches 10e, 10f. The resistive layers 7e, 7f are connected to the gate runner 21 via contacts 24, 25 provided in the resistive contact holes and a wiring layer 23 provided on the upper surface of the interlayer insulating film 8.

[0043] Figure 5 shows a schematic cross-sectional view of the line CC' passing over the resistance trench 10e, in a direction perpendicular to lines AA' and BB' in Figure 2. As shown in Figure 5, the resistance layer 7e embedded in the resistance trench 10e is connected to the gate runner 21 shown in Figure 2 via the contact 24 in the contact holes (resistive contact holes) provided in the insulating film 6 and the interlayer insulating film 8 and the wiring layer 23 provided on the upper surface of the interlayer insulating film 8. It is also connected to the gate pad 20 shown in Figures 2 and 4 via the contact 26 in the contact holes (resistive contact holes) provided in the insulating film 6 and the interlayer insulating film 8 and the wiring layer 22 provided on the upper surface of the interlayer insulating film 8. As schematically shown in Figure 5 with the circuit symbol for a resistor, the resistance layer 7e between contact 24 and contact 26 forms the resistor.

[0044] As shown in Figure 2, the resistive layer 7e embedded in the resistive trench 10e is connected to the wiring layer 23 via contact 24 and to the wiring layer 22 via contact 26 spaced at a predetermined distance from the junction of contact 24. The resistive layer 7f embedded in the resistive trench 10f is connected to the wiring layer 23 via contact 25 and to the wiring layer 22 via contact 27 spaced at a predetermined distance from contact 25. In other words, in the built-in resistor 100, the resistive layer 7e between contact 24 and contact 26 and the resistive layer 7f between contact 25 and contact 27 are connected in parallel to function as a resistor.

[0045] The resistance value of the internal resistor 100 can be adjusted as appropriate by adjusting the position of the contacts connected to the resistive layers 7d to 7g embedded in the resistive trenches 10d to 10g (in other words, the length of the resistive layers 7d to 7g between the contacts) and the number of resistive layers 7d to 7g connected in parallel as a resistor. For example, the overall resistance value of the internal resistor 100 can be increased by increasing the spacing between contacts 24 and 26 and between contacts 25 and 27 as shown in Figure 2. The overall resistance value of the internal resistor 100 can be decreased by increasing the number of resistive layers 7d to 7g connected in parallel.

[0046] When the semiconductor device according to the first embodiment is in operation, with the source electrode 28 at ground potential, a positive voltage is applied to the drain electrode 11, and when a positive voltage above a threshold is applied to the gate electrode 7b, an inversion layer (channel) is formed on the side of the gate trench 10b in the base regions 3b and 3c, and the device enters an ON state. The inversion layer is formed on the surface of the base regions 3b and 3c that is exposed on the side of the gate trench 10b, which is the interface between the insulating film 6 sandwiched between the base regions 3b and 3c at a position facing the gate electrode 7b. In the ON state, current flows from the drain electrode 11 to the source electrode 28 via the drain region 1, the drift layer 2, the inversion layer in the base regions 3b and 3c, and the source regions 4b and 4c. On the other hand, when the voltage applied to the gate electrode 7b is below the threshold, an inversion layer is not formed in the base regions 3b and 3c, so the device enters an OFF state, and no current flows from the drain electrode 11 to the source electrode 28.

[0047] According to the semiconductor device of the first embodiment, for example, in a structure in which trenches are provided across the entire area of ​​the active portion 101 and extending from both ends of the active portion 101, the built-in resistor 100 is constructed using resistive layers 7d to 7g embedded in resistive trenches 10d to 10g extending from both ends of the active portion 101. This makes it possible to easily incorporate the gate resistor into the semiconductor chip without significantly increasing the number of steps compared to forming a resistive element on the upper surface of the semiconductor substrate.

[0048] Furthermore, by making the depths d1 of the source trenches 10a and 10c, the depths d3 of the resistive trenches 10d to 10g, and the depths d4 of the outer trenches 10h and 10i approximately the same, the electric field in the active section 101 becomes more uniform, preventing localized electric field concentration.

[0049] Furthermore, by making the widths w1 of the source trenches 10a and 10c, w2 of the gate trench 10b, w3 of the resistive trenches 10d to 10g, and w4 of the outer trenches 10h and 10i approximately the same, trenches are evenly distributed throughout the entire active section 101, resulting in a more uniform electric field in the active section 101 and preventing localized electric field concentration.

[0050] Furthermore, by making the spacing s1 between the source trenches 10a, 10c and the gate trench 10b, the spacing s2 between the resistive trenches 10d to 10g, and the spacing s3 between the outer peripheral trenches 10h and 10i approximately the same, trenches are evenly distributed throughout the entire active section 101. As a result, the electric field of the active section 101 becomes more uniform, preventing localized electric field concentration.

[0051] Furthermore, by providing an electric field relaxation region 5c in contact with the gap s1 between the source trenches 10a, 10c and the gate trench 10b, the lower and side surfaces of the resistive trenches 10d to 10g, and the lower and side surfaces of the outer peripheral trenches 10h, 10i, the structure becomes similar to that of the electric field relaxation regions 5a, 5c of the source trenches 10a, 10c. As a result, the electric field of the active section 101 becomes more uniform, and localized electric field concentration can be prevented.

[0052] Figure 6 shows a circuit diagram of an example of a semiconductor module according to the first embodiment. The semiconductor module according to the first embodiment comprises a gate drive circuit 300 and a plurality of semiconductor chips 301, 302, ..., 30n (where n is an integer of 3 or more) whose gates are electrically connected to the gate drive circuit 300. A wiring resistor R1 is connected between the gate drive circuit 300 and the gates of the plurality of semiconductor chips 301, 302, ..., 30n. Each of the plurality of semiconductor chips 301, 302, ..., 30n corresponds to a semiconductor device according to the first embodiment shown in Figures 1 to 5.

[0053] Semiconductor chip 301 includes a parasitic gate resistor Rg11 with one end connected to wiring resistor R1, an internal gate resistor Rg21 with one end connected to the other end of parasitic gate resistor Rg11, and a transistor T1 with its gate connected to the other end of internal gate resistor Rg21. Semiconductor chip 302 includes a parasitic gate resistor Rg12 with one end connected to wiring resistor R1, an internal gate resistor Rg22 with one end connected to the other end of parasitic gate resistor Rg12, and a transistor T2 connected to the other end of internal gate resistor Rg22. Semiconductor chip 30n includes a parasitic gate resistor Rg1n (n is an integer of 3 or more) with one end connected to wiring resistor R1, an internal gate resistor Rg2n (n is an integer of 3 or more) with one end connected to the other end of parasitic gate resistor Rg1n, and a transistor Tn (n is an integer of 3 or more) connected to the other end of internal gate resistor Rg2n.

[0054] Transistors T1, T2, ..., Tn correspond to MOSFETs, which are active elements of the semiconductor device according to the first embodiment. Parasitic gate resistors Rg11, Rg12, ..., Rg1n correspond to the parasitic resistance of the gate electrode 7b of the semiconductor device according to the first embodiment. Internal gate resistors Rg21, Rg22, ..., Rgn correspond to the built-in resistor section 100 of the semiconductor device according to the first embodiment.

[0055] According to the semiconductor module of the first embodiment, semiconductor chips made of silicon carbide (SiC) have a lower yield rate compared to semiconductor chips made of silicon (Si). Therefore, multiple semiconductor chips 301, 302, ..., 30n that carry small currents are connected in parallel to increase the overall current. In this case, it is necessary to switch the semiconductor chips 301, 302, ..., 30n simultaneously. However, by adjusting the internal gate resistances Rg21, Rg22, ..., Rgn to be larger than the parasitic gate resistances Rg11, Rg12, ..., Rg1n, it is possible to reduce the imbalance in the switching operation of the semiconductor chips 301, 302, ..., 30n.

[0056] Figure 7 shows a semiconductor device according to a comparative example. As shown in Figure 7, the semiconductor device according to the comparative example differs from the semiconductor device according to the first embodiment shown in Figure 1 in that it does not have a built-in resistor 100 between the gate pad 20 and the gate runner 21. When the semiconductor device according to the comparative example is applied to the semiconductor chips 301, 302, ..., 30n of the semiconductor module shown in Figure 6, an imbalance in the switching operation of the semiconductor chips 301, 302, ..., 30n occurs. In contrast, the semiconductor device according to the first embodiment can reduce the imbalance in the switching operation of the semiconductor chips 301, 302, ..., 30n by including the built-in resistor 100.

[0057] <Manufacturing method for semiconductor devices> Next, focusing on the cross-sectional view shown in Figure 4, an example of a method for manufacturing a semiconductor device according to the first embodiment will be described. It should be noted that the semiconductor device manufacturing method described below is just one example, and it is of course possible to achieve this through various other manufacturing methods, including this modified example, within the scope of the claims.

[0058] First, n-type impurities such as nitrogen (N) are added. + A semiconductor substrate 1 made of type n SiC (see Figure 9) is prepared. Next, n-type impurities such as N are added to the upper surface of semiconductor substrate 1, and n is added with a lower impurity concentration than that of semiconductor substrate 1. - A drift layer 2 (see Figure 9) made of SiC of a specific type is epitaxially grown.

[0059] Next, a photoresist film 31 (see Figure 9) is applied to the upper surface of the drift layer 2, and the photoresist film 31 is patterned using photolithography or the like. Using the patterned photoresist film 31 as an ion implantation mask, p-type impurities such as boron (B) or aluminum (Al) are selectively ion-implanted into the drift layer 2, thereby forming a p-type base region 3 (see Figure 9) on the upper part of the drift layer 2 of the active part 101. Furthermore, using the photoresist film 31 as an ion implantation mask, n-type impurities such as phosphorus (P) or nitrogen (N) are selectively ion-implanted into the drift layer 2 at a shallower projection range than the ion implantation of the p-type impurities, thereby forming an n-type base region 3 on the upper part of the drift layer 2 of the active part 101, as shown in Figure 9. + A source region 4 of type p is formed. Note that the order of ion implantation of p-type and n-type impurities is not limited and may be in the reverse order. After that, the photoresist film 31 is removed. Note that instead of the photoresist film 31, an oxide film may be patterned and used as an ion implantation mask.

[0060] Next, a photoresist film 32 (see Figure 10) is applied to the upper surface of the drift layer 2, and the photoresist film 32 is patterned using photolithography or the like. Using the patterned photoresist film 32 as an etching mask, the upper part of the drift layer 2 is selectively removed by dry etching techniques such as reactive ion etching (RIE). As a result, as shown in Figure 10, source trenches 10a, 10c, gate trench 10b, resistance trenches 10d to 10g, outer peripheral trenches 10h, 10i, and stepped portions 10j are selectively formed.

[0061] The depths d6 of the source trenches 10a, 10c, gate trench 10b, resistance trenches 10d-10g, outer trenches 10h, 10i, and stepped section 10j shown in Figure 10 are the same as the depth d2 of the gate trench 10b shown in Figures 3 and 4, and are shallower than the depths d1 of the source trenches 10a, 10c, d3 of the resistance trenches 10d-10g, d4 of the outer trenches 10h, 10i, and d5 of the stepped section 10j shown in Figures 3 and 4. The source trenches 10a, 10c, and gate trench 10b divide the base region 3 into base regions 3a-3d, and the source region 4 into source regions 4a-4d. After that, the photoresist film 32 is removed. Alternatively, an oxide film may be patterned and used as an etching mask instead of the photoresist film 32.

[0062] Next, a photoresist film 33 (see Figure 11) is applied to the upper surface of the drift layer 2, and the photoresist film 33 is patterned using photolithography or the like. Using the patterned photoresist film 33 as an etching mask, the upper part of the drift layer 2 is selectively removed by dry etching techniques such as reactive ion etching (RIE). As a result, as shown in Figure 11, the source trenches 10a, 10c, resistance trenches 10d to 10g, outer trenches 10h, 10i, and stepped portion 10j, other than the gate trench 10b, are further excavated to a depth of d7.

[0063] The depths d7 of the source trenches 10a, 10c, resistance trenches 10d to 10g, outer trenches 10h, 10i, and stepped section 10j shown in Figure 11 are approximately the same as the depths d1 of the source trenches 10a, 10c, d3 of the resistance trenches 10d to 10g, d4 of the outer trenches 10h, 10i, and d5 of the stepped section 10j shown in Figures 3 and 4. After that, the photoresist film 33 is removed. Alternatively, an oxide film may be patterned and used as an etching mask instead of the photoresist film 33.

[0064] Next, a photoresist film 34 (see Figure 12) is applied to the upper surface of the drift layer 2, and the photoresist film 34 is patterned using photolithography or the like. Using the patterned photoresist film 34 as an ion implantation mask, p-type impurities such as boron (B) or aluminum (Al) are ion-implanted into the lower and side surfaces of the source trenches 10a, 10c, the resistance trenches 10d to 10g, the outer peripheral trenches 10h, 10i, and the stepped portion 10j. As a result, as shown in Figure 12, p-type impurities are ion-implanted into the upper part of the drift layer 2. + Type electric field relaxation regions 5a-5c and p + A type of guard ring 5d to 5f is formed.

[0065] p + Type electric field relaxation regions 5a-5c and p + For example, ion implantation to form the guard rings 5d to 5f of the type may be performed in two separate steps from oblique directions, each having an angle clockwise and counterclockwise relative to the depth direction of the source trenches 10a, 10c, resistance trenches 10d to 10g, outer trenches 10h, 10i, and stepped portion 10j. Alternatively, if the side walls of the source trenches 10a, 10c, resistance trenches 10d to 10g, and outer trenches 10h, 10i have a tapered shape, ion implantation can be performed in one vertical step. + Type electric field relaxation regions 5a-5c and p + A guard ring of type 5d~5f can be formed. Alternatively, considering the variation in the ion implantation angle, p can be formed by a single ion implantation. + Type electric field relaxation regions 5a-5c and p + A guard ring 5d to 5f of the mold can be formed. After that, the photoresist film 34 is removed. Alternatively, instead of the photoresist film 34, an oxide film may be patterned and used as an ion implantation mask.

[0066] Next, by performing heat treatment (activation annealing), the p-type base regions 3a to 3d and n + Source regions 4a~4d, p + Type electric field relaxation regions 5a-5c and p +The p-type and n-type impurities implanted in the guard rings 5d to 5f of the mold are simultaneously activated. Note that heat treatment (activation annealing) may be performed individually for each ion implantation.

[0067] Next, insulating film 6 (see Figure 13) is formed on the lower and side surfaces of the source trenches 10a, 10c, gate trench 10b, resistance trenches 10d-10g, and outer trenches 10h, 10i by thermal oxidation or CVD technology. Then, a polysilicon layer (doped polysilicon layer) with high concentrations of n-type or p-type impurities is deposited by CVD technology to fill the source trenches 10a, 10c, gate trench 10b, resistance trenches 10d-10g, and outer trenches 10h, 10i. Subsequently, a portion of the polysilicon layer and a portion of the insulating film 6 are selectively removed by photolithography and dry etching. As a result, an insulated gate electrode structure (6, 7b) (see Figure 13) is formed, consisting of the insulating film 6 as a gate insulating film embedded in the gate trench 10b and the gate electrode 7b. Conductive layers 7a, 7c are embedded in the source trenches 10a, 10c via the insulating film 6. Resistive trenches 10d to 10g are embedded with resistive layers 7d to 7g via insulating film 6. Conductive trenches 10h and 10i on the outer periphery are embedded with conductive layers 7h and 7i via insulating film 6.

[0068] Next, insulating film 6 is selectively formed on the upper surfaces of the polysilicon layers embedded in the source trenches 10a, 10c, gate trench 10b, resistive trenches 10d to 10g, and outer trenches 10h, 10i by thermal oxidation or CVD technology. As a result, as shown in Figure 13, the upper surfaces of the gate electrode 7b embedded in the gate trench 10b, the upper surfaces of the conductive layers 7a, 7c embedded in the source trenches 10a, 10c, the upper surfaces of the resistive layers 7d to 7g embedded in the resistive trenches 10d to 10g, and the upper surfaces of the conductive layers 7h, 7i embedded in the outer trenches 10h, 10i are each covered with insulating film 6.

[0069] Next, an interlayer insulating film 8 (see Figure 14) is deposited on the upper surface of the insulated gate electrode structure (6, 7b) using CVD technology or the like. A portion of the interlayer insulating film 8 is selectively removed using photolithography technology and dry etching technology. As a result, as shown in Figure 14, resistance contact holes are opened in the interlayer insulating film 8, exposing the upper surfaces of the resistance layers 7e and 7f. At this time, gate contact holes exposing the upper surface of the gate electrode 7b and source contact holes exposing the upper surfaces of the source regions 4a to 4d and the electric field relaxation regions 5a and 5b are also opened in the interlayer insulating film 8.

[0070] Next, a metal layer is deposited by sputtering or vapor deposition. The metal layer is patterned using photolithography and RIE techniques. As a result, as shown in Figure 15, a source electrode 28 (see Figure 3), gate pad 20, gate runner 21, wiring 22, 23 (see Figure 2), contacts 24, 25, etc., which are part of the metal layer, are formed. Wiring 23 is electrically connected to the resistive layers 7e, 7f via contacts 24, 25 and wiring 23 in the resistive contact holes of the interlayer insulating film 8. Gate runner 21 is electrically connected to gate electrode 7b via gate contact holes of the interlayer insulating film 8. Source electrode 28 is electrically connected to source regions 4a-4d and electric field relaxation regions 5a, 5b via source contact holes of the interlayer insulating film 8.

[0071] Next, the semiconductor substrate 1 is thinned from the bottom side by grinding or chemical mechanical polishing (CMP) to adjust its thickness and create a drain region. Then, a drain electrode 11 made of gold (Au) or the like (see Figure 2) is formed on the entire bottom surface of the drain region 1 by sputtering or vapor deposition. In this way, the semiconductor device shown in Figure 2 can be realized.

[0072] (Second Embodiment) The semiconductor device according to the second embodiment differs from the semiconductor device according to the first embodiment shown in Figure 4, as shown in Figure 16, in that the upper parts of the resistive layers 7e, 7f embedded in the resistive trenches 10e, 10f and the conductive layers 7h, 7i embedded in the outer peripheral trenches 10h, 10i protrude above the resistive trenches 10e, 10f and the outer peripheral trenches 10h, 10i. The upper ends of the resistive layers 7e, 7f and the conductive layers 7h, 7i are located above the upper ends of the conductive layers 7a, 7c and the gate electrode 7b. The other configurations of the semiconductor device according to the second embodiment are substantially the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0073] According to the second embodiment, similar to the first embodiment, the gate resistor can be easily incorporated by configuring the built-in resistor 100 using resistive layers 7d to 7g embedded in resistive trenches 10d to 10g that extend across both ends of the active portion 101.

[0074] Furthermore, according to the second embodiment, the upper parts of the resistive layers 7e, 7f embedded in the resistive trenches 10e, 10f and the conductive layers 7h, 7i embedded in the outer peripheral trenches 10h, 10i protrude above the resistive trenches 10d, 10f and the outer peripheral trenches 10h, 10i, thereby stabilizing the manufacturing process.

[0075] (Third embodiment) The semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment shown in Figure 4, in that, as shown in Figure 17, the upper parts of the resistive layers 7e, 7f embedded in the resistive trenches 10e, 10f and the conductive layers 7h, 7i embedded in the outer peripheral trenches 10h, 10i protrude above the resistive trenches 10e, 10f and the outer peripheral trenches 10h, 10i, similar to the semiconductor device according to the second embodiment shown in Figure 16.

[0076] Furthermore, the semiconductor device according to the third embodiment differs from the semiconductor device according to the first embodiment shown in Figure 4, in that, as shown in Figure 17, the resistive layers 7e and 7f embedded in the resistive trenches 10e and 10f are connected to each other by a connecting portion 7x made of a polysilicon layer. The other configurations of the semiconductor device according to the third embodiment are substantially the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0077] According to the third embodiment, similar to the first embodiment, the gate resistor can be easily incorporated by configuring the built-in resistor 100 using resistive layers 7d to 7g embedded in resistive trenches 10d to 10g that extend across both ends of the active portion 101.

[0078] Furthermore, according to the third embodiment, the upper parts of the resistive layers 7e and 7f embedded in the resistive trenches 10e and 10f and the conductive layers 7h and 7i embedded in the outer trenches 10h and 10i protrude above the resistive trenches 10e and 10f and the outer trenches 10h and 10i, and the resistive layers 7e and 7f are connected by the connection part 7x, thereby stabilizing the manufacturing process.

[0079] (Fourth Embodiment) The semiconductor device according to the fourth embodiment differs from the semiconductor device according to the first embodiment shown in Figure 4, in that the depth of the resistive trenches 10d and 10f is different from the depth of the resistive trenches 10e and 10g, as shown in Figure 18. The depth of the resistive trenches 10d and 10f is shallower than the depth of the resistive trenches 10e and 10g, and is approximately the same as the depth of the gate trench 10b. The resistive layers 7d and 7f embedded in the resistive trenches 10d and 10f are connected to the wiring layer 23 via contacts 24 and 25. The other configurations of the semiconductor device according to the fourth embodiment are substantially the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0080] According to the fourth embodiment, similar to the first embodiment, the gate resistor can be easily incorporated by configuring the built-in resistor 100 using resistive layers 7d to 7g embedded in resistive trenches 10d to 10g that extend across both ends of the active portion 101.

[0081] Furthermore, according to the fourth embodiment, since the depths of the resistive trenches 10d and 10f are different from the depths of the resistive trenches 10e and 10g, the structure becomes similar to the unit structure of the source trench 10a and gate trench 10b of the active section 101. As a result, the electric field of the active section 101 becomes more uniform, and localized electric field concentration can be prevented.

[0082] (Fifth embodiment) The semiconductor device according to the fifth embodiment is similar to the semiconductor device according to the fourth embodiment shown in Figure 18, but differs from the semiconductor device according to the first embodiment shown in Figure 4, in that the depths of the resistive trenches 10d and 10f are different from the depths of the resistive trenches 10e and 10g, as shown in Figure 19.

[0083] Furthermore, as shown in Figure 19, the semiconductor device according to the fifth embodiment differs from the semiconductor device according to the first embodiment shown in Figure 4 in that the upper parts of the resistive layers 7d, 7f embedded in the resistive trenches 10d, 10f and the conductive layers 7h, 7i embedded in the outer peripheral trenches 10h, 10i protrude above the resistive trenches 10d, 10f and the outer peripheral trenches 10h, 10i. The other configurations of the semiconductor device according to the fifth embodiment are substantially the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0084] According to the fifth embodiment, similar to the first embodiment, the gate resistor can be easily incorporated by configuring the built-in resistor 100 using resistive layers 7d to 7g embedded in resistive trenches 10d to 10g that extend across both ends of the active portion 101.

[0085] Furthermore, according to the fifth embodiment, since the depths of the resistive trenches 10d and 10f are different from the depths of the resistive trenches 10e and 10g, the structure becomes similar to that of the gate trench 10b and source trenches 10a and 10c of the active part 101, the electric field of the active part 101 becomes more uniform, and localized electric field concentration can be prevented. In addition, the upper parts of the resistive layers 7d and 7f embedded in the resistive trenches 10d and 10f and the conductive layers 7h and 7i embedded in the outer peripheral trenches 10h and 10i protrude above the resistive trenches 10d and 10f and the outer peripheral trenches 10h and 10i, thereby stabilizing the manufacturing process.

[0086] (Sixth Embodiment) The semiconductor device according to the sixth embodiment differs from the semiconductor device according to the first embodiment shown in Figure 4, in that, as shown in Figure 20, the depth of the resistive trenches 10d and 10f is different from the depth of the resistive trenches 10e and 10g, and the upper parts of the resistive layers 7d and 7f embedded in the resistive trenches 10d and 10f and the conductive layers 7h and 7i embedded in the outer peripheral trenches 10h and 10i protrude upward from the resistive trenches 10d and 10f and the outer peripheral trenches 10h and 10i.

[0087] Furthermore, the semiconductor device according to the sixth embodiment differs from the semiconductor device according to the first embodiment shown in Figure 4, in that, as shown in Figure 20, the upper parts of the resistive layers 7d and 7f embedded in the resistive trenches 10d and 10f are connected to each other by a connecting portion 7x made of polysilicon. The other configurations of the semiconductor device according to the sixth embodiment are substantially the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0088] According to the sixth embodiment, similar to the first embodiment, the gate resistor can be easily incorporated by configuring the built-in resistor 100 using resistive layers 7d to 7g embedded in resistive trenches 10d to 10g that extend across both ends of the active portion 101.

[0089] Furthermore, according to the sixth embodiment, since the depths of the resistive trenches 10d and 10f are different from the depths of the resistive trenches 10e and 10g, the structure becomes similar to that of the gate trench 10b and source trenches 10a and 10c of the active part 101, the electric field of the active part 101 becomes more uniform, and localized electric field concentration can be prevented. In addition, the upper parts of the resistive layers 7d and 7f embedded in the resistive trenches 10d and 10f and the conductive layers 7h and 7i embedded in the outer peripheral trenches 10h and 10i protrude above the resistive trenches 10d and 10f and the outer peripheral trenches 10h and 10i, and the resistive layers 7d and 7f are connected to each other at the connection part 7x, thereby stabilizing the manufacturing process.

[0090] (Seventh Embodiment) The semiconductor device according to the seventh embodiment differs from the semiconductor device according to the first embodiment shown in Figure 4, similar to the semiconductor device according to the sixth embodiment shown in Figure 20, in that, as shown in Figure 21, the depth of the resistive trenches 10d and 10f is different from the depth of the resistive trenches 10e and 10g, the upper parts of the resistive layers 7d and 7f embedded in the resistive trenches 10d and 10f and the conductive layers 7h and 7i embedded in the outer peripheral trenches 10h and 10i protrude above the resistive trenches 10d and 10f and the outer peripheral trenches 10h and 10i, and the upper parts of the resistive layers 7d and 7f embedded in the resistive trenches 10d and 10f are connected to each other by a connection part 7x made of polysilicon.

[0091] Furthermore, the semiconductor device according to the seventh embodiment differs from the semiconductor device according to the first embodiment shown in Figure 4, in that, as shown in Figure 21, the upper part of the resistive layer 7e embedded in the resistive trench 10e protrudes above the upper end of the resistive trench 10e and is connected to the connection portion 7x. The other configurations of the semiconductor device according to the seventh embodiment are substantially the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0092] According to the seventh embodiment, similar to the first embodiment, the gate resistor can be easily incorporated by configuring the built-in resistor 100 using resistive layers 7d to 7g embedded in resistive trenches 10d to 10g that extend across both ends of the active portion 101.

[0093] Furthermore, according to the seventh embodiment, since the depths of the resistive trenches 10d and 10f are different from the depths of the resistive trenches 10e and 10g, the structure becomes similar to that of the gate trench 10b and source trenches 10a and 10c of the active part 101, the electric field of the active part 101 becomes more uniform, and localized electric field concentration can be prevented. In addition, the upper parts of the resistive layers 7d to 7f embedded in the resistive trenches 10d to 10f and the conductive layers 7h and 7i embedded in the outer peripheral trenches 10h and 10i protrude above the resistive trenches 10d to 10f and the outer peripheral trenches 10h and 10i, and the resistive layers 7d to 7f are connected to each other by the connection part 7x, thereby stabilizing the manufacturing process.

[0094] (Eighth embodiment) The semiconductor device according to the eighth embodiment differs from the semiconductor device according to the first embodiment shown in Figure 4, similar to the semiconductor device according to the seventh embodiment shown in Figure 21, in that, as shown in Figure 22, the depth of the resistive trenches 10d and 10f is different from the depth of the resistive trenches 10e and 10g, the upper parts of the resistive layers 7d and 7f embedded in the resistive trenches 10d and 10f and the conductive layers 7h and 7i embedded in the outer peripheral trenches 10h and 10i protrude above the resistive trenches 10d and 10f and the outer peripheral trenches 10h and 10i, and the upper parts of the resistive layers 7d to 7f embedded in the resistive trenches 10d to 10f are connected to each other by a connection part 7x made of polysilicon.

[0095] Furthermore, the semiconductor device according to the eighth embodiment differs from the semiconductor device according to the first embodiment shown in Figure 4, in that, as shown in Figure 22, the upper part of the resistive layer 7g embedded in the resistive trench 10g protrudes above the upper end of the resistive trench 10g and is connected to the connection portion 7x. The other configurations of the semiconductor device according to the eighth embodiment are substantially the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0096] According to the eighth embodiment, similar to the first embodiment, the gate resistor can be easily incorporated by configuring the built-in resistor 100 using resistive layers 7d to 7g embedded in resistive trenches 10d to 10g that extend across both ends of the active portion 101.

[0097] Furthermore, according to the eighth embodiment, since the depths of the resistive trenches 10d and 10f are different from the depths of the resistive trenches 10e and 10g, the structure becomes similar to that of the gate trench 10b and source trenches 10a and 10c of the active part 101, the electric field of the active part 101 becomes more uniform, and localized electric field concentration can be prevented. In addition, the upper parts of the resistive layers 7d to 7g embedded in the resistive trenches 10d to 10g and the conductive layers 7h and 7i embedded in the outer peripheral trenches 10h and 10i protrude above the resistive trenches 10d to 10g and the outer peripheral trenches 10h and 10i, and the resistive layers 7d to 7g are connected to each other by the connection part 7x, thereby stabilizing the manufacturing process.

[0098] (Ninth Embodiment) The semiconductor device according to the ninth embodiment differs from the semiconductor device according to the first embodiment shown in Figure 2, in that, as shown in Figure 23, the resistive layers 7e and 7f embedded in the resistive trenches 10e and 10f of the built-in resistor 100 are connected in series. Wiring 51 is connected to the gate pad 20. Wiring 51 is connected to the resistive layer 7e (see Figures 3 and 4) embedded in the resistive trench 10e via contact 41. Wiring 52 is connected to the resistive layer 7e embedded in the resistive trench 10e via contact 42 at a predetermined interval from contact 41. Wiring 52 is connected to the resistive layer 7f (see Figures 3 and 4) embedded in the resistive trench 10f via contact 43. Wiring 53 is connected to the resistive layer 7f embedded in the resistive trench 10f via contact 44 at a predetermined interval from contact 43. A gate runner 21 is connected to wiring 53.

[0099] The resistor of the built-in resistor 100 is formed by a series connection of a resistive layer 7e embedded in the resistive trench 10e between contacts 41 and 42 and a resistive layer 7f embedded in the resistive trench 10f between contacts 43 and 44, forming a C-shaped current path on the planar pattern. The other configurations of the semiconductor device according to the ninth embodiment are substantially the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0100] According to the ninth embodiment, similar to the first embodiment, the gate resistor can be easily incorporated by configuring the built-in resistor 100 using resistive layers 7d to 7g embedded in resistive trenches 10d to 10g that extend across both ends of the active portion 101.

[0101] Furthermore, according to the ninth embodiment, by connecting the resistive layers 7e and 7f in series, the resistance value of the built-in resistive section 100 can be increased without increasing the size of the built-in resistive section 100, thereby improving the flexibility of the resistance value of the built-in resistive section 100. Additionally, three or more resistive layers may be connected in series by folding them back.

[0102] (Tenth embodiment) As shown in Figure 24, the semiconductor device according to the tenth embodiment differs from the semiconductor device according to the first embodiment shown in Figure 1 in the placement of the gate pad 20. The gate pad 20 is located in the center of the active portion 101. An internal resistor 100 is connected between the gate pad 20 and the gate runner 21. The other configurations of the semiconductor device according to the tenth embodiment are substantially the same as those of the semiconductor device according to the first embodiment, so redundant explanations are omitted.

[0103] According to the tenth embodiment, even if the arrangement positions of the gate pad 20 and the built-in resistor 100 are different, the gate resistor can be easily incorporated by configuring the built-in resistor 100 using a resistance layer embedded in a resistance trench extending across both ends of the active portion 101, similar to the first embodiment.

[0104] (Other embodiments) As described above, the first to tenth embodiments of this disclosure have been presented, but the statements and drawings that constitute part of this disclosure should not be understood as limiting the disclosure. Various alternative embodiments, examples, and operational techniques will become apparent to those skilled in the art from this disclosure.

[0105] For example, a MOSFET was given as an example of a semiconductor device according to the first to tenth embodiments, but n + Drain region 1 of type p + This can also be applied to insulated-gate bipolar transistors (IGBTs) with a collector region of the same type.

[0106] Furthermore, although semiconductor devices made of SiC were exemplified as semiconductor devices according to the first to tenth embodiments, the invention is also applicable to semiconductor devices made of semiconductors with a wider band gap than Si (wide bandgap semiconductors), such as gallium nitride (GaN), diamond (C), or aluminum nitride (AlN).

[0107] In this example, the semiconductor device forms an electric field relaxation region from the side walls to the bottom of the trench by ion implantation after trench formation. Since the bottom of the trench is used to form the electric field relaxation region at a deep location, it is necessary to form trenches in all areas except the edges. Because trenches are present in all areas except the edges, it is not easy to form a gate resistor on the upper surface of the substrate via an insulating film.

[0108] According to the present invention, the number of steps is reduced and the gate resistor can be easily incorporated by using the polysilicon contained within the trench as the built-in gate resistor.

[0109] Furthermore, the configurations disclosed in the first to tenth embodiments can be combined as appropriate, within the bounds of consistency. Thus, this disclosure naturally includes various embodiments not described herein. Therefore, the technical scope of this disclosure is determined solely by the inventive features relating to the claims that are appropriate based on the above description. [Explanation of symbols]

[0110] 1…Drain region (semiconductor substrate) 2…Drift layer 3,3a~3d...Base region 4,4a~4d…source area 4a~4d 5a~5c...Electric field relaxation region 5d~5f...Guard ring 6…Insulating film (gate insulating film) 7a, 7c... Conductive layer (polysilicon layer) 7b...Gate electrode (polysilicon layer) 7d~7g... Resistive layer (polysilicon layer) 7h, 7i... Conductive layer (polysilicon layer) 7x…connection part 8…Interlayer insulating film 10a, 10c... Trench (Sauce Trench) 10b... Trench (gate trench) 10d~10g... Trench (resistance trench) 10h, 10i... Trench (outer perimeter trench) 10j... Step section 11…Drain electrode 20…Gate pad 21…Gate Runner 22,23…wiring layer 24-27... Contact lenses 28…Source electrode 29...Wiring layer 31-34... Photoresist film 41-44... Contact 51-53...Wiring 100...Internal resistor 101...Active part 102...Terminal section 300... Gate drive circuit 301, 302, 30n… Semiconductor chips R1…Wiring resistance Rg11, Rg12, Rg1n... Parasitic gate resistors Rg21, Rg22, Rg2n... Internal gate resistors T1, T2, Tn... Transistors d1~d7... Depth s1~s3…interval w1~w4... width

Claims

1. An active portion, and a first conductive drift layer provided at the terminal portion surrounding the active portion, A base region of the second conductivity type provided on the upper surface side of the drift layer of the active portion, A first conductivity type main region is provided on the upper surface side of the drift layer of the active portion, in contact with the base region, A gate electrode is embedded in a gate trench, which is provided on the upper surface side of the drift layer of the active portion and extends in one direction across both ends of the active portion, via a gate insulating film. A gate runner is provided on the outer periphery of the active portion and is electrically connected to the gate electrode, A gate pad provided inside the gate runner of the activated part, A resistive layer is provided on the upper surface side of the drift layer of the active portion, embedded in a resistive trench extending in one direction across both ends of the active portion via an insulating film, and electrically connected between the gate pad and the gate runner, Equipped with Semiconductor equipment.

2. The depth of the resistance trench is greater than the depth of the gate trench. The semiconductor device according to claim 1.

3. A conductive layer is embedded in a source trench, which is provided on the upper surface of the drift layer adjacent to the gate trench and extends in one direction across both ends of the active portion, via an insulating film. A second conductivity type field relaxation region is provided in contact with the lower surface and side surface of the source trench, It also has The semiconductor device according to claim 1 or 2.

4. The depth of the resistor trench is the same as the depth of the source trench. The semiconductor device according to claim 3.

5. Multiple resistance trenches are provided spaced apart from each other. Multiple resistor layers embedded in the multiple resistor trenches are connected in parallel. The semiconductor device according to claim 1 or 2.

6. Multiple resistance trenches are provided spaced apart from each other. The spacing between the plurality of resistive trenches is the same as the spacing between the gate trench and the source trench. The semiconductor device according to claim 3.

7. The system further comprises a second conductivity type field relaxation region provided in contact with the lower surface and side surface of the aforementioned resistive trench. The semiconductor device according to claim 1 or 2.

8. The outermost trench, located directly beneath the gate runner and extending in one direction across both ends of the active portion, is further provided with a conductive layer embedded via an insulating film. The semiconductor device according to claim 1 or 2.

9. The depth of the outer circumferential trench is the same as the depth of the resistance trench. The semiconductor device according to claim 8.

10. The system further comprises a second conductivity type field relaxation region provided in contact with the lower surface and side surface of the outer circumferential trench. The semiconductor device according to claim 8.

11. A stepped portion of the same depth as the resistance trench is provided at the terminal end. The semiconductor device according to claim 1 or 2.

12. A second conductive guard ring is provided at the aforementioned terminal end. The semiconductor device according to claim 1 or 2.

13. The position of the upper end of the resistive layer is the same as the position of the upper end of the gate electrode. The semiconductor device according to claim 1 or 2.

14. The upper end of the resistive layer is located above the upper end of the gate electrode. The semiconductor device according to claim 1 or 2.

15. The resistive layers embedded in the aforementioned plurality of resistive trenches are connected to each other by connection points. The semiconductor device according to claim 14.

16. Multiple resistance trenches are provided spaced apart from each other. The aforementioned plurality of resistance trenches, A first trench that is deeper than the gate trench, A second trench having the same depth as the gate trench, Equipped with The semiconductor device according to claim 1 or 2.

17. Multiple resistance trenches are provided spaced apart from each other. Multiple resistor layers embedded in the multiple resistor trenches are connected in series. The semiconductor device according to claim 1 or 2.

18. The aforementioned drift layer is composed of an epitaxial growth layer made of silicon carbide. The semiconductor device according to claim 1 or 2.

19. The gate electrode and the resistive layer are made of polysilicon. The semiconductor device according to claim 1 or 2.

20. A step of forming a first conductivity type drift layer on the active portion and the terminal portion surrounding the active portion, The process of forming a base region of a second conductivity type on the upper surface side of the drift layer of the active portion, The process of forming a main region of the first conductivity type in contact with the base region on the upper surface side of the drift layer of the active portion, The process of forming a gate trench on the upper surface side of the drift layer of the active portion, extending in one direction from both ends of the active portion, The process of embedding a gate electrode in the gate trench via a gate insulating film, The process involves forming a gate runner on the outer periphery of the active portion, which is electrically connected to the gate electrode. A step of forming a gate pad inside the gate runner of the active part, A step of forming a resistance trench on the upper surface side of the drift layer of the active portion, extending in one direction from both ends of the active portion, A step of embedding a resistive layer in the resistive trench, via an insulating film, which is electrically connected between the gate pad and the gate runner, A method for manufacturing a semiconductor device containing [a specific component].

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