Silicon carbide semiconductor equipment

Abstract

To provide a SiC semiconductor device in which switching tolerance can be improved irrespective of a rate controlling place of tolerance dose.SOLUTION: In a SiC semiconductor device in which a trench gate structure semiconductor element is formed, an n-type JFET layer 14 and a p-type first deep layer 15 are formed in a cell region 1. And, in a connecting part 2b positioned on an outer periphery of the cell region 1, an outer periphery end position Po that is an outer peripheral side end position of the cell region 1 in the JFET layer 14 is arranged to be positioned on a side of the cell region 1 compared to an inner periphery end position Pi that is an end position on a side of the cell region 1 in gate wiring 26.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] This disclosure relates to a silicon carbide (hereinafter also referred to as SiC) semiconductor device having a trench gate structure. [Background technology]

[0002] In a SiC semiconductor device having a trench gate MOSFET, the gate insulating film extends to the outer periphery of the cell region where the MOSFET is formed, and a field oxide film is placed on top of it. The gate electrode of the MOSFET located in the cell region extends onto the gate insulating film and field insulating film that are placed to the outer periphery of the cell region, and is connected to the gate wiring. In SiC semiconductor devices configured in this way, thin insulating films such as the gate insulating film are easily destroyed by displacement current during high-speed switching. For this reason, Patent Document 1 shortens the distance from the source contact in the cell region to the step portion that forms the boundary between the gate insulating film and the field insulating film, thereby shortening the current path distance. This reduces the current path resistance, suppresses the destruction of the gate insulating film caused by displacement current, and improves the switching withstand capability. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Publication No. 2015-57850 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, in the structure of Patent Document 1, if the rate-limiting factor of the SiC semiconductor device is located at a point other than the stepped portion of the field oxide film, the configuration of Patent Document 1 does not provide the effect of reducing the current path resistance, and therefore the switching withstand capability cannot be improved.

[0005] The purpose of this disclosure is to provide a SiC semiconductor device that can improve switching withstand capability regardless of the rate-limiting location of the withstand capability. [Means for solving the problem]

[0006] One aspect of the present disclosure is a SiC semiconductor device having a cell region (1) on which a trench gate semiconductor element is formed, and an outer peripheral region (2) surrounding the cell region, which is provided with an outer peripheral breakdown structure portion (2a) constituting an outer peripheral breakdown structure (16) and a connecting portion (2b) located between the outer peripheral breakdown structure portion and the cell region, wherein the SiC semiconductor device has a substrate (11) made of a first conductivity type or a second conductivity type SiC, and a first impurity region (13) of the first conductivity type formed on the surface of the substrate and having a lower impurity concentration than the substrate. The cell region includes a JFET layer (14) formed on the surface of the first impurity region and made of first conductivity type SiC with a higher impurity concentration than the first impurity region, a deep layer (15) formed on the surface of the first impurity region and made of second conductivity type SiC arranged alternately with the JFET layer in the planar direction of the substrate, a base layer (18) made of second conductivity type SiC formed on the JFET layer and the deep layer, and gate trenches (21) formed on the inner wall surface of the gate trenches, which are deeper than the base layer and arranged in a row with one direction as the longitudinal direction. The semiconductor device comprises a trench gate structure having a gate insulating film (22) and a gate electrode (23) formed on the gate insulating film within the gate trench; a second impurity region (19) formed in contact with the trench gate structure on the surface of the base layer and made of first conductivity type SiC with a higher impurity concentration than the first impurity region; a first electrode (25) electrically connected to the second impurity region and the base layer; and a second electrode (28) arranged on the back side of the substrate and electrically connected to the substrate. The junction is provided with a gate insulating film extending from the cell region and formed on the first impurity region, a gate electrode extending from the cell region and arranged on the gate insulating film, and gate wiring (26) connected to the gate electrode. The outer peripheral termination position (Po), which is the outer peripheral termination position of the cell region in the JFET layer, is located closer to the cell region than the inner peripheral termination position (Pi), which is the cell region termination position of the gate wiring.

[0007] Thus, the electric field applied to the gate insulating film tends to be particularly large below the gate wiring. However, the JFET layer is not formed in that area, and the outer peripheral termination position of the JFET layer is located closer to the cell region than the inner peripheral termination position of the gate wiring. With this structure, the impurity concentrations of the p-type and n-type layers constituting the pn junction are reduced, and the displacement current generated during a voltage surge in switching can be reduced. Therefore, electric field concentration caused by the displacement current is mitigated, the breakdown of the gate insulating film can be suppressed, and the switching withstand capability can be improved. Furthermore, this effect can be obtained regardless of the rate-limiting location of the withstand capability. Thus, it is possible to create a SiC semiconductor device that can improve the switching withstand capability regardless of the rate-limiting location of the withstand capability.

[0008] In a second aspect of this disclosure, the JFET layer is formed only on the cell region side of the cell region and the junction.

[0009] Thus, a JFET layer is formed in the cell region and on the cell region side of the junction, but no JFET layer is formed on the outside. Therefore, the pn junction on the outer edge of the junction is composed of a low-concentration layer and a deep layer. As a result, the effects of the first aspect can be obtained.

[0010] In a third aspect of this disclosure, the JFET layer is also formed in the junction, and in the portion of the JFET layer outside the inner circumference termination position which is the termination position on the cell region side of the gate wiring, the concentration of the first conductivity type impurity is less than or equal to the first impurity region.

[0011] Thus, even if a JFET layer is formed at the junction, if the impurity concentration of the first conductivity type is lowered outside the inner circumference termination position of the gate wiring, the impurity concentrations of the p-type and n-type layers constituting the pn junction in the outer circumference region will be lowered. Therefore, the time variation dV / dt becomes smaller, and the displacement current can be reduced, improving the switching withstand capability. This makes it possible to create a SiC semiconductor device that can improve switching withstand capability regardless of the rate-limiting location of the withstand capability.

[0012] In addition, the reference numerals with parentheses attached to each component etc. indicate an example of the correspondence relationship between the component etc. and the specific components etc. described in the embodiments described later.

Brief Description of the Drawings

[0013] [Figure 1] It is a plan view of the SiC semiconductor device according to the first embodiment. [Figure 2] It is a perspective cross-sectional view when the region RA in FIG. 1 is viewed from the II direction. [Figure 3] It is a cross-sectional view taken along the line III-III in FIG. 1. [Figure 4] It is a cross-sectional view taken along the line IV-IV in FIG. 1. [Figure 5] It is a cross-sectional view for explaining the displacement current generated in the outer peripheral region. [Figure 6A] It is a cross-sectional view showing the manufacturing process of the SiC semiconductor device of the first embodiment. [Figure 6B] It is a cross-sectional view showing the manufacturing process following FIG. 6A. [Figure 6C] It is a cross-sectional view showing the manufacturing process following FIG. 6B. [Figure 6D] It is a cross-sectional view showing the manufacturing process following FIG. 6C. [Figure 6E] It is a cross-sectional view showing the manufacturing process following FIG. 6D. [Figure 7] It is a cross-sectional view of the SiC semiconductor device according to the second embodiment. [Figure 8A] It is a cross-sectional view showing the manufacturing process of the SiC semiconductor device of the first embodiment. [Figure 8B] It is a cross-sectional view showing the manufacturing process following FIG. 8A. [Figure 8C] It is a cross-sectional view showing the manufacturing process following FIG. 8B. [Figure 8D] It is a cross-sectional view showing the manufacturing process following FIG. 8C. [Figure 8E] It is a cross-sectional view showing the manufacturing process following FIG. 8D.

Modes for Carrying Out the Invention

[0014] The embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0015] (First Embodiment) The first embodiment will be described with reference to the drawings. As shown in Figure 1, the SiC semiconductor device of this embodiment has a configuration that includes a cell region 1 which is the active region where the element operates, and an outer peripheral region 2 which surrounds the cell region 1.

[0016] In addition, below the cell region 1 in Figure 1, various pads 3 are formed on the SiC semiconductor device for controlling the elements provided in the cell region 1, as well as for temperature detection.

[0017] As shown in Figure 2, the outer peripheral region 2 has a configuration that includes a guard ring portion 2a, which corresponds to the outer peripheral pressure-resistant structure portion in which the outer peripheral pressure-resistant structure is formed, and a connecting portion 2b, which is located inside the guard ring portion 2a. In other words, the outer peripheral region 2 has a configuration that includes a guard ring portion 2a and a connecting portion 2b, which is located between the cell region 1 and the guard ring portion 2a.

[0018] The following description of a SiC semiconductor device equipped with an n-channel vertical MOSFET as a trench gate semiconductor element in cell region 1 will be explained with reference to Figures 2 to 4. In the following description, one direction in the plane direction of the semiconductor substrate 10, which will be described later, will be defined as the X-axis direction, the direction intersecting one direction in the plane direction of the semiconductor substrate will be defined as the Y-axis direction, and the direction intersecting the X-axis direction and the Y-axis direction will be defined as the Z-axis direction. Here, the X-axis direction, Y-axis direction and Z-axis direction are considered to be mutually orthogonal axes. In this embodiment, the Z-axis direction corresponds to the thickness direction of the semiconductor substrate 10, which will be described later, and also corresponds to the stacking direction of the substrate 11 and the low-density layer 13, which will be described later. The Y-axis direction is, for example, the <11-20> direction.

[0019] The SiC semiconductor device is constructed using a semiconductor substrate 10 on which vertical MOSFET elements are formed. The semiconductor substrate 10 is made of n + The device is constructed by forming various semiconductor layers made of SiC on a substrate 11 of a specific type. In this embodiment, the substrate 11 is, for example, having an off-angle of 0 to 8° with respect to the (0001)Si plane, and having an n-type impurity concentration of 1.0 × 10¹⁶ such as nitrogen and phosphorus. 19 / cm 3 It is said that a substrate with a thickness of approximately 300 μm is used. In the case of a vertical MOSFET, the substrate 11 constitutes the drain region.

[0020] An n-type buffer layer 12 made of SiC is formed on the surface of the substrate 11 as needed. The buffer layer 12 is formed by epitaxial growth on the surface of the substrate 11. The n-type impurity concentration of the buffer layer 12 is set to a concentration between that of the substrate 11 and the low-concentration layer 13 described later, and the thickness is approximately 1 μm.

[0021] On the surface of buffer layer 12, for example, the n-type impurity concentration is 5.0 × 10 15 ~2.0×10 16 / cm 3 It is said that the n is made of SiC with a thickness of about 7 to 15 μm. - A low-concentration layer 13 of the type is formed. The impurity concentration of this low-concentration layer 13 may be constant in the Z-axis direction, but it is preferable that the concentration distribution is sloped so that the concentration is higher on the substrate 11 side of the low-concentration layer 13 than on the side away from the substrate 11. In this embodiment, the low-concentration layer 13 corresponds to the first impurity region.

[0022] In the surface layer portion of the low-concentration layer 13 in the cell region 1, a JFET layer 14 and a first deep layer 15 are formed. In the present embodiment, the JFET layer 14 and the first deep layer 15 each have a linear portion extending along the X-axis direction and arranged alternately and repeatedly in the Y-axis direction. That is, the JFET layer 14 and the first deep layer 15 are each formed in a stripe shape extending along the X-axis direction in the normal direction to the surface of the substrate 11 (hereinafter, also simply referred to as the normal direction), and they are configured to have a layout in which they are arranged alternately along the Y-axis direction. Note that the normal direction to the surface of the substrate 11 can also be described as when viewed from the normal direction to the surface of the substrate 11. Further, the normal direction to the surface of the substrate 11 is also the direction along the stacking direction of the drift layer 17 and the base layer 18, which will be described later, and is the direction along the Z-axis direction.

[0023] The JFET layer 14 is an n-type with an impurity concentration higher than that of the low-concentration layer 13, and its thickness is set to 0.3 to 1.5 μm. In the present embodiment, the JFET layer 14 has an n-type impurity concentration of about 5.0×10 16 ~1.0×10 17 / cm 3 The first deep layer 15 has a p-type impurity concentration of about 2.0×10 17 ~2.0×10 18 / cm 3

[0024] ​Furthermore, the first deep layer 15 may be the same depth as the JFET layer 14, or deeper or shallower than the JFET layer 14. In this embodiment, the first deep layer 15 is formed to be shallower than the JFET layer 14. In other words, the bottom of the first deep layer 15 is located within the JFET layer 14. To put it another way, the first deep layer 15 is formed so that the JFET layer 14 is located between it and the low-concentration layer 13. This suppresses the expansion of the depletion layer into the JFET layer 14 between the first deep layer 15, thereby reducing on-resistance. The JFET layer 14 and the first deep layer 15 are formed by appropriately ion-implanting impurities into the surface layer of the low-concentration layer 13.

[0025] On the other hand, in the outer peripheral region 2, the surface layer of the low-concentration layer 13 in the guard ring portion 2a is provided with multiple p-shaped guard rings 16 as an outer peripheral pressure-resistant structure, surrounding the cell region 1. In this embodiment, the upper surface layout of the guard rings 16 is a square or circular shape with rounded corners in the normal direction.

[0026] Furthermore, a p-type bonding layer 15a is provided on the surface of the low-concentration layer 13 in the bonding portion 2b of the outer peripheral region 2. The bonding layer 15a is positioned so that its inner edge surrounds the cell region 1, and its outer edge extends to the boundary with the guard ring portion 2a. The bonding layer 15a is formed by extending the first deep layer 15 to the bonding portion 2b, and has the same depth and the same p-type impurity concentration as the first deep layer 15.

[0027] Furthermore, a JFET layer 14 is formed in a portion of the connecting portion 2b within the outer peripheral region 2, specifically on the cell region 1 side of the connecting portion 2b, but not on the outside of that. Therefore, in positions where the JFET layer 14 is formed to a depth greater than the first deep layer 15, the JFET layer 14 is present below the cell region 1 side of the connecting layer 15a, but the JFET layer 14 is not present on the outer edge side or the guard ring portion 2a side of the connecting portion 2b.

[0028] Furthermore, a base layer 18, a source region 19, a contact region 20, and the like are formed on the JFET layer 14 and the first deep layer 15 in the cell region 1.

[0029] The base layer 18 is p-type and is formed on the JFET layer 14 and the first deep layer 15. Therefore, the first deep layer 15 is connected to the base layer 18. The base layer 18 has, for example, a p-type impurity concentration of 5.0 × 10⁻⁶. 16 ~2.0×10 19 / cm 3 It is said to have a thickness of approximately 2.0 μm.

[0030] Source region 19 is n + It is a type and is formed on the surface of the base layer 18. The contact area 20 is p + It is a mold and is formed on the surface of the base layer 18. Specifically, the source region 19 is formed to be in contact with the side surface of the trench 21, which will be described later, and the contact region 20 is formed on the opposite side of the trench 21, which will be described later, with the source region 19 in between. In this embodiment, the source region 19 has an n-type impurity concentration in the surface layer, i.e., a surface concentration of, for example, 1.0 × 10⁻⁶ 18 / cm 3 It is said that the thickness is approximately 0.3 μm. The contact region 20 has a p-type impurity concentration in the surface layer, i.e., a surface concentration of, for example, 1.0 × 10⁻⁶. 21 / cm 3 It is said that the thickness is approximately 0.3 μm. In this embodiment, the source region 19 corresponds to the second impurity region.

[0031] In the connecting portion 2b of the outer peripheral region 2, the low-concentration layer 13, JFET layer 14, first deep layer 15, and the base layer 18, contact region 20, and surface portion of the low-concentration layer 13 are formed on the connecting layer 15a. On the inner edge side of the connecting portion 2b, the base layer 18 and contact region 20 are formed on the connecting layer 15a and extend from the cell region 1. On the outer edge side of the connecting portion 2b, the base layer 18 and contact region 20 are not formed, and the surface portion of the low-concentration layer 13 is formed. In other words, in this embodiment, the base layer 18 and contact region 20 in the outer peripheral region 2 extend from the cell region 1 and are formed up to a certain point in the connecting portion 2b, but are not formed in the connecting portion 2b and guard ring portion 2a further out. Furthermore, from the boundary between the cell region 1 and the outer peripheral region 2 up to partway up the connecting portion 2b, the entire surface of the connecting portion 2b is designated as the contact region 20, and beyond that, the entire surface of both the connecting portion 2b and the guard ring portion 2a is designated as the low-concentration layer 13.

[0032] In this embodiment, as described above, the semiconductor substrate 10 is composed of a substrate 11, a buffer layer 12, a low-density layer 13, a JFET layer 14, a first deep layer 15, a base layer 18, a source region 19, a contact region 20, etc. Since each layer constituting the semiconductor substrate 10 is made of SiC, it can be said that the semiconductor substrate 10 is made of SiC. In addition, in this embodiment, one surface 10a of the semiconductor substrate 10 is composed of the source region 19 and the contact region 20, etc., on the inner edge side of the cell region 1 and the connecting portion 2b, while the other surface 10b of the semiconductor substrate 10 is composed of the substrate 11.

[0033] In this embodiment, the JFET layer 14, the first deep layer 15, the bridging layer 15a, the guard ring 16, the base layer 18, the source region 19, and the contact region 20 are composed of ion-implanted layers formed by ion implantation.

[0034] Furthermore, in the cell region 1, a trench 21 is formed in the semiconductor substrate 10 that penetrates the source region 19 and the base layer 18, etc., and reaches the JFET layer 14 and the first deep layer 15 from one side 10a. The trench 21 corresponds to a gate trench, and its depth is such that its bottom surface is located within the JFET layer 14 and the first deep layer 15, with a width of, for example, 0.4 to 0.8 μm.

[0035] Furthermore, multiple trenches 21 are extended along the Y-axis, and as shown in Figure 3, they are arranged at equal intervals with a gap of B1 in the X-axis direction to form a stripe pattern. In other words, in this embodiment, the trenches 21 are formed so that their longitudinal direction is perpendicular to the longitudinal direction of the first deep layer 15.

[0036] At the bottom of the trench 21, a second deep layer 30, which serves as an electric field relaxation layer, is formed so as to be in contact with the bottom surface of the trench 21. In this embodiment, the second deep layer 30 is composed of a p-type layer with a lower impurity concentration than the first deep layer 15. Specifically, the second deep layer 30 is formed along the longitudinal direction of the trench 21. In other words, the second deep layer 30 extends along the Y-axis direction that intersects with the first deep layer 15. Furthermore, in this embodiment, the second deep layer 30 is formed so that its bottom surface penetrates the JFET layer 14 and the first deep layer 15 and reaches the low-concentration layer 13.

[0037] By forming the second deep layer 30 along the bottom surface of the trench 21, the penetration of the electric field into the gate insulating film 22 located at the bottom of the trench 21 can be suppressed, thereby suppressing oxide film breakdown. Furthermore, by forming the second deep layer 30 so as to be in contact with the bottom surface of the trench 21, the capacitance between the gate electrode 23 and the lower electrode 28, i.e., the feedback capacitance, can be reduced, thereby improving the switching speed. Moreover, since the second deep layer 30 is formed so that its bottom surface penetrates the JFET layer 14 and the first deep layer 15 and reaches the low-concentration layer 13, the creeping of the electric field to the JFET layer 14 arranged between the second deep layers 30 is suppressed, thereby improving the breakdown voltage. In addition, breakdown is more likely to occur in the second deep layer 30 that protrudes downward when an overvoltage is applied, making it easier to cause breakdown in the cell region 1, thereby improving the avalanche withstand capability.

[0038] The second deep layer 30 may be formed by dividing it into multiple sections along the Y-axis. However, the second deep layer 30 is formed to be electrically connected to the base layer 18 via the first deep layer 15.

[0039] Furthermore, a gate insulating film 22 is formed on the inner wall surface of the trench 21, and a gate electrode 23 made of doped poly-Si or the like is formed on the gate insulating film 22. This constitutes a trench gate structure. The gate insulating film 22 is formed by thermal oxidation of the inner wall surface of the trench 21 or by depositing an insulating film using the CVD (chemical vapor deposition) method. The thickness of the gate insulating film 22 is approximately 100 nm on both the side and bottom surfaces of the trench 21.

[0040] The gate insulating film 22 is formed not only on the inner wall surface of the trench 21 but also on one surface 10a of the semiconductor substrate 10. In the cell region 1, a contact hole 22a is formed in the gate insulating film 22, exposing the source region 19 and the contact region 20.

[0041] A field oxide film 241 is formed on one surface 10a of the semiconductor substrate 10, surrounding the outer edge of the cell region 1. Furthermore, an interlayer insulating film 242 is formed to cover the gate electrode 23, gate insulating film 22, and the field oxide film 241, etc. The interlayer insulating film 242 is made of BPSG (abbreviation for Borophosphosilicate Glass), etc. Note that in Figure 2, the field oxide film 241 and interlayer insulating film 242, etc. located above the surface 10a of the semiconductor substrate 10 have been omitted.

[0042] As shown in Figure 3, the interlayer insulating film 242 has a contact hole 242a in the cell region 1 that communicates with the contact hole 22a and exposes the source region 19 and the contact region 20. Also, as shown in Figure 4, the interlayer insulating film 242 has a contact hole 242b that exposes the portion of the gate electrode 23 that extends to the connecting portion 2b.

[0043] An upper electrode 25 is formed on the interlayer insulating film 242, which is electrically connected to the source region 19 and the contact region 20 through contact holes 22a and 242a. The upper electrode 25 is designed to allow electrical connection to the outside. In this embodiment, the upper electrode 25 corresponds to the first electrode. In addition, a gate wiring 26 is formed on the interlayer insulating film 242, which is electrically connected to the gate electrode 23 through contact hole 242b. The gate wiring 26 is not shown in Figure 1, but is formed along the outer edge of the cell region 1, for example, along the right, left, and bottom sides of the rectangular chip SiC semiconductor device shown in Figure 1.

[0044] As described above, the JFET layer 14 is formed only on the cell region 1 side of the cell region 1 and the connecting portion 2b, but is not positioned below the gate wiring 26. In other words, the outer peripheral termination position Po of the JFET layer 14, which is located on the outer peripheral side of the cell region 1, is located on the cell region 1 side of the inner peripheral termination position Pi of the gate wiring 26, which is located on the cell region 1 side. Outside the inner peripheral termination position Pi, either a connecting layer 15a is formed or a low-density layer 13 is formed.

[0045] The upper electrode 25 of this embodiment is composed of multiple metals, such as Ni / Al. Of the multiple metals, the portion that contacts the n-type SiC, i.e., the portion constituting the source region 19, is composed of a metal capable of ohmic contact with the n-type SiC. Furthermore, at least the portion of the multiple metals that contacts the p-type SiC, i.e., the contact region 20, is composed of a metal capable of ohmic contact with the p-type SiC. The gate wiring 26 may have the same configuration as the upper electrode 25, or it may be composed of Al-Si or the like.

[0046] Furthermore, a protective film 27 made of polyimide or the like is formed to cover the connecting portion 2b and the guard ring portion 2a. In this embodiment, the protective film 27 is formed from the outer peripheral region 2 to the outer edge of the cell region 1 in order to suppress the occurrence of creepage discharge between the upper electrode 25 and the lower electrode 28, which will be described later. Specifically, in the cell region 1, the protective film 27 is formed to cover the portion of the upper electrode 25 on the outer peripheral region 2 side while exposing the portion of the upper electrode 25 on the inner edge side.

[0047] A lower electrode 28 is formed on the other side 10b of the semiconductor substrate 10, which is electrically connected to the substrate 11. In this embodiment, the lower electrode 28 corresponds to the second electrode.

[0048] In the SiC semiconductor device of this embodiment, a trench gate structure MOSFET with an n-channel inverting type is formed by this structure.

[0049] The above describes the configuration of the SiC semiconductor device in this embodiment. In this embodiment, n - type, n type, n + The type corresponds to the first conductivity type, p type, p + The type corresponds to the second conductivity type. Next, the operation of the above SiC semiconductor device will be explained.

[0050] First, in the SiC semiconductor device described above, in the off state before a gate voltage is applied to the gate electrode 23, no inversion layer is formed in the base layer 18. Therefore, even if a positive voltage, for example 1600V, is applied to the lower electrode 28, electrons do not flow from the source region 19 into the base layer 18, and no current flows between the upper electrode 25 and the lower electrode 28.

[0051] Furthermore, before a gate voltage is applied to the gate electrode 23, an electric field is applied between the drain and the gate, which can cause electric field concentration at the bottom of the gate insulating film 22. However, in the SiC semiconductor device described above, the first deep layer 15 and the JFET layer 14 are located deeper than the trench 21. As a result, the depletion layer formed between the first deep layer 15 and the JFET layer 14 suppresses the rise of equipotential lines due to the influence of the drain voltage, making it difficult for high electric fields to penetrate the gate insulating film 22. Moreover, since a second deep layer 30, which acts as an electric field relaxation layer, is provided at the bottom of the trench 21, it becomes even more difficult for high electric fields to penetrate the gate insulating film 22. Therefore, in this embodiment, the destruction of the gate insulating film 22 can be suppressed.

[0052] Furthermore, when a predetermined gate voltage is applied to the gate electrode 23, a channel is formed on the surface of the base layer 18 that is in contact with the trench 21. As a result, electrons injected from the upper electrode 25 pass through the channel formed in the base layer 18 from the source region 19, then through the JFET layer 14 to the low-concentration layer 13, and then through the substrate 11, which acts as the drain layer, to the lower electrode 28. This causes a current to flow between the upper electrode 25 and the lower electrode 28, turning on the SiC semiconductor device. In this embodiment, since the electrons that pass through the channel pass through the JFET layer 14 and the low-concentration layer 13 to the substrate 11, it can be said that a drift layer 17 having the JFET layer 14 and the low-concentration layer 13 is configured.

[0053] Here, as described above, the JFET layer 14 is placed only on the cell region 1 side of the cell region 1 and the junction 2b, and not on the outside. This configuration improves the switching withstand capability when turning the vertical MOSFET on and off based on the application of the gate voltage. This switching withstand capability will be explained below.

[0054] Figure 5 shows a comparative example where the JFET layer 14 is formed not only in the cell region 1 but also in the junction 2b and other areas. Figure 5 shows the displacement current A1 in a cross-section of a SiC semiconductor device cut along the Y direction, which is the longitudinal direction of the trench gate structure, between adjacent trench gate structures, i.e., in a location that is not a trench gate structure.

[0055] During high-speed switching of a vertical MOSFET, a displacement current A1 flows as shown by the dashed arrow in Figure 5. Specifically, in the outer peripheral region 2, the displacement current A1 flows from the lower electrode 28 through the substrate 11, the low-concentration layer 13, and the JFET layer 14 to the bridging layer 15a, then to the base layer 18 and the contact region 20, and within the contact region 20, it flows to the upper electrode 25 while moving in the plane direction of the semiconductor substrate 10. The displacement current A1 at this time is proportional to the time change dV / dt of the high voltage generated during switching. Furthermore, the higher the impurity concentration of the p-type and n-type layers constituting the pn junction in the outer peripheral region 2, the larger the source-drain capacitance, which increases the time change dV / dt and thus the larger the displacement current A1. In the comparative example shown in Figure 5, when a JFET layer 14 is formed in the bridging portion 2b, the pn junction is composed of the JFET layer 14 and the bridging layer 15a, resulting in a higher impurity concentration. Therefore, when the displacement current A1 becomes large and electric field concentration occurs, the thin gate insulating film 22 is destroyed, and the switching withstand capability is lost. In particular, dielectric breakdown occurs at the boundary position RB between the gate insulating film 22 and the field oxide film 241, as shown in the figure.

[0056] In contrast, if the JFET layer 14 is not provided on at least the outer edge side of the connecting portion 2b, as in this embodiment, the pn junction in that portion will be composed of a low-concentration layer 13 and a first deep layer 15. Because of this structure, in this embodiment, the impurity concentrations of the p-type and n-type layers constituting the pn junction are smaller compared to the comparative example, and the displacement current A1 that occurs when the voltage surges during switching can be reduced. As a result, electric field concentration caused by the displacement current A1 is mitigated, the breakdown of the gate insulating film 22 can be suppressed, and the switching withstand capability can be improved.

[0057] In particular, the electric field applied to the gate insulating film 22 tends to be large below the gate wiring 26. For this reason, it is preferable to prevent the formation of the JFET layer 14 below the gate wiring 26, and to ensure that the outer peripheral termination position Po, which is the outer peripheral termination position of the cell region 1 of the JFET layer 14, is closer to the cell region 1 than the inner peripheral termination position Pi of the gate wiring 26. With such a structure, the breakdown of the gate insulating film 22 can be further suppressed, and the switching withstand capability can be improved.

[0058] Next, the manufacturing method for the SiC semiconductor device of this embodiment will be described with reference to Figures 6A to 6E. Figures 6A to 6E show the manufacturing process corresponding to the cross-section of the cell region 1 and the connecting portion 2b in Figure 4.

[0059] First, as shown in Figure 6A, a substrate 11 is prepared, and then a buffer layer 12 and a low-concentration layer 13 are epitaxially grown on one side of the substrate 11. Then, a mask (not shown) with an opening corresponding to the JFET layer 14 is placed on the surface of the low-concentration layer 13, and then n-type impurities are ion-implanted to form the JFET layer 14.

[0060] Next, a mask (not shown) with an opening corresponding to the first deep layer 15 is formed, and then p-type impurities are ion-implanted to form the first deep layer 15 as shown in Figure 6B. At this time, the JFET layer 14 is formed up to the portion that will become the first deep layer 15, but by increasing the dose of p-type impurities, it can be converted back to p-type to form the first deep layer 15. After that, a mask (not shown) with an opening corresponding to the base layer 18 is formed, and then p-type impurities are ion-implanted to form the base layer 18. Furthermore, using a mask with an opening corresponding to the contact region 20, p-type impurities are further ion-implanted to form the contact region 20 on top of the base layer 18.

[0061] After this, a mask (not shown) is formed with an opening corresponding to the source region 19, and then n-type impurities are ion-implanted to form the source region 19 as shown in Figure 6C. At this time, the contact region 20 is formed up to the part that will become the source region 19, but by increasing the dose of n-type impurities, it can be converted back to n-type and the source region 19 can be formed.

[0062] Next, as shown in Figure 6D, a mask 50 with an opening corresponding to the trench 21 is placed, and then the trench 21 is formed by dry etching. Furthermore, p-type impurities are ion-implanted using the same mask 50 to form a second deep layer 30 at the bottom of the trench 21.

[0063] Next, as shown in Figure 6E, a gate insulating film 22 is formed by thermal oxidation or CVD, and then a gate electrode 23 is formed by doped polysilicon film deposition and patterning. Furthermore, after the process of forming the field oxide film 241 and the interlayer insulating film 242 is carried out, contact holes 242a and 242b are formed in the interlayer insulating film 242. After that, the process of forming the upper electrode 25 and gate wiring 26, the process of forming the protective film 27, and the process of forming the lower electrode 28 on the back side of the substrate 11 are carried out using conventional processes. This completes the SiC semiconductor device according to this embodiment.

[0064] In this SiC semiconductor device, the JFET layer 14 is formed on the cell region 1 side of the junction 2b, but not on the outside of it. Furthermore, the JFET layer 14 is not located below the gate wiring 26 in the junction 2b, but is located only on the cell region 1 side of the gate wiring 26.

[0065] As described above, in the SiC semiconductor device of this embodiment, a JFET layer 14 is formed on the cell region 1 side of the junction 2b, but not on the outside of it. Therefore, the pn junction on the outer edge side of the junction 2b is composed of a low-concentration layer 13 and a first deep layer 15. With this structure, the impurity concentrations of the p-type and n-type layers constituting the pn junction are reduced, and the displacement current A1 that occurs when the voltage surges during switching can be reduced. Therefore, electric field concentration caused by the displacement current A1 is mitigated, the breakdown of the gate insulating film 22 can be suppressed, and the switching withstand capability can be improved. Furthermore, this effect can be obtained regardless of the rate-limiting location of the withstand capability. Thus, it is possible to create a SiC semiconductor device that can improve the switching withstand capability regardless of the rate-limiting location of the withstand capability. In addition, because the switching withstand capability can be improved, it is possible to achieve high-speed switching of vertical MOSFETs.

[0066] In particular, the electric field applied to the gate insulating film 22 tends to be large below the gate wiring 26, but the JFET layer 14 is not formed in that area, and the outer peripheral termination position Po of the JFET layer 14 is located on the cell region 1 side of the inner peripheral termination position Pi of the gate wiring 26. As a result, the breakdown of the gate insulating film 22 can be further suppressed, and the switching withstand capability can be improved.

[0067] Furthermore, as described in Patent Document 1, shortening the distance of the current path causes the ends of structures such as source contacts, field oxide films, and trenches to become densely packed. This makes it difficult to manufacture each component with high precision, leading to an unstable manufacturing process and reduced yield. In contrast, the configuration of this embodiment allows for improved switching withstand capability regardless of the distance of the current path, thus suppressing a decrease in yield.

[0068] Furthermore, since the switching withstand capability can be improved simply by limiting the formation position of the JFET layer 14 to the cell region 1 side of the cell region 1 and the connecting portion 2b, it is only necessary to change the mask used to form the JFET layer 14 compared to the conventional manufacturing method. This makes it possible to simplify the manufacturing process.

[0069] (Second Embodiment) A second embodiment will now be described. This embodiment is similar to the first embodiment in that the formation range of the JFET layer 14 and other aspects are changed, but other aspects are the same as the first embodiment, so only the parts that differ from the first embodiment will be described.

[0070] In the first embodiment, the JFET layer 14 was formed on the cell region 1 side of the cell region 1 and the connecting portion 2b, but in this embodiment, the formation range of the JFET layer 14 is limited to the cell region 1 only.

[0071] Furthermore, in the first embodiment, the formation ranges of the ion implantation layer for forming the JFET layer 14 and the source region 19 were set separately, but in this embodiment, the formation ranges of the ion implantation layer for forming the JFET layer 14 and the source region 19 are aligned in the direction normal to the surface of the substrate 11.

[0072] Specifically, as shown in Figure 7, the JFET layer 14 is formed only in the cell region 1, and not in the outer peripheral region 2, which includes the connecting portion 2b. Furthermore, the formation range of the ion implantation layer when forming the JFET layer 14 is limited to the cell region 1. In addition, as shown in Figure 8B, which will be described later, the ion implantation range for n-type impurities when forming the source region 19 is the same as the formation range of the JFET layer 14.

[0073] The formation range of the ion implantation layer for forming the JFET layer 14 refers to the entire range in which n-type impurities are ion-implanted when forming the JFET layer 14, as viewed from the normal direction of the substrate 11. This range also includes the portion that becomes the p-type first deep layer 15 due to the reversal of p-type impurities. Similarly, the formation range of the ion implantation layer for forming the source region 19 refers to the entire range in which n-type impurities are ion-implanted when forming the source region 19, as viewed from the normal direction of the substrate 11. This range also includes the portion that becomes the p-type contact region 20 due to the reversal of p-type impurities. Furthermore, aligning the formation ranges of the ion implantation layers means that while it is preferable for them to be the same, they are manufactured with the aim of achieving the same formation range, and manufacturing tolerances are acceptable. The dashed line shown in Figure 7 indicates the ion implantation range of n-type impurities when forming the source region 19.

[0074] In this way, by aligning the formation range of the ion implantation layer when forming the JFET layer 14 and the source region 19, the ion implantation mask can be standardized when forming the JFET layer 14 and the source region 19 by ion implantation. The manufacturing method of the SiC semiconductor device according to this embodiment will be described with reference to Figures 8A to 8E. Figures 8A to 8E show the manufacturing process corresponding to the cross-section of the cell region 1 and the connecting portion 2b in Figure 4.

[0075] First, in the process shown in Figure 8A, a buffer layer 12 and a low-concentration layer 13 are formed on the substrate 11, similar to Figure 6A, and then a JFET layer 14 is formed. At this time, a mask 51 with an opening corresponding to the JFET layer 14 is placed on the surface of the low-concentration layer 13, and then n-type impurities are ion-implanted to form the JFET layer 14, so that ion implantation is performed only in the cell region 1. Subsequently, as shown in Figure 8B, the same mask 51 used during the formation of the JFET layer 14 is used to ion-implant n-type impurities to form the source region 19. Note that the implantation depth is varied by changing the ion implantation energy for the formation of the JFET layer 14 and the source region 19.

[0076] Next, in the process shown in Figure 8C, the first deep layer 15, the base layer 18, and the contact region 20 are formed by performing the same process as in Figure 6C. When forming the contact region 20, the source region 19 is formed up to the part that will become the contact region 20, but by increasing the dose of p-type impurities, it can be converted back to p-type to form the contact region 20.

[0077] Furthermore, as shown in Figure 8D, the same process as in Figure 6D is performed to form the trench 21, and then the second deep layer 30 is formed. Furthermore, as shown in Figure 8E, the same process as in Figure 6E is performed to form the gate insulating film 22, the gate electrode 23, the field oxide film 241 and the interlayer insulating film 242, and the contact holes 242a and 242b in the interlayer insulating film 242. After that, the upper electrode 25 and gate wiring 26 are formed, the protective film 27 is formed, and the lower electrode 28 is formed on the back side of the substrate 11. This completes the SiC semiconductor device according to this embodiment.

[0078] As described above, in this embodiment, the formation range of the ion implantation layer for forming the JFET layer 14 and the source region 19 is made uniform. This allows the ion implantation mask for the JFET layer 14 and the source region 19 to be shared, making it possible to simplify the manufacturing process and reduce manufacturing costs.

[0079] (Other embodiments) This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and idea of ​​this disclosure.

[0080] For example, in each of the above embodiments, the connecting portion 2b is structured to have a base layer 18 and a contact region 20 on the surface of the low-concentration layer 13, but it is also possible to have a structure in which one or both of these are not provided in the connecting portion 2b. When the base layer 18 is formed only in the cell region 1, the base layer 18 can also be formed using the ion implantation mask for the JFET layer 14 and the source region 19, as in the second embodiment. In this way, the ion implantation mask for the base layer 18 can be shared with the JFET layer 14 and the source region 19, making it possible to further simplify the manufacturing process and reduce manufacturing costs.

[0081] In the first embodiment described above, the outer peripheral termination position Po of the JFET layer 14 in the junction 2b is located on the cell region 1 side of the inner peripheral termination position Pi of the gate wiring 26, and outside of that, either a junction layer 15a is formed or a low-concentration layer 13 is formed. In other words, the JFET layer 14 is not formed outside the inner peripheral termination position Pi of the gate wiring 26. Alternatively, the JFET layer 14 may be formed outside the inner peripheral termination position Pi of the gate wiring 26, while ensuring that the n-type impurity concentration in that portion is less than or equal to that of the low-concentration layer 13. In this way, even if the JFET layer 14 is formed, if the n-type impurity concentration is reduced outside the inner peripheral termination position Pi of the gate wiring 26, the impurity concentrations of the p-type and n-type layers constituting the pn junction in the outer peripheral region 2 will be reduced, and the source-drain capacitance can be reduced. Therefore, the same effects as in the first embodiment can be obtained.

[0082] Furthermore, in the above embodiment, the bottom surface of the second deep layer 30 may be made shallower so that it is located within the JFET layer 14 and the first deep layer 15. In other words, the second deep layer 30 may be formed so as not to reach the low-concentration layer 13. This makes it difficult for the depletion layer to extend from the second deep layer 30, thereby reducing the on-resistance.

[0083] Furthermore, in the first embodiment described above, the JFET layer 14, the first deep layer 15, the base layer 18, and the contact region 20 or source region 19 were formed by ion implantation. Some or all of these may be composed of epitaxial layers formed by epitaxial growth.

[0084] Furthermore, in the above embodiment, a base layer 18 was formed on the surfaces of the JFET layer 14 and the first deep layer 15, but an n-type current dispersion layer with a higher n-type impurity concentration than the low-concentration layer 13 may be formed between them. In that case, in addition to the current dispersion layer, p-type connecting layers may be formed on both sides of the trench 21, and the base layer 18 may be formed on top of these current dispersion layers and connecting layers. In this case, the first deep layer 15 and the base layer 18 will be connected through the connecting layers. Also, the low-concentration layer 13, the JFET layer 14, and the current dispersion layer will be connected, and these will constitute the drift layer 17. Even in such a structure, the second deep layer 30 may be formed to a depth greater than the first deep layer 15, or it may be formed to a depth within the thickness of the first deep layer 15.

[0085] Furthermore, in the above embodiments, a vertical MOSFET with an n-channel trench gate structure, where the first conductivity type is n-type and the second conductivity type is p-type, was given as an example of a semiconductor element provided in the cell region 1. However, this is merely one example, and for example, a vertical MOSFET with a p-channel trench gate structure, where the conductivity types of each component are reversed compared to the n-channel type, may also be used. Moreover, instead of a vertical MOSFET, a vertical IGBT with a similar structure may also be used. In the case of an IGBT, it is the same as the vertical MOSFET described in the above embodiments, except that the conductivity type of the substrate 11 in each of the above embodiments is changed from n-type to p-type.

[0086] In addition, when indicating the orientation of a crystal, a bar (-) should ideally be placed above the desired number. However, due to the limitations on expression imposed by electronic filing, a bar is placed before the desired number in this specification. [Explanation of symbols]

[0087] 1...Cell area, 2...Outer perimeter area, 2a...Guard ring area, 2b...Connecting area, 11...Substrate 13...Low concentration layer (first impurity region), 14...JFET layer, 15...First deep layer 16...Guard ring, 17...Drift layer, 18...Base layer, 19...Source region 20... Contact area, 21... Trench, 22... Gate insulating film, 23... Gate electrode 24...Interlayer insulating film, 25...Upper electrode (first electrode), 26...Gate wiring 27…Protective film, 28…Lower electrode (second electrode), 30…Second deep layer Pi... Inner circumference end position, Po... Outer circumference end position

Claims

1. A silicon carbide semiconductor device having a cell region (1) on which a trench gate semiconductor element is formed, and an outer peripheral region (2) surrounding the cell region, which is provided with an outer peripheral breakdown structure portion (2a) constituting an outer peripheral breakdown structure (16) and a connecting portion (2b) located between the outer peripheral breakdown structure portion and the cell region, A substrate (11) made of first-conductivity type or second-conductivity type silicon carbide, It has a first impurity region (13) of a first conductivity type formed on the substrate and having a lower impurity concentration than the substrate, The aforementioned cell region includes: A JFET layer (14) is formed on the surface of the first impurity region and consists of a first conductivity type silicon carbide with a higher impurity concentration than the first impurity region, A deep layer (15) made of second-conductivity silicon carbide is formed on the surface of the first impurity region and is arranged alternately with the JFET layer in the planar direction of the substrate, A base layer (18) made of second-conductivity silicon carbide formed on the JFET layer and the deep layer, A trench gate structure having a gate insulating film (22) formed on the inner wall surface of multiple gate trenches (21) arranged in a row with one direction being the longitudinal direction and deeper than the base layer, and a gate electrode (23) formed on the gate insulating film within the gate trench, A second impurity region (19) is formed in contact with the trench gate structure in the surface portion of the base layer and consists of a first conductive type of silicon carbide with a higher impurity concentration than the first impurity region, A first electrode (25) electrically connected to the second impurity region and the base layer, The semiconductor element is configured having a second electrode (28) arranged on the back side of the substrate and electrically connected to the substrate, The aforementioned connecting portion includes, The gate insulating film extends from the cell region and is formed on the first impurity region, The gate electrode extends from the cell region and is disposed on the gate insulating film, The gate wiring (26) connected to the gate electrode is provided, A silicon carbide semiconductor device in which the outer peripheral termination position (Po), which is the outer peripheral termination position of the cell region in the JFET layer, is located closer to the cell region than the inner peripheral termination position (Pi), which is the cell region-side termination position in the gate wiring.

2. The silicon carbide semiconductor device according to claim 1, wherein the JFET layer is formed only in the cell region.

3. The silicon carbide semiconductor device according to claim 1 or 2, wherein the formation range of the ion implantation layer for forming the JFET layer and the formation range of the ion implantation layer for forming the second impurity region are aligned in the direction normal to the surface of the substrate.

4. The silicon carbide semiconductor device according to claim 1 or 2, wherein, in the direction normal to the surface of the substrate, the formation range of the ion implantation layer for forming the JFET layer, the formation range of the ion implantation layer for forming the second impurity region, and the formation range of the ion implantation layer for forming the base layer are aligned.

5. A silicon carbide semiconductor device having a cell region (1) on which a trench gate semiconductor element is formed, and an outer peripheral region (2) surrounding the cell region, which is provided with an outer peripheral breakdown structure portion (2a) constituting an outer peripheral breakdown structure (16) and a connecting portion (2b) located between the outer peripheral breakdown structure portion and the cell region, A substrate (11) made of first-conductivity type or second-conductivity type silicon carbide, It has a first impurity region (13) of a first conductivity type formed on the substrate and having a lower impurity concentration than the substrate, The aforementioned cell region includes: A JFET layer (14) is formed on the surface of the first impurity region and consists of a first conductivity type silicon carbide with a higher impurity concentration than the first impurity region, A deep layer (15) made of second-conductivity silicon carbide is formed on the surface of the first impurity region and is arranged alternately with the JFET layer in the planar direction of the substrate, A base layer (18) made of second-conductivity silicon carbide formed on the JFET layer and the deep layer, A trench gate structure having a gate insulating film (22) formed on the inner wall surface of multiple gate trenches (21) arranged in a row with one direction being the longitudinal direction and deeper than the base layer, and a gate electrode (23) formed on the gate insulating film within the gate trench, A second impurity region (19) is formed in contact with the trench gate structure in the surface portion of the base layer and consists of a first conductive type of silicon carbide with a higher impurity concentration than the first impurity region, A first electrode (25) electrically connected to the second impurity region and the base layer, The semiconductor element is configured having a second electrode (28) arranged on the back side of the substrate and electrically connected to the substrate, The aforementioned connecting portion includes, The gate insulating film extends from the cell region and is formed on the first impurity region, The gate electrode extends from the cell region and is disposed on the gate insulating film, The gate wiring (26) connected to the gate electrode is provided, The JFET layer is also formed in the connecting portion, and the portion of the JFET layer outside the inner circumference termination position (Pi), which is the termination position on the cell region side of the gate wiring, has a first conductivity type impurity concentration that is less than or equal to the first impurity region, in a silicon carbide semiconductor device.

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