Field-effect transistor with reduced parasitic capacitance and resistance

Abstract

A field effect transistor includes a gate structure formed adjacent a source / drain region and a spacer structure formed between the gate structure and the source / drain region, the spacer structure having a top spacer and a bottom spacer, the top spacer including an air gap having a bottom portion that is wider than a top portion, the wider bottom portion of the air gap being located between the gate structure and the source / drain region.

Description

Technical Field

[0001] The present invention generally relates to the field of semiconductor devices, and more particularly to forming field effect transistor devices having reduced parasitic capacitance and resistance.

[0002] Complementary metal oxide semiconductor (CMOS) technology is commonly used to fabricate field effect transistors (FETs) as part of advanced integrated circuits (ICs) such as CPUs, memories, memory devices, etc. As the size of integrated circuits continues to scale down, growth in CMOS technology is needed to achieve higher device density without sacrificing production cost and without affecting performance and / or reliability. However, as device dimensions and component spacing continue to shrink to meet the increasing demand for smaller electronic devices, parasitic capacitance and parasitic resistance increase, resulting in undesirable effects such as RC delay, power dissipation, and capacitive coupled signals also known as crosstalk.

Summary of the Invention

[0003] According to one embodiment of the present invention, a semiconductor structure includes a gate structure positioned adjacent to a source / drain region; and a spacer structure positioned between the gate structure and the source / drain region, wherein the spacer structure has a bottom spacer and a top spacer having an air gap, the air gap in the top spacer has a bottom portion that is wider than a top portion, and the wider bottom portion of the air gap is positioned between the gate structure and the source / drain region.

[0004] According to another embodiment of the present invention, the semiconductor structure comprises a metal gate stack in contact with a first portion of a channel layer on a substrate, wherein the first portion of the channel layer is located between source / drain regions; a first spacer located above a second portion of the channel layer extending outward from the metal gate stack, wherein the first spacer is positioned between the bottom portion of the metal gate stack and the portion of the source / drain region located above the substrate; and a contact structure above the source / drain region, wherein the contact structure is in contact with a second spacer located above the first spacer and between the contact structure and the metal gate stack, the second spacer including an air gap having a bottom portion that is wider than the top portion, the wider bottom portion of the air gap being positioned between the metal gate stack and the respective source / drain regions.

[0005] According to another embodiment of the present invention, a method for forming a semiconductor structure comprises the steps of: forming a metal gate stack in contact with a first portion of a channel layer on a substrate, wherein the first portion of the channel layer is located between source / drain regions; forming a first spacer above a second portion of the channel layer extending outward from the metal gate stack, wherein the first spacer is formed between the bottom portion of the metal gate stack and the portion of the source / drain region located above the substrate; forming a contact structure above the source / drain region; and forming a second spacer above the first spacer and between the contact structure and the metal gate stack, wherein the second spacer includes an air gap having a bottom portion that is wider than the top portion, the wider bottom portion of the air gap being located between the metal gate stack and the respective source / drain regions. [Brief explanation of the drawing]

[0006] The following detailed description is provided for illustrative purposes only and is not intended to limit the invention to the present invention, and will be best understood in conjunction with the accompanying drawings.

[0007] [Figure 1] This is a cross-sectional view of a semiconductor structure in an intermediate stage during a semiconductor manufacturing process, according to one embodiment of the present invention.

[0008] [Figure 1A] This is a top view of a semiconductor structure.

[0009] [Figure 2] This is a cross-sectional view of a semiconductor structure after a layer of spacer material has been deposited, according to one embodiment of the present invention.

[0010] [Figure 3] This is a cross-sectional view of a semiconductor structure after etching a spacer material to form a first spacer, according to one embodiment of the present invention.

[0011] [Figure 4] This is a cross-sectional view of a semiconductor structure after the source / drain region and sacrificial cap have been formed, according to one embodiment of the present invention.

[0012] [Figure 5] This is a cross-sectional view of a semiconductor structure after partially removing the first spacer, according to one embodiment of the present invention.

[0013] [Figure 6] This is a cross-sectional view of a semiconductor structure after a sacrificial spacer has been formed, according to one embodiment of the present invention.

[0014] [Figure 7] This is a cross-sectional view of a semiconductor structure after etching the sacrificial spacer, according to one embodiment of the present invention.

[0015] [Figure 8]A cross-sectional view of a semiconductor structure after a replacement metal gate process according to an embodiment of the present invention.

[0016] [Figure 9] A cross-sectional view of a semiconductor structure after patterning a first dielectric layer and forming a contact trench according to an embodiment of the present invention.

[0017] [Figure 10] A cross-sectional view of a semiconductor structure after selectively removing a sacrificial cap according to an embodiment of the present invention.

[0018] [Figure 11] A cross-sectional view of a semiconductor structure after forming a contact structure in a contact trench according to an embodiment of the present invention.

[0019] [Figure 12] A cross-sectional view of a semiconductor structure after removing a sacrificial spacer according to an embodiment of the present invention.

[0020] [Figure 13] A cross-sectional view of a semiconductor structure after removing an exposed portion of a contact liner according to an embodiment of the present invention.

[0021] [Figure 14] A cross-sectional view of a semiconductor structure after depositing a second dielectric layer and forming an air gap spacer according to an embodiment of the present invention.

[0022] The drawings are not necessarily to scale. The drawings are only schematic representations and are not intended to depict specific parameters of the present invention. The drawings are intended to show only typical embodiments of the present invention. In the drawings, like reference numerals represent like elements.

Mode for Carrying Out the Invention

[0023] Detailed embodiments of the claimed structure and method are disclosed herein; however, it should be understood that the disclosed embodiments are merely illustrative of the claimed structure and method, which may be embodied in various forms. Nevertheless, the present invention may be embodied in many different forms and should not be construed as being limited to the exemplary embodiments described herein. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0024] For the purposes of the following description in this specification, terms such as “upper,” “lower,” “right,” “left,” “vertical,” “horizontal,” “top,” “bottom,” and their derivatives shall refer to the structures and methods disclosed as oriented in the drawings. Terms such as “above,” “covering,” “top of,” “on top of,” “positioned on,” or “positioned on top of” mean that a first element of a first structure, etc., is located on a second element of a second structure, etc., and an intervening element, such as an interface structure, may be located between the first and second elements. The term “direct contact” means that a first element of a first structure, etc., and a second element of a second structure, etc., are connected at the interface of the two elements without any intermediate conductive, insulating, or semiconductor layers.

[0025] To avoid ambiguity in the presentation of embodiments of the present invention, in the following detailed description, some processing steps or operations known in the art may be combined for presentation and illustrative purposes, and in some cases they may not be described in detail. In other cases, some processing steps or operations known in the art may not be described at all. It should be understood that the following description focuses rather on the specific features or elements of various embodiments of the present invention.

[0026] As device dimensions and component spacing continue to shrink to meet the growing demand for smaller electronic devices, parasitic capacitance and resistance increase, thereby expanding power consumption and degrading device performance.

[0027] The formation of air gap spacers is being explored as an alternative to reducing parasitic capacitance in current CMOS technology. Conventional methods form air gap spacers by first depositing sacrificial spacers on the gate sidewall, forming the source / drain region and contacts, and then removing the sacrificial spacers after the source / drain region and contacts have been formed to create an air gap between the gate and the source / drain contacts. Furthermore, the formation of wrap-around contacts (WACs) on the source / drain region is being considered as a viable option to reduce contact resistance by increasing the contact area between the metal contacts and the source / drain region. However, conventional methods for forming air gap spacers and wrap-around contacts have the following drawbacks: 1) recessing sacrificial spacers into the channel region impairs the high-k / metal gate stack, which results in a threshold voltage shift, and 2) although WACs reduce contact resistance, the narrow width of the metal contacts results in high contact through resistance.

[0028] Accordingly, embodiments of the present invention provide a field-effect transistor device and a method for fabricating the same that can simultaneously form an air gap spacer and a wrap-around contact to simultaneously reduce parasitic capacitance and parasitic resistance. The proposed field-effect transistor includes a self-aligned sacrificial cap layer formed above the source / drain region during source / drain epitaxy. The sacrificial cap allows for the removal of most of the low-k spacer material from the gate sidewall while maintaining the low-k spacer material positioned adjacent to the channel region of the device. A new sacrificial spacer substantially thinner than the original low-k spacer is formed on the gate sidewall while the sacrificial cap is removed during contact patterning to allow for the formation of a wrap-around contact (WAC). After the WAC is formed, the sacrificial spacer is selectively removed relative to the original low-k spacer to form an air gap spacer. In the proposed embodiment, the high-k / metal gate around the channel region is completely protected by the low-k spacer. After the WAC is formed and the sacrificial spacer is removed, the inner portion of the contact liner located on the WAC sidewall can be removed to increase the size of the air gap spacer to meet reliability requirements while reducing contact through resistance.

[0029] Embodiments in which an air gap spacer and WAC can be formed to simultaneously reduce parasitic capacitance and resistance are described in detail below with reference to the accompanying drawings in Figures 1 to 14.

[0030] Referring here to Figures 1 to 1A, a cross-sectional view of a semiconductor structure 100 in an intermediate stage of a semiconductor manufacturing process, cut along line AA in Figure 1A, is shown according to one embodiment of the present invention. In this embodiment, Figure 1A is a top view of the semiconductor structure 100. Specifically, Figure 1 shows a cross-sectional view of the semiconductor structure 100 cut along a fin 120 formed by patterning a substrate 102 using a method well known in the art.

[0031] While the disclosed embodiments include a detailed description of exemplary FinFET architectures, it should be understood that implementations of the teachings described herein are not limited to the specific FET architectures described herein. Rather, embodiments of the present invention can be implemented in conjunction with any other type of FET device currently known or to be developed, including, but not limited to, planar FETs, FinFETs, nanowire transistors, nanosheet transistors, nanoribbon transistors, and the like.

[0032] Conventional techniques related to the manufacture of semiconductor devices and ICs may or may not be described in detail herein. Furthermore, various tasks and process steps described herein can be incorporated into more comprehensive procedures or processes that have additional steps or functions not described in detail herein. In particular, since the various steps in the manufacture of semiconductor devices and semiconductor-based ICs are well known, for the sake of brevity, many conventional steps are mentioned only briefly or omitted entirely herein without providing well known process details.

[0033] At this point in the manufacturing process, the semiconductor structure 100 comprises one or more channel layers, represented, for example, by fins 120 in the context of a FinFET architecture. The fins 120 are formed from a substrate 102. The substrate 102 may be made from any semiconductor material, including, but not limited to, silicon, germanium, silicon-germanium alloys, carbon-doped silicon, carbon-doped silicon-germanium alloys, and compound semiconductor materials. The semiconductor structure 100 may further comprise shallow trench isolation (STI) regions 110 formed within the substrate 102 to electrically insulate the active regions within the substrate 102. The process for forming the STI regions 110 is standard and typically involves etching the substrate 102 to create recesses into which insulating material is filled using any deposition method known in the art. The insulating material used to form the STI regions 110 may, but not limited to, any low-k dielectric material, including silicon nitride, silicon oxide, silicon oxynitride, and fluoride-doped silicate glass.

[0034] As is known to those skilled in the art, the fins 120 may be formed by any method known in the art. In exemplary embodiments, the fins 120 may be formed by a sidewall image transfer (SIT) technique. Note that although the embodiment shown in Figure 1A includes two fins 120, any number of fins may be formed from the substrate 102. In exemplary embodiments, the fins 120 may have a height in the range of approximately 5 nm to approximately 100 nm, a width in the range of approximately 5 nm to approximately 20 nm, and may be separated by a space in the range of approximately 20 nm to approximately 100 nm.

[0035] Referring again to Figures 1 to 1A, the semiconductor structure 100 may further comprise a sacrificial or dummy gate stack consisting of a sacrificial gate oxide 140 positioned above a portion of the fin 120 corresponding to the channel region of the semiconductor structure 100, a dummy gate 142 positioned above the sacrificial gate oxide 140, and a sacrificial gate hard mask 144 positioned above the dummy gate 142. Note that the FinFET device described may be manufactured using either a substituted metal gate (RMG), a gate-last process flow, or a gate-first process flow. Not as an limitation, but merely for illustrative purposes, the embodiments described below use a gate-last process flow.

[0036] In this embodiment, the channel region of the semiconductor structure 100 corresponds to a portion or section of the fin 120 covered by (i.e., beneath) the sacrificial gate stack (i.e., the sacrificial gate oxide 140, the dummy gate 142, and the sacrificial gate hard mask 144). The portion of the fin 120 not covered by the sacrificial gate structure defines the source / drain region of the semiconductor structure 100. As mentioned above, embodiments of the present invention can be applied to other device configurations, including planar and gate-all-around (GAA) transistors.

[0037] In exemplary embodiments, the sacrificial gate oxide 140 is made from oxide materials including, but not limited to, SiO2, HfO2, ZrO2, Al2O3, TiO2, La2O3, SrTiO3, LaAlO3, and mixtures thereof. The dummy gate 142 is formed from amorphous silicon (a-Si), and the sacrificial gate hard mask 144 is formed from silicon nitride (SiN), silicon oxide, oxide / nitride stacks, or similar materials and configurations. The sacrificial gate hard mask 144 is typically formed to cover the dummy gate 142 in order to function as an etch stop. It should be noted that the processes for forming the sacrificial gate oxide, dummy gate 142, and sacrificial gate hard mask 144 are typical and well-known in the art.

[0038] Referring here to Figure 2, a cross-sectional view of a semiconductor structure 100 after a layer of spacer material 230 has been deposited according to one embodiment of the present invention is shown. Preferably, the spacer material 230 is made of a low-k dielectric material. Non-limiting examples of various (low-k) materials for forming the spacer material 230 include silicon oxynitride (SiON), carbon-doped silicon oxide (SiOC), fluorine-doped silicon oxide (SiO:F), silicon carbonitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), silicon oxide, and combinations thereof. The dielectric material can be a low-k material having a dielectric constant less than about 7, more preferably less than about 5. The spacer material 230 may be deposited, for example, by atomic layer deposition (ALD), chemical vapor deposition (CVD), or any other suitable deposition process. Preferably, the spacer material is deposited by a conformal deposition process. The thickness of the spacer material 230 may vary within a range of approximately 6 nm to approximately 8 nm, and in between.

[0039] Referring here to Figure 3, a cross-sectional view of the semiconductor structure 100 after etching a spacer material 230 (Figure 2) to form a first spacer 330 according to one embodiment of the present invention is shown. The process for forming the first spacer 330 includes deposition of the spacer material 230 (Figure 2) and subsequent directional reactive ion etching (RIE) of the deposited spacer material 230 (Figure 2). As shown in this figure, the first spacer 330 is formed along the sidewalls of the sacrificial gate oxide 140, dummy gate 142, and sacrificial gate hard mask 144. Although multiple first spacers 330 are described herein, the first spacer 330 may consist of a single spacer surrounding the sacrificial gate structure formed by the sacrificial gate oxide 140, dummy gate 142, and sacrificial gate hard mask 144. In this embodiment, the first spacer 330 extends outward from the sacrificial gate structure. In other words, the first spacer 330 is formed on the portion of the fin 120 that is not covered by the sacrificial gate structure.

[0040] In one embodiment, the thickness (or horizontal width) of the first spacer 330 may be approximately 6 nm, but thicknesses less than or greater than this value may also be considered.

[0041] Referring now to Figure 4, a cross-sectional view of the semiconductor structure 100 after the source / drain region 410 and the sacrificial cap 420 have been formed according to one embodiment of the present invention is shown. As shown in this figure, the sacrificial cap 420 is formed directly above the source / drain region 410 and adjacent to the first spacer 330 and the STI region 110.

[0042] The process for forming the source / drain region 410 typically involves etching the upper portion of the fin 120 that is not covered by the sacrificial gate structure (i.e., sacrificial gate oxide 140, dummy gate 142, and sacrificial gate hard mask 144) and the first spacer 330 to form a source / drain recess (not shown). In exemplary embodiments, a RIE process can be used to recess such portions of the fin 120. An epitaxial layer growth process is then performed on the exposed surface of the recessed fin 120. Specifically, an in-situ doped material (e.g., phosphorus-doped silicon (Si:P) for n-type FETs or boron-doped silicon germanium (SiGe:B) for p-type FETs) is epitaxially grown within the source / drain recess (not shown) to form the source / drain region 410.

[0043] Generally, the source / drain region 410 can be formed by epitaxial growth by using the substrate 102 and the exposed sidewalls of the fins 120 as seed layers. Terms such as “epitaxial growth and / or deposition” and “epitaxial formation and / or grown” refer to the growth of semiconductor material on a deposition surface of semiconductor material, where the growing semiconductor material has the same or substantially similar crystalline properties as the semiconductor material on the deposition surface. In the epitaxial deposition process, the chemical reactants provided by the source gas are controlled, and the system parameters are set so that the atoms to be deposited have enough energy to move around on the surface and reach the deposition surface of the semiconductor substrate and orient themselves to the crystalline structure of the atoms on the deposition surface. Thus, the epitaxial semiconductor material has the same or substantially similar crystalline properties as the deposition surface on which it is formed. For example, an epitaxial semiconductor material deposited on a {100} crystalline surface will take a {100} orientation. In some embodiments, the epitaxial growth and / or deposition process is performed selectively on a semiconductor surface, and the material is not deposited on a dielectric surface such as a silicon dioxide or silicon nitride surface.

[0044] Non-limiting examples of various epitaxial growth processes include rapid thermochemical vapor deposition (RTCVD), low-energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), atmospheric pressure chemical vapor deposition (APCVD), metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), limited-reaction-treated CVD (LRPCVD), and molecular beam epitaxy (MBE). Temperatures for epitaxial deposition processes can range from 500°C to 900°C. Higher temperatures typically result in faster deposition, but faster deposition can lead to crystal defects and film cracks.

[0045] Many different precursors may be used for epitaxial growth of the source / drain region 410. In some embodiments, the gas source for depositing the epitaxial semiconductor material includes a silicon-containing gas source, a germanium-containing gas source, or a combination thereof. For example, an epitaxial silicon layer may be deposited from a silicon gas source that includes, but is not limited to, silane, disilane, trisilane, tetrasilane, hexachlorodisilane, tetrachlorosilane, dichlorosilane, trichlorosilane, and combinations thereof. An epitaxial germanium layer may be deposited from a germanium gas source that includes, but is not limited to, german, digermane, halogermane, dichlorogermane, trichlorogermane, tetrachlorogermane, and combinations thereof. By utilizing combinations of such gas sources, an epitaxial silicon-germanium alloy layer can be formed. Carrier gases such as hydrogen, helium, and argon can be used.

[0046] After forming the source / drain region 410, a sacrificial cap 420 can be formed by epitaxially growing a layer of silicon germanium (SiGe) from the source / drain region 410. In this embodiment, the SiGe layer forming the sacrificial cap 420 may have a germanium (Ge) concentration of approximately 20 to 40 atomic percent, which is higher than the germanium atomic percent of the source / drain region 410, so that the sacrificial cap 420 can be selectively removed from the source / drain region 410. In another embodiment, the sacrificial cap 420 can be formed by epitaxially growing a layer of germanium.

[0047] Accordingly, by using an epitaxy growth process to form the sacrificial cap 420, epitaxial growth occurs only on the semiconductor material forming the source / drain region 410 and not on the dielectric material forming the first spacer 330 and / or STI region 110. The sacrificial cap 420 may allow for the removal of most of the spacer material from the gate sidewall while maintaining the spacer material adjacent to the channel region (i.e., the first spacer 330). In addition, the sacrificial cap 420 may allow for the formation of wrap-around contacts in the semiconductor structure 100, as will be described in detail below. In exemplary embodiments, the thickness of the sacrificial cap 420 may vary in the range of approximately 5 nm to approximately 20 nm, and in between.

[0048] Referring now to Figure 5, a cross-sectional view of the semiconductor structure 100 after the first spacer 330 has been partially removed according to one embodiment of the present invention is shown. As shown in this figure, an isotropic etching process is performed to create the recess of the first spacer 330. In an exemplary embodiment in which the first spacer 330 includes SiOC, a hydrogen plasma treatment and a subsequent aqueous etching process including hydrogen fluoride (HF) can be performed to remove the upper portion of the first spacer 330. As shown in this figure, a portion of the first spacer 330 remains between the opposite side walls of the bottom of the sacrificial gate structure and the source / drain region 410. In particular, in this embodiment, the first spacer 330 remains along the opposite side walls of the sacrificial gate oxide 140 and the bottom portion of the dummy gate 142. After etching the first spacer 330, a gap 510 is formed between the sacrificial cap 420 and the dummy gate 142 located above the source / drain region 410. In some embodiments, the gap 510 may expose a portion of the source / drain region 410.

[0049] Referring now to Figure 6, a cross-sectional view of the semiconductor structure 100 after the formation of a sacrificial spacer 610 according to one embodiment of the present invention is shown. In this embodiment, the sacrificial spacer 610 is made from a dielectric material including, for example, silicon nitride (SiN). The sacrificial spacer 610 is deposited above the exposed upper surfaces and side walls of all elements in the semiconductor structure 100, as shown in this figure. In particular, the sacrificial spacer 610 is deposited above the first spacer 330 and pinches off each of the gaps 510 (Figure 5) located above the uppermost surface of the first spacer 330 between the sacrificial cap 420 and the dummy gate 142.

[0050] According to one embodiment, conformal deposition techniques (e.g., ALD, CVD, etc.) can be used to form the sacrificial spacer 610. Preferably, the thickness of the sacrificial spacer 610 is lower than the thickness of the (low-k) spacer material 230 that forms the first spacer 330. For example, if the thickness of the spacer material 230 that forms the first spacer 330 is approximately 6 nm, the thickness of the sacrificial spacer 610 is approximately 4 nm.

[0051] Referring now to Figure 7, a cross-sectional view of the semiconductor structure 100 after etching of the sacrificial spacer 610 according to one embodiment of the present invention is shown. In the exemplary embodiment, etching of the sacrificial spacer 610 is performed using a RIE process. Etching of the sacrificial spacer 610 exposes the top portions of the sacrificial cap 420 and the sacrificial gate hard mask 144, as shown in this figure.

[0052] Referring now to Figure 8, a cross-sectional view of the semiconductor structure 100 after the replacement metal gate process has been completed, according to one embodiment of the present invention, is shown.

[0053] In this embodiment, a first dielectric layer 840 is formed to fill the gap between the gate structure and other existing devices within the semiconductor structure 100. The first dielectric layer 840 can be formed, for example, by CVD of a first dielectric material. Non-limiting examples of dielectric materials for forming the first dielectric layer 840 include silicon oxide, silicon nitride, silicon hydride carbon oxide, silicon-based low-k dielectrics, fluid oxides, porous dielectrics, or organic dielectrics including porous organic dielectrics. After the deposition of the first dielectric layer 840, a CMP process may be performed on the semiconductor structure 100 to expose the top surface of the sacrificial gate stack (i.e., the sacrificial gate oxide 140, dummy gate 142, and sacrificial gate hard mask 144 shown in Figure 7).

[0054] At this stage of the manufacturing process, the sacrificial gate stack formed by the sacrificial gate oxide 140, dummy gate 142, and sacrificial gate hard mask 144 shown in Figure 7 is removed using known etching processes, such as RIE or chemical oxide removal (COR). In the gate last manufacturing process, the removed dummy gate 142 is then replaced with a metal gate as known in the art. Note that the sacrificial gate stack is selectively removed relative to the first spacer 330 and sacrificial spacer 610.

[0055] After removing the sacrificial gate stack, a metal gate stack, typically comprising a gate dielectric 820, a gate electrode 822, and a gate cap 824, is formed in the semiconductor structure 100. The gate dielectric 820 may include a high-k dielectric material. Non-limiting examples of high-k dielectric materials for forming the gate dielectric 820 include metal oxides, such as hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, aluminum lanthanum oxide, zirconium oxide, zirconium silicon oxide, zirconium silicon oxynitride, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. The gate dielectric 820 may be formed using standard deposition techniques such as CVD, plasma-assisted CVD, ALD, vapor deposition, reactive sputtering, chemical solution deposition, or other similar deposition processes. The thickness of the gate dielectric 820 may vary in the range of approximately 1.5 nm to approximately 5 nm, and in between. In some embodiments, an interface layer (not shown) can be formed between the high-k gate dielectric 820 and the channel layer.

[0056] The gate electrode 822 may be, but is not limited to, doped polycrystalline or amorphous silicon, germanium, silicon germanium, metals (e.g., tungsten (W), titanium (Ti), tantalum (Ta), ruthenium (Ru), hafnium (Hf), zirconium (Zr), cobalt (Co), nickel (Ni), copper (Cu), aluminum (Al), platinum (Pt), tin (Sn), silver (Ag), gold (Au)), or conductive metal compound materials (e.g., tantalum nitride (TaN), titanium nitride). The conductive material may consist of any suitable conductive material, including (TiN), tantalum carbide (TaC), titanium carbide (TiC), titanium aluminum carbide (TiAlC), tungsten silide (WSi), tungsten nitride (WN), ruthenium oxide (RuO2), cobalt silide (CoSi), nickel silide (NiSi), transition metal aluminides (e.g., Ti3Al, ZrAl), TaMgC, carbon nanotubes, conductive carbon, graphene, or any suitable combination of these materials. The conductive material may further include dopants incorporated during or after deposition. In some embodiments, the gate electrode 822 may further include a work function setting layer between the gate dielectric and the gate conductor. The work function setting layer may be a work function metal (WFM). The WFM can be any suitable material, but is not limited to, titanium nitride (TiN), titanium aluminum nitride (TiAlN), hafnium nitride (HfN), hafnium silicon nitride (HfSiN), tantalum nitride (TaN), tantalum silicon nitride (TaSiN), tungsten nitride (WN), molybdenum nitride (MoN), niobium nitride (NbN); carbides, but is not limited to, titanium carbide (TiC), titanium aluminum carbide (TiAlC), tantalum carbide (TaC), hafnium carbide (HfC), and combinations thereof. In some embodiments, a conductive material or a combination of several conductive materials can function as both a gate conductor and a WFM.The gate electrode 822 and WFM can be formed by any suitable process or any suitable combination of processes, including but not limited to atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, plating, vapor deposition, ion beam deposition, electron beam deposition, laser-assisted deposition, chemical solution deposition, etc.

[0057] The gate cap 824 may be formed above the gate electrode 822 using a standard deposition technique. The gate cap 824 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, boron nitride, or any suitable combination thereof.

[0058] Referring to Figure 9, a cross-sectional view of the semiconductor structure 100 after the first dielectric layer 840 has been patterned to form a contact trench 902, according to one embodiment of the present invention, is shown.

[0059] As is known to those skilled in the art, patterning the first dielectric layer 840 to form the contact trench 902 involves exposing a pattern (not shown) on a photoresist layer (not shown) and transferring the exposed pattern to the first dielectric layer 840. After transferring the pattern and forming the contact trench 902, the photoresist layer can be removed using any photoresist stripping method known in the art, including, for example, plasma ashing.

[0060] As shown in this figure, the contact trench 902 exposes the top surface of the sacrificial cap 420 and the top surface and side walls of the sacrificial spacer 610.

[0061] Referring to Figure 10, a cross-sectional view of the semiconductor structure 100 after selective removal of the sacrificial cap 420, according to one embodiment of the present invention, is shown.

[0062] Exemplary techniques suitable for removing the sacrificial cap 410 (Figure 9) from the semiconductor structure 100 may include, but are not limited to, vapor-phase etching with hydrogen fluoride (HCl) and wet etching with a mixture of ammonia and hydrogen peroxide, which cause minimal or no damage to the underlying layer or structure. As shown in this figure, the removal of the sacrificial cap 410 (Figure 9) expands the contact trench 902, exposing the source / drain region 410, including its top surface and sidewalls, and further exposing the sacrificial spacer 610. Exposing the sidewalls of the source / drain region 410 allows the subsequently formed metal contact to surround the source / drain region 410, thereby increasing the contact area and reducing contact resistance.

[0063] Referring to Figure 11, a cross-sectional view of the semiconductor structure 100 after a contact structure has been formed in the contact trench 902 (Figure 10) is shown, according to one embodiment of the present invention.

[0064] The process for forming a contact includes forming a contact trench 902 (Figure 10) within a first dielectric layer 840, and subsequently filling the contact trench with a conductive material or combination of conductive materials to form a contact structure. In this embodiment, a contact liner 1110 and a contact metal 1112 are deposited within the contact trench 902 to form a contact structure. Forming the contact liner 1110 within the contact trench 902 includes, for example, depositing a layer of a first conductive material containing titanium (Ti) or titanium nitride (TiN) using a standard deposition method. According to one embodiment, the thickness of the contact liner 1110 may be approximately 3 nm. The contact metal 1112 is subsequently deposited directly above the contact liner 1110 to fill the contact trench 902 (Figure 10) using a standard deposition method such as CVD, PECVD, PVD, plating, thermal or electron beam deposition, or sputtering. The contact metal 1112 is made from a second conductive material, for example, cobalt (Co), tungsten (W), aluminum (Al), platinum (Pt), gold (Au), titanium (Ti), or any combination thereof. In one or more embodiments, a planarization process, such as CMP, is performed to remove any conductive material from the upper surface of the semiconductor structure 100.

[0065] Referring to Figure 12, a cross-sectional view of the semiconductor structure 100 after the removal of the sacrificial spacer 610 is shown, according to one embodiment of the present invention.

[0066] Any suitable etching technique can be used to selectively remove the sacrificial spacer 610 from the semiconductor structure 100. Preferably, an etching chemistry that does not damage the rest of the first spacer 330 and the contact liner 1110 is used to selectively remove the sacrificial spacer 610. For example, plasma etching containing CHF3, CF4, hydrogen, and / or hydrogen can be used to remove the sacrificial spacer 610 from the semiconductor structure 100. In this embodiment, it should be noted that the removal chemistry used to remove the sacrificial spacer 610 does not affect or damage the gate dielectric 820 due to the presence of the first spacer 330. In other words, the rest of the first spacer 330 protects the gate dielectric 820 during the removal of the sacrificial spacer 610.

[0067] As shown in this figure, the removal of the sacrificial spacer 610 creates an air gap 1201 in the semiconductor structure 100, exposing the top surface of the first spacer 330 and the inner wall of the contact liner 1110. According to one embodiment, the size of the air gap 1201 is defined by the width or horizontal thickness of the contact liner 1110 and the width or horizontal thickness of the gate dielectric 820. Therefore, the size of the air gap 1201 can be adjusted or controlled according to design requirements by adjusting the dimensions of the contact liner 1110 and / or the gate dielectric 820.

[0068] Referring to Figure 13, a cross-sectional view of the semiconductor structure 100 after the exposed portion of the contact liner 1110 has been removed is shown, according to one embodiment of the present invention.

[0069] In an exemplary embodiment, an aqueous etching solution containing a mixture of hydrogen peroxide and ammonia can be used to remove the portion of the contact liner 1110 that is exposed after the removal of the sacrificial spacer 601 (Figure 11). As can be observed in this figure, removing the exposed portion of the contact liner 1110 located on the inner wall of the contact metal 1112 widens the air gap 1201. In other words, the exposed portion of the contact liner 1110 is removed from the semiconductor structure 100, increasing the size of the air gap 1201. As shown in this figure, the contact liner 1110 remains between the source / drain region 410 and the contact metal 1112, but it is removed from the area located between the contact metal 1112 and the gate electrode 822. As can be understood, the wider the air gap 1201, the lower the parasitic capacitance. Also, the removal of the exposed portion of the contact liner 1110 may provide additional space for essential device elements such as the gate, source / drain contacts, and spacers.

[0070] It should be noted that the contact liner 1110 has a higher resistance than the contact metal 1112. Therefore, removing the exposed portion of the contact liner 1110 does not increase the contact resistance in the semiconductor structure 100. Alternatively, or in addition, the inner wall of the gate dielectric 820 can be selectively etched (for example, using a dry etching technique) to reduce its thickness and further increase the size of the air gap 1201.

[0071] Referring to Figure 14, a cross-sectional view of the semiconductor structure 100 after the second dielectric layer 1402 has been deposited and the air gap spacer 1404 has been formed, according to one embodiment of the present invention, is shown.

[0072] The second dielectric layer 1402 can be formed, for example, by non-conformal deposition of the second dielectric material. Non-limiting examples of dielectric materials for forming the second dielectric layer 1402 include silicon oxide, silicon nitride, silicon hydride carbon oxide, silicon-based low-k dielectrics, fluid oxides, porous dielectrics, or organic dielectrics including porous organic dielectrics. After depositing the second dielectric layer 1402, a CMP process is performed on the semiconductor structure 100.

[0073] As shown in this figure, the second dielectric layer 1402 pinches off the air gap 1201 (Figure 13) to form the air gap spacer 1404. Specifically, the air gap 1201 (Figure 13), formed after the removal of the sacrificial spacer 610 (Figure 11), is pinched off by a non-conformal second dielectric layer 1402 that defines the region of trapped air forming the air gap spacer 1404. The air gap spacer 1404 may contain air, hydrogen, or any other gas. Alternatively, the air gap spacer 1404 may have a gas pressure lower than the ambient pressure or near vacuum, depending on the pressure during the deposition of the second dielectric layer 1402. In one embodiment, the second dielectric layer 1402 is deposited by plasma-enhanced chemical vapor deposition (PECVD). Alternatively, the second dielectric layer 1402 may be deposited by low-pressure chemical vapor deposition (LPCVD). Since air has a dielectric constant of approximately 1, the air gap spacer 1404 can reduce parasitic capacitance in the semiconductor structure 100.

[0074] As can be observed in this figure, the air gap spacer 1404 has a unique shape, which is a result of the non-conformal deposition process used to form the second dielectric layer 1402. The shape of the air gap spacer 1404 is narrower at the top of the air gap spacer 1404 and wider in the lower part of the air gap spacer 1404 closer to the source / drain region 410. The wider lower part of the air gap spacer 1404 allows for a larger air gap between the gate structure and the source / drain region 410, which further reduces the margin between the metal gate structure and the source / drain region 410.

[0075] Accordingly, the proposed embodiment provides a spacer structure located between the source / drain region 410, the contact metal 1112, and the metal gate stack. The spacer structure includes a bottom spacer formed by a first spacer 330 and a top spacer or second spacer formed by a second dielectric layer 1402. The second spacer formed by the second dielectric layer 1402 includes an air gap spacer (or simply an air gap) 1404.

[0076] Therefore, embodiments of the present invention enable the formation of a wrap-around contact structure and an air gap spacer 1404 simultaneously, thereby reducing parasitic capacitance and parasitic resistance at the same time. In addition, the proposed embodiments enable further reduction of the transistor size by removing a portion of the contact liner 1110, thereby providing additional space for essential device elements such as the gate, source / drain contacts, and spacers.

[0077] The methods described above are used in the manufacturing of integrated circuit chips. The resulting integrated circuit chip can be distributed by the manufacturer as a bare die in raw wafer form (i.e., as a single wafer with multiple unpackaged chips) or in packaged form. In the latter case, the chip is mounted in a single-chip package (such as a plastic carrier with leads that are anchored to a motherboard or other higher-level carrier) or in a multi-chip package (such as a ceramic carrier with either or both surface interconnects or embedded interconnects). In either case, the chip is then integrated into other chips, discrete circuit elements, and / or other signal processing devices as part of either (a) an intermediate product such as a motherboard, or (b) a final product. The final product can be any product containing an integrated circuit chip, ranging from toys and other low-cost applications to displays, keyboards or other input devices, and advanced computer products with a central processor.

[0078] The terminology used herein is solely for the purpose of describing specific embodiments and is not intended to limit the invention. Where used herein, the singular forms “a,” “an,” and “the” are intended to include the plural form unless otherwise explicitly stated in the context. Where used herein, the terms “comprises” and / or “comprising” specify the presence of the described features, integers, stages, actions, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, stages, actions, elements, components, and / or groups thereof. “Optional” or “optionally” means that the event or situation described thereafter may or may not occur, and the description includes cases in which the event occurs and cases in which it does not occur.

[0079] Spatial relative terms such as “inside,” “outside,” “down,” “below,” “underside,” “up,” “top,” and “bottom” may be used herein to describe the relationship of one element or feature to another, as shown in the diagram, for the sake of clarity. Spatial relative terms may be intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the diagram. For example, if the device in the diagram is inverted, an element described as being “below” or “below” another element or feature will then be oriented “above” that other element or feature. Therefore, the example term “below” may encompass both upward and downward orientations. The device may be oriented in other ways (by rotating 90 degrees or to other orientations), and the spatially relative descriptive terms used herein may be interpreted accordingly.

[0080] Where used herein throughout the specification and claims, the word "approximate" may be applied to modify any quantitative expression that is acceptablely variable, without altering its fundamental function. Accordingly, values ​​modified by singular or plural terms such as "about," "approximately," and "substantially" should not be limited to the exact value specified. In at least some cases, the word "approximate" may correspond to the precision of the instrument used to measure the value. Herein, and throughout the specification and claims, range limitations may be combined and / or interchangeable, and such ranges are specified and include all subranges contained therein unless otherwise indicated by context or wording. "Approximately," as applied to a particular value of a range, may apply to both values ​​and, unless otherwise dependent on the precision of the instrument used to measure the value separately, indicate + / - 10% of the stated value.

[0081] The descriptions of various embodiments of the present invention have been presented for illustrative purposes only and are not intended to be comprehensive or to limit the disclosed embodiments. Many changes and modifications will be apparent to those skilled in the art without departing from the scope of the described embodiments. The terminology used herein has been selected to best describe the principles of the embodiments, their practical applications or technological improvements over the technology available on the market, or to enable other those skilled in the art to understand the embodiments disclosed herein. (Other possible items) [Item 1] A gate structure located adjacent to the source / drain region; and A spacer structure located between the gate structure and the source / drain region, wherein the spacer structure has a top spacer and a bottom spacer, the top spacer includes an air gap having a bottom portion that is wider than the top portion, and the wider bottom portion of the air gap is located between the gate structure and the source / drain region. A semiconductor structure comprising the features described above. [Item 2] The semiconductor structure according to item 1, further comprising a contact structure above the source / drain region, wherein the contact structure has a contact liner above the source / drain region and a contact metal above the contact liner. [Item 3] The semiconductor structure according to item 2, wherein the top spacer includes a non-conformal dielectric material that pinches off the space located above the bottom spacer between the contact structure and the gate structure to form the air gap. [Item 4] The bottom spacer is a semiconductor structure according to item 1, comprising a low-k dielectric material. [Item 5] The gate structure has a metal gate stack that contacts a first portion of a channel layer on a substrate, the first portion of the channel layer being located between the source and drain regions; The spacer structure has a first spacer located above a second portion of the channel layer extending outward from the metal gate stack, the first spacer being positioned between the bottom portion of the metal gate stack and the source / drain region located above the substrate; The semiconductor structure according to item 1, comprising a contact structure above the source / drain region, the contact structure in contact with a second spacer positioned above the first spacer and between the contact structure and the metal gate stack, the second spacer including an air gap having a bottom portion that is wider than the top portion, the wider bottom portion of the air gap being located between the metal gate stack and the respective source / drain regions. [Item 6] The aforementioned contact structure is: Contact liner; and The contact metal above the contact liner, wherein the first portion of the contact liner is located above the source / drain region, the second portion of the contact liner is positioned on the outer wall of the contact metal, and the contact liner is not formed on the inner wall of the contact metal adjacent to the metal gate stack. A semiconductor structure as described in item 5, further comprising the above. [Item 7] The semiconductor structure according to item 6, wherein the inner wall of the contact metal is in direct contact with the second spacer in order to increase the size of the air gap. [Item 8] The aforementioned metal gate stack is: Gate dielectric; The gate electrode above the gate dielectric; and The gate cap above the aforementioned gate electrode The semiconductor structure described in item 5, further including the above. [Item 9] The semiconductor structure according to item 8, wherein the thickness of the gate dielectric is reduced, and the size of the air gap is further increased. [Item 10] The first spacer is a semiconductor structure according to any one of items 5 to 9, comprising a low-k dielectric material including SiOC. [Item 11] The semiconductor structure according to any one of items 5 to 9, wherein the second spacer includes a non-conformal dielectric material for pinching off the space located above the first spacer and between the contact structure and the metal gate stack to form the air gap. [Item 12] The top surface of the first spacer is located below the top surface of the source / drain region, as described in any one of items 5 to 9. [Item 13] The step of forming a metal gate stack that contacts a first portion of a channel layer on a substrate, wherein the first portion of the channel layer is located between the source and drain regions; The step of forming a first spacer above a second portion of the channel layer extending outward from the metal gate stack, wherein the first spacer is formed between the bottom portion of the metal gate stack and the source / drain region portion located above the substrate; A step of forming a contact structure above the source / drain region; The step of forming a second spacer above the first spacer and between the contact structure and the metal gate stack, wherein the second spacer includes an air gap having a bottom portion that is wider than the top portion, and the wider bottom portion of the air gap is located between the metal gate stack and the respective source / drain regions. A method for forming a semiconductor structure comprising the following features. [Item 14] The step of forming the aforementioned contact structure is: The step of forming a contact liner; and The step of forming the contact metal above the contact liner, wherein the first portion of the contact liner is above the source / drain region, and the second portion of the contact liner is positioned on the outer wall of the contact metal; and The step of etching the third portion of the contact liner from the inner wall of the contact metal adjacent to the metal gate stack. The method described in item 13, further comprising: [Item 15] The method according to item 14, wherein the inner wall of the contact metal is in direct contact with the second spacer in order to increase the size of the air gap. [Item 16] The steps for forming the aforementioned metal gate stack are: The step of forming the gate dielectric; The step of forming a gate electrode above the gate dielectric; and The step of forming the gate cap above the gate electrode. The method described in item 13, further comprising: [Item 17] The method according to item 16, further comprising the step of reducing the thickness of the gate dielectric to further increase the size of the air gap. [Item 18] The method according to any one of items 13 to 17, wherein the first spacer comprises a low-k dielectric material including silicon oxycarbide, and the second spacer comprises a non-conformal dielectric material for pinching off the space located above the first spacer and between the contact structure and the metal gate stack to form the air gap. [Item 19] The step of forming a sacrificial gate stack above the first portion of the channel layer, wherein the second portion of the channel layer extends outward from the sacrificial gate stack, and the channel layer is located between shallow trench isolation regions; A step of depositing a first spacer material above the second portion of the channel layer, the sacrificial gate stack, and the shallow trench isolation region; A step of etching the first spacer material to form the first spacer; A step of epitaxially growing the source / drain region from the second portion of the channel layer; A step of epitaxially growing a sacrificial cap from the source / drain region, wherein a first portion of the sacrificial cap is adjacent to the first spacer, and a second portion of the sacrificial cap is above the shallow trench isolation region; In the step of recessing the first spacer, a portion of the first spacer remains on the bottom region of the sacrificial gate stack; A step of depositing sacrificial spacers above the sacrificial gate stack, the first spacer, the sacrificial cap, and the shallow trench isolation region, wherein the thickness of the sacrificial spacers is lower than the thickness of the first spacers; The step of creating a recess in the sacrificial spacer to expose the top portion of the sacrificial cap and the top portion of the sacrificial gate stack; A step of depositing a first dielectric layer above the sacrificial spacer and the exposed top dielectric cap; and The step of replacing the sacrificial gate stack with the metal gate stack. The method according to any one of items 13 to 17, further comprising: [Item 20] The first dielectric layer is etched to form a contact trench, wherein the contact trench exposes the top portion of the sacrificial cap; and The step of removing the sacrificial cap, wherein the step of removing the sacrificial cap exposes the first portion of the source / drain region and the shallow trench isolation region. The method described in item 19, further comprising the above.

Claims

1. A semiconductor structure, A gate structure located adjacent to the source / drain region; and A spacer structure located between the gate structure and the source / drain region, wherein the spacer structure has a top spacer and a bottom spacer, the top spacer includes an air gap having a bottom portion that is wider than the top portion, and the wider bottom portion of the air gap is located between the gate structure and the source / drain region. Equipped with, The gate structure has a metal gate stack that contacts a first portion of a channel layer on a substrate, the first portion of the channel layer being located between the source and drain regions; The spacer structure has a first spacer located above a second portion of the channel layer extending outward from the metal gate stack, the first spacer being positioned between the bottom portion of the metal gate stack and the source / drain region located above the substrate; The semiconductor structure comprises a contact structure above the source / drain region, the contact structure in contact with a second spacer positioned above the first spacer and between the contact structure and the metal gate stack, the second spacer includes an air gap having a bottom portion that is wider than the top portion, the wider bottom portion of the air gap being located between the metal gate stack and the respective source / drain regions. The aforementioned contact structure is: Contact liner; and The contact metal above the contact liner, wherein the first portion of the contact liner is located above the source / drain region, the second portion of the contact liner is positioned on the outer wall of the contact metal, and the contact liner is not formed on the inner wall of the contact metal adjacent to the metal gate stack. A semiconductor structure that further possesses the following.

2. The semiconductor structure according to claim 1, further comprising a contact structure above the source / drain region, wherein the contact structure has a contact liner above the source / drain region and a contact metal above the contact liner.

3. The semiconductor structure according to claim 2, wherein the top spacer includes a non-conformal dielectric material that pinches off the space located above the bottom spacer between the contact structure and the gate structure in order to form the air gap.

4. The semiconductor structure according to claim 1, wherein the bottom spacer comprises a Low-k dielectric material.

5. The semiconductor structure according to claim 1, wherein the inner wall of the contact metal is in direct contact with the second spacer in order to increase the size of the air gap.

6. The aforementioned metal gate stack is: Gate dielectric; The gate electrode above the gate dielectric; and The gate cap above the aforementioned gate electrode The semiconductor structure according to claim 1, further comprising:

7. The semiconductor structure according to any one of claims 1 to 6, wherein the first spacer comprises a Low-k dielectric material including SiOC.

8. The semiconductor structure according to any one of claims 1 to 6, wherein the second spacer includes a non-conformal dielectric material for pinching off the space located above the first spacer and between the contact structure and the metal gate stack to form the air gap.

9. The semiconductor structure according to any one of claims 1 to 6, wherein the top surface of the first spacer is located below the top surface of the source / drain region.

10. The step of forming a metal gate stack that contacts a first portion of a channel layer on a substrate, wherein the first portion of the channel layer is located between the source and drain regions; The step of forming a first spacer above a second portion of the channel layer extending outward from the metal gate stack, wherein the first spacer is formed between the bottom portion of the metal gate stack and the source / drain region located above the substrate; A step of forming a contact structure above the source / drain region; The step of forming a second spacer above the first spacer and between the contact structure and the metal gate stack, wherein the second spacer includes an air gap having a bottom portion that is wider than the top portion, and the wider bottom portion of the air gap is located between the metal gate stack and the respective source / drain regions. Equipped with, The step of forming a sacrificial gate stack above the first portion of the channel layer, wherein the second portion of the channel layer extends outward from the sacrificial gate stack, and the channel layer is located between shallow trench isolation regions; A step of depositing a first spacer material above the second portion of the channel layer, the sacrificial gate stack, and the shallow trench isolation region; A step of etching the first spacer material to form the first spacer; A step of epitaxially growing the source / drain region from the second portion of the channel layer; A step of epitaxially growing a sacrificial cap from the source / drain region, wherein a first portion of the sacrificial cap is adjacent to the first spacer, and a second portion of the sacrificial cap is above the shallow trench isolation region; In the step of creating the first spacer recess, a portion of the first spacer remains on the bottom region of the sacrificial gate stack; A step of depositing sacrificial spacers above the sacrificial gate stack, the first spacer, the sacrificial cap, and the shallow trench isolation region, wherein the thickness of the sacrificial spacers is lower than the thickness of the first spacers; The step of creating a recess in the sacrificial spacer to expose the top portion of the sacrificial cap and the top portion of the sacrificial gate stack; A step of depositing a first dielectric layer above the sacrificial spacer and the exposed top dielectric cap; and The step of replacing the sacrificial gate stack with the metal gate stack. It also has, A method for forming a semiconductor structure.

11. The steps for forming the aforementioned contact structure are: The step of forming a contact liner; and The step of forming the contact metal above the contact liner, wherein the first portion of the contact liner is above the source / drain region, and the second portion of the contact liner is positioned on the outer wall of the contact metal; and The step of etching the third portion of the contact liner from the inner wall of the contact metal adjacent to the metal gate stack. The method according to claim 10, further comprising:

12. The method according to claim 11, wherein the inner wall of the contact metal is in direct contact with the second spacer in order to increase the size of the air gap.

13. The steps for forming the aforementioned metal gate stack are: The step of forming the gate dielectric; The step of forming the gate electrode above the gate dielectric; and The step of forming the gate cap above the gate electrode. The method according to claim 10, further comprising:

14. The method according to claim 13, further comprising the step of reducing the thickness of the gate dielectric to further increase the size of the air gap.

15. The method according to any one of claims 10 to 14, wherein the first spacer comprises a Low-k dielectric material comprising silicon oxycarbide, and the second spacer comprises a non-conformal dielectric material for pinching off the space located above the first spacer and between the contact structure and the metal gate stack to form the air gap.

16. The first dielectric layer is etched to form a contact trench, wherein the contact trench exposes the top portion of the sacrificial cap; and The step of removing the sacrificial cap, wherein the step of removing the sacrificial cap exposes the first portion of the source / drain region and the shallow trench isolation region. The method according to any one of claims 10 to 14, further comprising:

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