Anomaly detection circuits, semiconductor devices, electronic equipment, vehicles

Abstract

To provide an abnormality detection circuit that can realize miniaturization and cost reduction.SOLUTION: An abnormality detection circuit 35 includes: a first current source CS11 configured to generate a first current flowing from an external terminal 11 toward a reference potential terminal; a second current source CS12 configured to generate a second current flowing from a power supply potential terminal VDD toward the external terminal 11; a comparator CMP1 configured to generate an abnormality detection signal S35 by comparing a detection voltage V11 corresponding to an application voltage of the external terminal 11 with a predetermined threshold voltage V12; and a controller CTL1 configured to switch between a first abnormality detection mode in which an operation of generating the first current is performed and a second abnormality detection mode in which an operation of generating the second current is performed.SELECTED DRAWING: Figure 2

Description

Technical Field

[0006] , , , ,

[0005] , , , , ,

[0001] The invention disclosed in this specification relates to an abnormality detection circuit, a semiconductor device, an electronic device, and a vehicle using the same.

Background Art

[0002] In a switch device, an abnormality detection circuit is provided to detect an output abnormal state. The output abnormal state includes, for example, load open, output short to ground, or output short to power.

[0003] As an example of the related prior art, Patent Document 1 can be cited.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in a conventional abnormality detection circuit for detecting load open, output short to ground, or output short to power, a detection circuit (such as a comparator) is required for each of load open, output short to ground, and output short to power, and there is room for improvement in terms of reducing the circuit scale.

Means for Solving the Problems

[0006] An anomaly detection circuit disclosed herein comprises: a first current source configured to generate a first current flowing from an external terminal toward a reference potential terminal; a second current source configured to generate a second current flowing from a power supply potential terminal toward the external terminal; a comparator configured to generate an anomaly detection signal by comparing a detection voltage corresponding to the applied voltage at the external terminal with a predetermined threshold voltage; and a controller configured to switch between a first anomaly detection mode for generating the first current and a second anomaly detection mode for generating the second current.

[0007] The semiconductor device disclosed herein includes an abnormality detection circuit having the above configuration.

[0008] The electronic devices disclosed herein include a semiconductor device having the above configuration.

[0009] The vehicles disclosed herein are equipped with the electronic equipment having the above configuration. [Effects of the Invention]

[0010] The anomaly detection circuit disclosed herein makes it possible to provide an anomaly detection circuit that can be miniaturized and cost-effective, as well as semiconductor devices, electronic devices, and vehicles using the same. [Brief explanation of the drawing]

[0011] [Figure 1] Figure 1 shows the overall configuration of the low-side switch IC. [Figure 2] Figure 2 shows an example configuration of an anomaly detection circuit that can be applied to a low-side switch IC. [Figure 3] Figure 3 is a diagram illustrating the operation of the first anomaly detection mode. [Figure 4] Figure 4 shows the applied voltage to the external terminal 12 during operation in the first abnormality detection mode. [Figure 5] Figure 5 is a diagram illustrating the operation of the second anomaly detection mode. [Figure 6] Figure 6 shows the applied voltage to the external terminal 12 during operation in the second abnormality detection mode. [Figure 7] Figure 7 shows the applied voltage to the external terminal 12 during abnormality detection operation in an open load state. [Figure 8] Figure 8 shows a detailed example of the configuration of an anomaly detection circuit. [Figure 9] Figure 9 shows an example configuration of an anomaly detection circuit that can be applied to a high-side switch IC. [Figure 10] Figure 10 is an external view showing one example of the vehicle's configuration. [Modes for carrying out the invention]

[0012] <Semiconductor equipment (low-side switch IC)> Figure 1 shows the overall configuration of the low-side switch IC. In this configuration example, the low-side switch IC1 is an automotive low-side switch LSI (= a type of automotive IPD) that conducts / interrupts between the load 3 and the reference potential terminal (e.g., the ground terminal) in response to instructions from the ECU [electronic control unit] 2.

[0013] The low-side switch IC1 is equipped with external terminals 11 to 14 as a means of establishing an electrical connection with the outside of the device. External terminal 11 is a load connection terminal or output terminal (OUT pin) for connecting a load 3 (such as a bulb lamp, relay coil, solenoid, light-emitting diode, or motor) to the outside. External terminal 12 is a GND terminal (GND pin) for connecting to the reference potential terminal. External terminal 13 is a signal input terminal (IN pin) for receiving an external input of an external control signal Si from the ECU2. The external control signal Si is a logic signal for controlling the on / off state of the NMOSFET9, but it can also be understood as the power supply voltage of the low-side switch IC1. External terminal 14 is a signal output terminal (FAIL pin) for outputting an output abnormality notification signal FAIL to the ECU2.

[0014] In addition, the low-side switch IC1 is formed by integrating an NMOSFET 9, a control logic unit 23, a protection circuit 24, a gate control unit 25, and an active clamp circuit 26.

[0015] The NMOSFET 9 is a power transistor with its drain connected to the external terminal 11 and its source connected to the external terminal 12. The NMOSFET 9 connected in this way functions as an output switch element (low-side switch element) for conducting / interrupting the current path from the load 3 through the external terminals 11 and 12 to the ground terminal. Note that the NMOSFET 9 turns on when the gate drive signal G1 is at a high level and turns off when the gate drive signal G1 is at a low level.

[0016] The gate control unit 25 performs on / off control of the NMOSFET 9 by generating a gate drive signal G1 with enhanced current capacity of the gate control signal S1 and outputting it to the gate of the NMOSFET 9. Note that the gate control unit 25 has a function of controlling the NMOSFET 9 to limit the output current Io according to the overcurrent protection signal S34.

[0017] The control logic unit 23 generates a gate control signal S1 according to an external control signal Si. For example, when the external control signal Si is at a high level (= the logic level when turning on the NMOSFET 9), the control logic unit 23 is in an operating state and the gate control signal S1 is at a high level. On the other hand, when the external control signal Si is at a low level (= the logic level when turning off the NMOSFET 9), the control logic unit 23 is in a non-operating state and the gate control signal S1 is at a low level. Also, the control logic unit 23 monitors various output signals of the protection circuit 24. In particular, the control logic unit 23 also has a function of generating an output abnormality notification signal FAIL according to the monitoring result of the output abnormality detection signal S24.

[0018] In terms of this figure, the control logic unit 23 includes an internal power supply unit 32 and a reference voltage source / reference current source 33.

[0019] The internal power supply unit 32 generates a predetermined internal power supply voltage Vreg and supplies it to each part of the low-side switch IC1 (for example, the protection circuit 24). The operation of the internal power supply unit 32 is controlled according to the external control signal Si. More specifically, the internal power supply unit 32 operates when the external control signal Si is at a high level and deactivates when the external control signal Si is at a low level.

[0020] The reference voltage source / reference current source 33 generates the reference voltage VREF and reference current IREF for various circuits integrated into the low-side switch IC 1. The reference voltage VREF and reference current IREF are input to, for example, the protection circuit 24. If the above-mentioned circuits include a comparator, the reference voltage VREF and reference current IREF may also be input to the comparator.

[0021] The protection circuit 24 is a circuit block that detects various abnormal conditions of the low-side switch IC1, and includes an overcurrent protection circuit 34, an abnormality detection circuit 35, and a temperature protection circuit 36.

[0022] The overcurrent protection circuit 34 generates an overcurrent protection signal S34 according to the monitoring result (= whether or not an overcurrent abnormality has occurred in the output current Io) using an overcurrent detection means (not shown). The overcurrent protection signal S34 is, for example, low level when no abnormality is detected and high level when an abnormality is detected.

[0023] The abnormality detection circuit 35 generates an abnormality detection signal S35 according to the detection result (i.e., whether or not a load open is occurring, or whether or not an output ground fault is occurring). The abnormality detection signal S35 is low level when no abnormality is detected and high level when an abnormality is detected. An output ground fault refers to an abnormal condition in which the external terminal 11 is short-circuited to a ground potential terminal (or a similarly low potential terminal).

[0024] The temperature protection circuit 36 ​​includes a temperature detection element (not shown) that detects abnormal heat generation in the low-side switch IC1 (particularly around the NMOSFET9), and generates a temperature protection signal S36 according to the detection result (i.e., whether or not abnormal heat generation has occurred). The temperature protection signal S36 is, for example, low level when no abnormality is detected and high level when an abnormality is detected.

[0025] Furthermore, the overcurrent protection signal S34, the abnormality detection signal S35, and the temperature protection signal S36 may be configured to be high level when no abnormality is detected and low level when an abnormality is detected.

[0026] The active clamp circuit 26 is connected between the external terminal 11 and the gate of the NMOSFET 9, protecting the NMOSFET 9 from back electromotive force that may occur during the off-transition of the NMOSFET 9. The active clamp circuit 26 may include multiple diodes connected in forward bias to each other. Alternatively, the active clamp circuit 26 may include multiple diodes connected in reverse bias to each other. Or, the active clamp circuit 26 may include multiple diodes connected in forward bias to each other and multiple diodes connected in reverse bias to each other.

[0027] <Anomaly detection circuit (example of application to low-side switch IC)> Figure 2 shows an example configuration of an anomaly detection circuit 35 that can be applied to the low-side switch IC1. The anomaly detection circuit 35 in this figure includes a first current source CS11 and a second current source CS12, a comparator CMP1, a controller CTL1, first switches SW11 to eighth switches SW18, and resistors R10 to R16.

[0028] An external terminal 11 is connected to one end of resistor R10. The other end of resistor R10 is connected to the third switch SW13. Resistor R11, the second switch SW12, and the third switch SW13 are connected in parallel to one end of the first switch SW11. The first current source CS11 is connected to the other end of the first switch SW11. The first current source CS11 is connected between the first switch SW11 and ground potential.

[0029] The power supply voltage VDD is applied to one end of the second current source CS12. The other end of the second current source CS12 is connected to the second switch SW12. One end of resistor R12 is connected in parallel to resistor R11 and the inverting input terminal of comparator CMP1. The fourth switch SW14 is connected between resistor R12 and ground potential. One end of resistor R14 is connected in parallel to resistor R13 and the non-inverting input terminal of comparator CMP1. The other end of resistor R14 is connected in parallel to resistor R15, the seventh switch SW17, resistor R16, and the eighth switch SW18.

[0030] A reference voltage VBG is connected to one end of resistor R13. The other end of resistor R13 is connected in parallel to the non-inverting input terminal of comparator CMP1 and resistor R14. The output terminal of comparator CMP1 is connected to the application terminal of the abnormal detection signal S35. A resistor R15 and the seventh switch SW17 are connected in parallel to one end of the fifth switch SW15. The other end of the fifth switch SW15 is connected to ground potential. A resistor R16 and the eighth switch SW18 are connected in parallel to one end of the sixth switch SW16. The other end of the sixth switch SW16 is connected to ground potential.

[0031] Switches SW11 to SW18 are controlled by a control signal output from controller CTL1 to enable / disconnect switches SW17 to enable / disconnect switches SW18 to enable / disconnect switches SW17 to enable / disconnect switches SW18 to enable / disconnect switches SW18 to enable / disconnect switches SW18 to enable / disconnect switches SW17 to enable / disconnect switches SW18 to enable / disconnect switches SW18 to enable / disconnect switches SW17 to enable / disconnect switches SW18 to enable / disconnect switches SW18 to enable / disconnect switches SW17 to enable / disconnect switches SW18 to enable / disconnect switches SW18 to enable / disconnect switches SW17 to enable / disconnect switches SW18 to enable / disconnect switches SW18 to enable / disconnect switches SW11 to SW18 to enable / disconnect switches SW18 to enable / disconnect switches SW11 to SW18 to enable / disconnect switches SW18 to enable / disconnect switches SW11 to SW18 to enable / disconnect switches SW18 to enable / disconnect switches SW11 to SW18 to enable / disconnect switches SW18 to enable / disconnect switches SW11 to SW18 to enable / disconnect switches SW18 to enable / disconnect switches SW11 to enable / disconnect switches SW18 to enable / disconnect switches SW18 to enable / disconnect switches SW11 to enable / disconnect switches SW18 to enable / disconnect switches SW18 to enable / disconnect switches SW18 to enable / disconnect switches SW17 to enable / disconnect switches SW18

[0032] The first current source CS11 is configured to draw a first current I11 from the external terminal 12 to the reference potential terminal. The second current source CS12 is configured to supply a second current I12 from the power supply potential terminal to the external terminal 12. The comparator CMP1 compares a detection voltage V11 corresponding to the applied voltage Vo at the external terminal 12 with a predetermined threshold voltage V12 and generates an abnormality detection signal S35 according to the detection result.

[0033] The first switch SW11 is configured to conduct / interrupt the connection between the first current source CS11 and the external terminal 11. The second switch SW12 is configured to conduct / interrupt the connection between the second current source CS12 and the external terminal 11.

[0034] In the first anomaly detection mode, the controller CTL1 is configured to turn on the first switch SW11 and turn off the second switch SW12. In the second anomaly detection mode, the controller CTL1 is configured to turn off the first switch SW11 and turn on the second switch SW12.

[0035] Controller CTL1 switches between the operation of the first abnormality detection mode and the second abnormality detection mode by switching the first switch SW11 and the second switch SW12. The third switch SW13 is configured to conduct / disconnect between the external terminal 11 and the first switch SW11 and the second switch SW12.

[0036] The fourth switch SW14 is configured to conduct / interrupt between resistor R12 and ground potential. The fifth switch SW15 is configured to conduct / interrupt between resistor R15 and the seventh switch SW17 and ground potential. The sixth switch SW16 is configured to conduct / interrupt between resistor R16 and the eighth switch SW18 and ground potential. The seventh switch SW17 is configured to conduct / interrupt between resistor R14 and the fifth switch SW15, in other words, to switch whether or not to short the ends of resistor R15. The eighth switch SW18 is configured to conduct / interrupt between resistor R14 and the sixth switch SW16, in other words, to switch whether or not to short the ends of resistor R16.

[0037] During operation in the first abnormality detection mode, the first switch SW11, the third switch SW13, and the fifth switch SW15 are turned ON by control signals from the controller CTL1. At this time, the second switch SW12, the fourth switch SW14, and the sixth switch SW16 are turned OFF. The seventh switch SW17 and the eighth switch SW18 are turned ON by the abnormality detection signal S35 output from the output terminal of the comparator CMP1.

[0038] During operation in the second abnormality detection mode, the second switch SW12, third switch SW13, fourth switch SW14, and sixth switch SW16 are turned ON by control signals from the controller CTL1. At this time, the first switch SW11 and fifth switch SW15 are turned OFF. The seventh switch SW17 and eighth switch SW18 are turned ON by the abnormality detection signal S35 output from the output terminal of the comparator CMP1.

[0039] If neither the first nor the second abnormality detection mode is operating, the first switch SW11, the second switch SW12, the third switch SW13, the fourth switch SW14, the fifth switch SW15, and the sixth switch SW16 will all be in the off state.

[0040] Comparator CMP1 is configured to switch the threshold voltage V12 between the first and second anomaly detection modes. Comparator CMP1 can be configured to be common to both the first and second anomaly detection modes by switching the first switch SW11, second switch SW12, third switch SW13, fourth switch SW14, fifth switch SW15, and sixth switch SW16 using control signals from controller CTL1. This configuration allows for a reduction in the number of elements, resulting in miniaturization and cost reduction.

[0041] Figure 3 is a diagram illustrating the operation of the first abnormality detection mode. Note that the first switch SW11 and the fifth switch SW15, which are in the ON state, are assumed to be conductive in this diagram and are therefore not depicted. During operation in the first abnormality detection mode, the first switch SW11, the third switch SW13, and the fifth switch SW15 are turned ON by a control signal from the controller CTL1. The third switch SW13 is used as an enable switch. When the third switch SW13 is turned ON, the detection operation of the first abnormality detection mode begins. The detection operation of the first abnormality detection mode diagnoses whether load 3 is open or not.

[0042] When the third switch SW13 is turned on, the first current I11 generated from the first current source CS11 draws current from the external terminal 11. This creates a condition where the first current I11 can flow from the external terminal 11 to the reference potential terminal. Under normal conditions with load 3 connected, the first current I11 is only a few tens of μA, so the voltage drop across resistor R10 is small, and the detection voltage V11 corresponding to the applied voltage Vo at the external terminal 11 never falls below the predetermined threshold voltage V12 at which comparator CMP1 detects an abnormality. Therefore, no abnormality is detected.

[0043] When load 3 is open, the applied voltage Vo at external terminal 11 is reduced to the output level of the reference potential terminal by the first current source CS11. The detection voltage V11 corresponding to the applied voltage Vo at external terminal 11 becomes lower than the predetermined threshold voltage V12 at which comparator CMP1 detects an anomaly, thus enabling an anomaly to be detected. When an anomaly is detected, the output terminal of comparator CMP1 outputs a high level, and the seventh switch SW17 turns off. With the seventh switch SW17 turned off, resistor R14 is connected to the fifth switch SW15 (and consequently the reference potential terminal) via resistor R15. Therefore, the predetermined threshold voltage V12 at which comparator CMP1 detects an anomaly becomes higher than before the anomaly was detected.

[0044] Figure 4 shows the applied voltage Vo at the external terminal 12 during operation in the first abnormality detection mode. At time t11, the first switch SW11 and the third switch SW13 are synchronously turned ON, and operation in the first abnormality detection mode begins. At this time, a current IOLD (= first current I11) flows through the load 3 (impedance RL). As a result, the applied voltage Vo decreases by the voltage drop across the load 3 from the power supply potential VBB (RL × IOLD).

[0045] At time t12, when a load open (defined as LOAD_OPEN=H in this figure) occurs, the applied voltage Vo (and consequently the detected voltage V11) begins to decrease as it approaches the potential of the reference potential terminal. At time t13, when the detected voltage V11 falls below a predetermined threshold voltage V12 (depicted in this figure as the detection threshold Vth11 for the applied voltage Vo, e.g., Vth11=2.10V) that comparator CMP1 uses to detect abnormalities, an abnormality is detected, and the abnormality detection signal S35 outputs a high level.

[0046] In reality, it is unlikely that the load will normalize after an open circuit occurs, but for the sake of convenience, let's assume that it does normalize. At time t14, the open circuit will normalize. As a result of the normalization, the applied voltage Vo (and therefore the detected voltage V11) will approach the power supply potential VBB and begin to increase. At time t15, when the detected voltage V11 becomes higher than the predetermined threshold voltage V12 (in this figure, depicted as the release threshold Vth12 for the applied voltage Vo, for example Vth12 = 2.50V) detected by the comparator CMP1, the abnormality detection is released and the abnormality detection signal S35 outputs a low level. At this time, the applied voltage Vo returns to a potential lower than the power supply potential VBB by the voltage drop across load 3 (RL × IOLD).

[0047] Subsequently, at time t16, the first switch SW11 and the third switch SW13 are synchronously turned off, and the operation of the first abnormality detection mode ends. In this figure, since no abnormality was ultimately detected, NMOSFET9 is turned on at times t17-t18.

[0048] Figure 5 is a diagram illustrating the operation of the second abnormality detection mode. Note that the second switch SW12 and the sixth switch SW16, which are in the ON state, are assumed to be conductive in this diagram and are therefore not depicted. When the second abnormality detection mode is in operation, the second switch SW12, the third switch SW13, and the sixth switch SW16 are turned ON by a control signal from the controller CTL1. When the third switch SW13 is turned ON, the detection operation of the second abnormality detection mode begins. The detection operation of the second abnormality detection mode diagnoses whether the external terminal 11 is grounded.

[0049] When the third switch SW13 is turned on, the second current I12 generated from the second current source CS12 flows from the power supply potential end to the external terminal 11. If load 3 is connected and an output ground fault occurs, the applied voltage Vo at the external terminal 11 is determined by the resistive voltage divider of the impedance RL of load 3 and the impedance RG between the external terminal 11 and the reference potential (i.e., the output ground fault path). An abnormality is detected when the detection voltage V11 corresponding to the applied voltage Vo determined by the impedance RL of load 3 and the impedance RG between the external terminal 11 and the reference potential falls below a predetermined threshold voltage V12 that detects an abnormality in the comparator CMP1.

[0050] If load 3 is not connected and an output ground fault occurs, the applied voltage Vo at external terminal 12 drops to approximately ground potential via external terminal 11. As a result, the detection voltage V11 corresponding to the applied voltage Vo at external terminal 11 becomes lower than the predetermined threshold voltage V12 at which comparator CMP1 detects an anomaly, allowing the anomaly to be detected. When an anomaly is detected, the output terminal of comparator CMP1 outputs a high level, and the 8th switch SW18 turns off. With the 8th switch SW18 turned off, resistor R14 becomes connected to the 6th switch SW16 (and consequently the reference potential terminal) via resistor R16. Therefore, the predetermined threshold voltage V12 at which comparator CMP1 detects an anomaly becomes higher than before the anomaly was detected.

[0051] Figure 6 shows the applied voltage Vo at the external terminal 12 during operation in the second abnormality detection mode. At time t21, the second switch SW12 and the third switch SW13 are synchronously turned ON, and operation in the second abnormality detection mode begins. At time t22, when an output ground fault (defined as GROUND_SHORT=L in this figure) occurs, the applied voltage Vo (and thus the detected voltage V11) drops to the potential of the reference potential terminal and begins to decrease. At time t23, when the detected voltage V11 becomes lower than a predetermined threshold voltage V12 (depicted in this figure as the detection threshold Vth21 for the applied voltage Vo, for example Vth21=1.10V) detected by the comparator CMP1, an abnormality is detected, and the abnormality detection signal S35 outputs a high level.

[0052] In reality, it is unlikely that an output ground fault will normalize midway through the process, but for the sake of convenience, let's assume it does normalize. At time t24, the output ground fault normalizes. As a result of the normalization, the applied voltage Vo (and therefore the detected voltage V11) approaches the power supply potential VBB and begins to increase. At time t25, when the detected voltage V11 becomes higher than the predetermined threshold voltage V12 (in this figure, depicted as the release threshold Vth22 for the applied voltage Vo, e.g., Vth22 = 1.84V) detected by comparator CMP1, the abnormality detection is released, and the abnormality detection signal S35 outputs a low level. Subsequently, at time t26, the second switch SW12 and the third switch SW13 turn off synchronously, and the operation of the second abnormality detection mode ends. In this figure, since no abnormality is ultimately detected, NMOSFET9 is shown as being in the ON state at times t27-t28.

[0053] Figure 7 shows the applied voltage Vo at the external terminal 12 during abnormality detection operation in an open load state. Note that because the load is open, the applied voltage Vo, shown by the dashed line, is an undefined voltage.

[0054] At time t31, the first switch SW11 is turned ON, and the operation of the first abnormality detection mode begins. Because a load open (defined as LOAD_OPEN=H in this figure) occurs, the applied voltage Vo (and therefore the detected voltage V11) approaches the potential of the reference potential terminal and begins to decrease.

[0055] When the detected voltage V11 falls below a predetermined threshold voltage V12 (depicted in this figure as the detection threshold Vth11 for the applied voltage Vo, e.g., Vth11 = 2.10V) detected by the comparator CMP1 at time t32, an open load anomaly is detected, and the anomaly detection signal S35 (OLD) outputs a high level.

[0056] At time t33, the first switch SW11 turns off, and the operation of the first abnormality detection mode ends. As the operation of the first abnormality detection mode ends, the abnormality detection is canceled, and the abnormality detection signal S35 (OLD) outputs a low level.

[0057] Subsequently, at time t34, the second switch SW12 is turned ON, and the operation of the second abnormality detection mode begins. At time t35, when an output ground fault (defined as GROUND_SHORT=L in this figure) occurs, the applied voltage Vo (and thus the detected voltage V11) begins to decrease as it approaches the potential of the reference potential terminal. At time t36, when the detected voltage V11 becomes lower than a predetermined threshold voltage V12 (depicted in this figure as the detection threshold Vth21 for the applied voltage Vo, e.g., Vth21=1.10V) detected by comparator CMP1, an abnormality is detected, and the abnormality detection signal S35(SGD) outputs a high level. At this time, the applied voltage Vo drops to a potential higher than the potential of the reference potential terminal by RG×ISGD.

[0058] At time t37, the second switch SW12 turns off, and the operation of the second abnormality detection mode ends. As the operation of the second abnormality detection mode ends, the abnormality detection is canceled, and the abnormality detection signal S35 (SGD) outputs a low level. At this time, since an output ground fault has occurred, the applied voltage Vo outputs the voltage of the reference potential terminal.

[0059] Subsequently, at time t38, the first switch SW11 is turned ON, and the operation of the first abnormality detection mode begins. Because an output ground fault has occurred, the detection voltage V11 becomes lower than the predetermined threshold voltage V12 at which comparator CMP1 detects an abnormality, and the abnormality detection signal S35 (OLD) outputs a high level simultaneously with the first switch SW11 being turned ON.

[0060] At time t39, the first switch SW11 turns off, and the operation of the first abnormality detection mode ends. As the operation of the first abnormality detection mode ends, the abnormality detection is canceled, and the abnormality detection signal S35 (OLD) outputs a low level.

[0061] As explained above, when the load is open, the abnormality detection signal S35(OLD) becomes high level during operation of the first abnormality detection mode, regardless of whether an output ground fault has occurred (see times t32-t33 and t38-t39). In other words, since it is not possible to determine whether an abnormality has occurred, such as an open load or an output ground fault, by sequentially performing the operation of the first abnormality detection mode and the operation of the second abnormality detection mode, it is determined whether an output ground fault has occurred.

[0062] The abnormality detection circuit disclosed herein is configured to sequentially perform abnormality detection operations in a first abnormality detection mode and abnormality detection operations in a second abnormality detection mode, and to turn on the output switch element if neither abnormality is detected. With this configuration, it is possible to turn on the output switch element only after reliably confirming that there are no abnormalities such as an open load or an output ground fault.

[0063] Figure 8 shows details of an example configuration of the anomaly detection circuit 35. The anomaly detection circuit 35 in this figure is configured to include current mirror circuits CM11 and CMP12. Current mirror circuit CM11 includes transistors P1 to P3 (e.g., PMOSFETs). Current mirror circuit CM12 includes transistors N1 and N2 (e.g., NMOSFETs).

[0064] When the first current source CS11 generates the first current I11, the control signal from the controller CTL1 turns on the first switch SW11 and turns off the second switch SW12. The first current I11 generated by the first current source CS11 is replicated by the current mirror circuits CM11 and CM12 of the reference current I10 generated from the reference current source CS10.

[0065] Specifically, as shown in this diagram, the first current I11 is generated by further replicating the mirror current I10' of the reference current I10, which has been replicated by the current mirror circuit CM11, in the current mirror circuit CM12.

[0066] When generating the second current I12 with the second current source CS12, the control signal from the controller CTL1 turns off the first switch SW11 and turns on the second switch SW12. The second current I12 generated by the second current source CS12 is generated by duplicating the reference current I10 generated from the reference current source CS10 using the current mirror circuit CM11.

[0067] As explained above, the first current I11 and the second current I12 can be generated from the reference current I10 generated from the reference current source CS10 by switching the first switch SW11 and the second switch SW12, respectively.

[0068] <Anomaly detection circuit (Example of application to high-side switch IC)> Figure 9 shows an example configuration of an anomaly detection circuit 35 that can be applied to a high-side switch IC. The anomaly detection circuit 35 in this figure includes a first current source CS21 and a second current source CS22, a comparator CMP2, a controller CTL2, first switches SW21 to eighth switches SW28, and resistors R20 to R26.

[0069] In the first anomaly detection mode, the controller CTL2 is configured to turn on the first switch SW21 and turn off the second switch SW22. In the second anomaly detection mode, the controller CTL2 is configured to turn off the first switch SW21 and turn on the second switch SW22.

[0070] Controller CTL2 switches between the operation of the first anomaly detection mode and the second anomaly detection mode by switching the first switch SW21 and the second switch SW22.

[0071] Switches SW21 to SW28 are controlled by a control signal output from controller CTL2, which enables / disconnects them. Switches SW27 and SW28 are controlled by an abnormality detection signal S35 output from the output terminal of comparator CMP2, which enables / disconnects them. More specifically, when an abnormality such as an open load or output fault is detected and the abnormality detection signal S35 outputs a high level, switches SW27 and SW28 are turned off.

[0072] The anomaly detection circuit 35 in Figure 9 is simply the same as the anomaly detection circuit 35 in Figure 2, but with the polarity reversed: the circuit connected to ground is connected to the power supply, and the circuit connected to the power supply is connected to ground. Therefore, a detailed explanation is omitted here.

[0073] In this configuration example, the abnormality detection circuit 35 generates an abnormality detection signal S35 according to the detection result (i.e., whether or not a load open is occurring, or whether or not an output short circuit is occurring). The abnormality detection signal S35 is, for example, low level when no abnormality is detected and high level when an abnormality is detected. An output short circuit refers to an abnormal condition in which the external terminal 11 is short-circuited to the power supply potential terminal (or a similarly high potential terminal).

[0074] <Application to vehicles> Figure 10 is an external view showing one example of a vehicle configuration. In this example, vehicle X is equipped with various electronic devices that operate using power supplied from a battery.

[0075] Vehicle X includes not only gasoline-powered vehicles but also electric vehicles (xEVs such as BEVs [battery electric vehicles], HEVs [hybrid electric vehicles], PHEVs / PHVs (plug-in hybrid electric vehicles / plug-in hybrid vehicles), or FCEVs / FCVs (fuel cell electric vehicles / fuel cell vehicles)).

[0076] Furthermore, the low-side switch IC1 described earlier can be incorporated into any of the electronic devices mounted on vehicle X.

[0077] <Summary> The various embodiments disclosed herein will be described in general below.

[0078] For example, the abnormality detection circuit disclosed herein has a configuration (first configuration) comprising: a first current source configured to generate a first current that flows from an external terminal toward a reference potential terminal; a second current source configured to generate a second current that flows from a power supply potential terminal toward the external terminal; a comparator configured to generate an abnormality detection signal by comparing a detection voltage corresponding to the applied voltage of the external terminal with a predetermined threshold voltage; and a controller configured to switch between a first abnormality detection mode that performs the first current generation operation and a second abnormality detection mode that performs the second current generation operation.

[0079] Furthermore, in the abnormality detection circuit according to the first configuration described above, a configuration (second configuration) may be used in which the threshold voltage is switched between the first abnormality detection mode and the second abnormality detection mode.

[0080] Furthermore, in the abnormality detection circuit according to the first or second configuration described above, a current mirror circuit may be provided (third configuration) which is configured to generate the first current and the second current from a common reference current, respectively.

[0081] Furthermore, in an abnormality detection circuit according to any of the first to third configurations described above, the controller may further include a first switch configured to conduct / interrupt the connection between the first current source and the external terminal, and a second switch configured to conduct / interrupt the connection between the second current source and the external terminal, wherein the controller is configured to turn on the first switch and turn off the second switch in the first abnormality detection mode, and to turn off the first switch and turn on the second abnormality detection mode (fourth configuration).

[0082] Furthermore, the abnormality detection circuit according to the fourth configuration described above may also be further configured to include a third switch configured to conduct / disconnect between the external terminal and the first switch and the second switch (fifth configuration).

[0083] Furthermore, for example, the semiconductor device disclosed herein has a configuration (sixth configuration) comprising the external terminal, an abnormality detection circuit according to the fifth configuration described above, and an output switch element configured to conduct / interrupt the connection between the external terminal and the reference potential terminal or the power supply potential terminal.

[0084] Furthermore, in the semiconductor device according to the sixth configuration described above, the abnormality detection circuit is configured to sequentially perform abnormality detection operations in the first abnormality detection mode and abnormality detection operations in the second abnormality detection mode, and to turn on the output switch element if neither abnormality is detected (seventh configuration).

[0085] Furthermore, for example, the electronic equipment disclosed herein has a configuration (an eighth configuration) comprising a semiconductor device according to the sixth or seventh configuration described above, and a load externally connected to the external terminal.

[0086] Furthermore, for example, the vehicle disclosed herein is configured to include electrical equipment according to the eighth configuration described above (the ninth configuration).

[0087] <Other variations> The configuration of the present invention can be modified in various ways, in addition to the embodiments described above, without departing from the spirit of the invention. The embodiments described above should be considered in all respects to be illustrative and not restrictive, and the technical scope of the present invention is indicated by the claims, not by the descriptions of the embodiments described above, and should be understood to include all modifications that fall within the meaning and scope equivalent to the claims. [Explanation of Symbols]

[0088] 1 Low-side switch IC 2 ECU 3 load 9, 10 NMOSFET (first switching element, second switching element) 11, 12, 13, 14 External terminals 23 Control Logic Section 24 Protection circuit 25 Gate control unit 26 Active clamp circuit 32 Internal power supply section 33. Reference voltage source / reference current source 34 Overcurrent protection circuit 35 Anomaly detection circuit 36 Temperature protection circuit CM11, CM12 Current Mirror Circuit CMP1, CMP2 comparators CS11, CS12, CS21, CS22 current source CTL1, CTL2 Controllers G1 Gate drive signal N1, N2 transistors (NMOSFETs) P1~P3 Transistors (PMOSFETs) R11~R16, R21~R26 resistance RG, RL impedance S1 Gate control signal S24 Output Anomaly Detection Signal S34 Overcurrent protection signal S35 Anomaly detection signal S36 temperature protection signal SW11~SW18, SW21~SW28 switches V11, V21 Detected Voltage V12, V22 threshold voltage X Vehicle

Claims

1. A first current source configured to generate a first current that flows from an external terminal toward a reference potential terminal, A second current source configured to generate a second current that flows from the power supply potential terminal toward the external terminal, A comparator configured to generate an abnormality detection signal by comparing a detection voltage corresponding to the applied voltage at the external terminal with a predetermined threshold voltage, A controller configured to switch between a first abnormality detection mode for performing the first current generation operation and a second abnormality detection mode for performing the second current generation operation, A first switch configured to conduct / interrupt the connection between the first current source and the external terminal, A second switch configured to conduct / interrupt the connection between the second current source and the external terminal, Equipped with, The controller is configured to turn on the first switch and turn off the second switch in the first abnormality detection mode, and to turn off the first switch and turn on the second abnormality detection mode, in which case it is configured to turn off the second switch.

2. The threshold voltage is configured to switch between the first anomaly detection mode and the second anomaly detection mode. An anomaly detection circuit according to claim 1.

3. The circuit comprises a current mirror circuit configured to generate the first current and the second current from a common reference current, An anomaly detection circuit according to claim 1 or 2.

4. The system further includes a third switch configured to provide / disconnect electrical current between the external terminals and the first and second switches. An anomaly detection circuit according to any one of claims 1 to 3.

5. The aforementioned external terminal and, The abnormality detection circuit according to claim 4, An output switch element configured to conduct / interrupt the connection between the external terminal and the reference potential terminal or the power supply potential terminal, A semiconductor device equipped with the following features.

6. The abnormality detection circuit is configured to sequentially perform abnormality detection operations in the first abnormality detection mode and abnormality detection operations in the second abnormality detection mode, and to turn on the output switch element if no abnormality is detected in either mode. The semiconductor device according to claim 5.

7. A semiconductor device according to claim 5 or 6, The load connected to the external terminal, An electronic device equipped with the following features.

8. A vehicle comprising the electronic equipment described in claim 7.

Images