Semiconductor integrated circuits
The semiconductor integrated circuit addresses the challenge of chip size and cost by allowing multiple control units to share functional units through a selection unit, achieving high-speed operation with low power consumption.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- ROHM CO LTD
- Filing Date
- 2022-03-30
- Publication Date
- 2026-06-23
AI Technical Summary
Conventional semiconductor integrated circuits require separate high-speed and low-speed SRAMs, increasing chip size and cost due to the need for multiple control units with different operating speeds accessing a specific functional unit.
A semiconductor integrated circuit design that allows multiple control units with different operating speeds to share a specific functional unit through a selection unit that switches between paths based on control signals, using regions with varying threshold voltages for power management.
This design reduces chip size and cost by enabling high-speed operation with low power consumption by sharing functional units and optimizing power usage across regions with different operating speeds.
Smart Images
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Abstract
Description
Technical Field
[0001] The present invention relates to a semiconductor integrated circuit.
Background Art
[0002] In general-purpose microcomputers, high-speed operation is required while low power consumption is also required. As techniques for achieving both high-speed operation and low power consumption, a multi-Vt technique and a power-off technique are known. In the multi-Vt technique, the threshold voltage of elements constituting a circuit block that requires high-speed operation is made lower than the threshold voltage of elements constituting a circuit block that allows low-speed operation, thereby reducing leakage current. On the other hand, in the power-off technique, when shifting to a power-saving mode, the power supply to unnecessary circuit blocks is cut off.
[0003] For example, Patent Document 1 discloses a semiconductor integrated circuit including a first region where the power supply is cut off during standby and a second region where the power supply is always provided. In the first region, a first logic circuit such as a digital signal processor (DSP) that requires high-speed processing operation and a first SRAM are arranged. On the other hand, in the second region, a second logic circuit such as a central processing unit (CPU) and a second SRAM are arranged. Then, the threshold voltage of elements of circuit blocks in the first region where the power supply is cut off during standby is made lower than the threshold voltage of elements of other circuit blocks, thereby reducing leakage current.
Prior Art Documents
Patent Documents
[0004]
Patent Document 1
Summary of the Invention
Problems to be Solved by the Invention
[0005] However, this conventional circuit configuration requires both low-speed and high-speed SRAM, which increases the chip size and, consequently, the chip cost. This problem occurs not only when accessing SRAM, but also when accessing a specific functional unit from multiple control blocks with different operating speeds.
[0006] The present invention has been made in view of the above problems, and the object of the present invention is to provide a semiconductor integrated circuit in which multiple control units with different operating speeds can share a specific functional unit, thereby reducing the chip size. [Means for solving the problem]
[0007] The semiconductor integrated circuit of this disclosure includes: a first control unit included in a first region where a first operating speed is permissible; a second control unit included in a second region where the power supply is cut off in a power-saving mode and where operation faster than the first operating speed is required; a functional unit having a specific function; and a selection unit that selects either a first path connecting the first control unit and the functional unit, or a second path connecting the second control unit and the functional unit, according to a control signal. [Effects of the Invention]
[0008] According to the semiconductor integrated circuit of the present invention, multiple control units with different operating speeds can share a specific functional unit, thereby reducing the chip size. [Brief explanation of the drawing]
[0009] [Figure 1] This is a schematic diagram showing an example of the basic configuration of the present invention. [Figure 2] This is a schematic diagram showing a first modified example of the basic configuration shown in Figure 1. [Figure 3] This is a schematic diagram showing a second modified example of the basic configuration shown in Figure 1. [Figure 4] This is a block diagram showing an example of the configuration of a semiconductor integrated circuit according to the first embodiment of the present invention. [Figure 5] This is a flowchart illustrating an example of the operation of a semiconductor integrated circuit according to the first embodiment. [Figure 6] Figure 4 is a block diagram showing a modified example of the configuration of a semiconductor integrated circuit. [Figure 7] Figure 4 is a block diagram showing a modified example of the configuration of a semiconductor integrated circuit. [Figure 8] A block diagram showing an example of the configuration of a semiconductor integrated circuit according to a second embodiment of the present invention. [Figure 9] This is a flowchart showing an example of the operation of a semiconductor integrated circuit according to the second embodiment. [Figure 10] This is a block diagram showing the configuration of a conventional semiconductor integrated circuit using a combination of multi-Vt method and power cut-off technology. [Modes for carrying out the invention]
[0010] Hereinafter, an example of an embodiment of the present invention will be described in detail with reference to the drawings.
[0011] <Basic configuration> First, the basic configuration of the present invention will be described with reference to Figure 1. The semiconductor integrated circuit relating to the basic configuration includes a first control unit 102 included in a first region 100 where operation at normal speed is permitted, a second control unit 106 included in a second region 104 where operation at a speed faster than normal is required, a functional unit 108 having a specific function, and a selection unit 110 that selects either a first path connecting the first control unit 102 and the functional unit 108 or a second path connecting the second control unit 106 and the functional unit 108 according to a control signal.
[0012] Note that "normal speed" refers to the general-purpose processing speed. Below, operation faster than normal speed will be referred to as "high-speed operation," and operation at normal speed will be referred to as "low-speed operation" or "power-saving operation."
[0013] The first control unit 102 is a data transfer device such as a DMAC (DMA Controller). The second control unit 106 is a processor such as a CPU (Central Processing Unit) or a DSP (Digital Signal Processing). The selection unit 110 can be composed of an arbitration circuit or a multiplexer that functions as a selector.
[0014] The functional unit 108 mainly assumes a memory, but it may also be various arithmetic units, communication interfaces, etc. Examples of the memory include SRAM (Static Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FLASH (Flash Memory), FeRAM (Ferroelectric Random Access Memory), etc. Examples of the arithmetic unit include sensing circuits such as a random number generator and a low voltage detection circuit. Examples of the communication interface include SPI (Serial Peripheral Interface), UART (Universal Asynchronous Receiver / Transmitter), I2C, etc.
[0015] Also, according to the multi-Vt method, the threshold voltage of the elements included in the second region 104 is made lower than the threshold voltage of the elements included in the first region 100. The lower the threshold current, the faster the operating speed, but the leakage current also increases. Hereinafter, the higher threshold voltage is referred to as the "high threshold voltage", and the lower threshold voltage is referred to as the "low threshold voltage".
[0016] The functional unit 108 and the selection unit 110 may be composed of either high-threshold-voltage elements or low-threshold-voltage elements. Generally, since the functional unit 108 such as SRAM is expected to operate at high speed, it is composed of low-threshold-voltage elements, and the selection unit 110 such as a multiplexer is composed of high-threshold-voltage elements because low-speed operation is acceptable. However, it is only necessary to be able to support the desired operating speed, and the types of elements constituting the functional unit 108 and the selection unit 110 can be appropriately changed according to the desired power-saving effect and the desired operating speed.
[0017] Next, the operation of the semiconductor integrated circuit shown in FIG. 1 will be described. This semiconductor integrated circuit operates in a normal mode in which power is supplied to the entire circuit or in a power-saving mode in which power supply to a part of the circuit is cut off. In the basic configuration, only the second region 104 is targeted for power cut-off.
[0018] In the normal mode, power is supplied to the entire circuit including both the second region 104 and the first region 100. At this time, the selection unit 110 selects the second path to enable access from the second control unit 106 to the functional unit 108. Also, in the power-saving mode, power is supplied to the first region 100, but power supply to the second region 104 with a large leakage current is cut off. At this time, the selection unit 110 selects the first path to enable access from the first control unit 102 to the functional unit 108.
[0019] Note that in the normal mode, the selection unit 110 may appropriately switch the selection between the first path and the second path to enable access from the first control unit 102 to the functional unit 108.
[0020] Also, in the basic configuration shown in FIG. 1, although it is assumed that the functional unit 108 and the selection unit 110 may be arranged outside the first region 100, depending on where the functional unit 108 and the selection unit 110 are arranged and what elements they are composed of, the following modification examples can be considered.
[0021] (First modification example of the basic configuration) In the first modified configuration, as shown in Figure 2, the functional unit 108 and the selection unit 110 are arranged within the first region 100. Also, similar to the basic configuration shown in Figure 1, only the second region 104 is subject to power cutoff. Therefore, the functional unit 108 and the selection unit 110 are continuously supplied with power.
[0022] (First variation of the basic configuration) In the second modification, as shown in Figure 3, the functional unit 108 and the selection unit 110 are placed in a third region 112 that is distinct from both the first region 100 and the second region 104. In this example, the third region 112, i.e., the functional unit 108 and the selection unit 110, are always supplied with power. On the other hand, both the first region 100 and the second region 104 are subject to power cut-off. For example, while the second control unit 106 is accessing the functional unit 108, the power supply to the first region 100 is cut off.
[0023] The following describes a specific embodiment of a semiconductor integrated circuit in which the first control unit 102 includes a "DMAC", the second control unit 106 includes a "CPU", and the functional unit 108 includes an "ADC (Analog-to-Digital Converter)" and an "ADC controller".
[0024] <First Embodiment> Referring to Figure 4, the configuration of the semiconductor integrated circuit according to the first embodiment will be described. The semiconductor integrated circuit includes a first region 12 where low-speed operation is permitted, a second region 14 where high-speed operation is required, and a power switch 16 for turning the power supply (VDD) to the second region 14 on and off. Power is always supplied to the first region 12.
[0025] The first region 12 contains a DMAC 32, an SRAM / AHB bridge 34, an ADC controller 36, an ADC 38, an AHB (Advanced High-Performance Bus) bus 40, an SRAM 50, a multiplexer 52, and a PMU (Phasor Measurement Unit) 54. Each of the blocks except for the ADC 38, SRAM 50, and multiplexer 52 is composed of high threshold voltage elements and is capable of low-power operation. Therefore, the AHB bus 40 functions as a low-speed bus.
[0026] The second region 14 contains the CPU 20, FLASH / AHB bridge 22, SRAM / AHB bridge 24, peripheral 26, FLASH 28, and AHB bus 30. Each of the blocks except FLASH 28 is composed of low threshold voltage elements and is capable of high-speed operation. Therefore, the AHB bus 30 functions as a high-speed bus.
[0027] The CPU 20 and peripheral 26 are connected to the AHB bus 30. The FLASH 28 is connected to the AHB bus 30 via the FLASH / AHB bridge 22. The low-speed AHB bus 40 is also connected to the high-speed AHB bus 30. The DMAC 32 is also connected to the AHB bus 40. The ADC 38 is connected to the AHB bus 40 via the ADC controller 36.
[0028] SRAM 50 is connected to the AHB bus 30 via multiplexer 52 and SRAM / AHB bridge 24, and also to the AHB bus 40 via multiplexer 52 and SRAM / AHB bridge 34. PMU 54 is connected to both the power switch 16 and the multiplexer 52, and controls both the power switch 16 and the multiplexer 52, respectively. Although not shown in the diagram, PMU 54 is also connected to the CPU 20 for communication.
[0029] Each of the FLASH28, ADC38, SRAM50, and multiplexer52 only needs to be able to handle the desired operating speed, and the types of elements constituting them can be appropriately changed according to the desired power saving effect and desired operating speed. However, it is preferable that the multiplexer52 is composed of elements with a high threshold voltage that enable power-saving operation.
[0030] In the first embodiment, the semiconductor integrated circuit operates in two modes: a "normal mode" in which power is supplied to the entire circuit, and a "power-saving mode" in which power is cut off to the second region 14, which is a high-speed operating region. The PMU 54 inputs a control signal to the multiplexer 52 according to the operating mode. Depending on the control signal, the multiplexer 52 selects a second path connecting the CPU 20 and the SRAM 50 in normal mode, and a first path connecting the DMAC 32 and the SRAM 50 in power-saving mode.
[0031] (Power cutoff and startup process in the high-speed region) Next, we will explain how semiconductor integrated circuits work. In its basic operation, this semiconductor integrated circuit uses an ADC38 to periodically sample data. Once a certain amount of data has accumulated in the ADC38, it uses a DMAC32 to transfer the data to the SRAM50. When a certain amount of data has accumulated in the SRAM50, the CPU20 starts up and processes the data in the SRAM50.
[0032] Now, referring to Figure 5, the above procedure will be explained in more detail in relation to power shutdown. First, in step S10, the CPU 20 instructs the DMAC 32 to read data from the ADC 38 and write the data to the SRAM 50 a specified number of times when it receives a data transfer request from the ADC 38.
[0033] Next, in step S12, the CPU 20 instructs the ADC 38 to periodically acquire data.
[0034] Next, in step S14, the CPU 20 instructs the PMU 54 to switch the operating mode from normal mode to power-saving mode, at which point the power supply to the second region 14 is cut off.
[0035] Next, in step S16, the PMU 54 instructs the power switch 16 to cut off the power supply and simultaneously inputs a control signal corresponding to the power saving mode to the multiplexer 52 to select a first path connecting the SRAM 50 and the DMAC 32.
[0036] Next, in step S18, the ADC38 acquires data, and the DMAC32 transfers that data to the SRAM50. This process is repeated a specified number of times.
[0037] Next, in step S20, once the DMAC32 has completed the specified number of data transfers, it issues a transfer completion notification to the PMU54. This causes the operating mode to switch from power-saving mode to normal mode.
[0038] Next, in step S22, the PMU 54 instructs the power switch 16 to release the power cutoff for the second region 14, and also inputs a control signal corresponding to the normal mode to the multiplexer 52 to select a second path connecting the SRAM 50 and the CPU 20.
[0039] Next, in step S24, the CPU 20 processes the data in the SRAM 50, returns to step S10, and repeats the operation from steps S10 to S24.
[0040] (effect) In the circuit according to the first embodiment, power is supplied to the entire circuit while the CPU 20 is processing data in the SRAM 50, and power is cut off to the second region 14, which is a high-speed operation region, during data transfer from the DMAC 32 to the SRAM 50. This makes it possible to achieve both high-speed operation and low power consumption. Furthermore, by configuring the second region 14, which is a high-speed operation region, with elements with a low threshold voltage, high-speed operation is possible, while by configuring the first region 12, which is a low-speed operation region, with elements with a high threshold voltage, leakage current can be reduced and power consumption can be lowered.
[0041] Next, the effects of the first embodiment will be described in comparison with the conventional configuration. Figure 10 shows the configuration of a conventional semiconductor integrated circuit that uses both the multi-Vt method and power cut-off technology. The same reference numerals are used for the same components as in the semiconductor integrated circuit shown in Figure 4. In the conventional semiconductor integrated circuit, a high-speed SRAM 25 used by the CPU 20 is provided in the second region 14, and a low-speed SRAM 53 is also provided in the first region 12.
[0042] Compared to this conventional circuit configuration, in the semiconductor integrated circuit according to the first embodiment, the SRAM 50 is shared for both high-speed and low-speed operation, resulting in a smaller chip size and, consequently, a reduction in chip cost.
[0043] Furthermore, as shown in Figure 10, in conventional circuit configurations, when the CPU 20 processes data from the SRAM 53 for low-speed operation, it is necessary to go through the AHB bus 40, which is a low-speed bus, as shown by the dashed line, and processing can only be done at a low speed. As a result, the processing time by the CPU 20 increases, and power consumption increases. In contrast, in the semiconductor integrated circuit according to the first embodiment, the CPU 20 can process data from the SRAM 50 directly without going through the low-speed bus, so high-speed operation is possible, processing time is shorter, and power consumption can be reduced.
[0044] Here, we show a modified example of the configuration of the semiconductor integrated circuit shown in Figure 4.
[0045] (Bridge circuit omitted) In the circuit configuration shown in Figure 4, an SRAM / AHB bridge 24 is provided in the second region 14, and an SRAM / AHB bridge 34 is also provided in the first region 12. In contrast, in the example shown in Figure 6, a shared SRAM / AHB bridge 56 is placed between the SRAM 50 and the multiplexer 52, and the multiplexer 52 is connected to the AHB bus 30 and the AHB bus 40, respectively. By placing the shared SRAM / AHB bridge 56, one SRAM / AHB bridge can be omitted.
[0046] (Use of mediation circuit) In the circuit configuration shown in Figure 4, a multiplexer 52 is used as the selection unit (see selection unit 110 in Figure 1). The multiplexer 52 has the advantage of having a small number of logic stages and relatively fast processing speed. However, since the multiplexer 52 switches paths depending on the operating mode, in normal mode the second path is selected, and even though power is supplied to the first region 12, the SRAM 50 cannot be accessed from the first path.
[0047] In contrast, the example shown in Figure 7 uses an arbitration circuit 60 as the selection unit. The arbitration circuit 60 can receive access notifications from both the AHB bus 30 and the AHB bus 40, and selects the connection to the AHB bus from which it received the access notification. In the case of access from the CPU 20, the access notification is received from the AHB bus 30, and in the case of access from the DMAC 32, the access notification is received from the AHB bus 40. Therefore, when the arbitration circuit 60 is provided, it is possible to select the first path even in normal mode. In this case, since the selection is made based on the access notification from the AHB bus, input of a control signal from the PMU 54 is not required.
[0048] <Second Embodiment> As shown in Figure 8, in the second embodiment, the SRAM 50, multiplexer 52, and PMU 54 are removed from the first region 12 and placed in a third region 18 that is different from both the first region 12 and the second region 14. A power switch 17 is added to supply power to the third region 18 at all times and to turn the power supply to the first region 12 on and off. Except for these additions, the configuration is the same as the semiconductor integrated circuit according to the first embodiment, so the same components are denoted by the same reference numerals and their descriptions are omitted.
[0049] Since the third region 18 is constantly supplied with power, the PMU 54 included in the third region 18 is composed of high threshold voltage elements. Each of the SRAM 50 and the multiplexer 52 only needs to be able to handle the desired operating speed, and the types of elements that make them up can be appropriately changed according to the desired power saving effect and desired operating speed. However, it is preferable that the multiplexer 52 is composed of high threshold voltage elements that enable power saving operation.
[0050] In the second embodiment, the semiconductor integrated circuit operates in three modes: a "normal mode" in which power is supplied to the entire circuit, a "first power-saving mode" in which the power supply to the second region 14, which is a high-speed operating region, is cut off, and a "second power-saving mode" in which the power supply to the first region 12, which is a low-speed operating region, is cut off. In the normal mode and the second power-saving mode, the multiplexer 52 selects a second path connecting the SRAM 50 and the CPU 20, and in the first power-saving mode, it selects a first path connecting the SRAM 50 and the DMAC 32.
[0051] Referring to Figure 9, the operation of the semiconductor integrated circuit according to the second embodiment will be described below. The operation differs from that shown in Figure 5 in terms of the operating mode and the target of power cutoff.
[0052] First, in step S30, the CPU 20 instructs the DMAC 32 to read data from the ADC 38 and write the data to the SRAM 50 a specified number of times when it receives a data transfer request from the ADC 38.
[0053] Next, in step S32, the CPU 20 instructs the ADC 38 to periodically acquire data.
[0054] Next, in step S34, when the CPU 20 instructs the PMU 54 to switch the operating mode from normal mode to the first power-saving mode, the power supply to the second region 14 is cut off.
[0055] Next, in step S36, the PMU 54 instructs the power switch 16 to cut off the power supply and simultaneously inputs a control signal corresponding to the first power saving mode to the multiplexer 52 to select a first path connecting the SRAM 50 and the DMAC 32.
[0056] Next, in step S38, the ADC38 acquires data, and the DMAC32 transfers that data to the SRAM50, and this process is repeated for the specified number of transfers.
[0057] Next, in step S40, when the DMAC32 has completed the specified number of data transfers, it issues a transfer completion notification to the PMU54. This causes the operating mode to switch from the first power saving mode to the second power saving mode.
[0058] Next, in step S42, the PMU 54 instructs the power switch 16 to release the power cutoff for the second region 14, and instructs the power switch 17 to cut off the power for the first region 12, thereby inputting a control signal corresponding to the second power saving mode to the multiplexer 52 and causing it to select a second path connecting the SRAM 50 and the CPU 20.
[0059] Next, in step S44, the CPU 20 processes the data in the SRAM 50, returns to step S30, and repeats the operation from steps S30 to S44.
[0060] In the second embodiment, in addition to obtaining the same effects as in the first embodiment, the power supply to the first region 12 can also be cut off in the second power-saving mode, thereby further reducing overall power consumption.
[0061] In the second embodiment, as in the first embodiment, one bridge circuit can be omitted and an arbitration circuit can be used instead of a multiplexer.
[0062] <Variation> It goes without saying that the configuration of the semiconductor integrated circuit described in the above embodiment is merely an example, and its configuration may be modified without departing from the spirit of the present invention. [Explanation of symbols]
[0063] 12. First Domain 14. Second Domain 16 Power switch 17 Power switch 18. The Third Domain 20 CPU 22 FLASH / AHB Bridge 24 SRAM / AHB Bridge 26 Peripherals 28 FLASH 30 AHB bus 32 DMAC 34 SRAM / AHB Bridge 36 ADC Controllers 38 ADC 40 AHB bus 50 SRAM 52 Multiplexer 54 PMU 56 SRAM / AHB Bridge 60 Arbitration circuit 100 First Domain 102 First control unit 104 Second Domain 106 Second control unit 108 Functional Section 110 Selection Section 112 The Third Domain
Claims
1. A first control unit included in a first region where a first operating speed is permissible, A second control unit located in a second region where the power supply is cut off in power-saving mode, and where operation at a speed faster than the first operating speed is required. A functional part having a specific function, A selection unit that selects either a first path connecting the first control unit and the functional unit, or a second path connecting the second control unit and the functional unit, in accordance with a control signal. Equipped with, The functional unit and the selection unit are arranged within the first region. Semiconductor integrated circuit.
2. The semiconductor integrated circuit according to claim 1, wherein the first region other than the functional portion and the selection portion is composed of elements having a first threshold voltage, and the second region is composed of elements having a second threshold voltage lower than the first threshold voltage.
3. It operates in two modes: a normal mode in which power is supplied to the entire circuit, and a power-saving mode in which the power supply to the second region is cut off. The selection unit is composed of a multiplexer, and the multiplexer selects the second path in the normal mode and the first path in the power saving mode. A semiconductor integrated circuit according to claim 1 or claim 2.
4. It operates in two modes: a normal mode in which power is supplied to the entire circuit, and a power-saving mode in which the power supply to the second region is cut off. The selection unit is composed of an arbitration circuit, and in the normal mode, the arbitration circuit selects a first path in response to access from the first control unit and a second path in response to access from the second control unit, and in the power saving mode, it selects the first path. A semiconductor integrated circuit according to claim 1 or claim 2.
5. The functional unit and the selection unit are arranged in a third region that is different from both the first region and the second region. The first region is composed of elements having a first threshold voltage, and the second region is composed of elements having a second threshold voltage lower than the first threshold voltage. The semiconductor integrated circuit according to claim 1, wherein the third region other than the functional portion and the selection portion is composed of an element having the first threshold voltage.
6. It operates in three modes: a normal mode in which power is supplied to the entire circuit, a first power-saving mode in which the power supply to the second region is cut off, and a second power-saving mode in which the power supply to the first region is cut off. The selection unit is composed of a multiplexer, and the multiplexer selects the second path in the normal mode, the first path in the first power-saving mode, and the second path in the second power-saving mode. The semiconductor integrated circuit according to claim 5.
7. It operates in three modes: a normal mode in which power is supplied to the entire circuit, a first power-saving mode in which the power supply to the second region is cut off, and a second power-saving mode in which the power supply to the first region is cut off. The selection unit is composed of an arbitration circuit, and the arbitration circuit, in the normal mode, selects a first path in response to access from the first control unit and selects a second path in response to access from the second control unit; in the first power saving mode, it selects the first path; and in the second power saving mode, it selects the second path. The semiconductor integrated circuit according to claim 5.