Semiconductor equipment

Abstract

To provide a technique relating to a semiconductor device.SOLUTION: A semiconductor device includes: a semiconductor substrate that comprises an oxide semiconductor, and that has, when viewed from above, a rectangular shape defined by a pair of first sides extending along a first direction and a pair of second sides extending along a second direction orthogonal to the first direction; an upper electrode; and a lower electrode. The semiconductor substrate has, when the semiconductor substrate is viewed from above, an element region where a semiconductor element is formed and an outer peripheral region located around the element region. In the outer peripheral region, there is provided, on an upper face of the semiconductor substrate, a heat dissipation layer that comprises a material having a conductivity higher than that of the semiconductor substrate, and that is located to circulate around the element region. When La is a length of the first side, Lb is a length of the second side, κa is a thermal conductivity of the oxide semiconductor in the first direction, and κb is a thermal conductivity of the oxide semiconductor in the second direction, the relationship of κa<κb and κa / La<κb / Lb is satisfied.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The technology disclosed herein relates to semiconductor devices. [Background technology]

[0002] Patent Document 1 discloses a semiconductor device comprising a semiconductor substrate made of a Ga2O3-based semiconductor, an anode electrode provided on the upper surface of the semiconductor substrate, and a cathode electrode provided on the lower surface of the semiconductor substrate. In this semiconductor device, a recess is provided on the lower surface of the semiconductor substrate.

[0003] While Ga2O3 semiconductors have excellent voltage resistance, they suffer from poor heat dissipation. Patent Document 1 states that because the thickness of the semiconductor substrate is reduced in the area where the recess is formed, heat generated in the semiconductor substrate is easily dissipated, and because the thickness of the semiconductor substrate is increased in the area where the recess is not formed, the mechanical strength of the semiconductor substrate can be maintained. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Japanese Patent Publication No. 2021-106191 [Overview of the project] [Problems that the invention aims to solve]

[0005] In the semiconductor device described in Patent Document 1, the thickness of the semiconductor substrate varies significantly depending on the location, making it susceptible to localized stress due to the thermal cycles during operation of the semiconductor device. As a result, cracks may occur in the semiconductor substrate. This specification provides a technology that can improve heat dissipation while suppressing unintended stress applied to the semiconductor substrate. [Means for solving the problem]

[0006] The semiconductor device (10) disclosed in this specification is composed of an oxide semiconductor, and includes a semiconductor substrate (12) having a rectangular shape defined by a pair of first sides (14) extending along a first direction and a pair of second sides (16) extending along a second direction orthogonal to the first direction when viewed from above, an upper electrode (70), and a lower electrode (72). The semiconductor substrate has an element region (60) where semiconductor elements are formed and an outer peripheral region (62) disposed around the element region when viewed from above. The upper electrode is in contact with the upper surface (12a) of the semiconductor substrate within the element region. The lower electrode is in contact with the lower surface (12b) of the semiconductor substrate. In the outer peripheral region, a heat dissipation layer (28) made of a material having a higher thermal conductivity than the semiconductor substrate and disposed so as to surround the element region is provided on the upper surface of the semiconductor substrate. Let the length of the first side be L a , let the length of the second side be L b , let the thermal conductivity of the oxide semiconductor in the first direction be κ a , let the thermal conductivity of the oxide semiconductor in the second direction be κ b . When this is the case, κ a < κ b , and κ a / L a < κ b / L b The relationship is satisfied.

[0007] When the above semiconductor device operates, a current flows between the upper electrode and the lower electrode, and the semiconductor substrate in the element region generates heat. Since the oxide semiconductor has anisotropy in thermal conductivity, the heat generated in the semiconductor substrate is likely to conduct in the direction with high thermal conductance. In the above semiconductor device, the thermal conductance in the first direction and the second direction is κ a / L a < κ b / L bThe relationship is satisfied. Therefore, the heat generated in the element region first conducts along the second direction with higher thermal conductivity. Since a heat dissipation layer with a higher thermal conductivity than the semiconductor substrate is provided in the outer peripheral region, the heat conducted from the element region to the outer peripheral region along the second direction is dissipated to the outside of the semiconductor substrate through the heat dissipation layer. Thus, in the semiconductor device described above, by adjusting the thermal conductivity of the semiconductor substrate and providing a heat dissipation layer in the outer peripheral region, it is possible to improve the heat dissipation performance while suppressing the unintended stress applied to the semiconductor substrate.

Brief Description of the Drawings

[0008] [Figure 1] Plan view of the semiconductor device of the embodiment as viewed from above. [Figure 2] Cross-sectional view taken along line II-II of FIG. 1. [Figure 3] Diagram for explaining the manufacturing process of the semiconductor device of the embodiment. [Figure 4] Diagram for explaining the manufacturing process of the semiconductor device of the embodiment. [Figure 5] Diagram for explaining the manufacturing process of the semiconductor device of the embodiment. [Figure 6] Cross-sectional view corresponding to FIG. 2 of the semiconductor device of the modified example. [Figure 7] Plan view corresponding to FIG. 1 of the semiconductor device of another modified example.

Modes for Carrying Out the Invention

[0009] In a semiconductor device of an example disclosed in this specification, L a >L b The relationship may be satisfied.

[0010] In such a configuration, the second side along the second direction with high thermal conductivity is shorter than the first side. Since the heat generated in the element region easily conducts along the second direction with a shorter distance to the outer peripheral region, the heat dissipation performance can be further improved.

[0011] In a semiconductor device of an example disclosed in this specification, Lb It may be 6 mm or less.

[0012] In semiconductor devices, when the side length of the semiconductor substrate is 6 mm or less, the thermal resistance increases significantly, and heat dissipation deteriorates. For this reason, the technology disclosed herein is more effective in the above configuration.

[0013] In one example semiconductor device disclosed herein, the heat dissipation layer may have a higher dielectric breakdown field than the semiconductor substrate.

[0014] In this configuration, high pressure resistance can be maintained in the outer region.

[0015] An example semiconductor device disclosed herein may further include an insulating film covering the upper surface and the heat dissipation layer of the semiconductor substrate within the peripheral region, and a metal layer provided on the upper surface of the insulating film and connected to the upper electrode.

[0016] In this configuration, the metal layer can maintain the mechanical strength of the outer region, and the heat conducted to the heat dissipation layer is dissipated through the metal layer, thus improving heat dissipation.

[0017] In one example semiconductor device disclosed herein, a first type semiconductor device and a second type semiconductor device different from the first type semiconductor device may be formed in the device region of the semiconductor substrate, and the first type semiconductor device and the second type semiconductor device may be arranged along the second direction.

[0018] In this configuration, heat tends to accumulate near the boundary between the first and second type semiconductor elements. Therefore, by arranging the first and second type semiconductor elements along a second direction, heat can be dissipated efficiently.

[0019] In one example semiconductor device disclosed herein, the oxide semiconductor may be β-Ga2O3.

[0020] (Examples) The semiconductor device 10 in the embodiment shown in Figures 1 and 2 is a Schottky barrier diode. The semiconductor device 10 includes a semiconductor substrate 12, an upper electrode 70, a lower electrode 72, etc. In Figure 1, for the sake of clarity, some components on the upper surface 12a of the semiconductor substrate 12 are omitted from the illustration.

[0021] The semiconductor substrate 12 is composed of an oxide semiconductor. Specifically, the semiconductor substrate 12 is composed of β-Ga2O3. However, the material of the semiconductor substrate 12 is not limited to β-Ga2O3, and other gallium oxide semiconductors such as (Ga,Rh)2O3, (Ga,Ir)2O3, (Ga,Bi)2O3, and ZnGa2O4, or other oxide semiconductors may be used.

[0022] As shown in Figure 1, the semiconductor substrate 12 has a rectangular shape defined by a pair of sides 14 extending along the x-direction and a pair of sides 16 extending along the y-direction when viewed from above. In Figure 1, the planes along the x and z directions are the (010) planes of β-Ga2O3, the planes along the y and z directions are the (100) planes of β-Ga2O3, and the planes along the x and y directions are the (001) planes of β-Ga2O3. That is, the x-direction is the

[0100] direction, the y-direction is the

[0010] direction, and the z-direction is the

[0001] direction. Furthermore, β-Ga2O3 exhibits anisotropy in its thermal conductivity. Specifically, the thermal conductivity in the

[0100] direction is 13.6 W / mk, and the thermal conductivity in the

[0010] direction is 22.8 W / mk. In other words, the thermal conductivity in the

[0100] direction is lower than the thermal conductivity in the

[0010] direction. Also, in this embodiment, the first side 14 is longer than the second side 16. For example, the first side 14 is 10 mm and the second side 16 is 6 mm. In other words, the thermal conductance in the

[0100] direction (thermal conductivity divided by the side length) is lower than the thermal conductance in the

[0010] direction.

[0023] The semiconductor substrate 12 has an element region 60 and an outer peripheral region 62. As shown in Figure 1, the element region 60 is located in the center of the semiconductor substrate 12 when viewed from above. The element region 60 is the region where the semiconductor element (diode structure in this embodiment) is formed. The outer peripheral region 62 is the outer periphery of the semiconductor substrate 12 when viewed from above, and is located around the element region 60.

[0024] As shown in Figure 2, within the device region 60, a plurality of trenches 22 are provided on the upper surface 12a of the semiconductor substrate 12. Each trench 22 extends linearly in the x direction. Each trench 22 is spaced apart in the y direction. The inner surface of each trench 22 is covered with an oxide film 24. The upper electrode 70 is positioned within the device region 60 so as to straddle the upper surface 12a of the semiconductor substrate 12 from inside each trench 22. The upper electrode 70 also straddles a part of the outer peripheral region 62 from the device region 60. Inside each trench 22, the upper electrode 70 is insulated from the semiconductor substrate 12 by the oxide film 24. The upper electrode 70 is in Schottky contact with the upper surface 12a of the semiconductor substrate 12. The upper electrode 70 functions as an anode electrode.

[0025] As shown in Figure 2, a mesa portion 26 is provided on the upper surface 12a of the semiconductor substrate 12 within the outer peripheral region 62. The depth of the mesa portion 26 is slightly deeper than the depth of the trench 22 within the device region 60. Within the outer peripheral region 62, a plurality of heat dissipation layers 28 are formed on the upper surface 12a of the semiconductor substrate 12 (the bottom surface of the mesa portion 26). As shown in Figure 1, each heat dissipation layer 28 is arranged concentrically so as to encircle the device region 60. The heat dissipation layers 28 are made of a material that has a higher thermal conductivity and a higher dielectric breakdown field than the semiconductor substrate 12. For example, the heat dissipation layers 28 are made of AlN (i.e., aluminum nitride). The thermal conductivity of AlN is 230 W / mK, and the dielectric breakdown field of AlN is 12 MV / cm (β-Ga2O3 is 8 MV / cm). The heat dissipation layers 28 and the upper surface 12a of the semiconductor substrate 12 (including the inner surface of the mesa portion 26) are covered with an insulating film 29. The oxide film 24 within the element region 60 and the insulating film 29 within the outer peripheral region 62 are connected at the boundary between the element region 60 and the outer peripheral region 62.

[0026] As shown in Figure 2, the upper surface of the upper electrode 70 within the element region 60 and the upper surface of the insulating film 29 within the outer peripheral region 62 are covered by a passivation film 30. The passivation film 30 has an opening at a position not shown, at which the upper electrode 70 is connected to the outside (e.g., a bonding pad).

[0027] The lower electrode 72 is positioned on the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is formed over substantially the entire area of ​​the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 is in ohmic contact with the lower surface 12b of the semiconductor substrate 12. The lower electrode 72 functions as a cathode electrode.

[0028] As shown in Figure 2, the inside of the semiconductor substrate 12 contains n + n-type semiconductor layer 40, n-type semiconductor layer 42, n - A type semiconductor layer 44 is provided. + The n-type semiconductor layer 40 is provided in a position that spans the device region 60 and the outer peripheral region 62 and is in contact with the lower electrode 72. The n-type semiconductor layer 42 is n +It is provided on the upper side of the n-type semiconductor layer 40. The n-type semiconductor layer 42 is n + The n-type impurity concentration is lower than that of the n-type semiconductor layer 40. The n-type semiconductor layer 42 is provided spanning the device region 60 and the outer peripheral region 62. Within the device region 60, the n-type semiconductor layer 42 is n + It extends from the upper edge of the n-type semiconductor layer 40 to a position where it reaches the upper surface 12a of the semiconductor substrate 12. Within the outer peripheral region 62, on the upper side of the n-type semiconductor layer 42 - A type semiconductor layer 44 is provided. - The n-type semiconductor layer 44 has a lower n-type impurity concentration than the n-type semiconductor layer 42. - The n-type semiconductor layer 44 extends from the upper end of the n-type semiconductor layer 42 to a position where it reaches the upper surface 12a of the semiconductor substrate 12 (the bottom surface of the mesa portion 26).

[0029] In the semiconductor device 10 of this embodiment, when a forward bias is applied between the upper electrode 70 and the lower electrode 72, the Schottky barrier at the interface between the upper electrode 70 and the semiconductor substrate 12 (n-type semiconductor layer 42) decreases, and current flows from the upper electrode 70 to the lower electrode 72. On the other hand, when a reverse bias is applied between the upper electrode 70 and the lower electrode 72, the Schottky barrier at the interface between the upper electrode 70 and the semiconductor substrate 12 (n-type semiconductor layer 42) increases, and the current stops.

[0030] When the semiconductor device 10 operates in this manner, current flows between the upper electrode 70 and the lower electrode 72, causing the semiconductor substrate 12 within the element region 60 to heat up. As described above, β-Ga2O3 has anisotropy in its thermal conductivity, so the heat generated in the semiconductor substrate 12 is more easily conducted in the direction of higher thermal conductance. In the semiconductor device 10 of this embodiment, the first side 14 (the side along the

[0100] direction) is longer than the second side 16 (the side along the

[0010] direction), and the thermal conductance in the

[0100] direction is lower than the thermal conductance in the

[0010] direction. Therefore, the heat generated within the element region 60 is conducted along the

[0010] direction, where the thermal conductance is higher. Since the distance to the outer peripheral region 62 is short in the

[0010] direction, the heat within the element region 60 can be quickly conducted to the outer peripheral region 62. Furthermore, since a heat dissipation layer 28 with a higher thermal conductivity than the semiconductor substrate 12 is provided in the outer peripheral region 62, the heat conducted from the element region 60 along the

[0010] direction to the outer peripheral region 62 is dissipated to the outside of the semiconductor substrate 12 via the heat dissipation layer 28. In this way, in the semiconductor device 10 of this embodiment, by adjusting the thermal conductance of the semiconductor substrate 12 and providing a heat dissipation layer 28 in the outer peripheral region 62, it is possible to improve heat dissipation while suppressing unintended stress applied to the semiconductor substrate 12.

[0031] Furthermore, in the semiconductor device 10 of this embodiment, the second side 16 is 6 mm. In the semiconductor device 10, if one side of the semiconductor substrate 12 is 6 mm or less, the thermal resistance increases significantly, and the heat dissipation performance deteriorates. For this reason, the above-described technique is more effective when the size of the semiconductor substrate 12 is relatively small, as in this embodiment.

[0032] Furthermore, in this embodiment, the dielectric breakdown field of the heat dissipation layer 28 is higher than that of the semiconductor substrate 12. Therefore, a high dielectric strength can be maintained in the outer peripheral region 62.

[0033] Next, the manufacturing method of the semiconductor device 10 will be described. First, as shown in Figure 3, n composed of β-Ga2O3 +A semiconductor substrate 12 is prepared having a type semiconductor layer 40 and an n-type semiconductor layer 42 composed of β-Ga2O3, and a plurality of trenches 22 and mesa portions 26 are formed on the upper surface 12a of the semiconductor substrate 12. The semiconductor substrate 12 before processing is, for example, n + The device can be manufactured by forming an n-type semiconductor layer 42 on the upper surface of the n-type semiconductor layer 40 by epitaxial growth. In this process, each trench 22 is formed within the device region 60, and a mesa portion 26 is formed within the outer peripheral region 62 so as to encircle the device region 60.

[0034] Next, as shown in Figure 4, p-type impurities (e.g., Fe ions, N ions, Mg ions, etc.) are implanted in the outer peripheral region 62 in the area exposed to the upper surface 12a of the semiconductor substrate 12 and the bottom surface of the mesa portion 26, thereby creating an n-type semiconductor layer with a lower n-type impurity concentration than the n-type semiconductor layer 42. - A type semiconductor layer 44 is formed. Subsequently, a plurality of heat dissipation layers 28 made of AlN are formed on the upper surface 12a of the semiconductor substrate 12 within the outer peripheral region 62. The heat dissipation layers 28 are formed concentrically so as to encircle the element region 60. The heat dissipation layers 28 can be formed, for example, by depositing an AlN film over the entire upper surface 12a of the semiconductor substrate 12 using a CVD (chemical vapor deposition) method, and then selectively etching the AlN.

[0035] Next, as shown in Figure 5, an oxide film 24 is formed in the element region 60 to cover the upper surface 12a of the semiconductor substrate 12 and the inner surface of the trench 22, and an insulating film 29 is formed in the outer peripheral region 62 to cover the upper surface 12a of the semiconductor substrate 12 and the inner surface of the mesa portion 26. After this, the semiconductor substrate 12 is subjected to annealing. Subsequently, the oxide film 24 covering the upper surface 12a of the semiconductor substrate 12 in the element region 60 is selectively removed by etching, and then the upper electrode 70, lower electrode 72, and passivation film 30 are formed to complete the semiconductor device 10 shown in Figure 2.

[0036] In the above-described embodiment, as shown in Figure 6, a metal layer 74 may be further provided within the outer peripheral region 62, on the upper surface of the insulating film 29 and connected to the upper electrode 70. In this configuration, the metal layer 74 can maintain the mechanical strength of the outer peripheral region 62, and the heat conducted to the heat dissipation layer 28 is dissipated through the metal layer 74, thereby further improving heat dissipation.

[0037] Furthermore, although the above-described embodiment explained an example in which a Schottky barrier diode is formed as a semiconductor element within the element region 60, the semiconductor element formed within the element region 60 may be, for example, a MOSFET (metal-oxide-semiconductor field-effect transistor) or an IGBT (insulated-gate bipolar transistor). Also, as shown in Figure 7, two types of semiconductor elements 80 and 82 (for example, a diode and a MOSFET) may be formed within the element region 60 of a single semiconductor substrate 12. In this case, as shown in Figure 7, the semiconductor elements 80 and 82 may be arranged along the

[0010] direction, which has higher thermal conductance. With this configuration, heat that tends to accumulate near the boundary between semiconductor element 80 and semiconductor element 82 can be efficiently dissipated.

[0038] In the embodiment described above, the first side 14 was longer than the second side 16, but the relationship between the lengths of the first side 14 and the second side 16 is not limited to this. If the thermal conductance in the

[0100] direction is lower than the thermal conductance in the

[0010] direction, the first side 14 may be shorter than the second side 16, or the first side 14 and the second side 16 may be of equal length.

[0039] The components disclosed herein are listed below. (Composition 1) A semiconductor device, A semiconductor substrate made of an oxide semiconductor, having a rectangular shape defined by a pair of first sides extending along a first direction and a pair of second sides extending along a second direction perpendicular to the first direction when viewed from above, Upper electrode and Lower electrode and It is equipped with, The semiconductor substrate, when viewed from above, has an element region on which semiconductor elements are formed and an outer peripheral region arranged around the element region. The upper electrode is in contact with the upper surface of the semiconductor substrate within the element region. The lower electrode is in contact with the lower surface of the semiconductor substrate. In the outer peripheral region, a heat dissipation layer is provided on the upper surface of the semiconductor substrate, which is made of a material with a higher thermal conductivity than the semiconductor substrate and is arranged to encircle the element region. Let the length of the first side be L. a , the length of the second side is L b , the thermal conductivity of the oxide semiconductor in the first direction is κ a , the thermal conductivity of the oxide semiconductor in the second direction is κ b When this is the case, κ a <κ b , and κ a / L a <κ b / L b The relationship is satisfied, Semiconductor equipment. (Configuration 2) L a >L b A semiconductor device as described in Configuration 1, which satisfies the relationship. (Composition 3) L b A semiconductor device according to configuration 1 or 2, wherein the diameter is 6 mm or less. (Composition 4) The heat dissipation layer has a higher dielectric breakdown field than the semiconductor substrate, as described in any of configurations 1 to 3. (Composition 5) An insulating film covering the upper surface and the heat dissipation layer of the semiconductor substrate in the outer peripheral region, A metal layer provided on the upper surface of the insulating film and connected to the upper electrode, A semiconductor device according to any of configurations 1 to 4, further comprising the above. (Composition 6) A first type semiconductor element and a second type semiconductor element different from the first type semiconductor element are formed in the element region of the semiconductor substrate. A semiconductor device according to any one of configurations 1 to 5, wherein the first type semiconductor element and the second type semiconductor element are arranged along the second direction. (Composition 7) The semiconductor device according to any one of configurations 1 to 6, wherein the oxide semiconductor is β-Ga2O3.

[0040] Although embodiments have been described in detail above, these are merely illustrative and do not limit the scope of the claims. The technologies described in the claims include various modifications and changes to the specific examples illustrated above. The technical elements described in this specification or drawings exhibit technical usefulness individually or in various combinations, and are not limited to the combinations described in the claims at the time of filing. Furthermore, the technologies illustrated in this specification or drawings achieve multiple objectives simultaneously, and achieving even one of these objectives constitutes technical usefulness. [Explanation of symbols]

[0041] 10: Semiconductor device, 12: Semiconductor substrate, 12a: Top surface, 12b: Bottom surface, 14: First edge, 16: Second edge, 28: Heat dissipation layer, 29: Insulating film, 60: Element region, 62: Outer periphery region, 70: Upper electrode, 72: Lower electrode, 74: Metal layer

Claims

1. Semiconductor device (10), A semiconductor substrate (12) made of an oxide semiconductor, having a rectangular shape defined by a pair of first edges (14) extending along a first direction when viewed from above and a pair of second edges (16) extending along a second direction perpendicular to the first direction, Upper electrode (70) and Lower electrode (72) and It is equipped with, The semiconductor substrate, when viewed from above, has an element region (60) on which a semiconductor element is formed, and an outer peripheral region (62) arranged around the element region. The upper electrode is in contact with the upper surface (12a) of the semiconductor substrate within the element region. The lower electrode is in contact with the lower surface (12b) of the semiconductor substrate. In the outer peripheral region, a heat dissipation layer (28) is provided on the upper surface of the semiconductor substrate, which is made of a material with a higher thermal conductivity than the semiconductor substrate and is arranged to encircle the element region. Let the length of the first side be L ａ and the length of the second side be L ｂ Let the thermal conductivity of the oxide semiconductor in the first direction be κ ａ and the thermal conductivity of the oxide semiconductor in the second direction be κ ｂ When this is the case, κ ａ < κ ｂ and κ ａ / L ａ < κ ｂ / L ｂ The relationship is satisfied Semiconductor equipment.

2. L ａ > L ｂ The semiconductor device according to claim 1, wherein the relationship is satisfied.

3. L ｂ The semiconductor device according to claim 1, wherein the diameter is 6 mm or less.

4. The semiconductor device according to claim 1, wherein the heat dissipation layer has a higher dielectric breakdown field than the semiconductor substrate.

5. An insulating film (29) covering the upper surface and the heat dissipation layer of the semiconductor substrate within the outer peripheral region, A metal layer (74) provided on the upper surface of the insulating film and connected to the upper electrode, The semiconductor device according to claim 1, further comprising:

6. The element region of the semiconductor substrate has a first type semiconductor element (80) and a second type semiconductor element (82) that is different from the first type semiconductor element formed therein. The semiconductor device according to claim 1, wherein the first type semiconductor element and the second type semiconductor element are arranged along the second direction.

7. The oxide semiconductor is β-Ga ２ O ３ The semiconductor device according to claim 1.

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