Apparatus and method for reducing the resistance difference between near-near-far-far memory cells in a memory array.

Abstract

An apparatus and method for reducing the resistance difference of near-near-far-far memory cells in a memory array is provided. The device includes a first memory cell coupled between a first word line and a first bit line and coupled in series with a first word line resistance and a first bit line resistance, and a second memory cell coupled between a second word line and a second bit line and coupled in series with a second word line resistance and a second bit line resistance, wherein the first memory cell includes a first hard mask including a first hard mask material having a first resistivity, and the second memory cell includes a second hard mask including a second hard mask material having a second resistivity lower than the first resistivity. X The first hard mask compensates for a difference between a first sum of the first word line resistance and the first bit line resistance and a second sum of the second word line resistance and the second bit line resistance.

Description

[Technical Field]

[0001] Memory is widely used in various electronic devices such as mobile phones, digital cameras, personal information terminals, medical electronic devices, mobile computing devices, non-mobile computing devices, and data servers. Memory may include non-volatile memory or volatile memory. Non-volatile memory allows information to be stored and retained even when it is not connected to a power source (e.g., a battery).

[0002] One example of non-volatile memory is magnetoresistive random access memory (MRAM). In contrast to other memory technologies that use electron charge to store data, this memory uses magnetization to represent stored data. Generally, MRAM contains numerous magnetic memory cells formed on a semiconductor substrate, and each memory cell on the semiconductor substrate represents one bit of data.

[0003] Data bits are written to a memory cell by changing the magnetization direction of the magnetic elements within the memory cell, and bits are read out by measuring the resistance of the memory cell (low resistance typically represents a "0" bit, and high resistance typically represents a "1" bit). As used herein, the magnetization direction is the direction of orientation of the magnetic moment. Some memory cells may include selector devices such as obonic threshold switches or other selector devices.

[0004] MRAM is a promising technology, but many design and process challenges remain. [Brief explanation of the drawing]

[0005] [Figure 1A] Various embodiments of the memory system are shown. [Figure 1B] Various embodiments of the memory system are shown. [Figure 1C]Various embodiments of the memory system are shown. [Figure 1D] Various embodiments of the memory system are shown. [Figure 1E] Various embodiments of the memory system are shown. [Figure 1F] Various embodiments of the memory system are shown. [Figure 1G] Various embodiments of the memory system are shown. [Figure 1H] Various embodiments of the memory system are shown. [Figure 2A] This shows one embodiment of a three-dimensional memory array. [Figure 2B] Figure 2A shows one embodiment of a memory cell in a three-dimensional memory array. [Figure 2C] Figure 2B shows an exemplary current-voltage characteristic of the threshold selector device. [Figure 3A] One embodiment of a crosspoint memory array is shown. [Figure 3B] One embodiment of a crosspoint memory array is shown. [Figure 4A] This is a top-level diagram of a memory block. [Figure 4B] Figure 4A is a top-level diagram of the memory array of the memory block. [Figure 4C] A simplified model of the memory array shown in Figure 4B includes word line resistance and bit line resistance. [Figure 5A] This is a simplified perspective view of a memory block. [Figure 5B] Figure 5A is a simplified perspective view of one embodiment of a memory cell in a memory array of a memory block. [Figure 5C] Figure 5B is a simplified cross-sectional view of a memory cell during exemplary manufacturing. [Figure 5D] Figure 5B is a simplified cross-sectional view of an alternative, exemplary memory cell during manufacturing. [Figure 5E] Figure 5D is a simplified flowchart of the process for forming a memory array, including a portion of the memory array shown. [Figure 5F]Figure 5B is a simplified cross-sectional view of another alternative, exemplary memory cell during manufacturing. [Figure 5G] Figure 5B is a simplified cross-sectional view of another alternative, exemplary memory cell during manufacturing. [Figure 6] Figure 5A is a flowchart of one embodiment of a method for forming a memory array, such as a memory array of memory blocks. [Modes for carrying out the invention]

[0006] A certain type of memory array includes memory cells, which include multiple word lines, multiple bit lines, and magnetic memory elements coupled in series with selector elements located at the intersections of each word line and each bit line. The word lines are coupled to word line driver circuits, and the bit lines are coupled to bit line driver circuits. Due to the array configuration, some memory cells are located close to the word line driver circuits and bit line driver circuits, while other memory cells are located away from them.

[0007] As a result of resistance in the word and bit lines, a resistance difference exists between memory cells located close to the word and bit line driver circuits and memory cells located further away from them. This resistance difference can cause many problems during the operation of the memory array. In particular, memory cells located close to the word and bit line driver circuits experience higher read disturbance and endurance problems compared to memory cells located further away from them.

[0008] Techniques for reducing the resistance difference between memory cells located close to word line driver circuits and bit line driver circuits and memory cells located away from word line driver circuits and bit line driver circuits are described. In some embodiments, additional resistance is coupled to and / or incorporated into memory cells located close to word line driver circuits and bit line driver circuits. In some embodiments, the additional resistance is substantially equal to the resistance difference between memory cells located close to word line driver circuits and bit line driver circuits and memory cells located away from word line driver circuits and bit line driver circuits.

[0009] In some embodiments, the memory cell includes a memory element coupled in series with a selector device. In one embodiment, the memory element is a magnetic memory element. In one embodiment, the memory element is a magnetic tunnel junction memory element. In one embodiment, the selector device is an obonic threshold switch.

[0010] In one embodiment, memory cells in a memory array may include non-volatile memory cells that include a reversible resistive switching element. The reversible resistive switching element may include a reversible resistive switching material having a resistivity that can be reversibly switched between two or more states.

[0011] In one embodiment, the reversible resistive switching material may include a metal oxide, a solid electrolyte, a phase change material, a magnetic material, or other similar resistivity switching material. Various metal oxides, such as transition metal oxides, can be used. Examples of metal oxides include NiO, Nb2O5, TiO2, HfO2, Al2O3, and MgO. x Examples include, but are not limited to, CrO2, VO, BN, TaO2, Ta2O3, and AlN.

[0012] In one embodiment, the non-volatile memory cells in the memory array include one-time programmable memory cells. In another embodiment, the non-volatile memory cells in the memory array include rewritable memory cells.

[0013] Figure 1A shows one embodiment of the memory system 100 and host 102. The memory system 100 may include a non-volatile storage system interfaced with the host 102 (e.g., a mobile computing device or server). In some cases, the memory system 100 may be embedded within the host 102. For example, the memory system 100 may be a memory card, a solid-state drive (SSD) such as a high-density MLC SSD (e.g., 2 bits / cell or 3 bits / cell) or a high-performance SLC SSD, or a hybrid HDD / SSD drive.

[0014] As shown in the figure, the memory system 100 includes a memory chip controller 104 and a memory chip 106. The memory chip 106 may include volatile memory and / or non-volatile memory. Although a single memory chip is shown, the memory system 100 may include two or more memory chips. The memory chip controller 104 can receive data and commands from the host 102 and provide memory chip data to the host 102.

[0015] The memory chip controller 104 may include one or more of the following to control the operation of the memory chip 106: a control circuit, a state machine, a page register, an SRAM, a decoder, a sense amplifier, a read / write circuit, and / or a controller, or any combination thereof. One or more of the control circuits, state machines, page registers, SRAM, decoders, sense amplifiers, read / write circuits, and / or controllers for controlling the operation of the memory chip may be referred to as a management circuit or control circuit. The management circuit or control circuit can facilitate one or more memory array operations, including forming, erasing, programming, or reading operations.

[0016] In some embodiments, a management circuit or control circuit (or part of a management circuit or control circuit) for facilitating the operation of one or more memory arrays may be integrated within the memory chip 106. The memory chip controller 104 and the memory chip 106 may be located on a single integrated circuit or on a single die. In other embodiments, the memory chip controller 104 and the memory chip 106 may be located on different integrated circuits. In some cases, the memory chip controller 104 and the memory chip 106 may be integrated on a system board, circuit logic board, or PCB.

[0017] The memory chip 106 includes a memory core control circuit 108 and a memory core 110. The memory core control circuit 108 may include logic for selecting memory blocks (or arrays) within the memory core 110, for generating voltage references to bias a particular memory array into a read or write state, and for generating row and column addresses.

[0018] The memory core 110 may include one or more two-dimensional arrays of memory cells and / or one or more three-dimensional arrays of memory cells. In one embodiment, the memory core may include rewritable memory cells, one-time programmable memory cells, and / or multi-time programmable memory cells, or any combination thereof.

[0019] In one embodiment, the memory core control circuit 108 and the memory core 110 may be located on a single integrated circuit. In other embodiments, the memory core control circuit 108 (or a part of the memory core control circuit 108) and the memory core 110 may be located on different integrated circuits.

[0020] A memory operation can be initiated when the host 102 sends a command to the memory chip controller 104 indicating that it wants to read data from or write data to the memory system 100. In the case of a write (or programming) operation, the host 102 can send both the write command and the data to be written to the memory chip controller 104.

[0021] The memory chip controller 104 can buffer the data to be written and generate error correction code (ECC) data corresponding to the data to be written. The ECC data, which enables the detection and / or correction of data errors occurring during transmission or storage, can be written to the memory core 110 or stored on a non-memory chip within the volatile memory controller 104. In one embodiment, the ECC data is generated and data errors are corrected by circuitry within the memory chip controller 104.

[0022] The memory chip controller 104 can control the operation of the memory chip 106. For example, before issuing a write operation to the memory chip 106, the memory chip controller 104 can check the status register to confirm that the memory chip 106 is able to accept the data to be written.

[0023] In another example, before issuing a read operation to the memory chip 106, the memory chip controller 104 may pre-read overhead information related to the data to be read. This overhead information may include ECC data associated with the data to be read, or a redirection pointer to a new memory location in the memory chip 106 from which the requested data will be read.

[0024] When the memory chip controller 104 starts a read or write operation, the memory core control circuit 108 can generate appropriate bias voltages and / or currents for the word lines and bit lines in the memory core 110, as well as generate appropriate memory block, row, and column addresses.

[0025] Figure 1B shows one embodiment of the memory core control circuit 108. In one embodiment, the memory core control circuit 108 includes an address decoder 120, a voltage generator 122 for selected control lines, and a voltage generator 124 for unselected control lines. The control lines may include word lines, bit lines, or a combination of word lines and bit lines. The selected control lines may include selected word lines or selected bit lines, and they are used to place the memory cell in a selected state. The unselected control lines may include unselected word lines or unselected bit lines, and they are used to place the memory cell in an unselected state.

[0026] The voltage generator (or voltage regulator) 122 for the selected control line may include one or more voltage generators for generating the selected control line voltage. The voltage generator 124 for the unselected control line may include one or more voltage generators for generating the unselected control line voltage. The address decoder 120 can generate memory block addresses, as well as row and column addresses for a particular memory block.

[0027] Figures 1C to 1F show one embodiment of a memory core organization including a memory core 110 having a plurality of memory bays, each memory bay having a plurality of memory blocks. A memory core organization is disclosed in which the memory bays include memory blocks and the memory blocks include groups of memory cells, but other organizations or groupings can also be used in conjunction with the techniques described herein.

[0028] Figure 1C shows one embodiment of the memory core 110 of Figure 1A. As shown, the memory core 110 includes memory bays 130 and 132. In some embodiments, the number of memory buses per memory core may vary for different implementation configurations. For example, the memory core may include only a single memory bay or multiple memory bays (e.g., 16 memory bays, 256 memory bays, etc.).

[0029] Figure 1D shows one embodiment of the memory bay 130 of Figure 1C. As shown, the memory bay 130 includes memory blocks 140-144 and a read / write circuit 150. In some embodiments, the number of memory blocks per memory bay may vary for different implementation configurations. For example, a memory bay may contain one or more memory blocks (e.g., 32 memory blocks per memory bay).

[0030] The read / write circuit 150 includes circuits for reading and writing memory cells in memory blocks 140-144. As shown in the figure, the read / write circuit 150 may be shared across multiple memory blocks in the memory bay. This allows multiple memory blocks to be supported using a single group of read / write circuits 150, thereby reducing the chip area. However, in some embodiments, to avoid signal contention, only a single memory block may be electrically coupled to the read / write circuit 150 at any given time.

[0031] In some embodiments, the read / write circuit 150 may be used to write one or more pages of data to memory blocks 140-144 (or a subset of memory blocks). The memory cells in memory blocks 140-144 can enable direct overwriting of pages (i.e., data representing a page or part of a page can be written to memory blocks 140-144 without having to perform an erase or reset operation on the memory cells before writing the data).

[0032] In one example, the memory system 100 in Figure 1A may receive a write command that includes a target address and a set of data to be written to the target address. Before performing a write operation to write the set of data to the target address, the memory system 100 may perform a read-before-write (RBW) operation to read the data currently stored at the target address. The memory system 100 can then determine whether a particular memory cell can remain in its current state (i.e., the memory cell is already in the correct state), needs to be set to a "0" state, or needs to be reset to a "1" state.

[0033] Next, the memory system 100 can write a first subset of memory cells to the "0" state, and then write a second subset of memory cells to the "1" state. Memory cells that are already in the correct state can be skipped, thereby improving the programming speed and reducing the cumulative voltage stress applied to unselected memory cells.

[0034] A particular memory cell can be set to a "1" state by applying a first voltage difference across that particular memory cell with a first polarity (e.g., +1.5V). A particular memory cell can be reset to a "0" state by applying a second voltage difference across that particular memory cell with a second polarity opposite to that of the first polarity (e.g., -1.5V).

[0035] In some cases, the read / write circuit 150 may be used to program a particular memory cell to be in one of three or more data / resistance states (i.e., the particular memory cell may include a multilevel memory cell). For example, the read / write circuit 150 may apply a first voltage difference (e.g., 2V) across a particular memory cell to program it to a first state among three or more data / resistance states, or it may apply a second voltage difference (e.g., 1V) smaller than the first voltage difference across a particular memory cell to program it to a second state among three or more data / resistance states.

[0036] By applying a smaller voltage difference across a specific memory cell, the specific memory cell can be partially or fully programmed at a slower rate than when a larger voltage difference is applied. In another example, the read / write circuit 150 may apply a first voltage difference across the specific memory cell for a first period (e.g., 150 ns) to program the specific memory cell to a first state among three or more data / resistance states, or it may apply the first voltage difference across the specific memory cell for a second period shorter than the first period (e.g., 50 ns). The specific memory cell can be programmed to the correct state using one or more programming pulses following the memory cell verification phase.

[0037] Figure 1E shows one embodiment of the memory block 140 of Figure 1D. As shown, the memory block 140 includes a memory array 160, a row decoder 162, and a column decoder 164. The memory array 160 may include a contiguous group of memory cells having contiguous word lines and bit lines. The memory array 160 may include one or more layers of memory cells and may include a two-dimensional memory array and / or a three-dimensional memory array.

[0038] The row decoder 162 decodes the row address and, if appropriate (for example, when reading or writing memory cells in the memory array 160), selects a specific word line in the memory array 160. The column decoder 164 decodes the column address and selects a specific group of bit lines in the memory array 160, which are electrically coupled to a read / write circuit, such as the read / write circuit 150 in Figure 1D. In one embodiment, the number of word lines is 4K per memory layer, the number of bit lines is 1K per memory layer, the number of memory layers is 4, and the memory array 160 contains 16M memory cells. Other numbers of word lines per layer, bit lines per layer, and the number of layers may be used.

[0039] Figure 1F shows one embodiment of the memory bay 170. The memory bay 170 is an example of an alternative implementation of the memory bay 130 in Figure 1D. In some embodiments, the row decoder, column decoder, and read / write circuitry may be separated or shared between memory arrays. As shown, the row decoder 172 is shared between memory arrays 174 and 176 because the row decoder 172 controls the word lines in both memory arrays 174 and 176 (i.e., the word lines driven by the row decoder 172 are shared).

[0040] Row decoders 178 and 172 can be divided such that even word lines in the memory array 174 are driven by row decoder 178, and odd word lines in the memory array 174 are driven by row decoder 172. Column decoders 180 and 182 can be divided such that even bit lines in the memory array 174 are controlled by column decoder 182, and odd bit lines in the memory array 174 are driven by column decoder 180.

[0041] A selected bit line controlled by the column decoder 180 may be electrically coupled to the read / write circuit 184. A selected bit line controlled by the column decoder 182 may be electrically coupled to the read / write circuit 186. Dividing the read / write circuit into read / write circuits 184 and 186 when the column decoder is divided may allow for a more efficient layout of the memory bay.

[0042] Row decoders 188 and 172 can be divided such that even word lines in the memory array 176 are driven by row decoder 188 and odd word lines in the memory array 176 are driven by row decoder 172. Column decoders 190 and 192 can be divided such that even bit lines in the memory array 176 are controlled by column decoder 192 and odd bit lines in the memory array 176 are driven by column decoder 190.

[0043] A selected bit line controlled by the column decoder 190 may be electrically coupled to the read / write circuit 184. A selected bit line controlled by the column decoder 192 may be electrically coupled to the read / write circuit 186. Dividing the read / write circuit into read / write circuits 184 and 186 when the column decoder is divided may allow for a more efficient layout of the memory bay.

[0044] Figure 1G shows one embodiment of a schematic diagram (including word lines and bit lines) corresponding to the memory bay 170 in Figure 1F. As shown, word lines WL1, WL3, and WL5 are shared between memory arrays 174 and 176 and controlled by the row decoder 172 in Figure 1F. Word lines WL0, WL2, WL4, and WL6 are driven from the left side of memory array 174 and controlled by the row decoder 178 in Figure 1F. Word lines WL14, WL16, WL18, and WL20 are driven from the right side of memory array 176 and controlled by the row decoder 188 in Figure 1F.

[0045] Bit lines BL0, BL2, BL4, and BL6 are driven from the bottom of the memory array 174 and controlled by the column decoder 182 in Figure 1F. Bit lines BL1, BL3, and BL5 are driven from the top of the memory array 174 and controlled by the column decoder 180 in Figure 1F. Bit lines BL7, BL9, BL11, and BL13 are driven from the bottom of the memory array 176 and controlled by the column decoder 192 in Figure 1F. Bit lines BL8, BL10, and BL12 are driven from the top of the memory array 176 and controlled by the column decoder 190 in Figure 1F.

[0046] In one embodiment, memory arrays 174 and 176 may include memory layers oriented in a plane horizontal to the support substrate. In another embodiment, memory arrays 174 and 176 may include memory layers oriented in a plane perpendicular to the support substrate (i.e., the vertical plane is substantially perpendicular to the support substrate). In this case, the bit lines of the memory array may include substantially perpendicular bit lines.

[0047] Figure 1H shows one embodiment of a schematic diagram (including word and bit lines) corresponding to a memory bay configuration in which word and bit lines are shared across memory blocks, and both row and column decoders are separated. Sharing word and / or bit lines helps reduce layout area because a single row and / or column decoder can be used to support two memory arrays.

[0048] As shown in the diagram, word lines WL1, WL3, and WL5 are shared between memory arrays 200 and 202. Bit lines BL1, BL3, and BL5 are shared between memory arrays 200 and 204. Word lines WL8, WL10, and WL12 are shared between memory arrays 204 and 206. Bit lines BL8, BL10, and BL12 are shared between memory arrays 202 and 206.

[0049] The row decoder is divided such that word lines WL0, WL2, WL4, and WL6 are driven from the left side of the memory array 200, and word lines WL1, WL3, and WL5 are driven from the right side of the memory array 200. Similarly, word lines WL7, WL9, WL11, and WL13 are driven from the left side of the memory array 204, and word lines WL8, WL10, and WL12 are driven from the right side of the memory array 204.

[0050] The column decoder is divided such that bit lines BL0, BL2, BL4, and BL6 are driven from the bottom of the memory array 200, and bit lines BL1, BL3, and BL5 are driven from the top of the memory array 200. Similarly, bit lines BL7, BL9, BL11, and BL13 are driven from the bottom of the memory array 202, and bit lines BL8, BL10, and BL12 are driven from the top of the memory array 202. Dividing the row and / or column decoders also helps to relax layout constraints (for example, the column decoder pitch can be relaxed by only a factor of two, since the divided column decoder only needs to drive every other bit line instead of every bit line).

[0051] Figure 2A shows several embodiments of a monolithic three-dimensional memory array 210, which includes a first memory level 212 and a second memory level 214 positioned above the first memory level 212. The memory array 210 is an example of an implementation of the memory array 160 in Figure 1E. Word lines 216, 218 are arranged in a first direction, and bit lines 220 are arranged in a second direction perpendicular to the first direction. As shown, the upper conductor of the first memory level 212 can be used as the lower conductor of the second memory level 214. In a memory array with additional layers of memory cells, there are corresponding additional layers of bit lines and word lines.

[0052] The memory array 210 includes memory cells 222. In embodiments, the memory cells 222 may include rewritable memory cells, one-time programmable memory cells, and multi-time programmable memory cells. In one embodiment, each of the memory cells 222 is oriented vertically. The memory cells 222 may include non-volatile memory cells or volatile memory cells. With respect to the first memory level 212, the first portion of the memory cell 222 is located between the word line 216 and the bit line 220 and connected to them. With respect to the second memory level 214, the second portion of the memory cell 222 is located between the word line 218 and the bit line 220 and connected to them.

[0053] In one embodiment, each memory cell 222 includes a selector element coupled in series with a resistive switching memory element, and each memory cell 222 represents one bit of data. In one embodiment, the resistive switching memory element may be a magnetic memory element, a ReRAM memory element, a phase-change memory element, or another type of resistive switching memory element.

[0054] In one embodiment, each memory cell 222 includes a selector element coupled in series with a magnetic memory element, and each memory cell 222 represents one bit of data. Figure 2B is a simplified schematic diagram of a memory cell 222a, which is one exemplary implementation of the memory cell 222 of Figure 2A.

[0055] In one embodiment, the memory cell 222a is a selector element S x A magnetic memory element M is coupled in series with it. x This includes and both are coupled between the first terminal T1 and the second terminal T2. In one embodiment, the memory cell 222a is oriented vertically. In the embodiment of Figure 2B, the magnetic memory element M x The selector element S x It is disposed on top of. In other embodiments, the selector element S x is a magnetic memory element M x It may also be placed on top of.

[0056] In one embodiment, magnetic memory element Mx is a magnetic tunnel junction, and the selector element S x is a threshold selector device. In one embodiment, the selector element S x is a conductive bridge threshold selector device. In other embodiments, the selector element S x is an ovonic threshold switch (e.g., binary AsTeSi, CTe, BTe, AlTe, etc., or ternary types such as SiTe, AsTeGe, or AsTeGeSiN), a phase change material type of metal insulator transition (MIT) (e.g., VO2, NbO2, etc.), or other similar threshold selector devices.

[0057] In one embodiment, the magnetic memory element M x includes an upper ferromagnetic layer 230, a lower ferromagnetic layer 232, and a tunnel barrier (TB) 234 that is an insulating layer between the two ferromagnetic layers. In this example, the lower ferromagnetic layer 232 is a free layer (FL) having a magnetization direction that can be switched. The upper ferromagnetic layer 230 is a pinned (or fixed) layer (PL) having a magnetization direction that does not easily change.

[0058] In other embodiments, the magnetic memory element M x may include fewer layers, additional layers, or different layers than the layers shown in FIG. 2B. In other embodiments, the lower ferromagnetic layer 232 is a pinned layer (PL), and the upper ferromagnetic layer 230 is a free layer (FL).

[0059] When the magnetization direction of the free layer 232 is parallel to the magnetization direction of the pinned layer 230, the memory element M x has a relatively low resistance (referred to as the "P state" in this specification), and when the magnetization direction of the free layer 232 is antiparallel to the magnetization direction of the pinned layer 230, the memory element M x has a relatively high resistance (referred to as the "AP state" in this specification).

[0060] In one embodiment, the data state ("0" or "1") of the magnetic memory element M x of the magnetic memory element M xThe reading is obtained by measuring the resistance. By design, both parallel and antiparallel configurations remain stable (with sufficiently low reading currents) during quiet and / or reading operations.

[0061] In one embodiment, selector element S x This is an obonic threshold switch that includes a first region 236 and optionally a second region 238 disposed above the first region 236. In one embodiment, the first region 236 is a SiTe alloy and the optionally second region 238 is carbon nitride. Other materials can be used for the first region 236 and the optionally second region 238. In another embodiment, the selector element S x This is a conductive bridge threshold selector element. In one embodiment, the first region 236 is a solid electrolyte region, and the second region 238 is an ion source region.

[0062] Figure 2C shows the threshold selector device S x This figure shows the exemplary current-voltage (IV) characteristics of each threshold selector device S. x It is initially in a high-resistance (off) state. Threshold selector device S x To operate it as a threshold switch, threshold selector device S x However, an initial configuration operation may be required to ensure operation within the current range where switching can occur.

[0063] For example, the formation operation is such that each formation voltage V FORM One or more voltage pulses having a magnitude greater than or equal to the above threshold selector device S x This may include applying to the threshold selector device S. Following the forming operation, the threshold selector device S x It can be switched on and off and can be used as either a unipolar or bipolar threshold selector device. Therefore, threshold selector device S x This can be referred to as a bipolar threshold selector device.

[0064] In the exemplary IV characteristics shown in Figure 2C, the threshold selector device S responds to a positive applied voltage.x The voltage applied to the device is the first threshold voltage V TP The threshold selector device S remains in a high resistance state (HRS) (e.g., off) until it satisfies or exceeds (i.e., is more positive), at which point the threshold selector device S x It switches to a low resistance state (LRS) (e.g., ON). Threshold selector device S x The voltage across the device is the first holding voltage V HP It remains on until the threshold value drops below a certain level, at which point the threshold selector device 224 is turned off.

[0065] For a negative applied voltage, the threshold selector device S x The voltage across the device is the second threshold voltage V TN The threshold selector device 304 remains in HRS (e.g., off) until the condition is met or exceeded (i.e., more negative), at which point the threshold selector device 304 switches to LRS (e.g., on). x The voltage across the device is the second holding voltage V HN It remains on until it increases to or exceeds (i.e., not less than that), at which point the threshold selector device S x It will turn off.

[0066] Referring again to Figure 2B, in one embodiment, the magnetic memory element M x This uses spin-transfer torque (STT) switching. Magnetic memory element M x A write current is applied from the first terminal T1 to the second terminal T2 in order to "set" the bit value (i.e., select the direction of magnetization of the free layer). Since the pin layer 230 is a ferromagnetic metal, electrons in the write current are spin-polarized as they pass through the pin layer 230.

[0067] Substantially, the majority of conduction electrons in a ferromagnet have a spin orientation parallel to the direction of magnetization, resulting in a net spin-polarized current. (Electron spin refers to angular momentum, which is directly proportional to the electron's magnetic moment, but antiparallel. However, for the sake of simplicity, we will not proceed using this directional distinction.)

[0068] When spin-polarized electrons tunnel through TB234, the conservation of angular momentum can result in a torque on both the free layer 232 and the pinned layer 230, but this torque is (designed) insufficient to influence the magnetization direction of the pinned layer 230. In contrast, if the initial magnetization direction of the free layer 232 is antiparallel to the pinned layer 230, this torque is (designed) sufficient to switch the magnetization direction of the free layer 232 to be parallel to the magnetization direction of the pinned layer 230. The parallel magnetization then remains stable before and after such a write current is turned off.

[0069] In contrast, if the magnetizations of the free layer 232 and the pinned layer 230 are initially parallel, the direction of the magnetization of the free layer 232 can be STT-switched to be antiparallel to the direction of the magnetization of the pinned layer 230 by applying a write current in the opposite direction to that described above. Therefore, assuming the same STT physical characteristics, the magnetization direction of the free layer 232 can be definitively set to one of two stable orientations by appropriately selecting the direction (polarity) of the write current.

[0070] In the example above, spin-transfer torque (STT) switching is used to create a magnetic memory element M x The bit value is "set". In other embodiments, magnetic field-induced switching, spin-orbit torque (SOT) switching, VCMA (magnetoelectric) switching, or other switching techniques may be used.

[0071] Figures 3A and 3B are simplified schematic diagrams of an exemplary crosspoint memory array 300, which includes a first memory level 300a and a second memory level 300b positioned above the first memory level 300a. The crosspoint memory array 300 is an example of an implementation of the memory array 160 in Figure 1E. The crosspoint memory array 300 may include three or more memory levels.

[0072] The crosspoint memory array 300 includes word lines WL1a, WL2a, WL3a, WL1b, WL2b, and WL3b, and bit lines BL1, BL2, and BL3. The first memory level 300a is a memory cell 302 coupled to the word lines WL1a, WL2a, WL3a and the bit lines BL1, BL2, and BL3. 11a ,302 12a ,...,302 33a The second memory level 300b includes memory cells 302 coupled to word lines WL1b, WL2b, WL3b and bit lines BL1, BL2, and BL3. 11b ,302 12b ,...,302 33b Includes. In one embodiment, memory cell 302 11a ,302 12a ,...,302 33a Each of them is oriented vertically. In one embodiment, memory cell 302 11b ,302 12b ,...,302 33b Each of them is oriented vertically.

[0073] The first memory level 300a is an example of an implementation configuration of the first memory level 212 of the monolithic three-dimensional memory array 210 shown in Figure 2A, and the second memory level 300b is an example of an implementation configuration of the second memory level 214 of the monolithic three-dimensional memory array 210 shown in Figure 2A. In one embodiment, memory cell 302 11a ,302 12a ,...,302 33a ,302 11b ,302 12b ,...,302 33bEach of them is an implementation form of the memory cell 222a in FIG. 2B.

[0074] A person skilled in the art will understand that the cross-point memory array 300 may include more or fewer word lines than six, more or fewer bit lines than three, and more or fewer memory cells 302 than eighteen 11a 、302 12a 、...、302 33a 、302 11b 、302 12b 、...、302 33b In some embodiments, the cross-point memory array 300 may include 1000×1000 memory cells, but other array sizes may also be used.

[0075] Each memory cell 302 11a 、302 12a 、...、302 33a 、302 11b 、302 12b 、...、302 33b is coupled to one of the word lines and one of the bit lines, and includes a corresponding magnetic memory element M 11a 、M 12a 、...、M 33a 、M 11b 、M 12b 、...、M 33b respectively, and may be disposed above or below a corresponding selector element S 11a 、S 12a 、...、S 33a 、S 11b 、S 12b 、...、S 33b In one embodiment, each of the magnetic memory elements M 11a 、M 12a 、...、M 33a 、M 11b 、M 12b 、...、M 33b is an implementation form of the magnetic memory element M in FIG. 2B, and the selector elements S x の実装形態であり、セレクタ素子S 11a 、S 12a 、...、S 33a 、S 11b 、S12b through S 33b Each of which is an implementation form of the selector element S in FIG. 2B x .

[0076] Each memory cell 302 11a , 302 12a ,... 302 33a has a first terminal coupled to one of bit lines BL1, BL2, BL3 and a second terminal coupled to one of word lines WL1a, WL2a, WL3a. Each memory cell 302 11b , 302 12b ,... 302 33b has a first terminal coupled to one of bit lines BL1, BL2, BL3 and a second terminal coupled to one of word lines WL1b, WL2b, WL3b. For example, memory cell 302 13a includes a magnetic memory element M coupled in series with selector element S 13a and includes a first terminal coupled to bit line BL3 and a second terminal coupled to word line WL1a 13a .

[0077] Similarly, memory cell 302 22b includes a magnetic memory element M coupled in series with selector element S 22b and includes a first terminal coupled to bit line BL2 and a second terminal coupled to word line WL2b. Similarly, memory cell 302 22b includes a magnetic memory element M coupled in series with selector element S 33a and includes a first terminal coupled to bit line BL3 and a second terminal coupled to word line WL3a 33a . 33a .

[0078] Magnetic memory elements M 11a , M 12a ,... M 33a can be respectively disposed above or below the corresponding selector elements S 11a , S 12a ,... S 33a , and magnetic memory elements M 11b , M 12b,..., M 33b This corresponds to the selector element S 11b S 12b ,..., S 33b They can be positioned above or below, respectively.

[0079] In one embodiment, memory cell 302 of the first memory level 300a 11a ,302 12a ,...,302 33a The orientation is that of memory cell 302 of the second memory level 300b. 11b ,302 12b ,...,302 33b This is the opposite orientation.

[0080] In another embodiment, memory cell 302 of the first memory level 300a 11a ,302 12a ,...,302 33a The orientation is that of memory cell 302 of the second memory level 300b. 11b ,302 12b ,...,302 33b This is the opposite orientation.

[0081] Referring again to Figure 1A, in one embodiment, the memory core 110 may include one or more two-dimensional arrays of memory cells and / or one or more three-dimensional arrays of memory cells. In one embodiment, the memory core 110 may include rewritable memory cells, one-time programmable memory cells, and / or multi-time programmable memory cells, or any combination thereof.

[0082] Figures 4A to 4C are simplified diagrams of a memory block 400, which is an example of the memory block 140 in Figure 1E. The memory block 400 includes a memory array 402 coupled to a word line driver circuit 404 and a bit line driver circuit 406. The memory array 402 also includes word lines WL0, WL1, ..., WL9 coupled to the word line driver circuit 404, and bit lines BL0, BL1, ..., BL9 coupled to the bit line driver circuit 406. Those skilled in the art will understand that the memory array 402 may have more or fewer than nine word lines and more or fewer than nine bit lines.

[0083] In one embodiment, memory cell 408 xy These are located at the intersections of the word lines WL0, WL1, ..., WL9 and the bit lines BL0, BL1, ..., BL9 (x = word line number, y = bit line number). In one embodiment, each memory cell 408 xy This includes a selector element coupled in series with a resistive switching memory element, such as the exemplary memory cell 222 in Figure 2A. In one embodiment, each memory cell 408 xy This includes a selector element coupled in series with a magnetic memory element, such as the example memory cell 222a in Figure 2B.

[0084] Figure 4A is a top-level diagram of memory block 400, and Figure 4B is a top-level diagram of memory array 402, showing each memory cell 408 xy The numbers are shown. In Figure 4A, each memory cell 408 xy The numbers shown above represent each memory cell 408 xy This represents the total path length of the memory cell 408. As used herein, "total path length" refers to the total path length of the memory cell 408. xy This is the sum of the word line path length and the bit line path length up to the memory cell 408. As used herein, "word line path length" refers to the length from the word line driver circuit 404 to the memory cell 408. xy Corresponding to the length of the corresponding word line up to memory cell 408, the "bit line path length" is from the bit line driver circuit 406 to the memory cell 408. xy Corresponds to the length of the corresponding bit line up to that point.

[0085] For example, memory cell 408 located at the intersection of word line WL0 and bit line BL0 00 It is located at a word line path length of 1 from the word line driver circuit 404 and a bit line path length of 1 from the bit line driver circuit 406, and therefore the memory cell has a total path length of 2. Similarly, memory cell 408 is located at the intersection of word line WL1 and bit line BL5. 15 The word line driver circuit 404 has a word line path length of 6, and the bit line driver circuit 406 has a bit line path length of 2, so the memory cell has a total path length of 8.

[0086] Therefore, the illustrated total path length is equal to the length of each memory cell 408 for both the word line driver circuit 404 and the bit line driver circuit 406. xy Represents the relative proximity. Memory cells 408 coupled to bit lines BL0, BL1, ..., BL3. xy This is a relatively "close" word line driver circuit 404, and memory cells 408 coupled to word lines WL0, WL1, ..., WL3. xy This is the relatively "close" bit line driver circuit 406. In contrast, the memory cells 408 are coupled to bit lines BL6, BL7, ..., BL9. xy The memory cells 408 are located relatively "far" from the word line driver circuit 404 and are coupled to word lines WL6, WL7, ..., WL9. xy It is relatively "far" from the bit line driver circuit 406.

[0087] In one embodiment, memory cells 408 are coupled to bit lines BL0, BL1, ..., BL3 and word lines WL0, WL1, ..., WL3. xy Because the memory cell is located relatively "close" to both the word line driver circuit 404 and the bit line driver circuit 406, it is a "near-near" memory cell 408. nn This is called a near-near memory cell 408. In the exemplary embodiments shown in Figures 4A to 4C, nn It is shaded in light gray, and memory cell 408 00 ,408 01,408 02 ,408 03 ,408 10 ,408 11 ,408 12 ,408 20 ,408 21 and 408 30 Includes.

[0088] In one embodiment, the memory cell 408xy coupled to the bit lines BL6, BL7, ..., BL9 and the word lines WL6, WL7, ..., WL9 is a "far-far" memory cell 408 because the memory cell is located relatively "far" from the word line driver circuit 404 and the bit line driver circuit 406. ff This is called [name]. In the exemplary embodiments shown in Figures 4A to 4C, the far-far memory cell 408 ff It is shaded in dark gray, and memory cell 408 96 ,408 97 ,408 98 ,408 99 ,408 87 ,408 88 ,408 89 ,408 78 ,408 79 and 408 69 Includes.

[0089] Ideally, the word lines WL0, WL1, ..., WL9 and the bit lines BL0, BL1, ..., BL9 would have zero resistance. However, in reality, each of the word lines WL0, WL1, ..., WL9 and the bit lines BL0, BL1, ..., BL9 has a non-zero resistance that increases with increasing length. Figure 4B shows the word line resistance R. w0 , R w1 ,...R w9 For each of the word lines WL0, WL1, ..., WL9, the bit line resistor R b0 ,..., R b9 This is shown for each of the bit lines BL0, BL1, ..., BL9. Figure 4C shows the word line resistor R w and bit wire resistor R b A simplified model of memory array 402 including the following is shown.

[0090] For example, in the case of word line WL0, the word line resistance R w0 This is from the word line driver circuit 404 to the memory cell 408 00 This represents the resistance along the word line path length up to the word line, and the word line resistance R w1 This is memory cell 408 00 From memory cell 408 01 This represents the resistance along the word line path length up to [the specified point], and the same applies below. For simplicity, the word line resistance R is used. w0 , R w1 ,..., R w9 It is assumed that this is the same for each of the word lines WL0, WL1, ..., WL9, and this is accurate for a first-order approximation. In addition, the word line resistance R w0 ,R w1 ,..., R w9 It is assumed that they have the same value R.

[0091] Similarly, in the case of bit line BL0, the bit line resistor R b0 This is from the bit line driver circuit 406 to the memory cell 408 00 This represents the resistance along the bit line path length up to the bit line, and the bit line resistance R b9 This is memory cell 408 80 From memory cell 408 90 This represents the resistance along the bit line path length up to [the specified point], and the same applies below. For simplicity, the bit line resistance R is used. b0 ,..., R b9 It is assumed that this is the same for each of the bit lines BL0, BL1, ..., BL9, and this is accurate for a first-order approximation. In addition, the bit line resistor R b0 , R b1 ,..., R b9 It is assumed that they have the same value R.

[0092] In one embodiment, memory cell 408 xy Each of these is connected to the word line driver circuit 404 and the memory cell 408 xy The corresponding word line resistance up to memory cell 408 xy The corresponding "total path resistance" (TR) is the sum of the resistances of the corresponding bit lines from the bit line driver circuit 406 to the bit line driver circuit 406. xy ) has.

[0093] Therefore, memory cell 408 00 TR 00 =R w0 +R b0 =2 × R, corresponding total path resistance, memory cell 408 01 TR 01 =R w0 +R w1 +R b0 =3 × R, corresponding total path resistance, memory cell 408 99 TR 99 =R w0 +R w1 +...+R w9 +R b0 +R b1 +...+R b9 Each memory cell 408 in Figure 4A has a corresponding total path resistance of =20 × R, and so on. xy The numbers shown above also represent the corresponding total path resistance TR of each memory cell. xy It represents a multiplier.

[0094] Therefore, near-near memory cell 408 nn The distance from the word line driver circuit 404 and the bit line driver circuit 406b is relatively short, and the corresponding total path resistance TR xy It is relatively small, and the far-far memory cell 408 ff The distance from the word line driver circuit 404 and the bit line driver circuit 406b is relatively long, and the corresponding total path resistance TR xy It is relatively large.

[0095] In one embodiment, the memory array 402 is divided into multiple zones. That is, the first zone 410 (also referred to herein as the “near-near zone”) has the lowest corresponding total path resistance TR xy Near-near memory cell 408 nn Including the second zone 412 (also referred to herein as the “far-far zone”), the highest corresponding total path resistance TR xy Far-far memory cell 408 ffThe third zone 414 (also referred to herein as the “intermediate zone”) includes all memory cells 408 that are neither near-near-memory cells nor far-far-memory cells. xy This includes. A person skilled in the art will understand that the memory array 402 may be divided into more or fewer than 3 zones.

[0096] In one embodiment, near-near memory cell 408 nn This is the first (e.g., lower) threshold resistor R L The corresponding total path resistance TR is smaller than xy It has a far-far memory cell 408 ff This is the second (e.g., upper) threshold resistor R U The corresponding total path resistance TR is greater than the corresponding total path resistance TR xy It has, for example, in the embodiments shown in Figures 4A to 4C, the lower threshold resistance R L = 6 × R, and the upper threshold resistance R U = 16 × R. A person skilled in the art will know the upper threshold resistor R U and lower threshold resistor R L You will understand that other values ​​may be selected for this.

[0097] In the exemplary embodiments shown in Figures 4A to 4C, the near-near memory cell 408 nn and far-far memory cell 408 ff Total path resistance TR xy The difference is the lower total path resistance difference Δ TPRL =(17×R-5×R)=12×R ~Total resistance difference in the upper path Δ TPRU The range is (20 × R - 2 × R) = 18 × R, and Δ TPRA = 15 × R has an average total path resistance difference. For simplicity, the remaining explanation is for near-near memory cells 408 nn However, the average total path resistance difference Δ TPRA Only far-far memory cell 408 ff The corresponding total path resistance TR is lower than the total path resistance. xy Assume that it has

[0098] In some embodiments, the mean total path resistance difference Δ AThis can be approximately 25 kΩ, and memory cell 408 includes a selector element (such as an obonic threshold switch) coupled in series with a magnetic memory element, such as the example memory cell 222a in Figure 2B. xy This could have several negative consequences.

[0099] Specifically, when the ovonic threshold switch is turned on, the ovonic threshold switch S X The voltage across both ends drops to a relatively low value, and the remaining voltage is between the word line and the memory element M of the memory cell. x It drops between both ends. In this specification, this residual voltage is referred to as the “snapback voltage”. Snapback occurs when the memory element M x The state of the data may be unintentionally changed during reading, which could cause a read disturb.

[0100] Each memory cell contains 408 xy Regarding this, the resistance of the memory cell and the corresponding total path resistance TR of the memory cell xy It acts like a voltage divider. Therefore, the total path resistance TR xy The lower the value, the corresponding memory cell 408 xy The snapback voltage drop over the specified range becomes larger.

[0101] Therefore, near-near memory cell 408 nn is a far-far memory cell 408 ff The average total path resistance difference Δ TPRA Only the total path resistance TR is lower. xy It has near-near memory cells 408 nn is a far-far memory cell 408 ff It tends to experience higher read disturbance than the near-near memory cell 408. nn A higher snapback voltage over the far-far memory cell 408 ff Compared to that, it negatively impacts the durability of such memory cells.

[0102] Near-near memory cell 408 nn and far-far cell 408 ffThe average total path resistance difference Δ between the two points. TPRA A further problem arising from this is that if the word line driver circuit 404 and the bit line driver circuit 406 use constant voltage for memory operation, a higher voltage level will be required. Specifically, the far-far memory cell 408 ff This is a higher, corresponding total path resistance TR xy Therefore, the voltage drop along the line is, far-far memory cell 408 ff To achieve the required voltage level, higher voltages are needed in the word line driver circuit 404 and the bit line driver circuit 406. However, as a result, the near-near memory cell 408 nn It receives a higher voltage, and the near-near memory cell 408 nn This further degrades its durability.

[0103] As an alternative to the word line driver circuit 404 and bit line driver circuit 406 which use constant voltage, the memory cell 408 uses the CMOS voltage zoning technique. xy Based on the zone in which it is located, memory cell 408 xy Different voltages can be applied to it. However, such CMOS voltage zoning techniques require additional complex design and adjustments.

[0104] Also, far-far memory cell 408 ff Leakage current becomes a problem. Near-near memory cell 408 nn If the resistance increases, the far-far memory cell 408 ff The leakage current is near-near memory cell 408 nn This can be improved by reducing the leakage current passing through it.

[0105] Δ, the average total path resistance difference between near-near memory cells and far-far memory cells. TPRA Techniques for reducing are described. In some embodiments, near-near memory cell 408 nn An additional resistor is added to the near-near memory cell 408 nn Corresponding total path resistance TR xyThis effectively increases the near-near memory cell 408. In some embodiments, the added resistance is used to increase the near-near memory cell 408. nn and far-far cell 408 ff The average total path resistance difference Δ between the two points. TPRA It has a value that is practically equal to . Although we do not wish to be bound by any particular theory, the added resistance is near-near memory cell 408 nn and far-far cell 408 ff It is thought that the difference in total path resistance between them can be reduced.

[0106] Figure 5A is a simplified perspective view of memory block 500, which is an example of memory block 140 in Figure 1E. Memory block 500 includes a memory array 502 coupled to a word line driver circuit 504 and a bit line driver circuit 506. The memory array 502 also includes word lines WL0, WL1, ..., WL9 coupled to the word line driver circuit 504, and bit lines BL0, BL1, ..., BL9 coupled to the bit line driver circuit 506. Those skilled in the art will understand that the memory array 502 may have more or fewer than nine word lines and more or fewer than nine bit lines.

[0107] In one embodiment, memory cell 508 xy These are located at the intersections of the word lines WL0, WL1, ..., WL9 and the bit lines BL0, BL1, ..., BL9 (x = word line number, y = bit line number). In one embodiment, each memory cell 508 xy This includes a selector element coupled in series with a resistive switching memory element, such as the exemplary memory cell 222 in Figure 2A. In one embodiment, each memory cell 508 xy This includes a selector element coupled in series with a magnetic memory element, such as the example memory cell 222a in Figure 2B.

[0108] In one embodiment, the memory array 502 has near-near memory cells 508, similar to the near-near zone 410, far-far zone 412, and intermediate zone 414 of the memory array 402 in Figure 4A. nnThe first zone (e.g., near-near zone) and the far-far memory cell 508 ff This includes a second zone (e.g., far-far zone) and all other memory cells 508 xy A third zone (e.g., an intermediate zone) that includes and .

[0109] Therefore, similar to the memory array 402 in Figure 4A, the near-near zone of the memory array 502 is the memory cell 508 00 , 508 01 , 508 02 , 508 03 , 508 10 , 508 11 , 508 12 , 508 20 , 508 21 , and 508 30 Including the memory array 502, the far-far zone is 508 96 , 508 97 , 508 98 , 508 99 , 508 87 , 508 88 , 508 89 , 508 78 , 508 79 , and 508 69 This includes, some of which are shown in Figure 5A. Near-near memory cell 508 nn These are shown in shaded light gray, and near-near memory cells 508 nn Not all other 508 memory cells xy There is no shading applied to it.

[0110] In one embodiment, an additional resistor R Δ Each near-near memory cell 508 nn It is incorporated into and / or coupled to. In the exemplary embodiment of Figure 5A, an additional resistor R is added. Δ Each near-near memory cell 508 nn And, near-near memory cell 508 nn It is shown coupled between the corresponding word lines WL0, WL1, WL2, or WL3, which are coupled to it. In some alternative embodiments, an additional resistor R is added. Δ Each near-near memory cell 508nn and the corresponding bit lines BL0, BL1, BL2, or BL3 coupled to the near-near memory cell 508 nn are shown coupled therebetween.

[0111] In yet another alternative embodiment, an additional resistor R Δ is split into two parts, and the first part of the additional resistor R Δ is coupled between each near-near memory cell 508 nn and the corresponding word line WL0, WL1, WL2, or WL3, and the second part is coupled between each near-near memory cell 508 nn and the corresponding bit lines BL0, BL1, BL2, or BL3 coupled to the near-near memory cell 508 nn are shown coupled therebetween.

[0112] In one embodiment, each additional resistor R Δ has a value substantially equal to the average total path resistance difference Δ nn between the near-near memory cell 508 ff and the far-far memory cell 508. In some embodiments, the total path resistance difference Δ TPR is an average value, a median value, a maximum value, or a minimum value, or any of the total path resistance differences (e.g., determined empirically, by simulation, or by a combination thereof) between the near-near memory cell 508 TPR and the far-far memory cell 508 nn and the far-far memory cell 508 ff may be any of those.

[0113] In other embodiments, the total path resistance difference Δ TPR may be any other measurement or estimate of the total path resistance difference between the near-near memory cell 508 nn and the far-far memory cell 508 ff and the far-far memory cell 508. While not wishing to be bound by a particular theory, it is believed that the additional resistor R Δ may reduce the difference in the total path resistance TR nn between the near-near memory cell 508 ff and the far-far memory cell 508 xy shown.

[0114] In one embodiment, an additional resistor R Δ This includes all other memory cells 508 in the memory array 502. xy Compared to the structure of the near-near memory cell 508 nn By changing the structure of each near-near memory cell 508 nn It is incorporated into. In one embodiment, each memory cell 508 in the memory array 502 xy This includes selector elements such as the example memory cell 222a in Figure 2B. x A magnetic memory element M is coupled in series with it. x Includes.

[0115] In addition, although not shown in Figure 2B, each memory cell 222a also contains a magnetic memory element M x It includes a hard mask layer positioned above the magnetic memory element M. In some embodiments, the hard mask layer is used during manufacturing to form the magnetic memory element M. x and selector element S x Each of these forms a memory cell pillar.

[0116] For example, Figure 5B shows memory cell 508 of memory array 502. 03 and 508 04 This is a simplified perspective view of one embodiment. In this example, memory cell 508 03 508 near-near memory cells nn And memory cell 508 04 508 near-near memory cells nn No. Memory cell 508 03 and 508 04 Each of these is a selector element S x Magnetic memory element M positioned above x Includes each magnetic memory element M. x A hard mask is positioned above it.

[0117] Specifically, memory cell 508 04 (and all other memory cells 508 that are not in the near-near zone of memory array 502) xy ) is a magnetic memory element M xIt includes a first hard mask 510 disposed above it, and a memory cell 508 03 (and all other near-near memory cells 508 in the near-near zone of memory array 502) nn ) is a magnetic memory element M x A second hard mask 510 is positioned above it. X Includes.

[0118] In one embodiment, a first hard mask 510 and a second hard mask 510 X These include different hard mask materials, although they have substantially the same dimensions. In one embodiment, a first hard mask 510 and a second hard mask 510 X They have substantially the same thickness (e.g., about 10 nm to 100 nm, or the thickness of other similar hard masks).

[0119] In one embodiment, the first hard mask 510 is manufactured from a first hard mask material layer, and the second hard mask 510 X It is manufactured from a second hard mask material layer. In one embodiment, the first hard mask material layer has a first resistivity, and the second hard mask material layer has a second resistivity that is higher than the first resistivity. In one embodiment, the first hard mask 510 has a first resistance, and the second hard mask 510 X It has a second resistance that is higher than the first resistance.

[0120] In one embodiment, a second hard mask 510 X The difference between the second resistor and the first resistor of the first hard mask 510 is the near-near memory cell 508 nn and far-far cell 508 ff Total path resistance difference Δ between the two TPR An added resistor R has a value that is substantially equal to the original resistor. Δ That is the case.

[0121] In one embodiment, the first hard mask 510 is manufactured from a first hard mask material formed using first processing parameters, and the second hard mask 510 XThe hard mask is manufactured from a second hard mask material formed using a second processing parameter that differs from the first processing parameter. In some embodiments, the processing parameter includes one or more of the processing material, time, temperature, flow rate, and other similar processing parameters.

[0122] In some embodiments, a first hard mask 510 and a second hard mask 510 X Each of these is manufactured from one or more metallic materials, such as tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), chromium (Cr), ruthenium (Ru), and other similar metallic materials. In some embodiments, a first hard mask 510 and a second hard mask 510 X These are manufactured from the same metal material or from different metal materials. In some embodiments, the resistivity of the metal hard mask material can be controlled relatively well.

[0123] For example, Table 1 below shows exemplary thicknesses and resistivity of TaN films deposited with different sputtering times and nitrogen (N2) flow rates.

[0124] [Table 1]

[0125] For example, by changing the N2 flow rate from 12 sccm to 38 sccm for a 10-minute sputtering time, the resistivity of the resulting TaN film can be changed from 524.0 μΩ-cm to 27,136.6 μΩ-cm. Those skilled in the art will understand that the resistivity of other metal hard mask materials can be similarly controlled by controlling the processing parameters.

[0126] Figure 5C shows the memory cell 508 of the memory array 502. 03 and 508 04 This is a simplified cross-sectional view of an exemplary manufacturing process. In this example, the near-near memory cell 508 03It is located between the bit line BL3 and the word line WL0, and is connected to memory cell 508 04 It is disposed between the bit line BL4 and the word line WL0. In one embodiment, memory cell 508 03 and 508 04 Each of them is surrounded by a side wall liner 512 and separated from each other by a dielectric material (e.g., silicon dioxide) 514 and other memory cells 508 xy It is separated from.

[0127] In one embodiment, (non-near-near) memory cell 508 04 It includes a first hard mask 510 and a near-near memory cell 508 03 This is a second hard mask 510, which is different from the first hard mask 510. X This includes. In one embodiment, the first hard mask 510 has a first resistor, and the second hard mask 510 X It has a second resistance. In some embodiments, an additional photolithography step is used to form a first hard mask 510 from a first hard mask material and a second hard mask 510 from a second hard mask material different from the first hard mask material. X It forms.

[0128] In one embodiment, a second hard mask 510 X The difference between the second resistor and the first resistor of the first hard mask 510 is the near-near memory cell 508 nn and far-far cell 508 ff Total path resistance difference Δ between the two TPR An added resistor R has a value that is substantially equal to the original resistor. Δ That is the case. I don't want to be bound by any particular theory, but the added resistor R Δ 508 near-near memory cells nn and far-far cell 508 ff Total path resistance TR between xy It is thought that this can reduce the difference.

[0129] As described above, and as shown in Figures 5B to 5C, in one embodiment, an additional resistor RΔ This refers to all other memory cells 508 that are not located within the near-near zone of the memory array 502. xy Compared to the structure of the near-near memory cells 508 in the near-near zone nn By changing the structure of each near-near memory cell 508 nn It can be incorporated internally.

[0130] In another embodiment, all memory cells 508 in the memory array 502 xy They may have the same structure, but with an added resistor R Δ This refers to the near-near memory cell 508 in the near-near zone of memory 502. nn This can be incorporated by including an additional layer of resistive material in some of the word lines and / or bit lines that are coupled to it.

[0131] For example, Figure 5D shows memory cell 508 of memory array 502. 03 and 508 04 This is a simplified cross-sectional view of an alternative, exemplary manufacturing process. Similar to the embodiment in Figure 5C, the near-near memory cell 508 03 It is located between the bit line BL3 and the word line WL0, and is connected to memory cell 508 04 It is located between the bit line BL4 and the word line WL0. However, in the embodiment shown in Figure 5D, the near-near memory cell 508 03 and (non-near-near) memory cell 508 04 Each of these includes a first hard mask 510 having substantially the same resistance.

[0132] In the embodiment shown in Figure 5D, the word line WL0 is the first word line portion WL 0X And, near-near memory cell 508 nn and the first word line section WL 0X The second word line portion WL is positioned between them. 0R and, including. In one embodiment, the first word line portion WL 0X It has a first resistivity and a second word line portion WL 0R It has a second resistivity that is higher than the first resistivity. In one embodiment, the second word line portion WL 0Rincludes a resistive material (e.g., TaN, TiN, or other similar materials).

[0133] In some embodiments, a second word line portion (such as second word line portion WL nn (such as near-near memory cell 508 03 ) disposed above each near-near memory cell 508 0R has a region that constitutes an additional resistance R having a value substantially equal to the total path resistance difference Δ nn between the near-near memory cell 508 ff and the far-far memory cell 508 TPR . Without wishing to be bound by any particular theory, the additional resistance R Δ is thought to be able to reduce the difference in the total path resistance TR Δ between the near-near memory cell 508 nn and the far-far memory cell 508 ff . xy

[0134] FIG. 5E is a flow diagram of a simplified process 516 for forming a memory array, such as a portion of the memory array 502 shown in FIG. 5D.

[0135] In step 518, memory cell pillars are formed, each including a magnetic memory element M x disposed above a selector element S x . In one embodiment, each memory cell pillar also includes a hard mask 510 disposed above the magnetic memory element Mx.

[0136] In step 520, a liner and a dielectric filler are deposited and chemical mechanical polishing (CMP) is performed to expose the upper portion of the hard mask of the pillar.

[0137] In step 522, a second word line portion WL 0R ​A resistive film is deposited, which will form a resistive layer. In some embodiments, the resistive film may be TiN, TaN, or other similar material. In some embodiments, the resistive film may be about 2 nm to about 15 nm thick, but other thicknesses may be used.

[0138] In step 524, the resistive film deposited across the near-near memory cell zone is patterned and etched.

[0139] In step 526, a conductive material layer (e.g., W) that will form the word line is deposited. In some embodiments, the deposited conductive film may be about 40 nm to about 60 nm, but other thicknesses may be used.

[0140] In step 528, CMP is performed on the blanket conductive material layer to eliminate any steps across the resistive film.

[0141] In step 530, the conductive material layer and the added resistive film are patterned and etched to form word lines.

[0142] In the embodiment shown in Figure 5D, the added resistor R Δ 508 near-near memory cells nn This is incorporated by including an additional resistive material layer in a portion of the word wire coupled to it. In other embodiments, the added resistance R Δ 508 near-near memory cells nn This is incorporated by including an additional layer of resistive material in a portion of the bit wires that are coupled together.

[0143] For example, Figure 5F shows memory cell 508 of memory array 502. 03 and 508 04 This is a simplified cross-sectional view of another alternative, exemplary manufacturing process. Similar to the embodiment in Figure 5D, the near-near memory cell 508 03 It is located between the bit line BL3 and the word line WL0, and is connected to memory cell 508 04 It is located between the bit line BL4 and the word line WL0, and is a near-near memory cell 50803 and (non-near-near) memory cell 508 04 Each of these includes a first hard mask 510 having substantially the same resistance.

[0144] However, in the embodiment shown in Figure 5F, bit line BL3 is the first bit line portion BL 3X And, near-near memory cell 508 03 and the first bit line portion BL 03X The second bit line portion BL is positioned between them. 3R and, including. In one embodiment, the first bit line portion BL 3X It has a first resistivity and a second bit line portion WL 3R It has a second resistivity that is higher than the first resistivity. In one embodiment, the second bit line portion BL 3R This includes a resistive material (e.g., TaN, TiN, or other similar material).

[0145] In some embodiments, each near-near memory cell 508 nn (Near-near memory cell 508) 03 A second bit line portion (second bit line portion BL) is located below (etc.) 3R The region (etc.) is the near-near memory cell 508 nn and far-far cell 508 ff Total path resistance difference Δ between the two TPR An added resistor R has a value that is substantially equal to the original resistor. Δ This constitutes the structure. While we do not wish to be bound by any particular theory, the added resistor R Δ 508 near-near memory cells nn and far-far cell 508 ff Total path resistance TR between xy It is thought that this can reduce the difference.

[0146] In the embodiment shown in Figure 5D, the added resistor R Δ 508 near-near memory cells nn Incorporated by including an additional resistive material layer in a portion of the coupled word wire, in the embodiment shown in Figure 5F, the added resistance R Δ 508 near-near memory cellsnn This is incorporated by including an additional resistive material layer in a portion of the coupled bit wire. In another alternative embodiment, these techniques are combined to add resistance R Δ 508 near-near memory cells nn It can be incorporated into.

[0147] Specifically, Figure 5G shows the memory cell 508 of the memory array 502. 03 and 508 04 This is yet another alternative, exemplary, simplified cross-sectional view during manufacturing. As in the embodiments of Figures 5D and 5F, the near-near memory cell 508 03 It is located between the bit line BL3 and the word line WL0, and is connected to memory cell 508 04 It is located between the bit line BL4 and the word line WL0, and is a near-near memory cell 508 03 and (non-near-near) memory cell 508 04 Each of these includes a first hard mask 510 having substantially the same resistance.

[0148] However, in the embodiment shown in Figure 5G, the word line WL0 is the first word line portion WL 0X And, near-near memory cell 508 nn and the first word line section WL 0X The second word line portion WL is positioned between them. 0R This includes the bit line BL3, the first bit line portion BL 3X And, near-near memory cell 508 03 and the first bit line portion BL 03X The second bit line portion BL is positioned between them. 3R This includes,

[0149] In one embodiment, the first word line portion WL 0X It has a first resistivity and a second word line portion WL 0R It has a second resistivity that is higher than the first resistivity. In one embodiment, the first bit line portion BL 3X It has a third resistivity and a second bit line portion BL 3RIt has a fourth resistivity that is higher than the third resistivity. In one embodiment, the second word line portion WL 0R and the second bit line portion BL 3R This includes a resistive material (e.g., TaN, TiN, or other similar material).

[0150] In some embodiments, each near-near memory cell 508 nn (Near-near memory cell 508) 03 The second word line portion (second word line portion WL) is located above the (etc.) 0R (etc.) and each near-near memory cell 508 nn (Near-near memory cell 508) 03 A second bit line portion (second bit line portion BL) is located below (etc.) 3R The region (etc.) is the near-near memory cell 508 nn and far-far cell 508 ff Total path resistance difference Δ between the two TPR An added resistor R has a value that is substantially equal to the original resistor. Δ It collectively constitutes the following. While we do not wish to be bound by any particular theory, the added resistor R Δ 508 near-near memory cells nn and far-far cell 508 ff Total path resistance TR between xy It is thought that this can reduce the difference.

[0151] Figure 6 shows a flowchart of one embodiment of a method 600 for forming a memory array, such as the memory array 502 in Figure 5A.

[0152] In step 602, a first plurality of memory cell pillars and a second plurality of memory cell pillars are formed. The first plurality of memory cell pillars include near-near memory cells, and the second plurality of memory cell pillars include far-far memory cells.

[0153] In step 604, a resistive film is formed above the first plurality of memory cell pillars and the second plurality of memory cell pillars.

[0154] In step 606, a resistive film is patterned and etched across the first set of memory cell pillars.

[0155] In step 608, a conductive material layer is formed across the resistive film and the second plurality of memory cell pillars.

[0156] In step 610, the conductive material layer and the resistive film are patterned and etched to form word lines coupled to the first plurality of memory cell pillars and the second plurality of memory cell pillars.

[0157] While we do not wish to be bound by any particular theory, it is thought that resistive films can compensate for the resistance difference between far-far memory cells and near-near memory cells.

[0158] One embodiment of the disclosed technology includes an apparatus comprising a first memory cell and a second memory cell. The first memory cell is coupled between a first word line and a first bit line and coupled in series with a first word line resistor and a first bit line resistor. The first memory cell includes a first hard mask comprising a first hard mask material. The second memory cell is coupled between a second word line and a second bit line and coupled in series with a second word line resistor and a second bit line resistor. The second memory cell includes a second hard mask comprising a second hard mask material. The first hard mask material has a first resistivity, and the second hard mask material has a second resistivity that is lower than the first resistivity. The first hard mask is configured to compensate for the difference between a first sum of the first word line resistor and the first bit line resistor and a second sum of the second word line resistor and the second bit line resistor.

[0159] One embodiment of the disclosed technology includes a device comprising: a first word line comprising a first word line portion comprising a first word line portion comprising a first resistivity and a second word line portion comprising a second resistivity higher than the first resistivity; a first memory cell coupled between the first word line comprising a first word line resistance and a first bit line comprising a first bit line resistance; and a second memory cell coupled between the second word line comprising a second word line resistance and a second bit line comprising a second bit line resistance. The second word line portion of the first word line is disposed between the first memory cell and the first word line portion of the first word line. The second word line portion is configured to compensate for the difference between a first sum of the first word line resistance and the first bit line resistance and a second sum of the second word line resistance and the second bit line resistance.

[0160] One embodiment of the disclosed technology includes a method comprising: forming a first plurality of memory cell pillars and a second plurality of memory cell pillars, wherein the first plurality of memory cell pillars include near-near memory cells and the second plurality of memory cell pillars include far-far memory cells; forming a resistive film above the first plurality of memory cell pillars and the second plurality of memory cell pillars; patterning and etching the resistive film across the first plurality of memory cell pillars; forming a conductive material layer across the resistive film and the second plurality of memory cell pillars; and patterning and etching the conductive material layer and the resistive film to form word lines coupled to the first plurality of memory cell pillars and the second plurality of memory cell pillars. The resistive film is configured to compensate for the resistance difference between far-far memory cells and near-near memory cells.

[0161] For the purposes of this document, the first layer may be zero, or if one or more intervening layers are between the first layer and the second layer, it may extend across or above the second layer.

[0162] Please note that, for the purposes of this document, the dimensions of the various features shown in the drawings do not necessarily have to be drawn to scale.

[0163] For the purposes of this specification, references in the specification to “one embodiment,” “several embodiments,” or “another embodiment” are used to describe different embodiments and do not necessarily refer to the same embodiment.

[0164] For the purposes of this specification, a connection may be direct or indirect (e.g., through another part). Where it is stated that one element is connected to or joined to another, this element may be directly connected to the other element or indirectly connected to the other element through an intervening element. Where it is stated that one element is directly connected to another, there is no intervening element between this element and the other element.

[0165] For the purposes of this specification, the term "based on" can be read as "based on at least in part."

[0166] For the purposes of this specification, the use of numerical terms such as “first” object, “second” object, and “third” object, without additional context, does not imply an order of objects, but rather may be used for identifying purposes to distinguish between different objects.

[0167] For the purposes of this specification, the term “set” of objects may refer to a set of one or more objects from among the objects.

[0168] While the subject matter is described in language specific to structural features and / or methodological actions, it should be understood that the subject matter as defined in the attached claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms of implementing the claims.

Claims

1. It is a device, Multiple word lines coupled to a word line driver circuit, Multiple bit lines coupled to a bit line driver circuit, A plurality of memory cells are coupled between one word line among the plurality of word lines and one bit line among the plurality of bit lines, It is equipped with, Each of the plurality of memory cells has a total path resistance which is the sum of the resistance of the word line path from the word line driver circuit to the memory cell and the resistance of the bit line path from the bit line driver circuit to the memory cell. The aforementioned plurality of memory cells are Among the plurality of word lines, a near-near memory cell whose total path resistance is less than a predetermined first threshold, Among the plurality of word lines, a far-far memory cell comprising the memory cell whose total path resistance is greater than a predetermined second threshold greater than the first threshold, It includes, The aforementioned near-near memory cell includes a first memory cell having a first hard mask, The aforementioned far-far memory cell includes a second memory cell having a second hard mask, The resistance of the first hard mask is greater than the resistance of the second hard mask. An apparatus in which the difference between the resistance of the first hard mask and the resistance of the second hard mask is substantially equal to the difference between the total path resistance of the first memory cell and the total path resistance of the second memory cell.

2. The apparatus according to claim 1, wherein each of the first hard mask and the second hard mask includes a metallic material.

3. The apparatus according to claim 1, wherein each of the first hard mask and the second hard mask comprises one or more of tantalum, tantalum nitride, titanium, titanium nitride, tungsten, tungsten nitride, chromium, and ruthenium.

4. The apparatus according to claim 1, wherein the first hard mask material included in the first hard mask and the second hard mask material included in the second hard mask include the same material.

5. The apparatus according to claim 1, wherein the first hard mask material included in the first hard mask and the second hard mask material included in the second hard mask include different materials.

6. The apparatus according to claim 1, wherein each of the first memory cell and the second memory cell comprises a magnetic memory element coupled in series with a selector element.

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