Multi-stage current profiling technology for phase-change memory

Abstract

1 provides a multi-step current profile for a phase change memory implemented as part of the SET algorithm. [Solution] In logic flow 804, the change from the amorphous state to the crystalline state includes a nucleation stage to generate crystalline seeds, and a crystal growth stage after the nucleation stage to promote crystal growth to set the crystalline state and place the memory cell in a SET logic state, wherein the nucleation stage includes applying a first current for a first period followed by applying at least one second current for a second period, and the crystal growth stage includes applying at least one third current and a fourth current for a third period and a fourth period, respectively.

Description

Technical Field

[0001] The examples described herein generally relate to the technology of multi-stage current profiles of phase change memories implemented as part of the SET algorithm.

Background Art

[0002] Memory resources have numerous applications in electronic devices and other computing environments. To provide memory resources, scale issues have arisen with respect to conventional memory devices based on the use of electric charges for data storage and access by continuously fabricating smaller and more energy-efficient memory devices. Phase change materials (PCMs) are based on the properties of certain compounds that take on one of two or more states based on the heat applied to the materials contained in the PCM. In some examples, the PCM includes a chalcogenide material that can exhibit at least two states, namely a structured crystalline state and a disordered amorphous state. These two states typically depend on the characteristics of the application of heat to the chalcogenide material. Since PCMs are non-volatile and data storage and access are based on the structure / state of the material rather than the maintenance of electric charges, they can potentially scale to relatively small memory cells, so PCMs offer potential advantages for use in memory.

Brief Description of the Drawings

[0003] [Figure 1] An exemplary first system is shown.

[0004] [Figure 2] An exemplary second system is shown.

[0005] [Figure 3] An exemplary third system is shown.

[0006] [Figure 4] An exemplary representation is shown.

[0007] [Figure 5] An exemplary first current profile is shown.

[0008] [Figure 6] An exemplary second current profile is shown.

[0009] [Figure 7] An exemplary block diagram of the device is shown.

[0010] [Figure 8] An example of a logical flow is shown below.

[0011] [Figure 9] An example of a storage medium is shown.

[0012] [Figure 10] This illustrates an exemplary computing platform. [Modes for carrying out the invention]

[0013] Historically, the access performance of memory based on memory cell structures containing PCMs has been inferior to that of established memory technologies with memory cell structures arranged to maintain electronic charge. In recent years, read latency has improved to be comparable to these other established memory technologies, but write latency remains unmatched. The write latency of PCMs is most limited by the SET algorithm, which involves a first current pulse to RESET, i.e., SET, the PCM contained in the memory cell, which crystallizes it from an amorphous state. Some SET algorithms may use a fixed ramp rate for either a ramp-down method (which attempts to change the material to a crystalline state by first heating it to an amorphous state and then controlling the cooling) or a ramp-up method (which attempts to accelerate crystallization by controlling the rise in temperature). These methods of SET algorithms attempt to ensure that the memory cell experiences an optimal SET temperature to minimize SET latency / duration, and as a result, write latency is usually reduced.

[0014] In some cases, both the ramp-up and ramp-down methods of the SET algorithm work well for memory cells containing unconstrained PCMs, but are not effective for cells containing fully amorphous PCMs. In these cases, unconstrained PCMs refer to PCMs that are not fully amorphous in the RESET state and therefore may contain crystal nuclei or crystalline regions. Thus, the ramp-up / ramp-down SET algorithm method may only include a crystal growth step to convert the amorphous regions into a crystalline state based on already existing crystal nuclei. However, smaller memory cell sizes are required to scale PCM-based memory with reduced cost and power consumption. Since we have observed that the degree to which a cell is fully amorphous correlates with the thickness of the PCM and / or the area of ​​the memory cell, scaling PCM-based memory to smaller shapes results in memory cells that may not be efficiently SET by the ramp-up / ramp-down SET algorithm. Therefore, the ramp-up / ramp-down SET algorithm may require constrained memory cells to grow crystals, and scaling to smaller shapes increases SET latency / duration because the number of crystal nuclei or the amount of crystalline regions in the PCM contained in these smaller memory cells decreases. The PCM contained in these smaller memory cells may not properly transition to a crystalline state if there are insufficient crystal nuclei or crystalline regions to promote subsequent crystal growth. Therefore, ramp-up / ramp-down SET algorithms may result in unacceptably long SET latency / duration, negatively impacting write latency and / or resulting in memory cells that are not effectively SET. In the absence of an effective SET state, the bit error rate (BER) of data maintained in or accessed from these smaller memory cells may be high.

[0015] According to several new approaches for SET algorithms, memory cells containing PCMs can be SET using multi-stage SET algorithms. In these newer methods, the logic of the memory device (e.g., in the control unit) may cause the PCM contained in the memory cell to be heated to a first temperature over a first period. This first temperature may be adjusted to promote nucleation of the crystalline state of the PCM. This logic may cause the PCM temperature to rise to a second temperature over a second period. This second temperature may be adjusted to promote crystal growth within the PCM. Nucleation and crystal growth allow the PCM to be SET into a crystalline state. As a result, this exemplary multi-stage SET algorithm involves two stages of temperature ramp-up, resulting in separate nucleation and growth stages. These types of two-stage, multi-stage SET algorithms can function well when the time allocated to low temperatures is relatively long. However, these newer methods may limit latency reduction because increasingly smaller memory cells contain less PCM and require longer time in the nucleation stage to produce enough crystal nuclei to bring about a valid SET state following the growth stage.

[0016] In some cases, if the nucleation phase is not long enough to produce a sufficient amount of small crystal nuclei, the second, higher temperature in the growth phase can result in a PCM temperature that is too high during the growth phase. Therefore, the combination of insufficient time in the nucleation state and high temperatures during the subsequent growth phase can result in unstable and small crystal nuclei. Unstable and small crystal nuclei can result in memory cells where the PCM is not effectively SET. In the absence of an effective SET state, using two-stage, multi-stage SET algorithms can result in a higher bit error rate (BER) of data maintained in or accessed from these smaller memory cells.

[0017] As some examples show, and as will be described in more detail below, an improved SET algorithm may include a multi-stage current profile for a crystallization SET process having two distinct stages: a nucleation stage for generating crystal nuclei and a crystal growth stage for promoting crystal growth from those nuclei generated during the nucleation stage. Nucleation rates, which are typically stochastic processes and occur at a much slower rate, have a peak at a lower temperature compared to the crystal growth temperature, which is typically orders of magnitude higher than the peak of crystal growth at higher temperatures. As used herein, a SET algorithm including a multi-stage current profile may refer to an algorithm or procedure in which distinct temperature levels or temperature ramps are applied for a certain period of time (e.g., through controlled application of current and / or light) before the temperature level is changed. Thus, in one example, each time the temperature level exceeds a threshold level, it can be considered a different stage of the SET algorithm. Applying temperature or heat in multiple stages to the PCM contained in a memory cell can result in isothermal states, which can lead to changes in distinct material states (nucleation and / or crystal growth).

[0018] In some examples, the logic of a memory device having memory cells including PCMs may induce the application of different temperature levels through Joule heating by applying different amounts of current to the PCMs according to a multi-stage current profile. It will be understood that the specific value of the current used for Joule heating may vary depending on the type of material used for the PCMs and / or based on the relative positions of the memory cells within the memory array of the memory device. As described herein, the improved SET algorithm includes a nucleation stage at a lower temperature level to generate crystal nuclei, followed by multiple stages at a higher temperature level to complete crystal growth. With respect to Joule heating by current application, the improved SET algorithm can be performed via current pulses of lower amplitude to initiate the crystallization process through the generation of crystal nuclei, and then by current pulses of increasing amplitude to complete the crystallization process and accelerate crystal growth.

[0019] References to memory devices can apply to different memory types. Memory devices generally refer to volatile memory technologies. Volatile memory is memory whose state (and therefore the data stored within it) is uncertain when the power supply to the device is cut off. Non-volatile memory is memory whose state remains fixed even when the power supply to the device is cut off. Dynamically volatile memory requires refreshing the data stored in the device to maintain its state. Examples of dynamically volatile memory include dynamic random-access memory (DRAM) or any variation thereof, such as synchronous DRAM (SDRAM). The memory subsystems described herein may be compatible with various memory technologies. Various memory technologies include DDR3 (Double Data Rate Version 3, JESD79-3, first published by JEDEC (Japan Electronics Technology Association) on June 27, 2007), DDR4 (DDR Version 4, JESD79-4, first published by JEDEC in September 2012), LPDDR3 (Low Power DDR Version 3, JESD209-3B, first published by JEDEC in August 2013), LPDDR4 (Low Power DDR Version 4, JESD209-4, first published by JEDEC in August 2014), and WIO2 (Wide I / O). This may include, but is not limited to, technologies based on the following: 2 (WideIO2), JESD229-2 (first published by JEDEC in August 2014), HBM (High Bandwidth Memory DRAM, JESD235, first published by JEDEC in October 2013), LPDDR5 (first published by JEDEC in February 2019), HBM2 (HBM version 2, first published by JEDEC in December 2018), DDR5 (DDR version 5, currently under discussion by JEDEC), combinations of memory technologies, and technologies based on derivatives and extensions of these specifications.

[0020] In addition to, or instead of, volatile memory, in some examples, references to a memory device may refer to a non-volatile memory device whose state is determined even when the power supply is cut off. A non-volatile memory device may include non-volatile memory. Non-limiting examples of non-volatile memory include planar or 3D NAND flash memory or NOR flash memory, 3D cross-point memory, memory devices using chalcogenide phase change materials (e.g., chalcogenide glass), byte-addressable non-volatile memory devices, ferroelectric memory, silicon-oxide-nitride-oxide-silicon (SONOS) memory, polymer memory (e.g., ferroelectric polymer memory), ferroelectric transistor random access memory (Fe-TRAM) ovonic memory, nanowire memory, electrically erasable programmable read-only memory (EEPROM), resistive RAM, various other types of non-volatile random access memory (RAM), and / or any or combination of magnetic storage memory may be included.

[0021] FIG. 1 shows an exemplary system 100. In some examples, as shown in FIG. 1, the system 100 has a substrate 120 on which a PCM 110 is disposed. In some examples, the substrate 120 may be a semiconductor substrate on which semiconductor PCM is processed as a memory cell. In these examples, the substrate 120 may be a plastic or other material on which chalcogenide glass or other PCM is disposed as a storage medium. As shown in FIG. 1, the PCM 110 may have a thickness 114. The thickness 114 may enable reduction of the memory cell size for a higher density bit array or memory cell array.

[0022] According to some examples, for a thickness of 114, the PCM 110 may be a completely amorphous material in the RESET logic state. The reference to a "completely" amorphous material does not necessarily mean that every bit of the PCM deposited or otherwise processed on the substrate 120 is amorphous in the RESET logic state. Rather, a completely amorphous material may refer to all active regions within an amorphous PCM, as indicated by region 112 in Figure 1. Region 112 may or may not completely contain all of the phase-change material within the PCM 110 (as indicated by the shaded / patterned region not extending completely to the corners). Rather, region 112 may be completely amorphous in that it does not contain enough nuclei to promote crystal growth without first seeding the crystal growth. The System 100 and other figures herein are not necessarily drawn to scale. The amount of crystal nuclei required to promote growth may vary from PCM to PCM. In general, crystal growth occurs much faster and at much higher temperatures than nucleation. The crystalline state or SET logic state of PCM 110 can be highly ordered, have relatively low resistance and relatively high reflectivity, compared to the amorphous state or RESET logic state of PCM 110. Therefore, the logic state of PCM 110 can be read by calculating the resistance of the PCM or by the refractive index of light. Thus, PCM 110 may be, for example, a PRAM or PCM or an optical rotating disk or other memory.

[0023] In some examples, the heat source 130 may represent a heat source for the PCM 110. The PCM 110 can be integrated on an integrated circuit (I / C). The heat source 130 can include a terminal or a resistive element adjacent to a memory cell or other component of the I / C that can generate heat when current is applied to the terminal or the resistive element. In some examples, the heat source 130 can be a light source (e.g., a laser) that optically generates heat. In some respects, in a particular circuit application, a resistive element adjacent to a memory cell can be an optical circuit because more light and more heat are generated as more current is conducted through the resistive element. Thus, in some examples, the heat source 130 may be integrated adjacent to the PCM 110 and be local to the PCM 110. In other examples, the heat source 130 may be remote from the PCM 110 and include a laser or other electromagnetic wave source that transmits at various intensities over the PCM 110 to cause heating of the PCM 110.

[0024] According to some examples, the set control logic 140 can represent a circuit configuration configured to control the operation of the heat source 130. The set control logic 140 can be integrated on a common I / C that includes the PCM 110. For example, the set control logic 140 can be integrated on a common substrate 120 that includes the PCM 110. The set control logic 140 can control the heat source 130 to heat the PCM 110 in a plurality of different stages, first promoting nucleation and then promoting crystal growth from the generated crystal nuclei. In some examples, the set control logic 140 can separate the nucleation and / or growth stages into a plurality of stages as part of an implementation of a SET algorithm for setting the PCM 110 to a SET logic state.

[0025] Figure 2 shows an exemplary system 200. The system 200 shown in Figure 2 can represent a block diagram of a system that applies a multi-stage phase-change set procedure using a current-based heat source. System 200 may be an example of system 100 in Figure 1. In some examples, system 200 can represent a component of a memory subsystem having a phase-change random-access memory (PRAM) 220 to store and provide data in response to the operation of a processor 210. In these examples, system 200 can receive memory access requests from a host or processor 210, which is processing logic to perform an operation based on data stored in the PRAM 220 or to generate data to be stored in the PRAM 220. The processor 210 may be, or include, a host processor, central processing unit (CPU), microcontroller or microprocessor, graphics processor, peripheral processor, application-specific processor, or other processor, whether single-core or multi-core.

[0026] In some examples, as shown in Figure 2, the system 200 includes a memory control unit 230 that interfaces with the PRAM 220 and represents logic for managing access to the data stored in memory. In some examples, the memory control unit 230 may be integrated within the processor 210. In other examples, the memory control unit 230 may be standalone hardware separate from the processor 210. In other examples, the memory control unit 230 may be a separate circuit on the same board as the processor 210. In other examples, the memory control unit 230 may be a separate die or chip integrated on a common board with another die containing the processor 210 (for example, as part of a system-on-a-chip (SoC)). In some examples, at least a portion of the PRAM 220 may be included on the SoC with the memory control unit 230 and / or the processor 210.

[0027] In some examples, the memory control unit 230 may include read / write logic 234, which includes hardware that interfaces with the PRAM 220. The read / write logic 234 may enable the memory control unit 230 to generate read and write commands to process data access requests generated by the execution of instructions by the processor 210. In some examples, as shown in Figure 2, the memory control unit 230 includes a scheduler 232 for scheduling the transmission of access commands to the PRAM 220 based on known timing parameters for read and write access to the PRAM 220. The known timing parameters may be, for example, pre-programmed within the system 200, or they may be pre-configured. Such parameters may be stored in the PRAM 220 and accessed by the memory control unit 230. At least some of the parameters may be determined by a synchronization procedure. The timing parameters may also include timing related to the write latency of the PRAM 220. The write latency of the PRAM 220 can be determined by the PRAM 220's ability to change the logical state of bits held in the PCM memory cells contained in the memory array. For example, according to any embodiment described herein, the PCM contained in these memory cells is changed from an amorphous RESET logical state (e.g., bit = 0) to a crystalline SET logical state (e.g., bit = 1).

[0028] In some examples, the memory resources, memory arrays, or cache lines contained in the PRAM 220 can be represented by PCM memory cells 226. In these examples, the PCM memory cells 226 contain PCM, and the PCM for a given memory cell of the PCM memory cell 226 is fully amorphous in the RESET logic state. The PRAM 220 includes interface logic 224 for controlling access to the PCM memory cells 226. The interface logic 224 may include decoding logic to address specific rows, columns, or bits of data held in the PCM memory cells 226. In some examples, the interface logic 224 can control the amount of current supplied to a specific memory cell of the PCM memory cells 226. Thus, control of writing to the PCM memory cells 226 may be contained in the interface logic 224 or via a driver and / or other access circuit configuration coupled thereto.

[0029] In some examples, the control unit 222 of the PRAM 220 may be an on-die control unit for controlling the internal operation of the PRAM 220 in order for the PRAM 220 to execute commands received from the memory control unit 230. For example, the control unit 222 may control the timing, addressing, I / O (input / output) margining, scheduling, or error correction of the PRAM 220.

[0030] In some examples, the control unit 222 may be configured to write data to the PCM memory cell 226 according to any example involving separate nucleation and growth stages described herein. In these examples, the control unit 222 can control the operation of the interface 224 to supply or pass current to the memory cell of the PCM memory cell 226 selected to be written to. For example, the selected memory cell may be heated in stages to write data to the selected memory cell.

[0031] In some examples, the system 200 includes a power supply 240, as shown in Figure 2. The power supply 240 may be a voltage source or regulator that supplies power to the PRAM 220. The control unit 222 and / or interface logic 224 may use the power available from the power supply 240 to heat a selected memory cell of the PCM memory cell 226 to write data. Heating of the selected memory cell, including bringing the selected memory cell into a crystalline state (SET logic state), according to any example described herein. The control unit 222 and interface logic 224 can be considered a control circuit configuration that heats the PCM memory cell 226 to a first temperature over a first period, under the control of the control unit 222. The first temperature and first period are provided to promote nucleation with respect to the crystalline state of the PCM memory cell 226. The control unit 222 may then conduct more current to the interface logic 224, thereby raising the temperature of the PCM memory cell 226 from the first temperature to subsequent higher temperatures corresponding to a plurality of stages, each having a period. To set the PCM into a crystalline state, a series of steps having subsequent higher temperatures and respective durations are used to promote crystal growth of the PCM contained in the selected memory cell of the PCM memory cell 226. The control unit 222 and interface logic 224 may heat the PCM contained in the selected memory cell by passing current through the selected memory cell of the PCM memory cell 226, in addition to the possibility of passing current through other interface hardware.

[0032] Figure 3 shows an exemplary system 300. In some examples, system 300 can represent a block diagram of a system that applies a multi-stage current profile to a phase-change memory SET process utilizing an optical-based heat source. System 300 may be an example of system 100 described above and shown in Figure 1. In some examples, system 300 shown in Figure 3 includes a memory 320 having PCM memory cells 322 for storing and providing data stored in response to the operation of processor 310. Processor 310 may be any processor as described above for processor 210 of system 200. Processor 310 may perform operations based on data stored in memory 320 or generate data to be stored in memory 320.

[0033] In some examples, as shown in Figure 3, the system 300 also includes control logic 330 for controlling writing to the memory 320. In some examples, the control logic 330 is either a memory control unit or part thereof. In some examples, the control logic 330 may be integrated with the processor 310, integrated on the same board as the processor 310, or integrated with the processor 310 as part of a SoC. In some examples, the control logic 330 can control access to the memory 320 via a laser 340, for example, when the memory 320 is optically written to.

[0034] In some examples, as shown in Figure 3, the system 300 includes a laser 340. In these examples, the laser 340 may be able to optically heat selected memory cells of the PCM memory cell 322. Power from the power supply 350 may be used to control the intensity (energy per unit area) of the light produced by the laser 340. For example, based on the control of the intensity of the laser 340, the control logic 330 may write to selected memory cells of the PCM memory cell 332 according to any example described herein, which involves separate nucleation and growth stages. Thus, the control logic 330 may control the laser 340 to irradiate selected memory cells of the PCM memory cell 322 and write data to the memory 320 according to any example described herein, which includes bringing the PCM contained in the selected memory cells into a crystalline state.

[0035] In some examples, the control logic 330 and the laser 340 can be considered a control circuit that heats a selected memory cell of the PCM memory cell 322 to a first temperature over a first period of time, under the control of the control logic 330. The first temperature and the first period promote nucleation of the crystalline state of the PCM contained in the selected memory cell of the PCM memory cell 322. The control logic 330 can then cause the laser 340 to increase the intensity of light through a multi-step process, thereby raising the temperature of the selected memory cell from the first temperature to subsequent higher temperatures corresponding to a plurality of steps, each having a period of time. The second temperature and the second period can promote crystal growth within the PCM memory cell 322, setting the PCM into a crystalline state. A plurality of steps, each having a higher temperature and each having a period of time, to promote crystal growth of the PCM contained in the selected memory cell of the PCM memory cell 322 in order to set the PCM into a crystalline state.

[0036] Figure 4 shows an exemplary representation 400. In some examples, representation 400 includes diagrams 410 and 430, as shown in Figure 4. In these examples, diagrams 410 and 430 separate the heating of the PCM into multiple stages to provide a basis for transitioning the PCM contained in a selected memory cell to a crystalline state. For example, diagram 410 shows a probability density 414 plotted against temperature 412. Diagram 410 includes two curves, namely curve 422 showing the probability density of nucleation with temperature change and curve 424 showing the probability density of crystal growth with temperature change.

[0037] As mentioned above, some conventional methods of heating the PCM contained in a memory cell to transition the PCM to a crystalline state as part of the SET algorithm assume that crystal nuclei are already present in the PCM. Therefore, the SET algorithm initially focuses on crystal growth, and a temperature ramp through multiple stages attempts to reduce the time required to reach an acceptable amount of crystal growth (e.g., maximum crystal growth) by applying an increasing temperature range. As shown in Diagram 410, the maximum efficiency of nucleation can be achieved somewhere in the 400°C range for a particular PCM that generated Diagram 410 through testing, while the maximum efficiency of growth occurs somewhere closer to the 500°C range for that particular PCM. It is also observed that there is overlap in the 400-500°C range, which allows both nucleation and growth to occur, but at a much lower efficiency, and the time required to set the crystalline state is longer. It will be understood that various PCMs may have different temperatures and temperature ranges. For example, another PCM tested could be expected to achieve nucleation somewhere in the 250°C range and maximum growth somewhere above 300°C. Therefore, this example is merely one example and not limiting. Other PCM materials with other temperature ranges can also be used according to any example of the multi-stage SET process or procedure described herein.

[0038] In some examples, as shown in Figure 4, diagram 430 shows similar information to diagram 410, but on a logarithmic scale. Thus, in one embodiment, diagram 430 shows log(P)434, which is the logarithm of the probability density 414 with respect to temperature 432. Curve 442 shows nucleation occurring most efficiently around the 400°C range, and curve 444 shows growth occurring most efficiently around the 500°C range. Thus, it will be understood that performing SET to a crystalline state is beneficial because efficiency is improved by separating the nucleation and growth stages as part of a multi-step SET process.

[0039] Figure 5 shows an exemplary current profile 500. In some examples, the current profile 500 may be a schematic representation of an example of a multi-stage current profile for a crystal growth stage of a crystallization SET process having two distinct stages shown in Figure 5 as nucleation 510 and growth 520. In these examples, nucleation 510 may represent a nucleation stage for generating crystal nuclei, and growth 520 may represent a crystal growth stage for promoting crystal growth from the nuclei generated during nucleation 510. The current profile 500 may be a diagram of an exemplary multi-stage current profile for an algorithm or procedure in which different and separate temperature levels are applied for a certain period of time as the nucleation stage 510 and growth stage 520 progress, and then changed to or stepped up to a higher temperature level. The current profile 500 may show a current profile established or tested to complete a crystallization SET process with a particular PCM structure relating to a memory architecture or configuration. While the basic concept of the multi-stage current profile shown in Figure 5 for current profile 500 is expected to be the same, it should be understood that different memory architectures and / or different PCM structures may establish variations compared to the illustrated values.

[0040] According to some examples, the multiple stages of the current profile 500 can be seen in contrast to conventional SET algorithms, which either melt the crystal and then quench it to allow crystal growth, or continuously ramp up the current and temperature in a single stage to achieve crystallization, or result in pulses with a nucleation stage that is relatively long (e.g., 8 to 10 times longer) compared to the growth stage. The current profile 500 can be understood as having four distinct stages: initialization 530, nucleation 510, growth 520, and finalization 540.

[0041] In some examples, the current profile 500 begins with a current initiation pulse at A, which may initially melt the PCM contained in the selected memory cell. The current spike at A can be minimized to the minimum amount of current required to amorphousize the PCM, which allows the PCM to cool to a lower temperature more quickly and initiates the nucleation phase. For example, the current pulse at A may be limited to less than 150 microamperes (μA) for approximately 0.1 nanoseconds (ns), allowing the current to dissipate and PCM cooling to occur at B. In this example, the time from the initiation pulse to the start of nucleation (i.e., the initialization time 530) is expected to be less than 30 ns.

[0042] In some examples, as shown in Figure 5, nucleation 510 begins at C, which involves the application of a current of approximately 20–30 μA. This application of 20–30 μA may occur for approximately 65 ns. In these examples, this 20–30 μA can raise the temperature of the PCM contained in the selected memory cell to the minimum temperature that promotes the formation of crystal nuclei in the PCM. Next, nucleation 510 continues at D, where a first stepwise increase takes place for approximately 35 ns, during which the current increases to approximately 30–40 μA. The first stepwise increase at D can raise the temperature of the PCM to capture the remaining bits of the nucleation distribution and begin to promote crystal growth. Next, growth 520 begins at E, where a second stepwise increase takes place for approximately 35 ns, during which the current increases to approximately 40–50 μA, bringing the PCM to a medium temperature and enhancing crystal growth in the low-growth current bits. Next, growth continues up to F, where a third stepwise increase occurs, increasing the current to approximately 50-70 μA for about 35 ns. This third stepwise increase at F is the highest temperature, allowing the PCM to further enhance crystal growth, and the PCM enters the SET logic state.

[0043] In some examples, as shown in Figure 5, the current profile 500 at G includes a ramp-down of the current during the finalization stage 540 to reach H. In these examples, the current is ramped down to about 20-30 μA for less than about 30 ns and maintained. The finalization stage 540 may include a controlled ramp-down or step-down with a hold in the SET reverse current. It can be understood that certain regions of the PCM contained in the selected memory cell may be disturbed during the growth 520 process, melt, and return to an amorphous state. The finalization stage 540 may provide a short period of low-temperature control to allow the PCM to anneal and "recover" any disturbances in the grown crystal that may result from some overheating in a portion of the PCM's crystal structure.

[0044] Figure 6 shows an exemplary current profile 600. In some examples, current profile 600 may be a similar schematic representation to current profile 500 shown in Figure 5. For example, current profile 600 may also be a multi-stage current profile of the crystal growth stage of a crystallization SET process, which has two distinct stages shown in Figure 6 as nucleation 610 and growth 620. Current profile 600 shown in Figure 6 differs from current profile 500 in that, instead of keeping the temperature constant for a certain period to move the PCM from the nucleation stage to the growth stage, a relatively slow ramp of current can be applied to selected memory cells to allow a relatively slow sweep from low to high temperature. Also, as described above for current profile 500, current profile 600 may represent different current profiles established or tested to complete a crystallization SET process with a particular PCM structure of a memory architecture or configuration. The basic idea of ​​the ramp and multi-stage current profile combination as shown in Figure 6 for current profile 600 is expected to apply the same, but it will be understood that different memory architectures and / or different PCM structures may establish variations compared to the illustrated values.

[0045] According to some examples, the combination of ramping current profile 600 and multiple current stages can be seen in contrast to conventional SET algorithms, which either melt the crystal and then quench it to allow crystal growth, or achieve crystallization by continuously ramping up the current and temperature in a single stage, or result in pulses with nucleation stages that are substantially longer (e.g., about 8-10 times longer) compared to the growth stages. Current profile 600 can be understood as having four distinct stages: initialization 630, nucleation 610, growth 620, and finalization 640.

[0046] In some examples, the current profile 600 begins with a current initiation pulse at A, which initially melts the PCM contained in the selected memory cell. As shown in Figure 6, the current pulse at A may be limited to less than 150 μA for approximately 0.1 ns, allowing the current to dissipate and PCM cooling to occur at B. In this example, the time from the initiation pulse to the start of nucleation (i.e., the initialization time 630) is expected to be less than 30 ns.

[0047] In some examples, as shown in Figure 6, nucleation 610 begins at C, which involves the application of a current of approximately 20–30 μA. This application of 20–30 μA may occur for approximately 65 ns. In these examples, this 20–30 μA can raise the temperature of the PCM contained in the selected memory cell to the minimum temperature that promotes the formation of crystal nuclei in the PCM. Nucleation 610 then continues over a first portion of D, which includes a linear ramp for approximately 35 ns, steadily sweeping from 20–30 μA to approximately 40–50 μA to complete nucleation 610. The linear ramp of current over the first portion of D can linearly increase the temperature of the PCM, capturing the remaining bits of the nucleation distribution and beginning to promote crystal growth. Next, growth 620 begins in the second part of D, which involves a further ramp of current to a high current of about 70 μA for about 35 ns, steadily raising the PCM to its maximum temperature and continuously enhancing crystal growth of the low-growth current bits. Growth 620 then continues to E, which involves maintaining a high current of about 70 μA for about 35 ns to further enhance crystal growth and allow the PCM to enter the SET logic state.

[0048] In some examples, as shown in Figure 6, the current profile 600 at F includes a ramp-down of the current during the finalization 640 to reach F. In these examples, the current may be ramped up to 20-30 μA for less than approximately 30 ns and then maintained. Finalization 640 may include a controlled ramp-down or step-down with a hold in the SET reverse current. It can be understood that certain regions of the PCM contained in the selected memory cell may be disturbed during the growth 620 process, melt, and return to an amorphous state. Finalization 640 may provide a short period of low-temperature control to allow the PCM to anneal and "recover" any disturbances in the grown crystal that may result from some overheating in a portion of the PCM's crystal structure.

[0049] Figure 7 shows an exemplary block diagram of the device 700. While the device 700 shown in Figure 7 has a limited number of elements in a particular topology, it can be understood that the device 700 may include several elements in alternative topologies as desired for a given implementation.

[0050] The device 700 may be supported by a circuit configuration 720, which may be a control unit maintained in a memory device, or a control unit with a memory system coupled to a memory array of the memory device via an interface 703 which may also be used to access memory cells (e.g., via read or write operations). The memory device may be coupled to or included in a host computing platform. The circuit configuration 720 may be configured to run one or more logics, components, or modules 722-a, which are implemented with software or firmware (e.g., at least partially implemented by the control unit of the memory device). It is worth noting that as used herein, “a”, “b”, and “c” and similar designators are intended to be variables representing any positive integer. Thus, for example, if the implementation is set to the value a=3, the complete set of software or firmware corresponding to the logic, component, or module 722-a may include logics 722-1, 722-2, or 722-3. Furthermore, at least a portion of the "logic" may be software / firmware stored on a computer-readable medium, or at least partially implemented in hardware, and although the logic is shown as a separate box in Figure 7, this does not limit the logic to being stored on a separate computer-readable media component (e.g., a separate memory) or implemented on a separate hardware component (e.g., a separate application-specific integrated circuit (ASIC) or field-programmable gate array (FPGA)).

[0051] According to some examples, the circuit configuration 720 may include a processor or processor circuit configuration. The processor or processor circuit configuration may be any of the various commercially available processors, including but not limited to AMD® Athlon®, Duron®, and Opteron® processors, ARM® application, embedded, and secure processors, IBM® and Motorola® DragonBall® and PowerPC® processors, IBM and Sony® Cell processors, Intel® Atom®, Celeron®, Core(2)Duo®, Core i3, Core i5, Core i7, Itanium®, Pentium®, Xeon®, XeonPhi®, and XScale® processors, and similar processors. According to some examples, the circuit configuration 720 may also include one or more ASICs or FPGAs, and in some examples, at least some logic 722-a may be implemented as hardware elements of these ASICs or FPGAs.

[0052] In some examples, the device 700 may include selection logic 722-1. The selection logic 722-1 may be logic and / or function performed by a circuit configuration 720 that selects one memory cell from among the memory cells of a memory array and implements a SET write operation via interface 703. In these examples, the memory cell includes a phase-change material that changes its resistivity based on whether it is in a crystalline or amorphous state, the phase-change material having a constrained structure, being completely amorphous in all active regions of the amorphous state, and lacking sufficient crystalline nuclei to promote crystal growth. In these examples, the selection logic 722-1 can select a memory cell in response to a write request contained in a write request 710. For example, the write request 710 may be sent from a host CPU or processor (e.g., processor 210 or processor 310) and may trigger the selection of a memory for a SET write operation. The selection information 730 may also be routed from interface 703 and may include address information used to select a memory cell for the write operation.

[0053] In some examples, the device 700 may also include SET logic 722-2. SET logic 722-2 may be logic and / or function performed by a circuit configuration 720 that controls the change from an amorphous state to a crystalline state of the phase-change material contained in the memory cell by applying current to the terminals of the memory cell, the change from an amorphous state to a crystalline state including a nucleation step that generates a crystal seed and a crystal growth step that, after the nucleation step, promotes crystal growth to set the crystalline state and put the memory cell into a SET logic state. In these examples, the nucleation step may include applying a first current over a first period, followed by applying at least one second current over a second period, and the crystal growth step may include applying at least one third current and a fourth current over a third and fourth period, respectively. SET logic 722-2 can route current information 740 via interface 703 to indicate the respective currents and corresponding periods, causing the currents to be applied to the terminals of the memory cell.

[0054] This specification includes a set of logical flows representing exemplary methodologies for implementing novel embodiments of the disclosed architecture. For the sake of simplicity, one or more methodologies shown herein are presented and described as a series of operations, but those skilled in the art will understand and recognize that such one or more methodologies are not limited by the order of their operations. Some operations may, accordingly, occur in a different order than and / or concurrently with other operations shown and described herein. For example, those skilled in the art will understand and recognize that methodologies may be alternatively represented as a series of interrelated states or events, such as in a state diagram. Furthermore, not all operations shown in a methodology are necessarily required for a novel implementation.

[0055] Logical flows can be implemented in software, firmware, and / or hardware. In software and firmware embodiments, logical flows can be implemented by computer-executable instructions stored in at least one non-transient computer-readable or machine-readable medium, such as an optical memory, magnetic memory, or semiconductor memory. Embodiments are not limited in this context.

[0056] Figure 8 shows an example of a logic flow 800. The logic flow 800 can represent some or all of the operations performed by one or more logics, functions, or devices described herein, such as device 700. More specifically, the logic flow 800 may be implemented by one or more selection logics 722-1 or SET logics 722-2.

[0057] According to some examples, the logic flow 800 in block 802 can implement a SET write operation by selecting memory cells included in a memory array, the memory cells comprising a phase-change material that changes its resistivity based on whether it is in a crystalline or amorphous state, the phase-change material having a constrained structure, being completely amorphous in all active regions of the amorphous state and lacking enough crystalline nuclei to promote crystal growth. In these examples, the memory cells may be selected by selection logic 722-1.

[0058] In some examples, the logic flow 800 in block 804 can control the change from an amorphous state to a crystalline state of the phase change material contained in the memory cell by applying current to the terminals of the memory cell, and this change from an amorphous state to a crystalline state includes a nucleation step that generates a crystal seed, and a crystal growth step that, after the nucleation step, promotes crystal growth to set the crystalline state and put the memory cell into a SET logic state, the nucleation step including applying a first current over a first period, and then applying at least one second current over a second period, and the crystal growth step including applying at least one third current and a fourth current over a third and fourth period, respectively. In these examples, the current can be applied to the terminals by the SET logic 722-2.

[0059] Figure 9 shows an example of a storage medium 900. The storage medium 900 may include manufactured goods. In some examples, the storage medium 900 may include any non-temporary computer-readable or machine-readable medium, such as an optical memory device, a magnetic memory device, or a semiconductor memory device. The storage medium 900 can store various types of computer-executable instructions, such as instructions for implementing the logic flow 800. Examples of computer-readable or machine-readable storage media may include any tangible medium capable of storing electronic data, such as volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory. Examples of computer-executable instructions may include any appropriate type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, object-oriented code, or visual code. These examples are not limited to those in this context.

[0060] Figure 10 shows an exemplary computing platform 1000. In some examples, as shown in Figure 10, the computing platform 1000 may include a memory system 1030, processing components 1040, other platform components 1050, or a communication interface 1060. According to some examples, the computing platform 1000 may be implemented in a computing device.

[0061] In some examples, the memory system 1030 may include a control unit 1032 and a memory device 1034. In these examples, the logic and / or functions residing in or located in the control unit 1032 may perform at least some of the processing operations or logic of the device 700 and may include a storage medium including a storage medium 900. The memory device 1034 may also include a non-volatile memory (not shown) of a similar type described above for systems 100, 200, or 300 shown in Figures 1-3. In some examples, the control unit 1032 may be part of the same die as the memory device 1034. In other examples, the control unit 1032 and the memory device 1034 may be located on the same die, or on the same substrate or die having a processor (e.g., included in processing component 1040). In yet another example, the control unit 1032 may be in a separate die or integrated circuit coupled with the memory device 1034.

[0062] According to some examples, the processing component 1040 may include various hardware elements, software elements, or a combination of both. Examples of hardware elements may include devices, logic devices, components, processors, microprocessors, circuits, processor circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, programmable logic devices (PLDs), digital signal processors (DSPs), FPGAs / programmable logic, memory units, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. Examples of software elements may include software components, programs, applications, computer programs, application programs, system programs, software development programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The decision of whether an example is implemented using hardware and / or software elements may vary according to any number of factors, such as desired computing speed, power level, heat tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed, and other design or performance constraints, as desired for a given example.

[0063] In some examples, other platform components 1050 may include common computing elements such as one or more processors, multi-core processors, coprocessors, memory units, chipsets, control units, peripherals, interfaces, oscillators, timing devices, video cards, audio cards, multimedia I / O components (such as digital displays), and power supplies. Examples of memory units related to either other platform components 1050 or memory system 1030 may include, but are not limited to, various types of computer-readable and machine-readable storage media in the form of one or more faster memory units, such as read-only memory (ROM), RAM, DRAM, DDR DRAM, synchronous DRAM (SDRAM), DDR SDRAM, SRAM, programmable ROM (PROM), EPROM, EEPROM, flash memory, ferroelectric memory, SONOS memory, polymer memory such as ferroelectric polymer memory, nanowires, FeTRAM or FeRAM, ovonic memory, phase-shift memory, memristors, STT-MRAM, magnetic or optical cards, and other types of storage media suitable for storing information.

[0064] In some examples, communication interface 1060 may include logic and / or functionality to support the communication interface. In these examples, communication interface 1060 may include one or more communication interfaces that operate according to various communication protocols or standards for communication directly or over a network communication link. Direct communication may be performed via the direct interface through the use of communication protocols or standards described in one or more industry standards (including successors and variations), such as those related to the SMBus specification, PCIe specification, NVMe specification, SATA specification, SAS specification, or USB specification. Network communication may be performed via the network interface through the use of communication protocols or standards described in one or more Ethernet® standards published by the IEEE. For example, one such Ethernet standard may include "IEEE 802.3-2018, Carrier sense Multiple access with Collision Detection (CSMA / CD) Access Method and Physical Layer Specifications" ("IEEE 802.3-2018 specification"), published in August 2018.

[0065] The computing platform 1000 may be part of a computing device, such as a user device, computer, personal computer (PC), desktop computer, laptop computer, notebook computer, netbook computer, tablet, smartphone, embedded electronic device, game console, server, server array or server farm, web server, network server, internet server, workstation, minicomputer, mainframe computer, supercomputer, network appliance, web appliance, distributed computing system, multiprocessor system, processor-based system, or a combination thereof. Accordingly, the functions and / or specific configurations of the computing platform 1000 described herein may be included in or omitted from various embodiments of the computing platform 1000 as appropriately desired.

[0066] The components and functions of computing platform 1000 can be implemented using any combination of discrete circuit configurations, ASICs, logic gates, and / or single-chip architectures. Furthermore, the functions of computing platform 1000 may be implemented using microcontrollers, programmable logic arrays, and / or microprocessors, or, where appropriate, any combination thereof. Note that hardware, firmware, and / or software elements may be referred to collectively or individually as “logic,” “circuits,” or “circuit configurations” in this specification.

[0067] Although not shown in the illustration, any system may include and use a power source, including but not limited to a battery, an AC-DC converter for receiving AC and supplying DC, and a renewable energy source (e.g., solar power or motion-based power).

[0068] One or more embodiments of at least one example may be implemented by representative instructions representing various logics within a processor, stored in at least one machine-readable medium, such that when read by a machine, computing device, or system, these instructions cause the machine, computing device, or system to create logic for performing the techniques described herein. Such representations are stored in tangible machine-readable medium and supplied to various customers or manufacturing facilities to be loaded into manufacturing machines that actually produce logic or processors.

[0069] Various examples can be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processors, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. The decision of whether an example is implemented using hardware and / or software elements may vary according to any number of factors, such as desired computing speed, power level, heat tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus rate, and other design or performance constraints, as desired for a given implementation.

[0070] Some examples may include a manufactured product or at least one computer-readable medium. The computer-readable medium may include a non-temporary storage medium for storing logic. In some examples, the non-temporary storage medium may include one or more types of computer-readable storage medium capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or rewritable memory, etc. In some examples, the logic may include various software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0071] According to some examples, computer-readable media may include non-temporary storage media for storing or holding instructions, which, when executed by a machine, computing device, or system, cause the machine, computing device, or system to perform methods and / or actions in accordance with the examples described. Instructions may include any appropriate type of code, such as source code, compiled code, interpreted code, executable code, static code, dynamic code, etc. Instructions may be implemented according to a predefined computer language, method, or syntax to instruct a machine, computing device, or system to perform a particular function. Instructions may be implemented using any appropriate high-level language, low-level language, object-oriented programming language, visual programming language, compiled programming language, and / or interpreted programming language.

[0072] Some examples can be described using the expressions “in one example” or “one example,” along with their derivatives. These terms mean that a particular function, structure, or characteristic described in relation to an example is included in at least one example. The phrase “in one example” found in various parts of this specification does not necessarily refer to the same example in all instances.

[0073] Some examples can be described using the expressions “coupled” and “connected,” along with their derivatives. These terms are not necessarily intended to be synonyms of each other. For example, a description using the terms “connected” and / or “coupled” may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term “coupled” may also mean that two or more elements are not in direct contact with each other but are working together or interacting with each other.

[0074] It is emphasized that the abstract of this disclosure is provided in accordance with 37 C.FR. Section 1.72(b) requires an abstract so that readers may quickly confirm the nature of the technical disclosure. It is submitted on the understanding that it will not be used to interpret or limit the scope or meaning of each claim. Furthermore, it is found that in the modes for carrying out the invention described herein, various features are grouped into a single example for the purpose of streamlining the disclosure. This method of disclosure should not be interpreted as reflecting an intention that the claimed example requires more features than those explicitly described in each claim. Rather, as reflected in the following claims, the subject matter of the invention is less than all the features of the single disclosed example. Accordingly, the appended claims are incorporated into the modes for carrying out the invention herein, and each claim stands alone as a separate example. In the appended claims, the terms “including” and “in which” are used as plain English equivalents of the terms “comprising” and “wherein,” respectively. Furthermore, terms such as "first," "second," and "third" are used simply as labels and are not intended to impose numerical requirements on those entities.

[0075] While the subject matter has been described in language specific to structural features and / or methodological actions, it should be understood that the subject matter as defined in the attached claims is not necessarily limited to the specific features or actions described above. Rather, the specific features and actions described above are disclosed as exemplary forms that implement each claim.

[0076] [Other adjacent items] (Item 1) A memory cell in a memory array, A phase change material that changes its resistivity based on whether it is in a crystalline or amorphous state, having a constrained structure, being completely amorphous in all active regions of the amorphous state, and lacking sufficient crystalline nuclei to promote crystal growth, A memory cell of a memory array, comprising a terminal to the memory cell for providing an electric current to control the change of the phase change material from an amorphous state to a crystalline state, wherein the change from the amorphous state to the crystalline state comprises a nucleation step of generating a crystal seed, and a crystal growth step after the nucleation step of promoting crystal growth to set the crystalline state and put the memory cell into a SET logic state, wherein the nucleation step comprises applying a first current over a first period, and then applying at least one second current over a second period, and the crystal growth step comprises applying at least one third current and a fourth current over a third and a fourth period, respectively. (Item 2) A memory cell according to item 1, comprising the terminals for generating the above currents and controlling the change of the phase change material from the amorphous state to the crystalline state via temperature control associated with the first current, the at least one second current, the at least one third current, and the fourth current. (Item 3) The memory cell according to item 2, comprising: at least one second current including a single second current higher than the first current; and at least one third current including a single third current higher than the single second current and lower than the fourth current, wherein the single second current changes the phase change material to a second temperature higher than the first temperature produced by the first current; the single third current changes the phase change material to a third temperature higher than the second temperature; and the fourth current changes the phase change material to a fourth temperature higher than the third temperature. (Item 4) The memory cell according to item 2, comprising: at least one second current including a plurality of currents that increase linearly over the second period; and at least one third current including a plurality of currents that increase linearly over the third period, wherein the at least one second current linearly raises the phase change material to a second temperature higher than a first temperature produced by the first current; the at least one third current linearly raises the phase change material to a third temperature higher than the second temperature; and the fourth current causes the phase change material to maintain the third temperature. (Item 5) The memory cell according to item 1, further comprising a final step of annealing the phase change material, and including the change from the amorphous state to the crystalline state of the phase change material. (Item 6) The memory cell according to item 1, wherein the first period and the second period, when combined, are less than 1.5 times the duration of the third period and the fourth period, when combined. (Item 7) A memory array is a memory cell as described in item 1, including a crosspoint memory array. (Item 8) An interface for accessing the memory cells of a memory array, Control unit and A device equipped with, The above control unit has logic, at least a portion of the above logic is implemented as hardware, and the above logic is A memory cell is selected from the memory cells of the above memory array, and a SET write operation is implemented via the above interface, wherein the single memory cell is a phase change material that changes its resistivity based on whether it is in a crystalline or amorphous state, has a constrained structure, is completely amorphous in all active regions of the amorphous state, and lacks sufficient crystalline nuclei to promote crystal growth, An electric current is applied to the terminals of the memory cell to control the change of the phase change material contained in the memory cell from an amorphous state to a crystalline state, wherein the change from the amorphous state to the crystalline state includes a nucleation step of generating a crystal seed, and a crystal growth step after the nucleation step of promoting crystal growth to set the crystalline state and put the memory cell into a SET logic state, wherein the nucleation step includes applying a first current over a first period, and then applying at least one second current over a second period, and the crystal growth step includes applying at least one third current and a fourth current over a third and fourth period, respectively. Device. (Item 9) The apparatus according to item 8, comprising the logic for controlling the change of the phase change material from an amorphous state to a crystalline state via temperature control associated with the first current, the at least one second current, the at least one third current, and the fourth current, by applying the above current to the above terminals. (Item 10) The apparatus according to item 9, comprising at least one second current including a single second current higher than the first current, and at least one third current including a single third current higher than the single second current and lower than the fourth current, wherein the single second current changes the phase change material to a second temperature higher than the first temperature produced by the first current, the single third current changes the phase change material to a third temperature higher than the second temperature, and the fourth current changes the phase change material to a fourth temperature higher than the third temperature. (Item 11) Apparatus according to item 9, comprising at least one second current comprising a plurality of currents that increase linearly over the second period, and at least one third current comprising a plurality of currents that increase linearly over the third period, wherein the at least one second current linearly raises the phase change material to a second temperature higher than a first temperature produced by the first current, the at least one third current linearly raises the phase change material to a third temperature higher than the second temperature, and the fourth current causes the phase change material to maintain the third temperature. (Item 12) The apparatus according to item 8, further comprising the logic for bringing about a final step of annealing the phase change material, which includes the logic for bringing about the application of a fifth current over a fifth period, the change of the phase change material from the amorphous state to the crystalline state. (Item 13) The apparatus according to item 8, wherein the combined duration of the first and second periods is less than 1.5 times the combined duration of the third and fourth periods. (Item 14) One or more processors are communicably coupled to the control unit. A network interface connected to the above device in a communication-enabled manner, A battery connected to the above device, or A display that is communicatively coupled to the above device. The apparatus described in item 8, comprising one or more of the following. (Item 15) A step of selecting memory cells included in a memory array and implementing a SET write operation, wherein the memory cells are phase-change materials that change their resistivity based on whether they are in a crystalline or amorphous state, and include a phase-change material having a constrained structure, being completely amorphous in all active regions of the amorphous state, and lacking sufficient crystalline nuclei to promote crystal growth. A step of controlling the change from the amorphous state to the crystalline state of the phase change material contained in the memory cell by applying an electric current to the terminals of the memory cell, wherein the change from the amorphous state to the crystalline state includes a nucleation step of generating a crystal seed, and a crystal growth step of promoting crystal growth after the nucleation step to set the crystalline state and put the memory cell into a SET logic state, wherein the nucleation step includes applying a first current over a first period, and then applying at least one second current over a second period, and the crystal growth step includes applying at least one third current and a fourth current over a third and fourth period, respectively. A method for providing this. (Item 16) The method according to item 15, further comprising the step of applying the above current to the above terminals to control the change of the phase change material from the amorphous state to the crystalline state via temperature control associated with the first current, the at least one second current, the at least one third current, and the fourth current. (Item 17) The method according to item 15, comprising at least one second current including a single second current higher than the first current, and at least one third current including a single third current higher than the single second current and lower than the fourth current, wherein the single second current changes the phase change material to a second temperature higher than the first temperature produced by the first current, the single third current changes the phase change material to a third temperature higher than the second temperature, and the fourth current changes the phase change material to a fourth temperature higher than the third temperature. (Item 18) The method according to item 15, comprising the at least one second current comprising a plurality of currents that increase linearly over the second period, and the at least one third current comprising a plurality of currents that increase linearly over the third period, wherein the at least one second current linearly raises the phase change material to a second temperature higher than a first temperature produced by the first current, the at least one third current linearly raises the phase change material to a third temperature higher than the second temperature, and the fourth current causes the phase change material to maintain the third temperature. (Item 19) The method of item 15, further comprising the change of the phase change material from the amorphous state to the crystalline state, wherein the change is brought about by applying a fifth current over a fifth period of time to bring about a final step of annealing the phase change material. (Item 20) The method according to item 15, wherein the combined duration of the first and second periods is less than 1.5 times the combined duration of the third and fourth periods.

Claims

1. A memory cell of a memory array, wherein the memory cell is A phase change material that changes its resistivity based on whether it is in a crystalline or amorphous state, having a constrained structure, being completely amorphous in all active regions of the amorphous state, and lacking sufficient crystalline nuclei to promote crystal growth, and A terminal to the memory cell for generating an electric current to control the change from the amorphous state to the crystalline state of the phase change material, Equipped with, The change from the amorphous state to the crystalline state includes a nucleation step that generates crystal seeds, and a crystal growth step that, after the nucleation step, promotes crystal growth to set the crystalline state. The nucleation step is, Applying a first current over a first period of time, The first stepwise increase from the first current to the second current, Applying the second current over a second period, Includes, The aforementioned crystal growth step is The second stepwise increase from the second current to the third current, Applying the third current over a third period, The third stepwise increase from the third current to the fourth current, Applying the fourth current over a fourth period, Includes, The third period and the fourth period have the same duration. Memory cell.

2. The terminals provide an electric current and control the change of the phase change material from an amorphous state to a crystalline state via temperature control associated with the first current, the second current, the third current, and the fourth current, The memory cell according to claim 1.

3. The first current comprises a single first current, the second current comprises a single second current greater than the single first current, the third current comprises a single third current greater than the single second current, the fourth current comprises a single fourth current greater than the single third current, the single second current causes the phase change material to a second temperature higher than the first temperature produced by the single first current, the single third current causes the phase change material to a third temperature higher than the second temperature, and the single fourth current causes the phase change material to a fourth temperature higher than the third temperature. The memory cell according to claim 2.

4. In the crystal growth step, the third current is constant during the third period, and the fourth current is constant during the fourth period. The memory cell according to claim 3.

5. The change of the phase change material from the amorphous state to the crystalline state further comprises a finalization step of annealing the phase change material. The memory cell according to claim 1.

6. The combined duration of the first and second periods is less than 1.5 times the combined duration of the third and fourth periods. The memory cell according to claim 1.

7. The memory array includes a crosspoint memory array. The memory cell according to claim 1.

8. An interface for accessing memory cells of a memory array, A device comprising a control unit, The control unit has logic, at least a portion of which is implemented as hardware, and the logic is The selection of one memory cell from among the memory cells of the memory array, wherein the one memory cell has a phase change material that changes its resistivity based on whether it is in a crystalline or amorphous state, and the phase change material has a constrained structure, is completely amorphous in all active regions of the amorphous state, and lacks sufficient crystalline nuclei to promote crystal growth, The process involves applying a current to a terminal of one of the memory cells to control the change of the phase change material contained in the one memory cell from an amorphous state to a crystalline state, wherein the change from the amorphous state to the crystalline state includes a nucleation step to generate crystal seeds and a crystal growth step to promote crystal growth after the nucleation step, and applying the current. The nucleation step is, Applying a first current over a first period of time, The first stepwise increase from the first current to the second current, Applying the second current over a second period, Includes, The aforementioned crystal growth step is The second stepwise increase from the second current to the third current, Applying the third current over a third period of time, The third stepwise increase from the third current to the fourth current, Applying the fourth current over a fourth period, Includes, The third period and the fourth period have the same duration. Device.

9. The logic causes the terminals to apply current to control the change of the phase change material from the amorphous state to the crystalline state, via temperature control associated with the first current, the second current, the third current, and the fourth current. The apparatus according to claim 8.

10. The first current comprises a single first current, the second current comprises a single second current greater than the single first current, the third current comprises a single third current greater than the single second current, the fourth current comprises a single fourth current greater than the single third current, the single second current causes the phase change material to a second temperature higher than the first temperature produced by the single first current, the single third current causes the phase change material to a third temperature higher than the second temperature, and the single fourth current causes the phase change material to a fourth temperature higher than the third temperature. The apparatus according to claim 9.

11. The change of the phase change material from an amorphous state to a crystalline state includes the logic of applying a fifth current over a fifth period of time, and further includes the logic of performing a final step of annealing the phase change material. The apparatus according to claim 8.

12. The combined duration of the first and second periods is less than 1.5 times the combined duration of the third and fourth periods. The apparatus according to claim 8.

13. The second period, the third period, and the fourth period have the same duration. The apparatus according to claim 8.

14. In the crystal growth stage, the third current is constant for the third period and the fourth current is constant for the fourth period. The apparatus according to claim 8.

15. One or more processors connected to the control unit in a communicative manner, A network interface connected to the aforementioned device in a communication manner, A battery coupled to the aforementioned device, and A display that is communicatively coupled to the aforementioned device. The apparatus according to claim 8, comprising one or more of the above.

16. A method, A step of selecting memory cells included in a memory array and implementing a write operation, wherein the memory cells include a phase-change material that changes its resistivity based on whether it is in a crystalline or amorphous state, and the phase-change material has a constrained structure, is completely amorphous in all active regions of the amorphous state, and lacks sufficient crystalline nuclei to promote crystal growth, A step of controlling the change of a phase change material contained in the memory cell from an amorphous state to a crystalline state by applying a current to the terminals of the memory cell, wherein the change from an amorphous state to a crystalline state includes a nucleation step of generating a crystal seed, and a crystal growth step after the nucleation step of promoting crystal growth to set the crystalline state, The nucleation step is, Applying a first current over a first period of time, The first stepwise increase from the first current to the second current, Applying the second current over a second period, Includes, The aforementioned crystal growth step is The second stepwise increase from the second current to the third current, Applying the third current over a third period, The third stepwise increase from the third current to the fourth current, Applying the fourth current over a fourth period, Includes, The third and fourth periods have the same duration. method.

17. Includes applying current to the terminals to control the change of the phase change material from the amorphous state to the crystalline state via temperature control associated with the first current, the second current, the third current, and the fourth current. The method according to claim 16.

18. The first current comprises a single first current, the second current comprises a single second current greater than the single first current, the third current comprises a single third current greater than the single second current, the fourth current comprises a single fourth current greater than the single third current, the single second current causes the phase change material to a second temperature higher than the first temperature produced by the single first current, the single third current causes the phase change material to a third temperature higher than the second temperature, and the single fourth current causes the phase change material to a fourth temperature higher than the third temperature. The method according to claim 16.

19. The change of the phase change material from an amorphous state to a crystalline state further comprises performing a finalization step of annealing the phase change material by applying a fifth current over a fifth period of time. The method according to claim 16.

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