High-performance, high-voltage reverse-conducting semiconductor device

Abstract

To eliminate or significantly suppress the snapback phenomenon in a small cell area by using a highly concentrated buffer layer suitable for realizing ultra high breakdown voltage, and to reduce losses by utilizing this small cell size to reduce steady-state ON loss and switching time, in 8 to 25 kV-class ultra high breakdown voltage reverse conduction IGBTs.SOLUTION: A buffer layer structure, which has both semiconductor and insulator regions is provided, furthermore, insulating protrusions in the semiconductor region connected to the insulating region provide high resistance conductive paths in the semiconductor region, and a buffer layer in the form of a double-tooth comb, which is suitable for stripe cell structures, or a triangular buffer layer, which is suitable for polygonal cell structures such as honeycombs, is used to eliminate or significantly suppress the snapback phenomenon of ultra high breakdown voltage reverse conduction IGBTs in a small area.SELECTED DRAWING: Figure 7

Description

[Technical Field]

[0001] This invention relates to high-voltage semiconductor devices, and more particularly to high-performance ultra-high-voltage wide-gap reverse-conducting semiconductor devices and methods for manufacturing the same. [Background technology]

[0002] Traditionally, for high-voltage, high-power, and medium-power applications, Si-IGBT semiconductor devices made primarily of silicon (Si) have been the mainstream and widely used in various application fields, with products supplied up to the 6.5kV class. However, for ultra-high voltage applications beyond that, it is difficult to achieve compatibility with other characteristics such as power loss, and commercialization has not yet been achieved. In recent years, wide-bandgap semiconductor materials such as silicon carbide (SiC) have attracted attention as semiconductor materials suitable for high-voltage applications, and 1.2kV class SiC MOSFETs have been developed and are beginning to be put into practical use for electric vehicles. Ultra-high voltage SiC MOSFETs of the 10kV class have also been developed, but they have not yet been commercialized due to the large temperature dependence of their characteristic on-resistance, which leads to high power loss at high temperatures. On the other hand, SiC-IGBTs are attracting attention because of their potential for low losses in the high-current range due to the conductivity modulation effect unique to bipolar elements, and their small temperature dependence of on-voltage characteristics. As a result, ultra-high voltage elements in the 8-20kV class have been developed. However, they have the problem that they cannot be used because their built-in voltage is high, about 2.7V, which is about four times that of Si, and they cannot conduct power or operate below an on-voltage of about 3V. Furthermore, there is a demand for reducing switching losses by reducing the switching time, especially the turn-off time.

[0003] Reverse-conducting Si IGBTs, such as those described in [Non-Patent Document 1] and [Non-Patent Document 2], have been developed as a technology to reduce the turn-off time of IGBTs. In reverse-conducting Si IGBTs, the n-drift layer is short-circuited to the collector electrode by an n-short-circuit region provided in the p-collector layer. By removing carriers remaining in the n-drift layer during turn-off through this n-short-circuit region, the turn-off time can be shortened and switching losses can be significantly reduced. Similar effects can be expected with reverse-conducting SiC IGBTs.

[0004] Furthermore, while the built-in voltage of Si IGBTs is small at approximately 0.7V and does not pose a significant obstacle to reducing the on-voltage, in the case of SiC IGBTs, as mentioned above, it is large at 2.7V, which becomes a serious problem. However, in the case of reverse-conducting IGBTs, the MOSFET exists in parallel with the IGBT via a short-circuit region, so in the case of reverse-conducting SiC IGBTs, even below the built-in voltage, the current flowing through the short-circuit region can be utilized to significantly mitigate the problem.

[0005] However, in the output characteristics of the Si reverse-conducting IGBTs of Conventional Example 1 in [Non-Patent Document 1] and Conventional Example 2 in [Non-Patent Document 2], i.e., the Ice-Vce characteristic between the collector-emitter voltage (hereinafter referred to as Vce) and the collector-emitter current (hereinafter referred to as Ice), a snapback phenomenon occurs as shown in Figure 1, where the collector-emitter voltage immediately before turning on is greater than the collector-emitter voltage immediately after turning on. [Non-Patent Document 1] In the conventional example 1, it is called the knee point voltage. [Non-Patent Document 2] In the conventional example 2, this is called the pre-snapback peak voltage, but below we will call it the snapback voltage and denote it as Vsb. The collector-emitter current at this Vsb will be called the snapback current and denote it as Isb. However, because these reverse-conducting IGBTs have a short turn-on time, the time it takes from just before to just after turning on is short, so if the snapback phenomenon is present, a sharp voltage change (hereinafter denoted as dV / dt) and a sharp current change (hereinafter denoted as dI / dt) occur at turn-on. As a result, a sharp current jump (Cs·dv / dt) is generated by the parasitic capacitance Cs present in the circuit, and a sharp voltage jump (Ls·dI / dt) is generated by the parasitic reactor Ls, which in turn induces a large transient phenomenon. Therefore, this can cause a large disturbance in the circuit using this reverse-conducting IGBT, leading to malfunctions, and in some cases, damage or destruction of the element or circuit. Therefore, eliminating or reducing the snapback phenomenon to an acceptable level is an extremely serious problem.

[0006] To solve this problem, in Conventional Example 2, a Si reverse-conducting IGBT is composed of a reverse-conducting Si-IGBT region and a pilot IGBT region for improvement. That is, in addition to the reverse-conducting IGBT standard cell in the chip, a pilot IGBT region is provided. The width of the collector of the pilot IGBT region is made significantly larger than the width of the collector of the reverse-conducting IGBT cell, and the lateral resistance of the buffer layer on the p collector is made significantly larger. First, with a small Ice, the pilot IGBT region is driven ahead of the reverse-conducting IGBT region, and the entire Si reverse-conducting IGBT chip is turned on by significantly suppressing or eliminating the snap-back phenomenon.

[0007] However, in the case of this Conventional Example 2, the area of the pilot IGBT region in the entire IGBT chip area becomes quite large. For example, in the case of Conventional Example 2, when read from the data, even for a relatively low breakdown voltage of 3.3 kV design, the p collector width of the Si reverse-conducting IGBT standard cell is 240 micrometers, while by making the p collector width of the pilot IGBT about 650 micrometers or more, which is more than three times that of the standard cell, Vsb is set to about 0.7 V, which is the built-in voltage. Since the snap-back phenomenon becomes more severe as the breakdown voltage of the semiconductor device increases, the p collector width of this pilot IGBT further increases significantly. As a result, the snap-back phenomenon is eliminated, but the area of the reverse-conducting IGBT region in the entire IGBT chip of a predetermined area decreases, so the number of standard reverse-conducting cells to be integrated decreases, and the original function of the reverse-conducting IGBT to eliminate the carriers remaining at turn-off cannot be effectively exerted. Also, at turn-off, the elimination of the remaining carriers of the pilot IGBT, which occupies a large area, becomes significantly slower than that of the standard reverse-conducting cell, so the turn-off time becomes long and the turn-off loss becomes large. Also, in the current situation of wide-gap semiconductors where the chip size of the element is usually set to about 15 mm x 15 mm or less from the perspective of economic efficiency such as yield, the fact that the pilot IGBT occupies a large area becomes a more serious problem as the breakdown voltage increases.

[0008] Therefore, as shown in [Patent Document 1], the present inventor significantly thinned the drift layer using a wide-gap semiconductor such as SiC to reduce losses and size in a reverse-conducting IGBT with high breakdown voltage. At the same time, an element structure was provided to eliminate the obstacle that even if it is significantly thinned, it is easily broken in the manufacturing process and the economic efficiency is impaired. That is, unevenness is provided on the collector side of the element, an IGBT section is provided in the concave portion, and a MOSFET section is provided in the convex portion. The portion thicker than the IGBT section is utilized as a high-concentration drain layer of the MOSFET and a support layer for strength enhancement, maintaining high strength while maintaining the low-loss property of the reverse-conducting IGBT with high breakdown voltage to achieve high economic efficiency.

[0009] In addition, as shown in [Patent Document 2] and [Non-Patent Document 3], the present inventor used a wide-gap semiconductor such as SiC and, through a detailed analysis of the buffer layer structure of the SiC pilot IGBT, made the impurity concentration and thickness of the buffer layer appropriate or adopted a multiple buffer layer structure, thereby significantly reducing the width of the collector layer (i.e., the width of the buffer layer) even at ultra-high breakdown voltage and achieving miniaturization comparable to a standard cell. A standard cell with a pilot IGBT function was provided. The active region of the SiC reverse-conducting IGBT was composed only of this standard cell with a pilot IGBT function to eliminate or significantly suppress the snap-back phenomenon.

Prior Art Documents

Patent Documents

[0010]

Patent Document 1

Patent Document 2

Non-Patent Documents

[0011]

Non-Patent Document 1

[0012] However, in order to realize ultra-high voltage reverse-conducting semiconductor devices with a withstand voltage of 8kV or more for power generation and industrial use, if the above-mentioned prior art, such as the techniques described in [Patent Document 1] and [Patent Document 2], which use wide-bandgap semiconductors such as SiC and standard cells with pilot IGBT functionality, is used, if the impurity concentration of the buffer layer is low, it is necessary to increase the thickness of the drift layer in order to achieve ultra-high voltage, which can cause problems in reducing the on-resistance of the reverse-conducting semiconductor device. On the other hand, if the impurity concentration of the buffer layer is increased and a punch-through type is used to reduce the on-resistance, the lateral resistance of the buffer layer becomes small. For this reason, a relatively large Isb current is required to make the voltage drop across the buffer layer greater than the built-in voltage and inject holes from the collector to turn on the IGBT, which significantly increases the snapback phenomenon and can cause Vsb to exceed 1000V, leading to major problems. In this case, in order to eliminate the snapback phenomenon or significantly reduce Vsb to a practically acceptable range, for example, 10V or less, the lateral length of the buffer layer (corresponding to the p-collector width of the reverse-conducting IGBT cell) would need to be, for example, 7mm or more, which would increase the cell size and necessitate a considerably larger chip area composed of multiple cells. Furthermore, this would lead to problems such as slower discharge of residual carriers during element turn-off, longer turn-off times, and increased turn-off losses, potentially undermining the purpose of reverse conduction.

[0013] The present invention aims to solve the problems of the prior art described above and to provide a high-performance reverse-conducting semiconductor device that can eliminate or significantly suppress the snapback phenomenon even with a high-density buffer layer, which is particularly suitable for reverse-conducting semiconductor devices such as ultra-high voltage reverse-conducting IGBTs. It also aims to provide a highly economical, high-performance reverse-conducting semiconductor device that is suitable for ultra-high voltage reverse-conducting semiconductor devices, with a small p-collector width, which allows for a smaller cell size and, consequently, a smaller chip size. Furthermore, it aims to provide a high-performance reverse-conducting semiconductor device that can reduce steady-state losses and turn-off losses. [Means for solving the problem]

[0014] In the following, to avoid complexity and facilitate understanding, we will focus on n-channel type wide-bandgap semiconductors, particularly SiC reverse-conducting IGBTs, as reverse-conducting semiconductor elements. Naturally, the solutions described below are particularly effective when applied to wide-bandgap reverse-conducting semiconductor devices such as SiC due to their physical properties. However, they are also highly effective in the case of Si semiconductors, which offer significant economic advantages compared to wide-bandgap semiconductors because they allow for lower wafer costs, larger diameters, and fewer constraints on large chip sizes.

[0015] In order to solve the above-mentioned problems and achieve the objectives of the present invention, the reverse-conducting semiconductor device according to this invention is The IGBT semiconductor device is primarily a reverse-conducting IGBT semiconductor device, the IGBT reverse-conducting semiconductor device having a reverse-conducting IGBT chip, the reverse-conducting IGBT chip having an active region having one or more reverse-conducting IGBT standard cells and a withstand voltage structure surrounding the active region, and the IGBT chip having an active region containing multiple reverse-conducting IGBT standard cells and a withstand voltage structure surrounding the active region. The reverse-conducting IGBT standard cell of the IGBT chip has a cross-sectional configuration that minimizes the following: a MOS surface region is provided between one main surface and the drift layer surface of the first conductivity type, exposed on one main surface of the active region; an emitter main electrode is provided on the exposed surface of the MOS surface region; a buffer layer is provided in contact with the back surface of the drift layer of the first conductivity type; a collector region of the second conductivity type and a short-circuit region of the first conductivity type (which also serves as the drain region of the MOSFET section) are provided on the back surface of the buffer layer, with a portion of each side in contact with the other region; and a collector main electrode is provided on the back surface of the collector region of the second conductivity type and the short-circuit region (which also serves as the drain region) of the first conductivity type. A first conductivity type current density increasing layer CEL may be provided between the MOS surface region and the first conductivity type drift layer. Furthermore, the buffer layer on the collector region is characterized by being a reverse-conducting IGBT standard cell having a semiconductor region of a first conductivity type that serves as a conductive path and an insulating region or a semi-insulating region. The MOS surface region is defined as follows: Each reverse-conducting IGBT cell is composed of an IGBT section and a MOSFET section connected in parallel. However, each MOS surface section on the main surface side of the drift layer is shared by both the MOSFET section and the IGBT section, and is connected to the emitter main electrode of the uppermost reverse-conducting IGBT. This region where the shared MOS surface sections are gathered, including the emitter main electrode, is collectively defined and referred to as the MOS surface region. Furthermore, the term "insulating region" in this patent refers to a region composed of either an insulator or a semi-insulating material, or both, and an insulator is defined as having a resistivity of 1 x 10⁻¹⁰. 11 A material with a resistivity exceeding Ωcm is considered a semi-insulator, meaning its resistivity is 1 x 10⁻⁶. 5 Ωcm~1x10 11 This refers to materials in the Ωcm range. In this patent, to avoid complexity in explanation, unless there is a strong need to distinguish between them, they will generally be referred to simply as the insulating region. Furthermore, it is effective to provide an n-current density enhancement layer (CEL) between the MOS surface region and the n-drift layer to increase the current density by accumulating carriers within the n-drift layer, and this is often provided, especially in the case of ultra-high voltage IGBTs of 8kV or higher.

[0016] In order to solve the above-mentioned problems and achieve the objectives of the present invention, the reverse-conducting semiconductor device according to this invention is The reverse-conducting IGBT standard cell within the active region has a stripe structure or a stripe structure that is equally divided in the longitudinal direction, the buffer layer has a stripe-shaped double-toothed comb-type planar shape as shown in Figure 4, a plurality of comb teeth are connected to a comb shaft, the comb shaft, the comb teeth and the comb tooth assembly are composed of the semiconductor region, and the spaces between the comb teeth are composed of the insulating region or semi-insulating region. The comb teeth, the comb tooth assembly, and the insulating or semi-insulating region between them are in contact with the collector region, and the comb shaft is in contact with the short-circuit region.

[0017] In order to solve the above-mentioned problems and achieve the objectives of the present invention, the reverse-conducting semiconductor device according to this invention is The reverse-conducting IGBT standard cell has a polygonal planar shape enclosed by three or more line segments, and the triangular portion connecting the intersection of the line segments to the center point of the polygon is composed of the semiconductor region or the insulating region, and the triangular portions of the semiconductor region and the triangular portions of the insulating region are arranged alternately to constitute the buffer layer.

[0018] In order to solve the above-mentioned problems and achieve the objectives of the present invention, the reverse-conducting semiconductor device according to this invention is The semiconductor region of the reverse-conducting IGBT standard cell is provided with insulating protrusions made of the same insulating material as the insulating region, and the insulating protrusions are in contact with either the upper or lower insulating region adjacent to the semiconductor region. The resistance of the conductive path in the buffer layer can be set by setting the shape and number of the insulating protrusions, and Isb and consequently Vsb can be set.

[0019] In order to solve the above-mentioned problems and achieve the objectives of the present invention, the reverse-conducting semiconductor device according to this invention is In the reverse-conducting semiconductor device having the reverse-conducting IGBT standard cell, In addition to the aforementioned reverse-conducting IGBT standard cell, the configuration is characterized by including, instead of the aforementioned reverse-conducting IGBT standard cell, reverse-conducting IGBT cells with smaller cell widths other than the aforementioned reverse-conducting IGBT standard cell.

[0020] In order to solve the above-mentioned problems and achieve the objectives of the present invention, the reverse-conducting semiconductor device according to this invention is The reverse-conducting IGBT semiconductor device is characterized in that the insulating region of the buffer layer is made of a vanadium-doped epitaxial film, the conductive path is made of a first conductivity type ion implantation layer that reaches the first conductivity type drift layer, and the impurity concentration of the ion implantation layer is higher than the impurity concentration of the drift layer.

[0021] In order to solve the above-mentioned problems and achieve the objectives of the present invention, the method for manufacturing a reverse-conducting semiconductor device according to this invention is: In the method for manufacturing the reverse-conducting IGBT semiconductor device, The insulating region fabrication process is characterized in that it includes a selective implantation step of insulating ions, or includes a trench formation step for trench MOS gates and the like, and a subsequent step of forming an oxide film of semiconductor exposed on the trench surface, and the insulating region fabrication process is performed after the collector region fabrication process.

[0022] In order to solve the above-mentioned problems and achieve the objectives of the present invention, the operating method of the reverse-conducting semiconductor device according to this invention is: The reverse-conducting semiconductor device is characterized in that, by energizing the majority carrier current of the MOSFET section, the temperature of the built-in pn junction diode and IGBT section is raised to a temperature above the on-voltage degradation suppression temperature, and then predetermined electrical operations are performed.

[0023] In order to solve the above-mentioned problems and achieve the objectives of the present invention, the reverse-conducting IGBT semiconductor device of the present invention is as follows: In a reverse-conducting IGBT cell with a stripe structure, unlike conventional stripe-structured buffer layers on the p-collector region, the stripe-structured buffer layer on the p-collector region has a planar configuration consisting of a conductive path made of a semiconductor with a comb-like shape and comb teeth on both the left and right sides of the comb axis, and an insulator or semi-insulator filling the spaces between the comb teeth, as shown in Figure 4. This buffer layer is defined as a double-comb type buffer layer and will be referred to by this name below.

[0024] As a result, each comb tooth portion functions as a key structural factor that suppresses the snapback phenomenon. However, since the space between the comb teeth is an insulator or semi-insulator, there is almost no current flowing through this space between the comb teeth. The current flows from the comb tooth assembly, i.e., the conductive path facing the JFET on the main surface side, through each comb tooth and into the short-circuit region. Therefore, it is preferable to satisfy the following conditions, for example, as this makes it relatively easy to design the resistance value Ri of each comb tooth to a desired value. (1) The comb teeth shall be of the same shape and consist of N teeth, with the width, length, and thickness of the comb teeth being Wa, La, and t, the width, length, and thickness between the comb teeth being Wb, Lb, and t, and the length of the left and right insulators at both the upper and lower ends of the comb tooth group being Lb / 2. (2) The width of a conventional simple stripe-type buffer layer is W, the length is L, and the thickness is t. (3) Make sure that Nx(La+Lb)=L and Wa=Wb=W. In this case, since the resistance Ri of each of the N comb teeth is connected in parallel, the total resistance RbufferT of the buffer layer for half a cell is given by the following equation, where ρ is the resistivity of the conductive path. Ri = ρx(Wa / (Laxt) [1] RbufferT=1 / (1 / R1+1 / R2+··+1 / Ri+··+1 / RN) [2]

[0025] As a result, when the surface area {Nx(La+Lb)xW} of the double-tooth comb-type buffer layer of the present invention is the same as that of a conventional simple stripe-type buffer layer, the cross-sectional area of ​​the conductive path is reduced by the cross-sectional integral of the inter-tooth insulator, so the total resistance Rbuffer of the double-tooth comb-type buffer layer can be increased accordingly. Therefore, carrier injection from the p collector can be started with a smaller current Isb, and the IGBT can be turned on. Furthermore, since Isb is smaller, the voltage drop across the drift layer is also smaller, and the Vsb of the snapback phenomenon just before IGBT is turned on can be reduced. Furthermore, the total resistance RbufferT of the buffer layer can be further increased by reducing only the comb tooth length La. Thus, with this invention, Rbuffer can be increased or decreased by the comb tooth length La and comb tooth width Wa, making it easy and flexible to eliminate or suppress the snapback phenomenon to an acceptable range. Furthermore, in Figure 4, the length of both teeth of the comb is made to roughly match the length of the cell, but by dividing it equally and providing multiple units in the length direction and connecting them in parallel, the degree of freedom in manufacturing and design is increased, making it easier and more flexible. Moreover, by dividing the cell itself equally in the length direction and providing multiple units and connecting them freely, the degree of freedom in manufacturing and design is further increased, making it easier and more flexible.

[0026] Furthermore, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the reverse-conducting IGBT semiconductor device of the present invention provides: In the comb-tooth region, as shown in Figure 6, insulating protrusions (hereinafter referred to as insulating protrusions) connected to the adjacent upper insulating region and insulating protrusions connected to the adjacent lower insulating region are alternately provided, thereby forming a conductive path made of semiconductor between the comb-tooth assembly and the short-circuit region. This buffer layer is defined as a double-tooth comb-type buffer layer with insulating protrusions, and will be described by this name below. This double-tooth comb-type buffer layer with insulating protrusions is folded in a zigzag pattern in the width direction of the cell within the comb teeth, and can be made longer and narrower in width compared to the comb-shaped buffer layer of the double-tooth comb-type buffer layer in Figure 4. Therefore, if the thickness of the buffer layer is the same, the resistance Ri of the comb teeth of the buffer layer can be increased, and the total RbufferT of the parallel resistance of N comb teeth can also be increased. As a result, carrier injection from the p collector can be started with an even smaller current Isb, and the IGBT can be turned on. Furthermore, because Isb is even smaller, the voltage drop in the drift layer is also smaller, and the Vsb of the snapback phenomenon just before IGBT is turned on can be further reduced. In this double-toothed comb-type buffer layer with insulating protrusions, the total resistance RbufferT can be further increased by keeping the surface area of ​​the comb teeth the same, increasing the number of protrusions, and further reducing the width of the protrusions. In this way, the number and shape of the protrusions can be easily and flexibly set to eliminate or suppress the snapback phenomenon to an acceptable range, according to the purpose.

[0027] Furthermore, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the reverse-conducting IGBT semiconductor device of the present invention provides: The reverse-conducting IGBT cell can be applied to various structures other than the stripe structure, such as polygonal structures like the honeycomb structure shown in Figure 8. These polygonal cell structures are relatively easy to apply the trench gate structure to, resulting in significant cell miniaturization and substantial cost savings through reduced losses and chip area. Furthermore, similar to the double-toothed comb-type buffer layer described above, the conductive path resistance can be increased by providing insulating protrusions in the triangular semiconductor region. Additionally, the number and shape of the protrusions can be easily and flexibly adjusted to eliminate or suppress the snapback phenomenon to an acceptable range, depending on the objective. Furthermore, by dividing each triangular insulating region into, for example, three triangles with the center as the vertex, and making the two left and right triangles adjacent to the semiconductor region semiconductor regions while leaving only the middle triangle as an insulating region, the area of ​​the insulating region can be substantially reduced, thereby increasing the collector area within the cell, reducing on-resistance, and also reducing turn-off time.

[0028] Furthermore, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the reverse-conducting IGBT semiconductor device of the present invention provides: In addition to the aforementioned reverse-conducting IGBT standard cell, the configuration includes, instead, reverse-conducting IGBT standard cells with smaller cell widths and other reverse-conducting IGBT cells with smaller cell widths other than the standard cell. This eliminates or significantly suppresses the snackback phenomenon with the aforementioned reverse-conducting IGBT standard cell, while allowing for the integration of more reverse-conducting IGBT cells within the same size active region, thereby reducing on-resistance. Furthermore, it allows for the integration of more reverse-conducting IGBT cells with smaller cells and shorter turn-off times, leading to further loss reduction.

[0029] Furthermore, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the reverse-conducting IGBT semiconductor device of the present invention provides: Vanadium-doped semiconductor epitaxial films, despite their semi-insulating properties, readily undergo homoepitaxial growth on the drift layer without crystal mismatch. This ensures good compatibility with the preceding and succeeding reverse-conducting IGBT semiconductor device fabrication processes, allowing for direct ion implantation for conductive path formation before collector layer formation, and reducing the ion implantation depth by the collector thickness. As a result, implantation energy can be reduced, eliminating the need for expensive ultra-high-energy ion implantation equipment. Furthermore, implantation damage can be reduced, mask formation for selective ion implantation can be simplified, and yield can be improved, leading to high economic efficiency. In addition, the vanadium-doped layer has a function of suppressing the growth of stacking faults, and is expected to have an effect in suppressing on-voltage degradation of reverse-conducting IGBTs and built-in pn diodes for flywheeling.

[0030] Furthermore, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the reverse-conducting IGBT semiconductor device of the present invention provides: In the method for manufacturing a reverse-conducting IGBT semiconductor device, a p-collector formation step is performed after the n-buffer layer formation step, and then a trench-type insulating region formation step similar to the trench gate formation step of known MOSFETs and IGBTs is selectively performed. However, the insulating oxide film formed after trench formation is sufficiently thicker than in the case of a trench gate, and the concave oxide film is filled with a subsequent ohmic contact p-epitaxial layer 57, polished, and smoothed. This allows for the simultaneous formation of a p-collector layer of the same shape directly beneath the conductive path of the n-buffer layer, reducing the number of steps, and effectively utilizing the on-current of the MOSFET section to form a voltage drop that promotes injection from the p-collector, which is also effective in reducing ISB.

[0031] Furthermore, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the reverse-conducting IGBT semiconductor device of the present invention provides: In the method for manufacturing a reverse-conducting IGBT semiconductor device, a p-collector formation step is performed after the semiconductor buffer layer formation step, and then selective ion implantation is performed to selectively form insulating protrusions and insulating regions within the semiconductor region of the buffer layer. Specifically, a photomask for selective implantation is provided, and insulating or ultra-high-resistance semi-insulating dopants such as oxygen or vanadium ions are selectively implanted into areas other than the conductive path of the buffer layer, from the p-collector side to the drain layer. After that, annealing is performed to recover from the damage caused by ion implantation. This allows for the simultaneous formation of a p-collector layer of the same shape directly beneath the n-buffer layer which forms the conductive path, reducing the number of steps, and effectively utilizing the on-current of the MOSFET to form a voltage drop that promotes injection from the IGBT's p-collector, thereby reducing ISB. Furthermore, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the reverse-conducting IGBT semiconductor device of the present invention provides: In the method for manufacturing the reverse-conducting IGBT semiconductor device, after the drain layer is formed, a vanadium-doped epitaxial growth process is carried out, and then a process is performed to form a conductive path of the same first conductivity type as the drain layer by selective ion implantation of nitrogen into this vanadium-doped epitaxial layer. As a result, the parts where nitrogen is not implanted automatically become insulating or semi-insulating regions. Subsequently, a second conductive collector layer is formed by epitaxial growth. This method avoids crystal structure mismatch with the vanadium-doped epitaxial layer, resulting in the formation of a high-quality collector layer with good crystallinity. Furthermore, since it is not necessary to penetrate the collector layer, the implantation energy is small, allowing the use of a conventional ion implantation device. Implantation damage is also reduced, making annealing for recovery easier, and the mask for selective implantation is simpler, resulting in significantly higher cost-effectiveness.

[0032] Furthermore, in order to solve the above-mentioned problems and achieve the objectives of the present invention, the reverse-conducting IGBT semiconductor device of the present invention provides: In the operation method of a reverse-conducting semiconductor device, the heat generated by the flow of majority carrier current in the MOSFET section raises the temperature of the built-in pn junction diode to above the on-voltage degradation suppression temperature before performing predetermined electrical operations. This suppresses on-voltage degradation of the built-in pn junction diode and IGBT, which are unique to SiC bipolar devices caused by stacking faults, and characteristic degradation due to device damage caused by higher-order snapback phenomena. [Effects of the Invention]

[0033] As described above, the present invention enables the use of a buffer layer with a high impurity concentration, which is advantageous for achieving ultra-high breakdown voltage with low loss, and allows for the elimination or suppression of the snapback phenomenon to an acceptable range with a significantly smaller cell area. If the active region is the same size, more cells can be integrated due to the reduction in cell area, resulting in lower losses. Furthermore, the miniaturization of the cell by reducing the cell area allows for the effective discharge of residual carriers during turn-off, reducing turn-off time and switching losses. In addition, the built-in pn diode of the cell can be used as a flywheel diode, eliminating the need to provide one separately inside or outside the chip, thus significantly reducing the chip area. Moreover, the TEDREC operation method, which utilizes the heat generated by the conduction of majority carrier current in the MOSFET section, can eliminate or significantly suppress the on-voltage degradation and characteristic degradation due to higher-order snapback of the SiC-specific reverse-conducting IGBT and built-in pn diode. [Brief explanation of the drawing]

[0034] [Figure 1] Diagram illustrating the snapback phenomenon in the output characteristics of a reverse-conducting IGBT. [Figure 2] Plan view showing the main part of the SiC reverse-conducting IGBT chip of Example 1 of the present invention. [Figure 3] This is a cross-sectional view of the SiC reverse-conducting IGBT cell in the active region of Example 1, and is a cross-sectional view between the dotted lines A and B in Figure 4, which is a plan view of both comb-shaped buffer layers. [Figure 4] Plan view illustrating the configuration of the double-toothed comb-type buffer layers in Example 1. [Figure 5] Main fabrication process flow diagram of the SiC reverse conducting IGBT in Example 1 [Figure 6] Plan view of the double-toothed comb-type buffer layer with insulating protrusions in Example 2 [Figure 7] This is a cross-sectional view of the SiC reverse-conducting IGBT cell in the active region of Example 2, and Figure 6 shows a cross-sectional view between CDs corresponding to the portion where insulating protrusions are present. [Figure 8a] Explanatory cross-sectional view of the reverse-conducting IGBT having a honeycomb-type buffer layer with insulating protrusions according to Example 6. [Figure 8b] Plan view illustrating the buffer layer of the reverse-conducting IGBT having a honeycomb-type buffer layer with insulating protrusions in Example 6. [Figure 9] Main fabrication process flow diagram of the SiC reverse conducting IGBT in Example 8 [Modes for carrying out the invention]

[0035] The high-voltage wide-gap reverse-conducting semiconductor device of the present invention will be described in more detail below with reference to the drawings, using examples. In this specification and the accompanying drawings, layers and regions prefixed with n or p indicate that electrons or holes are the majority carriers, respectively. In principle, only one number and arrow indicating layers and regions in the drawings are shown for each layer or region, with others mostly omitted. Furthermore, each figure is a schematic diagram for better illustrating the invention, and there is no correlation such as proportionality between the dimensions within and between the figures. [Examples]

[0036] The first embodiment of the present invention is a 15kV class SiC double-tooth comb buffer layer type ultra-high voltage reverse conducting IGBT made of 4H-SiC. Figures 2 to 4 are schematic diagrams illustrating this embodiment, with Figure 2 being a plan view of the chip surface of Embodiment 1, Figure 3 being a cross-sectional view of the cell, and Figure 4 being a plan view of the buffer layer of the cell. Note that Figure 3 shows a cross-sectional view of the portion corresponding to the dotted line A-B in the plan view of the buffer layer in Figure 4.

[0037] First, the main planar configuration of the surface of Example 1 will be explained using Figure 2. Below, to avoid complexity and facilitate understanding, the explanation will focus on an n-channel type reverse-conducting IGBT. In Figure 2, an active region 2, composed of striped IGBT cells, is provided in the center of the chip as shown by the thick line, and a pressure-resistant structure is provided surrounding this active region 2 to achieve pressure resistance. In this embodiment 1, this pressure-resistant structure consists, for example, of a JTE (Junction Termination Extension) 3 and a field region 4 for electric field relaxation, followed by an n-channel stopper 5, in order from the active region. The chip size of the reverse-conducting IGBT is 8mm x 8mm, and the size of the active region 2 is approximately 6mm x 6mm. The width of the pressure-resistant structure is approximately 1mm, which is wider than the width originally required, to absorb the difference between the sum of the widths of an integer number of standard cells and 6mm, and also includes a dicing area. The active region 2 is provided with one or more cells of the present invention, which are double-toothed comb buffer layer type reverse conductive IGBTs. Figure 3 illustrates the case where there are four cells for the purpose of explaining the principle.

[0038] Figure 3 is a cross-sectional view of the reverse-conducting IGBT standard cell shown in Figure 2, and as mentioned above, it is a cross-sectional view of the portion between dotted lines A and B in the plan view of the buffer layer in Figure 4. The general configuration is briefly explained below. Each reverse-conducting IGBT cell is configured with an IGBT section and a MOSFET section connected in parallel. On one main surface side of Figure 3, a MOS surface region 114 is provided, which is a collection of MOS surface sections shared by both the MOSFET section and the IGBT section constituting each reverse-conducting IGBT cell, and the emitter main electrode 113 of the reverse-conducting IGBT is provided on the uppermost surface. A current density increasing layer CEL 106 is provided between the MOS surface region 114 and the n-drift layer 100. The p-body region 107 has two regions, separated to the left and right, that function as an n-emitter region 108 for the IGBT section and as an n-source region for the MOSFET section. A gate electrode 112 is provided above the right end of the p-body region 107 and the right end of the right n-emitter region 108 via a gate oxide film 111. When a predetermined gate voltage is applied to the gate electrode 112 during operation, a channel 109 is formed. The same applies to the left end of the p-body region 107. The exposed surface of the p-body region 107 between the two n-emitter regions 108 (or between the n-source regions) functions as an ohmic contact 110 and is directly connected to the emitter main electrode 113 of the reverse-conducting IGBT. The n-emitter region 108 (or n-source region) is also directly connected to the emitter main electrode 113 of the reverse-conducting IGBT, but each gate electrode 112 is insulated from the emitter main electrode 113 via an insulating film 115. A large number of MOS surface regions with this configuration are gathered together to form a MOS surface region 114. Each n-emitter region 108 (or n-source region) is electrically connected via the emitter main electrode 113, and each gate electrode 112 is also electrically connected to the gate main electrode (not shown).

[0039] Furthermore, a buffer layer 104 is provided in contact with the back surface of the n-drift layer 100, extending from one main surface to the other main surface (back surface), and consisting of nSiC conductive paths 116, 116Y, and 118, and an insulating region 117. In addition, a p-collector layer 102 of the IGBT section, an ion-implanted collector region 117Z, and an n-short circuit region (which also serves as the drain region of the MOSFET section) 103 are provided in contact with the back surface of the n-buffer layer 104. The n-short circuit region 103 is in contact only with the conductive path 116Y corresponding to the comb-tooth assemblies at both ends of the cell and is provided in substantially the same shape. These are provided in contact with the collector main electrode 101 of the reverse-conducting IGBT. The p-collector layer 102 is provided in substantially the same shape as the conductive path 116 of the buffer layer, and the ion-implanted collector region 117Z is provided in substantially the same shape as the insulating region 117 of the buffer layer. All gate electrodes are connected and aggregated and connected to the gate main electrode (not shown) of the reverse-conducting IGBT.

[0040] Next, the operation leading to turn-on during forward bias of the reverse-conducting IGBT standard cell with the above configuration will be briefly described below. In FIG. 6, the main current paths a and b of the on-current of the MOSFET section during forward bias are schematically shown by dotted lines. That is, the current in the MOSFET section of the stripe structure flows through the route of emitter main electrode 113 → source region 108 → channel region 109 → drift layer 100 → conductive path 116 to 116Y in the buffer layer → n short-circuit region 103 → collector main electrode 101. Focusing on the IGBT section, the conductive path from 116 of the n comb-shaped buffer region 104 to 116Y via the comb teeth 118 is connected to the p collector 102 to form a pn junction and exists. When the voltage drop in the conductive path due to the current flowing through the above route exceeds the built-in voltage Vbi (about 2.7 V) of SiC, the injection of holes starts from the p collector 102 and eventually leads to the turn-on of the IGBT section.

[0041] Regarding the main structural factors of the standard cell in this Example 1, for example, the following values are selected. The impurity concentration and thickness of the n emitter region 108 are 5e19 cm -3 and 0.3 μm, the impurity concentration and thickness of the p body region are 1e18 cm -3 and 0.6 μm, the impurity concentration and thickness of the nCSL are 5e16 cm -3 and 0.3 μm, the impurity concentration and thickness of the n drift layer are 2 to 5e14 cm -3 and 150 μm, the impurity concentration and thickness of the n buffer layer are 1e17 cm -3 and 2 μm, the impurity concentration and thickness of the p collector layer are 4e18 cm -3 and 1 to 3 μm.

[0042] Next, the snapback phenomenon of this embodiment will be described. The generation mechanism of the snapback phenomenon during forward bias is almost the same as the mechanism disclosed in Patent No. 7385932 of the prior art documents by the present inventor and Non-Patent Document 3. Therefore, the general description will be omitted by referring to the above publication, and the description will be focused on the main part that expresses the features of the present invention. First, the analytical expressions of Vsb, Isb, and Rbuffer necessary for quantitative description in each embodiment will be

[0043] summarized and shown in

[0044] and an analysis example of Vsb and Rbuffer in Example 1 using these analytical expressions will be shown in

[0043] <Analytical Expressions of Vsb, Isb, and Rbuffer> FIG. 5 schematically shows the main current paths a and b of the on-current of the MOSFET part during forward bias. That is, the current of the stripe-structured MOSFET flows through the route of emitter main electrode → source region → channel region → drift layer → comb-axis part of the two comb-shaped conduction paths in the buffer layer → conduction path of the comb teeth → conduction path of the comb tooth collection part → n short-circuit region → collector main electrode. Focusing on the IGBT part, the n-comb-shaped buffer region 104 is connected to the p collector 102 to form a pn junction. When the voltage drop of the current flowing through the conduction path of the comb-shaped buffer region exceeds the built-in voltage Vbi 2.7V of SiC in the above route, the injection of holes starts from the p collector 102 and finally leads to the on-state of the IGBT part. The Vsb just before the on-state of the SiC reverse-conducting IGBT flowing through such a route can be approximated by Equation [3]. Vsb = Isb×Rch + Isb×Rdrift + Vbi [3] Here, Rch is the channel resistance of the MOS gate, Rdrift is the resistance of the drift layer, and Vbi is the built-in voltage of the collector junction. In a high-voltage reverse-conducting IGBT, Rch is significantly smaller than Rdrift and can be ignored. Focusing on current path a, when the voltage drop caused by Isb flowing through the buffer layer reaches Vbi at the SiC collector junction, hole injection from the SiC reverse-conducting IGBT collector junction to the drift layer begins, and the IGBT starts to turn on. Therefore, Isb can be approximated by equation [4], where Rbuffer is the lateral resistance in the n buffer layer conductive path in current path a. Isb = Vbi / Rbuffer [4] Here, Rbuffer is the resistance of the n buffer layer conductive path on the p collector creepage surface from the center of the p collector (Wp / 2) to the collector electrode, but n + The short-circuit region is highly concentrated and thin, so its resistance is ignored. Since ISB flows through the buffer layer portion of the junction formed between the p-collector layer and the n-buffer layer conduction path that is not depleted by Vbi, Rbuffer can be approximated by equation [5]. Rbuffer=ρbuffer x (Wp / 2) / {(Tbuffer-Tdep-buffer) x Lcell} [5] Here, ρbuffer is the resistivity of the n-buffer layer conduction path, Tbuffer is its thickness, and Lcell is its length in the direction perpendicular to the plane of the paper (6 mm). Tdep-buffer is the depletion layer thickness in the n-buffer layer when Vbi is applied at 2.7 V, and can be approximated by equation [6]. Tdep-buffer={(2ε / q)x(Na / Nd)+(Vbi / (Nd+Na))} 0.5 [6] Na and Nd are the impurity concentrations in the p-collector layer and n-buffer layer conductive paths, respectively. Using the Rbuffer obtained from equation [5], Isb can be calculated from equation [4], and Vsb can be calculated from equation [3].

[0044] Figure 4 shows a plan view illustrating the configuration of the double-toothed comb-type buffer layer 104 of a SiC reverse-conducting IGBT cell. Focusing on the configuration of the buffer layer for one cell, it is in the shape of a double-toothed comb. That is, there is a conductive path 116 in the center that corresponds to the axis of the double-toothed comb (hereinafter referred to as the comb axis), made of nSiC, and five conductive paths corresponding to the comb teeth, made of nSiC semiconductors, are connected to each side, with insulating regions 117 between the comb teeth. In this specification, a buffer layer of this shape is defined as a double-toothed comb-type buffer layer, and this name will be used below. If we let La be the length of the SiC semiconductor region constituting the comb teeth 116, Lb be the length of the insulating region 117 constituting the space between the comb teeth, and L be the length of the cell, and if we set the width of the insulating region 117-2 at the upper and lower ends of the cell to 0.5 Lb each, L=N(La+Lb) [7] Therefore, in the case of Figure 4 for explaining the principle, N is 5. The cell length Lcell is 6 mm, so (La + Lb) is 1200 μm. If La = Lb is set, each becomes 600 μm. The 6 mm active region in Figure 2 is composed of 4 cells, so the cell width is 1500 μm. If the width of the p collector is Wp, the width of both teeth of the comb, i.e., Wp / 2, is 730 μm considering the width of the comb shaft and the comb tooth assembly, which is 20 μm. The length La of the comb teeth is 600 μm, so Rbuffer can be calculated from equation [5] and is 1795 Ω. Since there are 5 comb teeth connected in parallel, the total resistance RbufferT is 359 Ω. Therefore, Isb is calculated to be 7.5 mA from equation [4] and Vsb is calculated to be 17.8 V from equation [3]. By setting the cell width (=Wp+Wn) to 3040 μm, Vsb can be suppressed to 10.0 V. In conventional examples where the buffer layer is simply a stripe structure, in order to suppress Vsb to 10.0V, the impurity concentration of the conductive path in the buffer layer must be the same 1x19 17 cm -3 In this case, the cell width needs to be 6110 μm, slightly exceeding the active region width. Therefore, the effect of using the double-tooth comb buffer layer type reverse-conducting IGBT standard cell of this embodiment is clear, and the cell can be miniaturized by approximately half. If (La+Lb) is kept constant at, for example, 1200 μm, the resistance of the comb teeth can be increased as La is made smaller than Lb, allowing for further miniaturization of the cell while maintaining the same 10.0 V Vsb.

[0045] Next, the main process flow (5a) to (5f) for fabricating the double-tooth comb buffer layer type reverse conductive IGBT of this embodiment will be briefly explained below with reference to Figure 5. (5a): First, a 200 μm thick n-type SiC off-angle single crystal wafer 50 made of 4-inch thick 4-layer hexagonal n-type SiC Drift layer 51 To promote epitaxial growth. Next, the n buffer layer 52 is formed by epitaxial growth. A thickness of approximately 1 to 2 μm is preferred. Then, the p collector layer 53 is formed by epitaxial growth. A thickness of approximately 2 μm is preferred.

[0046] (5b): Subsequently, the inter-tooth insulating region 117 shown in Figures 3 and 4 is formed. Several methods, including <Method a>, <Method b>, and <Method c>, were devised and investigated for this formation. Ultimately, the choice will be made considering the device structure and process economics, but in most embodiments, including this embodiment 1, both <Method a> and <Method b> are considered for comparison. In any case, from the p-collector side, through the p-collector 53 and across the n-buffer layer 52 completely Drift layer 51 A comb tooth insulating region 54 (same as 117) is formed to reach the following: The comb teeth of the desired shape are formed, i.e., a conductive path 118 (same as 55) is formed from the comb axis 116 in Figure 4 to the short-circuit region 116Y. That is crucial. Note that <Method c> is Vanadium-doped epitaxial layer There are many considerations regarding the maintenance of semi-insulating properties at high temperatures, and this patent only applies it to Example 8. <Method a> This method involves adapting and improving the gate formation process for high-voltage SiC trench-gate or U-groove-gate MOSFETs for the formation of inter-comb-tooth insulating regions. This embodiment differs from the gate described above in that the trench width is wider and the trench depth is somewhat deeper, and modifications and improvements may be necessary in some cases. For example, to accommodate a wide insulating area, methods such as forming multiple trenches or U-grooves close together, adjacent to each other, and in parallel may be employed. Furthermore, in addition to conventional electric field relaxation techniques for trench corners, electric field relaxation techniques to cope with high electric fields may also be implemented. In the case of <Method a>, for example, the p-collector and n-buffer layers in the parts forming the insulating region are removed by dry etching, and then an insulating oxide film is formed and coated onto the exposed trench etch wall. Furthermore, the depressions within the oxide film are filled with polycrystalline silicon or similar material, and then flattened and filled by polishing. Since it is a reverse-conducting IGBT, the voltage applied between the p-collector and n-buffer is low, and the risk of performance degradation due to this filling is relatively small. <Method b> This method involves modifying technologies such as SIMOX for high-voltage applications and adapting them for the formation of insulating regions between comb teeth. In this embodiment, insulating or semi-insulating ions such as oxygen ions and vanadium ions are used. It is necessary to implant selected ions to a depth of approximately 3-5 μm so that they pass through the p-collector layer 53, through the n-buffer layer 52, and completely reach the drift layer 51. Therefore, it is essential to implant ions at high voltage, and it is necessary to use a 60 MeV class high-voltage ion implantation device equipped with a 15 MeV class tandem accelerator that has a track record of implanting ions to depths of 10 μm or more. Furthermore, it is essential to use a selective ion implantation mask that can withstand such high-voltage selective ion implantation, and to apply annealing technology to eliminate implantation damage such as defects that occur during implantation. In the case of the above <method b>, The p collector portion (117z in Figure 3) facing the insulating region 117 is For example, there are concerns that the damage caused by oxygen ion implantation will be significant and that advanced annealing techniques will be required. The collector 117z in this section does not need to function as a perfect collector capable of good carrier injection, like the collector section 102 below the conductive path 55 (corresponding to conductive paths 118 and 116 in Figure 4). It only needs to function as a material with low conductivity, and since it conducts in reverse, the applied voltage is also small, so it is unlikely to impair the characteristics of the reverse-conducting IGBT. <Method c> this is, This method involves epitaxially growing an n-type drift layer 51 on the aforementioned n-type SiC off-angle single crystal wafer 50, followed by epitaxial growth of a vanadium-doped semi-insulating layer, and then forming conductive paths 55 such as comb teeth or comb shafts of a desired shape by selective ion implantation of nitrogen. Naturally, when selective ion implantation of nitrogen occurs The insulating region between the comb teeth is covered by a mask and remains a semi-insulating region. This method has advantages such as requiring fewer steps, being suitable for high-voltage ion implantation equipment with relatively low implantation energy, and minimizing implantation damage. Furthermore, the subsequent epitaxial growth layer of the p-collector and the vanadium-doped epitaxial growth layer are Another advantage is that there is almost no mismatch in the crystal structure, allowing for the formation of high-quality, excellent collectors. Below, we will discuss Example 1, which uses method b, a relatively simple process, following (5b). Describe the continuation process flow (5c) to (5e).

[0047] (5c): Next, a mask is formed for selective ion implantation to form the n short-circuit region 56, Nitrogen-selective ion implantation is performed at varying concentrations. Then, the wafer is inverted vertically, and the n-type drift layer is placed on the epitaxial growth surface. The n-type single crystal substrate is separated by cutting parallel to the dotted line in Figure (5b), and then the n-type drift layer is separated. The cut surface is polished, and for example, an n-drift layer 51 and 1 with a thickness of approximately 150 μm that matches the operating pressure. SiC wafers are composed of an n-buffer layer with a thickness of ~2 μm and a p-collector layer with a thickness of approximately 2 μm. -Finish it to a perfect score. (5d) Next, an n-type current density increasing layer C is placed on the n-type drift layer of this SiC wafer. Forms the EL58. (5e) Next, using fabrication techniques for high-voltage SiC MOSFETs and high-voltage Si power ICs, a MOS surface region 59 excluding the emitter main electrode is formed on the n-type current density increasing layer CEL 58. Then, the emitter main electrode 60 and gate main electrode (not shown) are formed, and further, the collector main electrode 61 is formed and diced to complete the double-toothed comb buffer layer type reverse conducting IGBT element.

[0048] Next, the operation and typical characteristics of this embodiment will be described. The aforementioned double-toothed comb buffer layer type reverse-conducting IGBT element is die-bonded to a TO-type package, multiple 100 μm diameter Al (aluminum) wires for connection are wire-bonded onto the emitter main electrode 113, Al wire bonding is then performed on the gate main electrode, and finally the chip and Al wires are coated with Nanotech Resin, a highly heat-resistant resin for protection, to complete the reverse-conducting IGBT semiconductor device, after which an operational test is performed.

[0049] The breakdown voltage of the collector and emitter main electrodes, measured with the emitter and gate main electrodes short-circuited, is approximately 16.6kV, which is good. It exhibits good forward blocking characteristics, and the leakage current at 12kV applied at room temperature is typically 5.5 x 10⁻¹⁰. -5 A / cm 2 It is to that extent.

[0050] When a gate voltage above the threshold voltage is applied to the gate main electrode, and then a voltage is applied between the collector main electrode 101 and the emitter main electrode 113 such that the potential of the collector main electrode is higher than the potential of the emitter main electrode, a so-called forward state, an on-current begins to flow from around zero V, and as this applied voltage is increased, the on-current increases almost linearly. This is because the MOSFET section is turned on. If the applied voltage is further increased, the on-resistance per unit area at around 5V is approximately 220 mΩ·cm. 2This results in an output current of approximately 8A. This is sufficient current to suppress the on-voltage degradation specific to SiC in the TEDREC method described later.

[0051] 80A / cm when reverse conduction IGBT is ON 2 The on-voltage is 5.4V, indicating good on-characteristics. Furthermore, the turn-on time is approximately 280ns ​​and the turn-off time is approximately 550ns, demonstrating good high-speed operation. These results are attributed to the miniaturization of the cell by using a double-tooth comb buffer layer as described in

[0041] . In Figure 4, the length of both teeth of the comb is made to roughly match the length of the cell, but by dividing it into equal parts and connecting multiple cells in the length direction, the degree of freedom in manufacturing and design can be increased, making it easier and more flexible.

[0052] Furthermore, it was a concern that stacking faults within the element could cause an increase in the internal resistance of the SiC-IGBT during energization, leading to so-called on-voltage degradation and an increase in on-voltage ΔVon, significantly impairing reliability. It was also a concern that high-order snapbacks with a large Isb associated with the snapback phenomenon would accelerate the above-mentioned on-voltage degradation. Moreover, it was a concern that the ΔVon due to on-voltage degradation would be superimposed on the Vsb associated with the snapback phenomenon, leading to malfunctions due to increased noise voltage generated during operation, imbalances in the switching operation balance of IGBT modules connected in parallel with multiple elements, and other operational problems or element damage. However, the Vsb reduction and TEDREC method application in this embodiment proved effective, and even in stress tests such as 1000-hour energization tests, the fluctuation in on-voltage remained below 0.2V, and no significant adverse effects on reliability were found. This TEDREC operation method is disclosed by the inventor in Patent No. 5835679.

[0053] As described above, the double-toothed comb buffer layer type reverse-conducting IGBT semiconductor device consisting of a striped SiC reverse-conducting IGBT cell as in this embodiment 1, unlike conventional simple striped buffer layer types, can reduce Vsb to a practically acceptable level of 10V even with a high buffer layer impurity concentration suitable for ultra-high voltage resistance, and in that case the cell area can be halved compared to conventional simple striped buffer type. By making the comb tooth length La smaller than the comb tooth spacing Lb, the SB suppression effect can be achieved with an even smaller cell area, but this tends to increase on-resistance and turn-off time, so a balance needs to be struck. [Examples]

[0054] A second embodiment of the present invention is a 15kV class double-tooth comb buffer layer type reverse conducting IGBT with insulating protrusions made of 4H-SiC. Compared to the first embodiment, the chip structure and element components are almost the same, except that insulating protrusions are provided within the comb teeth of the buffer layer connected to the inter-tooth insulating region in order to suppress the snapback phenomenon in an even smaller cell area. Furthermore, the method described in

[0046] <Method b> is used to form the inter-tooth insulating region and insulating protrusions.

[0055] Figure 6 is a schematic diagram illustrating the configuration of the buffer layer 104 in this embodiment 2, and Figure 7 is a cross-sectional view between CDs corresponding to the dotted line portion passing through the insulating projection 119 in Figure 6. The comb-tooth portion 118 made of SiC semiconductor in Figure 6 is provided with insulating protrusions 119 made of rectangular insulators. Two are provided on each comb tooth, and since there are 10 comb teeth per 1 / 2 cell, there are a total of 20 insulating protrusions 119 in one cell. The width of the insulating protrusions 119 is 10 μm, and each insulating protrusion 119 is provided 10 μm away from the inter-comb tooth insulating regions 117-1 and 117-2 that are opposite the connected inter-comb tooth insulating region, and the spacing between each insulating protrusion 119 is set to 10 μm. As a result, a conductive path with a width of 10 μm is formed on the comb teeth 118. Compared to the resistance of a single comb tooth in Example 1, the conductive path resistance is significantly larger because the length and width of this conductive path are longer and narrower. In this specification, this buffer layer is defined as a double-tooth comb buffer layer with insulating protrusions, and this designation will be used below. This double-toothed comb buffer layer with insulating protrusions allows for arbitrary setting of the resistance of the comb-shaped buffer layer by adjusting the number and shape of the protrusions. This enables arbitrary setting of Isb and consequently Vsb, thereby eliminating the snapback phenomenon or suppressing it to a predetermined acceptable level.

[0056] In this actual embodiment 2, unlike the explanatory plan view of the configuration in Figure 6, eight insulating protrusions 119 are provided per comb tooth to further increase the snapback phenomenon suppression effect, so there are 80 insulating protrusions 119 in one cell. Also, since there are eight insulating protrusions per comb tooth, the total width of one comb tooth is 170 μm, so the cell width is 380 μm. On the other hand, the conductive path length per comb tooth is 4290 μm, and the conductive path resistance is approximately 631 kΩtp. Since five comb teeth are connected in parallel in half a cell, the total conductive path resistance RbufferT of the buffer layer for half a cell is approximately 125 kΩ. Analysis of these results

[0044] shows that the voltage drop due to the current flowing through the conductive path of the comb-shaped buffer region with insulating protrusions exceeds the SiC built-in voltage Vbi of 2.7 V, and the current Isb when hole injection from the p collector 102 begins is approximately 21 μA, which is significantly smaller. Therefore, the voltage drop in the drift region is small at 0.04V, and the Vsb just before the IGBT turns on can be reduced to approximately 2.74V.

[0057] For example, based on the analysis method disclosed in prior art document 2

[0043] , the buffer layer of a conventional stripe-structured cell 15kV class reverse-conducting IGBT is 1x10 17 cm ―3 In the first case, to suppress the snapback phenomenon to a practically acceptable level of Vsb of 10V, the width Wp of the p collector had to be 6110μm. However, in this embodiment 2, even with a Wp of 380μm, Vsb can be suppressed to 2.74V. After snapback, the on-current of the IGBT flows, so the on-voltage is 3.7V for a 15kV class ultra-high voltage IGBT, for example, as shown in Figure 1. However, since the Vsb in this embodiment is smaller at approximately 2.74V, the snapback phenomenon is eliminated. In Example 1, it was difficult to eliminate Vsb, and even to achieve a Vsb within the acceptable range of 10V, the Wp had to be set to 3040μm. However, in Example 2, the snapback phenomenon can be eliminated with a significantly smaller cell width of 380μm, which is a tremendous advantage.

[0058] Next, the operation and typical characteristics of the reverse-conducting IGBT in this embodiment 2 will be described below. After mounting the reverse-conducting IGBT element in a TO-type package in the same manner as in Example 1 to create a reverse-conducting IGBT semiconductor device, an operational test was performed. The breakdown voltage between the collector main electrode 101 and the emitter main electrode 113, measured with the emitter main electrode and gate main electrode short-circuited, was approximately 16.2kV, which is good. When a forward voltage is applied between the collector main electrode 101 and the emitter main electrode 113 without applying a gate voltage, a leakage current flows, but good forward blocking characteristics are observed, and the leakage current is typically 4 x 10⁻¹⁰. -5 A / cm 2 It is of a good degree.

[0059] When a gate voltage above the threshold voltage is applied to the gate main electrode, and then a voltage is applied to bring it into the so-called forward state, an on-current begins to flow from around zero V and increases almost linearly. This is because the MOSFET section has turned on. If the applied voltage is further increased, the current begins to increase sharply from around 2.7 V, which corresponds to the built-in voltage. This is because the IGBT section also turns on, and its on-current begins to flow in a superimposed manner. The on-resistance per unit area below the built-in voltage is approximately 185 mΩ·cm. 2 Therefore, even with a forward voltage below the built-in voltage, a considerable output current can be obtained, which can be used for countermeasures against on-voltage degradation, as described later, and thus high performance can be achieved.

[0060] On the other hand, the differential on-resistance per unit area of ​​an IGBT above its built-in voltage is approximately 32 mΩ·cm. 2 And, 80 A / cm 2 The on-voltage is 5.5V, indicating good on-characteristics. Furthermore, the turn-on time is approximately 310ns and the turn-off time is approximately 570ns, demonstrating high-speed operation. Furthermore, by applying the aforementioned TEDREC operating method, even during long-term energization tests, on-voltage degradation and rapid on-voltage degradation due to higher-order snapback phenomena remained below 0.2V, and no significant adverse effects on reliability were found, indicating good performance.

[0061] As described above, despite having an ultra-high voltage rating of 15kV, this embodiment 2 utilizes a double-toothed comb buffer layer type SiC reverse-conducting IGBT structure with insulating protrusions, which effectively eliminates the snapback phenomenon with a significantly smaller cell area, achieving high noise immunity and high cost-effectiveness. Furthermore, because the cell area can be significantly reduced, residual carriers can be discharged quickly during turn-off, shortening the turn-off time and enabling high-speed operation, while also significantly reducing turn-off losses. [Examples]

[0062] A third embodiment of the present invention is a 15kV class double-tooth comb buffer layer type reverse conducting IGBT made of 4H-SiC, which improves on-characteristics and switching characteristics while maintaining the snapback phenomenon suppression effect compared to the first and second embodiments. Except for reducing the comb tooth length La and the length Lb of the inter-comb tooth insulation region, the element components, dimensions, and impurity concentration are the same as those of Embodiment 2 described in

[0038] . In the first and second embodiments, the on-voltage at the same current is higher and the switching time is longer compared to conventional reverse-conducting IGBTs with a stripe structure. After investigating the cause, it was concluded that this is due to the comb-tooth buffer layer, a feature of the present invention provided to eliminate or significantly suppress the snapback phenomenon, being composed of an insulating region in addition to the wide-bandgap semiconductor region that forms the conductive path. In other words, when the comb-tooth buffer layer type reverse-conducting IGBT of the present invention is turned on, current is passed through the conductive path within the comb teeth, injecting holes from the p-collector below the conductive path, and first turning on the IGBT portion facing the p-collector and energizing it. Then the on-current region is expanded to the drain region on the insulating region close to the on-current energizing region, and subsequently expanded to the drain region on the insulating region a little further away, and this operation is repeated sequentially to turn on the entire cell. Consequently, in the drain region on the insulating region, the current density gradually decreases as it moves away from the p-collector region, so the on-voltage increases when compared at the same current level.

[0063] Furthermore, during turn-off, carriers are discharged sequentially from the parts closest to the short-circuit region and the parts of the conductive path connected to the short-circuit region that are close to the short-circuit region. Finally, almost all residual carriers in the insulating region, which is far from the short-circuit region and the conductive path, are discharged, completing the turn-off operation. For this reason, compared to conventional reverse-conducting IGBTs, it was considered that the presence of the insulating region slows down the removal of carriers in the insulating region, which is further away from the short-circuit region and the conductive path, resulting in a longer turn-off time. In Example 2, there are additional insulating protrusions, but since their width is small (approximately 10 μm), it is considered that they have little effect on the above operating mechanism. Therefore, in this embodiment 3, measures were taken by reducing the length Lb of the insulating region so that the distance within the insulating region furthest from the short-circuit region and the conductive path connected thereto is shortened. In addition, the width La of the comb teeth was also reduced to the same length as the insulating region.

[0064] Specifically, in Examples 1 and 2, the length Lb of the insulating region was 600 μm, but this was reduced to 1 / 6, or 100 μm, and La was also reduced to 100 μm. However, the other chip structures and element components were almost the same. As a result, the maximum distance from the conductive paths on both sides adjacent to the insulating region is 300 μm in Examples 1 and 2, which is large, but in this embodiment it is 50 μm, which is 1 / 6 of that. Although it varies depending on the carrier lifetime, in the ultra-high voltage IGBT of this embodiment, which also incorporates known methods for suppressing lifetime reduction and increasing lifetime, the current expansion during on-on and the discharge of carriers from the insulating region during turn-off are relatively rapid up to about 50 μm, and it is expected that the on-voltage and turn-off time can be reduced.

[0065] On the other hand, regarding the snapback phenomenon, in this actual embodiment 3, unlike the explanatory plan view of the configuration in Figure 6, eight insulating protrusions 119 are provided per comb tooth, similar to embodiment 2, in order to further increase the effect of suppressing the snapback phenomenon. Therefore, the total width of the comb teeth is 170 μm, and the cell width Wp is 380 μm. Consequently, the conductive path length per comb tooth is 790 μm, and the resistance is approximately 540 kΩ. Since 30 comb teeth are connected in parallel per 1 / 2 cell, the total conductive path resistance of the buffer layer for 1 / 2 cell is approximately 8.5 kΩ.

[0066] Based on the analysis method in

[0049] , the voltage drop due to the current Isb, i.e., the current flowing through the conductive path of the comb-shaped buffer region, exceeds the SiC's built-in voltage Vbi of 2.7V, and the current Isb when hole injection from the p collector begins is approximately 320μA. As a result, the voltage drop in the drift region is small at 0.6V, and Vsb just before the IGBT section turns on can be reduced to approximately 3.3V. Therefore, when the switch is turned on, it simply switches from the Vsb of 3.3V just before turning on to the on voltage of around 3.7V immediately after turning on, as shown in Figure 1, and the problematic snapback phenomenon is eliminated and does not occur. For example, based on the analysis method disclosed in prior art document 2

[0040] , in a conventional stripe structure cell 15kV class reverse conduction IGBT, the buffer layer is 1x10 17 cm ―3 In the case of a thickness of 1 μm, even to suppress the snapback phenomenon to a practically acceptable level of 10 Vsb, the width Wp of the p-collector had to be 6110 μm. However, in this embodiment 3, the width Wp of the p-collector is reduced to 380 μm, and the snapback phenomenon can be eliminated even with a significant reduction in cell area, which is a major advantage.

[0067] Next, the operation and typical characteristics of the reverse-conducting IGBT in this embodiment 3 will be described below. After mounting the reverse-conducting IGBT element in a TO-type package similar to that of Example 1 to create a reverse-conducting IGBT semiconductor device, an operational test was performed. The breakdown voltage of the collector and emitter electrodes, measured with the emitter and gate electrodes short-circuited, was approximately 16.4kV, which is good. When a forward voltage is applied between the collector main electrode 101 and the emitter main electrode 113 without applying a gate voltage, a leakage current flows, but good forward blocking characteristics are observed, and the leakage current is typically 1.5 x 10⁻¹⁰ at room temperature. -5 A / cm 2 It is to that extent.

[0068] Also, 80 A / cm 2 The on-voltage is 4.9V, indicating good on-characteristics. Furthermore, the turn-on time is approximately 240ns and the turn-off time is approximately 480ns, demonstrating good high-speed operation. Furthermore, even in long-term energization tests using the aforementioned TEDREC operating method, no on-voltage degradation due to stacking faults or rapid on-voltage degradation due to higher-order snapback phenomena occurred, and the on-voltage change remained below 0.2V. No significant adverse effects on reliability were found, indicating good performance.

[0069] As described above, in this embodiment 3, the double-tooth comb buffer layer type SiC reverse conducting IGBT structure with insulating protrusions is effective in eliminating the snapback phenomenon with a small cell area, and further reducing losses is achieved by reducing the on-voltage and turn-off time through the reduction of the comb tooth length La and the length Lb of the inter-tooth insulating region. [Examples]

[0070] A fourth embodiment of the present invention is a 25kV class reverse-conducting IGBT with insulating protrusions and a double-toothed comb buffer layer made of 4H-SiC. Compared to the first to third embodiments, it has a significantly increased voltage rating, intended for use in power businesses and other applications, and aims to suppress the snapback phenomenon of the reverse-conducting IGBT. The element configuration is the same as in Example 2, except that the dimensions and impurity concentrations of each element component were set to accommodate 25kV. Examples of the main element components are shown below. The concentration and thickness of the non-standard material in the n-emitter region 108 are 5e19cm². -3 And the concentration and thickness of the non-standard material in the 0.3 μm, p-body region is 1 e 18 cm². -3 And 0.6 μm, the concentration and thickness of the non-standard substance in nCEL is 4e16 cm -3 The non-standard concentration and thickness of the 0.4 μm, n-drift layer are 2 e 14 cm². -3 The non-standard concentration and thickness of the 250 μm, n buffer layer are 1 e 17 cm². -3 The non-standard concentration and thickness of the p-collector layer are 2 μm and 4 e 18 cm². -3 and 2 μm.

[0071] Furthermore, the length La of the comb teeth and the length Lb of the insulating region are both 600 μm, and the cell width is 1020 μm. There are 20 insulating protrusions provided within each comb tooth to form a conductive path, with a conductive path length of 11600 μm and a width of 10 μm. Performing the analysis described in

[0043] , the total resistance RbufferT of the five parallel n buffer layer conductive paths is 342kΩ, Isb is 7.9μA, and Vsb is approximately 2.76V. As a result, the voltage immediately before the 25kV class reverse conduction IGBT turns on is 2.7V, which is smaller than the on-voltage immediately after turning on, which is approximately 3.7V as shown in Figure 1, so the snapback phenomenon can be almost completely eliminated. The reason we were able to reduce Vsb so much is that by providing as many as 20 insulating protrusions on the comb teeth, we were able to dramatically increase the conductive path length and reduce Isb, which in turn significantly reduced the voltage drop within the drift layer for a 25kV withstand voltage.

[0072] Typical characteristics of the reverse-conducting IGBT in this embodiment 4 include a withstand voltage of 26.2kV at room temperature and a current of 50A / cm² when energized. 2 The on-voltage is approximately 5.2V. As described above, according to this embodiment, by employing a double-toothed comb buffer layer type SiC reverse-conducting IGBT structure with insulating protrusions, the snapback phenomenon can be almost completely eliminated despite the ultra-high voltage of 25kV class. [Examples]

[0073] A fifth embodiment of the present invention is a reverse-conducting IGBT with a double-toothed comb buffer layer and protrusions, made of Si, with a proven track record in applications such as Si-GTOs for power generation. This embodiment targets a reverse-conducting Si-IGBT with a proven 8kV withstand voltage, aiming to suppress the snapback phenomenon with a small cell area, achieve high speed and low loss, and significantly improve economic efficiency by enabling lower wafer costs and larger diameters compared to SiC. The chip configuration is almost the same as in Figure 2, except for the chip size, and the buffer layer is a double-toothed comb buffer layer with insulating protrusions, similar to that in Example 2. Furthermore, the process for forming the insulating region and insulating protrusions uses Method b described in

[0046] . The following values, for example, have been selected as major structural factors. The concentration and thickness of the non-standard material in the n-emitter region 808 are 5e19cm². -3The non-standard concentration and thickness of the 10 μm, p-body region 807 are 1 e 18 cm². -3 The non-standard concentration and thickness of the 12 μm, n-drift layer 800 are 7 e 12 cm -3 The non-standard concentration and thickness of the semiconductor region of the 650 μm n buffer layer 804 are 1 e 17 cm². -3 The non-standard concentration and thickness of the 1 μm p-collector layer 802 are 3 e 18 cm². -3 and 2 μm.

[0074] Figure 6 is a schematic plan view illustrating the configuration of the buffer layer 104 in this embodiment 5, and Figure 7 is a cross-sectional view between CDs corresponding to the dotted line portion passing through the insulating protrusions 119 in Figure 6. Each comb-tooth portion 118 in Figure 6 is provided with two insulating protrusions 119 made of rectangular insulators, In this actual embodiment 5, unlike the explanatory plan view in Figure 6, 16 insulating protrusions 119 are provided for each comb tooth to further increase the snapback phenomenon suppression effect (not shown in the diagram for simplicity). Therefore, the total width of the comb teeth is 330 μm, the cell width Wp is 700 μm, the conductive path length per comb tooth is 10380 μm, and the resistance is approximately 1.22 MΩ. Since 5 comb teeth are connected in parallel for 1 / 2 cell, the total conductive path resistance RbufferT of the buffer layer for 1 / 2 cell is approximately 245 kΩ. Therefore, when the analysis described in

[0043] is performed with the case of a Si reverse-conducting IGBT, the voltage drop due to the current Isb, i.e., the current flowing through the conductive path of the comb-shaped buffer region, exceeds the Si built-in voltage Vbi of 0.7V, and the current Isb when hole injection from the p collector 102 begins becomes significantly smaller, to about 2.9μA. As a result, the voltage drop in the drift region is small at 0.5V, and Vsb when the Si-IGBT turns on can be reduced to about 1.20V. After snapback, the Si-IGBT on-current flows, so the on-voltage is greater than 0.7V in the case of an 8kV Si-IGBT. Therefore, the amount by which Vsb exceeds the on-voltage is 0.5V or less, and the snapback phenomenon is almost eliminated.

[0075] Next, the operation and typical characteristics of the reverse-conducting Si-IGBT of this embodiment 5 will be described below. After mounting the reverse-conducting IGBT element in a TO-type package similar to that of Example 1 to create a reverse-conducting IGBT semiconductor device, an operational test was performed. The breakdown voltage of the collector and emitter electrodes, measured with the emitter and gate electrodes short-circuited, was approximately 8.9kV, which is good. When a forward voltage is applied between the collector main electrode 101 and the emitter main electrode 113 without applying a gate voltage, a leakage current flows, but good forward blocking characteristics are observed, and the leakage current is typically 1 x 10⁻¹⁶ at room temperature. -4 A / cm 2 It is of good quality.

[0076] IGBT 50A / cm 2 The on-voltage when powered on is 6.1V. Furthermore, the turn-on time is approximately 560ns and the turn-off time is approximately 950ns, achieving high-speed operation. In the case of Si-IGBTs, on-voltage degradation due to stacking faults does not occur, so the TEDREC operation method described above can be omitted. On the other hand, since the first-order snapback phenomenon is almost eliminated, rapid on-voltage degradation due to higher-order snapback phenomena does not occur, and no adverse effects on reliability were found, which is good.

[0077] As described above, in this embodiment 5, although the 8kV class reverse-conducting Si-IGBT was used, which is different from the SiC-reverse-conducting IGBTs of the first to third, the snapback phenomenon can be almost completely eliminated with a small cell area of ​​700 μm cell width Wp despite the 8kV withstand voltage, achieving high noise performance and high cost-effectiveness. In addition, in addition to the reduction in losses due to the increased switching speed resulting from the reverse-conducting IGBT, the wafer can be made cheaper and larger in diameter compared to SiC, resulting in a significant improvement in cost-effectiveness. [Examples]

[0078] The sixth embodiment of the present invention is an 8kV class honeycomb buffer layer type reverse conducting IGBT with insulating protrusions made of 4H-SiC. The main difference from the first to fifth embodiments is that the cells in the active region have a honeycomb structure and a trench gate structure. This allows for a significant reduction in cell size, greatly improving the loss reduction effect and cost savings through reduced chip area.

[0079] Figures 8a and 8b are explanatory cross-sectional views and plan views of the buffer layer 804, respectively, with Figure 8a being a cross-sectional view between E and F corresponding to the dotted line portion passing through both the semiconductor region 818-1 and the insulating region 817-3, which include the insulating protrusion 819 in Figure 8b. In Figure 8b, the semiconductor regions 818-1 to 818-3, which are made of SiC semiconductor material, are provided with rectangular insulating protrusions 819 made of an insulator. Each triangular semiconductor region 818 is provided with five insulating protrusions 819, and since there are three triangular semiconductor regions 818 per cell, there are a total of 15 insulating protrusions 819 in one cell. Each insulating protrusion 819 has a width of 10 μm. Focusing on the triangular semiconductor region 818-1, each insulating protrusion 819 is provided at an average distance of 10 μm from the adjacent insulator regions 817-1 and 817-2, and the spacing between the five insulating protrusions 819 is set to 10 μm. As a result, in the triangular semiconductor region 818, a conductive path with a width of 10 μm is formed between the buffer layer 816 facing the trench gate 820 and the buffer layer 816Y on the short-circuit region 803, passing through the insulating protrusions 819 and the adjacent insulator regions 817-1 and 817-2. Therefore, the ON current of the MOSFET section splits from the conductive path 816 in the center of the cell, opposite the trench gate on the main surface side, into the triangular semiconductor regions 818-1 to 818-3, and flows into the short-circuit region 816Y.

[0080] Incidentally, compared to the resistance of a simple triangular shape without insulating protrusions 819, the conductive path of this embodiment is longer and narrower, so the conductive path resistance can be significantly increased. In this specification, this buffer layer is defined as a honeycomb buffer layer with insulating protrusions, and will be described by this designation below. In the case of this honeycomb buffer layer with insulating protrusions, the resistance of the conductive path can be arbitrarily set by setting the number and shape of insulating protrusions 819, and a feature is that Isb and Vsb can be arbitrarily set to eliminate or suppress the snapback phenomenon to an acceptable range. However, from the point of mitigating the electric field at the trench corner of the trench gate structure, it is preferable to apply this to elements with relatively low withstand voltage among ultra-high withstand voltage reverse conducting elements.

[0081] In this actual embodiment 6, unlike Figure 8b, ten insulating protrusions are provided in one triangular semiconductor region to increase the snapback phenomenon suppression effect, resulting in a cell width of 440 μm. The width of the buffer layer 816 facing the trench gate 820 is 20 μm, and the width of the buffer layer 816Y on the short-circuit region 803 is also 20 μm. Approximately 180 cells are provided within a 6 mm square active region. For example, the following values ​​are selected as the main structural factors. The concentration and thickness of the non-standard material in the n-emitter region 808 are 5e19cm². -3 The non-standard concentration and thickness of the 0.3 μm, p-body region 807 are 1 e 18 cm². -3 And the concentration and thickness of the non-standard material in nCEL806 are 0.6 μm and 5 e 16 cm. -3 The non-standard concentration and thickness of the 0.3 μm, n-drift layer 800 are 7 e 14 cm². -3 The non-standard concentration and thickness of the semiconductor region 818 of the 80 μm n buffer layer 804 are 1 e 17 cm². -3 The non-standard concentration and thickness of the 1 μm p-collector layer 802 are 3 e 18 cm². -3 and 2 μm. Performing the same analysis as described in

[0043] , Vsb is 2.8V, which is smaller than the on-voltage Von of approximately 3.7V immediately after the reverse-conducting IGBT is turned on, and therefore the snackback phenomenon has been eliminated.

[0082] Next, the operation and typical characteristics of the honeycomb buffer layer type SiC reverse conducting IGBT with insulating protrusions of this embodiment 6 will be described below. After mounting the reverse-conducting IGBT element in a TO-type package similar to that of Example 1 to create a reverse-conducting IGBT semiconductor device, an operational test is performed. The breakdown voltage between the collector main electrode 801 and the emitter main electrode 807, measured with the emitter main electrode 807 and the gate main electrode (not shown) short-circuited, is approximately 8.5kV, which is good. The leakage current is typically 3 x 10⁻¹⁰ at room temperature and 7kV. -5 A / cm 2 It is of a good degree. Current density 80A / cm 2 The on-voltage is 4.5V, indicating good on-characteristics. Furthermore, the turn-on time is approximately 220 ns and the turn-off time is approximately 450 ns, enabling high-speed operation. Furthermore, in each triangular insulating region, for example, by dividing it equally into three triangles with the center as the vertex, making the two adjacent triangles touching the semiconductor region semiconductor regions, and leaving only the middle triangle as an insulating region, the area of ​​the insulating region is substantially reduced, resulting in a current density of 80 A / cm². 2 The on-voltage can be reduced to approximately 4.3V, the turn-on time to approximately 205ns, and the turn-off time to approximately 410ns. Furthermore, in long-term operation tests using the TEDREC method, no on-voltage degradation due to stacking faults was found, nor was rapid on-voltage degradation due to higher-order snapback phenomena. No adverse effects on reliability were found in long-term operation tests, indicating good performance.

[0083] As described above, according to this embodiment 6, the honeycomb buffer layer type reverse conducting IGBT with insulating protrusions allows for a significant increase in the conductive path resistance of the buffer layer in a small-area cell, eliminating or suppressing the snapback phenomenon to an acceptable range. Furthermore, the cell can be significantly miniaturized, leading to substantial loss reduction and cost savings due to reduced chip area. [Examples]

[0084] In the above [Example 1] to [Example 6], each IGBT chip is constructed based on the concept of configuring the active region cell with a reverse-conducting IGBT standard cell specific to each example according to the present invention. The reverse-conducting IGBT standard cell here refers to a cell equipped with a snapback suppression measure, such as a cell with a pilot function, disclosed by the present inventor in [Patent Document 2] Japanese Patent No. 7385932. Therefore, the snapback phenomenon is either almost eliminated or significantly suppressed to an acceptable range (up to a Vsb of about 10V, which is not a practical problem). As a result, in Example 2, for example, Vsb could be set to approximately 2.74V and the snapback phenomenon could be eliminated, but only 15 reverse-conducting IGBT standard cells could be integrated within a predetermined 6mm square active area. Therefore, in this embodiment 7, the number of integrated cells is significantly increased to further reduce on-resistance. To this end, in the active region where cells are integrated in parallel as shown in Figure 1, only the three central cells are standard cells with a stripe structure as in embodiment 2, and the remaining cells are standard cells with a narrow stripe structure to increase the number of cells. Specifically, the three central cells are standard cells with a cell width of 380 μm and eight insulating protrusions, similar to embodiment 2, and the remaining cells are standard cells with a narrow stripe structure with a cell width of 140 μm and two insulating protrusions. As a result, in the case of an active region of the same size, a composite element can be constructed with a total of 34 narrow stripe structure cells, 17 on each side of the three central standard cells. If the active region is composed solely of these narrow stripe structure cells, Vsb is 3.0V. Therefore, the Vsb of this composite element will be at least 3V in the worst-case scenario. Consequently, it is approximately 0.6V lower than the on-voltage immediately after switching on in Figure 1, and the snapback phenomenon can be almost completely eliminated. On the other hand, the number of integrated cells per chip can be more than doubled from 15 to 37, and therefore, losses can be reduced significantly due to a substantial decrease in on-resistance.

[0085] In the case of the composite element in this embodiment, the breakdown voltage is 16.3kV and the current is 80A / cm². 2The on-voltage has been reduced to 5.2V. On the other hand, regarding turn-off losses, when the composite element turns off, the discharge of residual carriers from the narrow stripe structure cells, which have a significantly smaller cell area, is faster than that from the three standard cells in the center. As a result, the total turn-off time of the composite element can be shortened, and the reduction in turn-off losses due to the significant increase in the number of cells in the composite element can be enjoyed. Furthermore, since the Vth of the composite element in this embodiment is still about 0.6V lower than the on-voltage immediately after turning on, as described above, by constructing a separate composite element using various narrow stripe structure cells with even smaller cell widths, based on the concept of this embodiment 7, it is possible to significantly increase the number of cells while eliminating the snapback phenomenon and further reduce losses. [Examples]

[0086] This Example 8 differs from Example 3 in that it uses <Method C> described in

[0042] as the manufacturing method, and the non-standard concentration in the semiconductor region of the n buffer layer is 1e17cm -3 It is essentially the same as before, except that its thickness has been reduced to 1 μm.

[0087] First, I will briefly explain the main production process flow below. Figure 9 shows the first half of the fabrication process flow from (9a) to (9c). First, in (9a), an n-type drain layer 51 is epitaxially grown on an n-type SiC off-angle single crystal wafer 50. Next, a vanadium-doped non-standard concentration of 1e17cm³ is grown. -3 A semi-insulating layer 71 with a thickness of 1 μm is epitaxially grown. Semi-insulating means that the resistivity is 1 x 10⁻¹⁶. 5 ~1x10 10 This means the resistivity is approximately Ωcm, but in this embodiment, the resistivity is approximately 5 x 10⁻⁶. 6 It's set to Ωcm. Next (9b), selective ion implantation of nitrogen is performed to form conductive paths 55 such as comb teeth or comb shafts of the desired shape as shown in Figure 6. It is important to set the implantation depth so that the conductive paths reach the n-type drain layer 51 via a semi-insulating layer with a thickness of 1 μm. After that, a predetermined annealing is performed to eliminate implantation damage, and then (9c) the p-collector layer 53 is epitaxially grown, and a short-circuit region 56 is formed by selective ion implantation of nitrogen. Subsequently, although the process is the same and therefore not shown, the SiC reverse conduction IGBT wafer is completed by performing the same steps as in (5d) to (5f) in Figure 5.

[0088] Unlike the process in Figure 5, the process shown in Figure 9 does not require penetration of the p-collector layer 53 during ion implantation. Therefore, the implantation depth only needs to be slightly above 1 μm, which reaches the drift layer 51. This eliminates the need for expensive ultra-high energy ion implantation equipment of 20 MeV or more, reduces implantation damage, and allows for lower equipment costs and simplification of the annealing process, resulting in extremely high economic efficiency.

[0089] In this embodiment 8, as in embodiment 3, eight insulating protrusions 119 are provided per comb tooth. Therefore, the total width of the comb teeth is 170 μm, and the cell width Wp is 380 μm. The conductive path length per comb tooth is 790 μm, and the resistance is approximately 1080 kΩ. Since 30 comb teeth are connected in parallel per half cell, the total conductive path resistance of the buffer layer for half a cell is approximately 18.5 kΩ. Based on the analysis method in

[0049] , the voltage drop due to the current Isb, i.e., the current flowing through the conductive path of the comb-shaped buffer region, exceeds the SiC's built-in voltage Vbi of 2.7V, and the current Isb when hole injection from the p collector begins is approximately 145μA. As a result, the voltage drop in the drift region is small at 0.3V, and Vsb just before the IGBT section turns on can be reduced to approximately 3.0V. Therefore, when the switch is turned on, it simply switches from Vsb of 3.0V just before turning on to an on voltage of around 3.7V, as shown in Figure 1, and the problematic snapback phenomenon is eliminated and does not occur. Furthermore, the withstand voltage at room temperature is good, at approximately 8.7kV. The leakage current is typically 2x10 at 6kV at room temperature. -4 A / cm 2 It is approximately 80 A / cm². 2 The on-voltage is 5.1V, indicating good on-characteristics. In long-term operation tests using the TEDREC method, no on-voltage degradation due to stacking faults was found, nor was rapid on-voltage degradation due to higher-order snapback phenomena. No adverse effects on reliability were found in long-term operation tests, indicating good performance. The vanadium-doped buffer layer has a function of suppressing the growth of stacking faults and is expected to be effective in suppressing on-voltage degradation, which is also expected to contribute to the above-mentioned good long-term test results. It should be noted that the effects related to the instability of maintaining semi-insulation at high temperatures were not observed in this embodiment.

[0090] As described above, according to this embodiment, since an epitaxial growth film doped with semi-insulating vanadium is used to form the insulating region of the buffer layer, it is not necessary to implant ultra-high energy ions for conductive path formation, and implantation damage is reduced. This allows for a significant simplification of the process and equipment, resulting in high economic efficiency, as well as the expectation of suppressing on-voltage degradation caused by stacking faults.

[0091] The present invention has been described above based on Examples 1 to 8, but it is obvious to those skilled in the art that the present invention is not limited to these and can be easily modified and applied in various ways. For example, by changing the numerical values ​​of the structural specifications, it is possible to develop reverse conducting IGBTs with breakdown voltages of 7kV or less, or even ultra-high breakdown voltages of approximately 30kV or more, in addition to the breakdown voltages of the examples. Furthermore, although the case of JTE in the field relaxation structure has been described, the same applies to other field relaxation structures such as FLR and RESURF, and to JTE composed of multiple regions with different concentrations. It is also obvious that various cell structures other than stripe structures, equally divided stripe structures, and honeycomb structures, such as polygonal structures, can be adopted for the cell shape, and it is also obvious that the planar shape and area ratio of unipolar transistors and bipolar transistors can be changed and optimized according to the specifications of the reverse conducting IGBT. Furthermore, although the process of forming conductive paths and insulating regions in the buffer layer has been mentioned in terms of <Method a>, <Method b>, and <Method c>, it is obvious to those skilled in the art that various other modifications and applications are possible. Furthermore, while planar gate IGBTs and trench gate IGBTs were mentioned, the same principles apply to IGBTs with other gate structures such as V-gates. Additionally, while SiC and Si were mentioned, the principles can be applied to reverse-conducting IGBTs using other wide-bandgap semiconductors such as GaN and diamond, and can also be modified and applied to other reverse-conducting semiconductor devices such as reverse-conducting GTO thyristors and JMGBTs. Naturally, the principles can also be applied to wide-bandgap semiconductor materials using p-type drift layers. [Industrial applicability]

[0092] This invention can be used in various high-voltage converters and power stabilization devices directly connected to power distribution systems, enabling significant miniaturization, weight reduction, and energy savings for the system. It has considerable potential for use in grid connection of renewable energy power generation equipment such as wind power, allowing for miniaturization, weight reduction, and energy savings. It can also be used in control devices for industrial equipment such as large fans, pumps, and rolling mills. [Explanation of symbols]

[0093] 1: SiC trench drain reverse conducting IGBT tip 2: Active area 3: JTE for electric field relaxation 4: Surface exposed area of ​​the field region 5: n-channel stopper layer 50: SiC off-angle single crystal wafer 51,100:n drift layer 52,104,804:n buffer layer 53, 102, 802: p collector area 56,103,803;n short-circuit region 57: P-layer for Ohmic contact lenses 58, 106, 806: Current density increasing layer CEL 59, 114: MOS surface area 60, 113, 813: Emitter main electrode 61,101,801: Collector main electrode 71: Vanadium-doped epitaxial semi-insulating layer 107, 807: p body area 108, 808: Emitter region 109: Channel 110: Ohmic Contact 111, 811: Gate oxide film 112, 812: Gate metal electrode 115: Insulating film 116: Comb shaft and corresponding conductive path to the comb shaft 116Y, 816Y: Conductive path in the short-circuit region 117, 817: Insulating region 117Z, 118Z: Ion-implanted p-collector region 118, 818: Semiconductor region or semiconductor conductive path 119, 819: Insulating protrusions 816: Trench gate opposing conductive path 820: Grid gate

Claims

1. A reverse-conducting IGBT semiconductor device, wherein the IGBT chip has an active region containing a plurality of reverse-conducting IGBT standard cells and a voltage-resistant structure surrounding the active region, The reverse-conducting IGBT standard cell of the IGBT chip has a cross-sectional configuration that minimizes the following: a MOS surface region is provided between one main surface and the drift layer surface of the first conductivity type, exposed on one main surface of the active region; an emitter main electrode is provided on the exposed surface of the MOS surface region; a buffer layer is provided in contact with the back surface of the drift layer of the first conductivity type; a collector region of the second conductivity type and a short-circuit region (which also serves as the drain region) of the first conductivity type are provided on the back surface of the buffer layer, with a portion of each side in contact with the other region; and a collector main electrode is provided on the back surface of the collector region of the second conductivity type and the short-circuit region (which also serves as the drain region) of the first conductivity type. A first conductivity type current density increasing layer CEL may be provided between the MOS surface region and the first conductivity type drift layer. A reverse-conducting semiconductor device characterized in that the buffer layer on the collector region is a reverse-conducting IGBT standard cell having a semiconductor region of a first conductivity type that serves as a conductive path and an insulating region or a semi-insulating region.

2.

1. The reverse-conducting IGBT standard cell in the active region has a stripe structure or a stripe structure that is equally divided in the longitudinal direction, the buffer layer has a stripe-shaped double-toothed comb-type planar shape, a plurality of comb teeth are connected to a comb shaft, the comb shaft, the comb teeth and the comb tooth assembly are composed of the semiconductor region, and the spaces between the comb teeth are composed of the insulating region or the semi-insulating region. A reverse-conducting semiconductor device characterized in that the comb teeth, the comb shaft, and the insulating region or semi-insulating region between them are in contact with the collector region, and the comb tooth assembly is in contact with the short-circuit region.

3.

1. The reverse-conducting semiconductor device is characterized in that the reverse-conducting IGBT standard cell has a polygonal planar shape enclosed by three or more line segments, the triangular portion connecting the intersection of the line segments to the center of the polygon is composed of the semiconductor region, the insulating region, or the semi-insulating region, and the triangular portion of the semiconductor region and the triangular portion of the insulating region or the semi-insulating region are alternately arranged to constitute the buffer layer.

4. A reverse conducting semiconductor device according to claim 2 or claim 3, wherein the semiconductor region of the reverse conducting IGBT standard cell is provided with insulating protrusions made of the same insulating material as the insulating region or semi-insulating region, the insulating protrusions are in contact with either the upper or lower insulating region or semi-insulating region adjacent to the semiconductor region, and the resistance of the conductive path of the buffer layer can be set by setting the shape and number of the insulating protrusions, thereby setting Isb and Vsb.

5. In a reverse-conducting semiconductor device having the reverse-conducting IGBT standard cell described in any one of claims 2 to 4, A reverse-conducting semiconductor device characterized in that, in addition to the reverse-conducting IGBT standard cell, it is configured to include, instead of the reverse-conducting IGBT standard cell, narrow-width reverse-conducting IGBT cells with smaller cell widths other than the reverse-conducting IGBT standard cell.

6. In the reverse-conducting IGBT semiconductor device described in any one of Claims 1 to 4, A reverse-conducting semiconductor device characterized in that the insulating region or semi-insulating region of the buffer layer is composed of an oxygen or vanadium-doped epitaxial film, the conductive path is composed of a first conductivity type ion implantation layer that reaches the first conductivity type drift layer, and the impurity concentration of the ion implantation layer is higher than the impurity concentration of the drift layer.

7. In the method for manufacturing a reverse-conducting IGBT semiconductor device according to claim 1, A method for manufacturing a reverse-conducting semiconductor device, characterized in that the manufacturing process for the insulating region or the semi-insulating region includes a selective implantation of insulating ions, or includes a trench formation process followed by a semiconductor oxide film formation process on the trench surface, and the manufacturing process for the conductive path is carried out after the manufacturing process for the collector region.

8. In the reverse-conducting semiconductor device described in Claim 2, A method for operating a reverse-conducting semiconductor device, characterized by raising the temperature of the built-in pn junction diode and IGBT section to above the on-voltage degradation suppression temperature by energizing the majority carrier current of the MOSFET section, and then performing predetermined electrical operations.

9. In the reverse-conducting semiconductor device described in Claim 4, A method for operating a reverse-conducting semiconductor device, characterized by raising the temperature of the built-in pn junction diode and IGBT section to above the on-voltage degradation suppression temperature by energizing the majority carrier current of the MOSFET section, and then performing predetermined electrical operations.

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