Semiconductor device and method for manufacturing the same

Abstract

To improve the performance of a semiconductor device.SOLUTION: A floating region PF covers a bottom face BS2 of a trench TR of an active cell AC. The floating region PF covers a bottom face BS3 of a trench TR of an inactive cell IAC to reach a semiconductor substrate SUB between a pair of trenches TR of the inactive cell IAC. The distance Diac between a base region PB in the inactive cell IAC and the floating region PF is shorter than the distance Dac between a base region PB in the active cell AC and the floating region PF.SELECTED DRAWING: Figure 4

Description

[Technical Field]

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a gate electrode formed inside a trench and a method for manufacturing the same. [Background technology]

[0002] In recent years, semiconductor devices equipped with power semiconductor elements such as IGBTs (Insulated Gate Bipolar Transistors) have been widely used. Furthermore, IGBTs with low on-resistance, specifically those with a structure in which the gate electrode is embedded inside a trench, are known.

[0003] For example, Patent Document 1 discloses an IGBT with a GGEE structure that utilizes the IE (Injection Enhancement) effect. The IE effect is a technique that increases the concentration of charge accumulated in the drift region by making it difficult for holes to be discharged to the emitter electrode EE side when the IGBT is in the ON state.

[0004] In the GGEE structure, the "G" refers to a structure in which a gate electrode connected to the gate potential is embedded inside a trench, and this is called a gate trench. Similarly, the "E" refers to a structure in which a gate electrode connected to the emitter potential is embedded inside a trench, and this is called an emitter trench. Therefore, a GGEE structure is a structure in which a pair of emitter trenches are formed at a certain distance from a pair of gate trenches.

[0005] As disclosed in Patent Document 1, in order to utilize the IE effect, a p-type floating region is formed in the semiconductor substrate between a pair of gate trenches and a pair of emitter trenches. This p-type floating region is formed to a depth greater than the depth of each of the pair of gate trenches and the pair of emitter trenches. Furthermore, an n-type hole barrier region having a higher impurity concentration than the drift region is formed in the semiconductor substrate sandwiched between the pair of gate trenches and the semiconductor substrate sandwiched between the pair of emitter trenches.

[0006] Furthermore, Patent Document 2 discloses an IGBT with a GGEEs structure in which the cell pitch of the GGEE structure is shrunk. In the GGEEs structure, the distance between a pair of emitter trenches is shorter than the distance between a pair of gate trenches. In other words, the "s" in the GGEEs structure means that the distance between a pair of emitter trenches is shrunk. [Prior art documents] [Patent Documents]

[0007] [Patent Document 1] Japanese Patent Publication No. 2013-140885 [Patent Document 2] Japanese Patent Publication No. 2017-157733 [Overview of the project] [Problems that the invention aims to solve]

[0008] During the transient state of IGBT switching operation, excess holes tend to accumulate in the p-type floating region. Therefore, in transient states, uncontrollable potential fluctuations occur in the p-type floating region, and these potential fluctuations become a source of noise, leading to a problem of reduced IGBT performance.

[0009] Patent documents 1 and 2 utilize parasitic PMOS transistors to discharge excess holes in the p-type floating region. A parasitic PMOS transistor is configured with a p-type floating region as the source, an n-type hole barrier region as the channel, and a p-type base region as the drain.

[0010] When a hole is injected into the p-type floating region, the potential of the source increases, creating a negative potential difference between the gate electrode and the source. As a result, the parasitic PMOS transistor turns on, and the hole in the p-type floating region is discharged to the drain.

[0011] These parasitic PMOS transistors are formed in both a pair of gate trenches and a pair of emitter trenches. The inventors of this invention investigated the robustness of the IGBT, including load short-circuit testing using a short circuit and the RBSOA (Reverse Bias Safe Operating Area). As a result, the inventors of this invention found that the robustness can be improved by increasing the Hall current flowing through the parasitic PMOS transistors in the pair of emitter trenches and decreasing the Hall current flowing through the parasitic PMOS transistors in the pair of gate trenches.

[0012] The primary objective of this application is to improve the performance of semiconductor devices having IGBTs by enhancing robustness against load short circuits and RBSOA. Other challenges and novel features will become apparent from the description herein and the accompanying drawings. [Means for solving the problem]

[0013] A brief overview of some of the representative embodiments disclosed in this application is as follows:

[0014] A semiconductor device according to one embodiment includes a semiconductor substrate of a first conductivity type having an upper surface and a lower surface, a first trench, a second trench, a third trench and a fourth trench formed in the semiconductor substrate on the upper surface side of the semiconductor substrate, a first gate electrode formed inside the first trench via a first gate insulating film, a second gate electrode formed inside the second trench via a second gate insulating film, a third gate electrode formed inside the third trench via a third gate insulating film, a fourth gate electrode formed inside the fourth trench via a fourth gate insulating film, and the semicircular area between the first trench and the second trench on the upper surface side of the semiconductor substrate. The semiconductor substrate comprises: a first hole barrier region of the first conductivity type formed in the conductive substrate; a first base region of the second conductivity type opposite to the first conductivity type formed within the first hole barrier region; an emitter region of the first conductivity type formed within the first base region; a second hole barrier region of the first conductivity type formed in the semiconductor substrate between the third trench and the fourth trench on the upper side of the semiconductor substrate; a second base region of the second conductivity type formed within the second hole barrier region; and a first floating region of the second conductivity type formed in the semiconductor substrate between the second trench and the third trench on the upper side of the semiconductor substrate. The first floating region covers the second bottom surface of the second trench and covers the third bottom surface of the third trench so as to reach the semiconductor substrate between the third trench and the fourth trench, and the first distance between the second base region and the first floating region is shorter than the second distance between the first base region and the first floating region.

[0015] A method for manufacturing a semiconductor device according to one embodiment includes: (a) a step of preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface; (b) a step of forming a first hole barrier region of the first conductivity type and a second hole barrier region of the first conductivity type in the semiconductor substrate on the upper surface side of the semiconductor substrate; (c) a step of forming a first floating region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate on the upper surface side of the semiconductor substrate; (d) a step of forming a first trench, a second trench, a third trench and a fourth trench in the semiconductor substrate on the upper surface side of the semiconductor substrate after steps (b) and (c); (e) a step of forming a first gate insulating film inside the first trench and a second gate insulating film inside the second trench and the (f) After step (e), a step of forming a third gate insulating film inside a third trench and a fourth gate insulating film inside a fourth trench; (g) After step (f), a step of forming a first gate electrode inside a first trench via the first gate insulating film, a second gate electrode inside a second trench via the second gate insulating film, a third gate electrode inside a third trench via the third gate insulating film, and a fourth gate electrode inside a fourth trench via the fourth gate insulating film; (h) After step (g), a step of forming a first base region of the second conductivity type inside a first hole barrier region and a second base region of the second conductivity type inside a second hole barrier region; (g) After step (g), a step of forming an emitter region of the first conductivity type inside a first base region.The first trench has a first side surface, a second side surface facing the first side surface, and a first bottom surface connecting the first side surface and the second side surface. The second trench has a third side surface, a fourth side surface facing the third side surface, and a second bottom surface connecting the third side surface and the fourth side surface. The third trench has a fifth side surface, a sixth side surface facing the fifth side surface, and a third bottom surface connecting the fifth side surface and the sixth side surface. The fourth trench has a seventh side surface, an eighth side surface facing the seventh side surface, and a fourth bottom surface connecting the seventh side surface and the eighth side surface. The first trench and the second trench are provided separately such that the second side surface and the third side surface are adjacent. The third trench and the fourth trench are provided separately such that the sixth side surface and the seventh side surface are adjacent. The first hole barrier region is formed in the semiconductor substrate between the second side surface and the third side surface. The second hole barrier region is formed in the semiconductor substrate between the sixth side surface and the seventh side surface. The first floating region is formed in the semiconductor substrate between the fourth side surface and the fifth side surface, covering the second bottom surface and covering the third bottom surface so as to exceed the sixth side surface. A first distance between the second base region and the first floating region is shorter than a second distance between the first base region and the first floating region.

Effect of the Invention

[0016] According to one embodiment, the performance of the semiconductor device can be improved.

Brief Description of the Drawings

[0017] [Figure 1] It is a plan view showing a semiconductor device in Embodiment 1. [Figure 2] It is a plan view of a main part showing a semiconductor device in Embodiment 1. [Figure 3] It is a cross-sectional view showing a semiconductor device in Embodiment 1. [Figure 4] It is a cross-sectional view showing a main part of a semiconductor device in Embodiment 1. [Figure 5] This is experimental data by the inventors of the present application. [Figure 6] This is experimental data by the inventors of the present application. [Figure 7] It is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 1. [Figure 8] It is a cross-sectional view showing the manufacturing process following FIG. 7. [Figure 9] It is a cross-sectional view showing the manufacturing process following FIG. 8. [Figure 10] It is a cross-sectional view showing the manufacturing process following FIG. 9. [Figure 11] It is a cross-sectional view showing the manufacturing process following FIG. 10. [Figure 12] It is a cross-sectional view showing the manufacturing process following FIG. 11. [Figure 13] It is a cross-sectional view showing the manufacturing process following FIG. 12. [Figure 14] It is a cross-sectional view showing the manufacturing process following FIG. 13. [Figure 15] It is a cross-sectional view showing the manufacturing process following FIG. 14. [Figure 16] It is a cross-sectional view showing the manufacturing process following FIG. 15. [Figure 17] It is a cross-sectional view showing the semiconductor device in Embodiment 2. [Figure 18] It is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 2. [Figure 19] It is a cross-sectional view showing the manufacturing process following FIG. 18. [[ID=,42]] [Figure 20] It is a cross-sectional view showing the manufacturing process following FIG. 19. [Figure 21] It is a cross-sectional view showing the GGEEs structure and the GGEE structure. [Figure 22] It is a cross-sectional view showing the manufacturing process of the semiconductor device in Embodiment 3. [Figure 23] It is a cross-sectional view showing the main part of the semiconductor device in the study example. [Figure 24] It is a cross-sectional view showing the manufacturing process of the semiconductor device in the study example. [Figure 25] It is a cross-sectional view showing the manufacturing process following FIG. 24. [Modes for carrying out the invention]

[0018] The embodiments will be described in detail below with reference to the drawings. In all the drawings used to describe the embodiments, the same reference numerals are used for members having the same function, and repeated descriptions of them will be omitted. In addition, in the following embodiments, descriptions of the same or similar parts will not be repeated unless it is particularly necessary.

[0019] Furthermore, the X, Y, and Z directions described in this application intersect and are orthogonal to each other. In this application, the Z direction is described as the vertical direction, height direction, or thickness direction of a structure. Also, expressions such as "plan view" or "planar view" used in this application mean that the surface formed by the X and Y directions is called a "plane," and this "plane" is viewed from the Z direction.

[0020] (Embodiment 1) <Structure of a semiconductor device> The structure of the semiconductor device 100 in Embodiment 1 will be described below with reference to Figures 1 to 4.

[0021] Figure 1 is a plan view showing a semiconductor chip, which is a semiconductor device 100. As shown in Figure 1, most of the semiconductor device 100 is covered by an emitter electrode EE. The gate wiring GW is formed to surround the emitter electrode EE in a plan view.

[0022] Although not shown in the diagram, the emitter electrode EE and gate wiring GW are covered with a protective film such as a polyimide film. Openings are provided in a portion of the protective film on the emitter electrode EE and gate wiring GW, and the areas exposed by these openings become the emitter pad EP and gate pad GP. By connecting external connection members such as bonding wires or clips (copper plates) to the emitter pad EP and gate pad GP, the semiconductor device 100 is electrically connected to other semiconductor chips or wiring boards.

[0023] The semiconductor device 100 comprises a cell region and an outer peripheral region surrounding the cell region. Major semiconductor elements such as IGBTs are formed in the cell region. Gate wiring GWs and the like are formed in the outer peripheral region. Region 1A shown in Figure 1 represents a part of the cell region.

[0024] Figure 2 is a plan view of the main part corresponding to region 1A shown in Figure 1. The IGBT shown in Figure 2 is an IGBT with a GGEEs structure that utilizes the IE effect. The semiconductor device 100 has an active cell AC for performing the main operation of the IGBT and inactive cells IAC other than the active cell AC.

[0025] As shown in Figure 2, multiple trenches TR extend in the Y direction and are adjacent to each other in the X direction. A gate electrode GE1 is formed inside the trench TR of the active cell AC. A gate electrode GE2 is formed inside the trench TR of the inactive cell IAC. The trench TR formed in the active cell AC and the gate electrode GE1 formed inside it constitute a gate trench. The trench TR formed in the inactive cell IAC and the gate electrode GE2 formed inside it constitute an emitter trench.

[0026] The gate electrode GE1 of the active cell AC is electrically connected to the gate wiring GW, supplying the gate potential during IGBT operation. The gate electrode GE2 of the inactive cell IAC is electrically connected to the emitter electrode EE, supplying the emitter potential during IGBT operation. Additionally, the base region PB and emitter region NE of the active cell AC and the base region PB of the inactive cell IAC are electrically connected to the emitter electrode EE, supplying the emitter potential during IGBT operation.

[0027] Figure 3 is a cross-sectional view along line AA shown in Figure 2. The semiconductor device 100 includes an n-type semiconductor substrate SUB having an upper surface and a lower surface. The semiconductor substrate SUB has an n-type drift region NV. Here, the n-type semiconductor substrate SUB itself constitutes the drift region NV. The semiconductor substrate SUB may also be a laminate of an n-type silicon substrate and an n-type silicon layer grown on the silicon substrate by an epitaxial growth method while introducing phosphorus (P). In that case, the n-type silicon layer having a lower impurity concentration than the n-type silicon substrate constitutes the drift region NV.

[0028] On the lower surface of the semiconductor substrate SUB, an n-type field stop region (impurity region) NS is formed within the semiconductor substrate SUB. The impurity concentration in the field stop region NS is higher than that in the drift region NV. The field stop region NS is provided to prevent the depletion layer extending from the pn junction on the upper surface of the semiconductor substrate SUB from reaching the p-type collector region PC during IGBT turn-off.

[0029] On the underside of the semiconductor substrate SUB, a p-type collector region (impurity region) PC is formed within the semiconductor substrate SUB. The collector region PC is located below the field stop region NS.

[0030] A collector electrode CE is formed beneath the lower surface of the semiconductor substrate SUB. The collector electrode CE is electrically connected to the collector region PC and supplies the collector potential to the collector region PC. The collector electrode CE is either a single-layer metal film such as an Au film, Ni film, Ti film, or AlSi film, or a multilayer metal film formed by appropriately stacking these.

[0031] On the upper surface of the semiconductor substrate SUB, a trench TR is formed within the semiconductor substrate SUB. The trench TR penetrates the emitter region NE and the base region PB, which will be described later, and reaches the semiconductor substrate SUB. The depth of the trench TR is, for example, 2 μm or more and 5 μm or less.

[0032] A gate insulating film GI is formed inside the trench TR. Through the gate insulating film GI, gate electrodes GE1 and GE2 are formed inside the trench TR. The gate insulating film GI is an insulating film, for example, a silicon oxide film. The gate electrodes GE1 and GE2 are conductive films, for example, polycrystalline silicon films into which n-type impurities have been introduced. The thickness of the gate insulating film GI is, for example, 70 nm or more and 150 nm or less.

[0033] On the upper surface of the semiconductor substrate SUB of the active cell AC, a hole barrier region (impurity region) NHB is formed in the semiconductor substrate SUB between a pair of trenches TR (a pair of gate electrodes GE1). The impurity concentration in the hole barrier region NHB is higher than that in the drift region NV.

[0034] Within the hole barrier region (NHB), a p-type base region (impurity region) PB is formed. Within the p-type base region PB, an n-type emitter region (impurity region) NE is formed. The impurity concentration in the emitter region NE is higher than that in the drift region (NV). The base region PB is formed to be shallower than the depth of the trench TR, and the emitter region NE is formed to be shallower than the depth of the base region PB.

[0035] As shown in Figure 2, multiple emitter regions NE are formed between a pair of trenches TR (a pair of gate electrodes GE1) and are spaced apart from each other at a predetermined distance along the Y direction. The base region PB located below the emitter region NE adjacent to the gate electrodes GE1 is used as the channel region.

[0036] On the upper surface of the inactive cell IAC, a hole barrier region (NHB) is formed in the semiconductor substrate SUB between a pair of trenches TR (a pair of gate electrodes GE2). Additionally, a p-type floating region (impurity region) PF is formed in the semiconductor substrate SUB between gate electrodes GE1 and GE2. Within the hole barrier region NHB and the floating region PF, a p-type base region PB is formed. The impurity concentration in the base region PB is lower than that in the floating region PF.

[0037] The floating region PF and the base region PB formed within the floating region PF are not electrically connected to the gate wiring GW and the emitter electrode EE, and no potential is supplied to them; they are in an electrically floating state.

[0038] In the active cell AC and inactive cell IAC, an interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB so as to cover each trench TR. The interlayer insulating film IL is, for example, a silicon oxide film. The thickness of the interlayer insulating film IL is, for example, 600 nm or more and 1500 nm or less.

[0039] In the active cell AC, the pores CH penetrate the interlayer insulating film IL and the emitter region NE, and reach the interior of the base region PB. The pores CH are formed to be in contact with the emitter region NE and the base region PB.

[0040] In the upper part of the pore CH, the interlayer insulating film IL recedes. That is, the size of the opening of a pore CH located above the upper surface of the semiconductor substrate SUB is larger than the size of the opening of a pore CH located below the upper surface of the semiconductor substrate SUB. As a result, a portion of the upper surface of the emitter region NE is exposed from the interlayer insulating film IL. Consequently, the emitter electrode EE not only contacts the side surface of the emitter region NE within the pore CH, but also contacts a portion of the upper surface of the emitter region NE. This reduces the contact resistance between the emitter electrode EE and the emitter region NE.

[0041] In the inactive cell IAC, the pore CH penetrates the interlayer insulating film IL and reaches the interior of the base region PB. Furthermore, the pore CH is formed to overlap the gate electrode GE2 in a plan view. Therefore, the pore CH in the inactive cell IAC is formed to be in contact with both the gate electrode GE2 and the base region PB.

[0042] In active cell AC and inactive cell IAC, a p-type high-concentration diffusion region (impurity region) PR is formed in the base region PB surrounding the bottom of the pore CH. The impurity concentration in the high-concentration diffusion region PR is higher than that of the base region PB. The high-concentration diffusion region PR is provided to reduce the contact resistance with the emitter electrode EE and to prevent latch-up.

[0043] A plug PG is embedded inside the pore CH. The plug PG includes a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a laminated film of a titanium film and a titanium nitride film formed on the titanium film. The conductive film is, for example, a tungsten film.

[0044] Although not shown in the diagram, pore CH is also formed on a portion of the gate electrode GE1, and plug PG is formed inside this pore CH.

[0045] An emitter electrode EE is formed on the interlayer insulating film IL. The emitter electrode EE is electrically connected to the emitter region NE, the base region PB, the high-concentration diffusion region PR, and the gate electrode GE2 via holes CH (plug PG), supplying the emitter potential to these regions. Although not shown in the diagram, a gate wiring GW is also formed on the interlayer insulating film IL using the same manufacturing process as the emitter electrode EE. The gate wiring GW is electrically connected to the gate electrode GE1 via holes CH (plug PG), supplying the gate potential to the gate electrode GE1.

[0046] Such emitter electrode EE and gate wiring GW include a barrier metal film and a conductive film formed on the barrier metal film. The barrier metal film is, for example, a TiW film. The conductive film is, for example, an aluminum alloy film doped with copper or silicon. The aluminum alloy film is the main film of the emitter electrode EE and gate wiring GW and is sufficiently thicker than the TiW film.

[0047] <Main features of Embodiment 1> Figure 4 is a detailed cross-sectional view of the trench TR and its surrounding area, showing the cross-sectional structure of Figure 3.

[0048] As shown in Figure 4, of the pair of trenches TR formed in the active cell AC, one trench TR has a side surface SS1, a side surface SS2 opposite to side surface SS1, and a bottom surface BS1 connecting side surfaces SS1 and SS2. The other trench TR of the active cell AC has a side surface SS3, a side surface SS4 opposite to side surface SS3, and a bottom surface BS2 connecting side surfaces SS3 and SS4. One trench TR and the other trench TR are spaced apart so that side surfaces SS2 and SS3 are adjacent to each other.

[0049] Furthermore, of the pair of trenches TR formed in the inactive cell IAC, one trench TR has a side surface SS5, a side surface SS6 opposite to side surface SS5, and a bottom surface BS3 connecting side surfaces SS5 and SS6. The other trench TR of the inactive cell IAC has a side surface SS7, a side surface SS8 opposite to side surface SS7, and a bottom surface BS4 connecting side surfaces SS7 and SS8. One trench TR and the other trench TR are spaced apart so that side surfaces SS6 and SS7 are adjacent to each other.

[0050] Furthermore, the spacing between the pair of trenches TR in the inactive cell IAC is narrower than the spacing between the pair of trenches TR in the active cell AC. In other words, the distance between side SS6 and side SS7 is shorter than the distance between side SS2 and side SS3.

[0051] Each floating region PF covers the bottom surfaces BS1 and BS2 of the trench TR of the active cell AC, and the bottom surfaces BS3 and BS4 of the trench TR of the inactive cell IAC. Furthermore, each floating region PF is diffused laterally (in the X direction) so as to reach the semiconductor substrate SUB between each trench TR of the active cell AC and the semiconductor substrate SUB between each trench TR of the inactive cell IAC. Because the floating regions PF not only cover the bottom surfaces of the trench TRs but also extend laterally (in the X direction), electric field concentration directly beneath the trench TRs can be mitigated, thereby improving the junction breakdown voltage.

[0052] In other words, the floating region PF formed in the semiconductor substrate SUB on side SS1 extends beyond side SS2 and covers the bottom surface BS1. The floating region PF formed in the semiconductor substrate SUB between side SS4 and side SS5 extends beyond side SS3 and covers the bottom surface BS2. These floating regions PF (floating regions PF covering the bottom surfaces of the pair of trenches TR of the active cell AC) are not in contact with each other and are spaced apart.

[0053] Furthermore, the floating region PF formed in the semiconductor substrate SUB between side SS4 and side SS5 extends beyond side SS6 and covers the bottom surface BS3. The floating region PF formed in the semiconductor substrate SUB on side SS8 extends beyond side SS7 and covers the bottom surface BS4. These floating regions PF (floating regions PF that cover the bottom surfaces of the pair of trenches TR of the inactive cell IAC) are in contact.

[0054] Furthermore, the hole barrier region NHB of the active cell AC is formed in the semiconductor substrate SUB between side SS2 and side SS3, and the hole barrier region NHB of the inactive cell IAC is formed in the semiconductor substrate SUB between side SS6 and side SS7.

[0055] Figure 5 shows the impurity concentration profiles (dashed lines) between a pair of trenches TR in the active cell AC and the impurity concentration profiles (solid lines) between a pair of trenches TR in the inactive cell IAC. Note that the impurity concentration profile (dashed lines) for the active cell AC is in a position close to side SS2 or side SS3, and the impurity concentration profile (solid lines) for the inactive cell IAC is in a position close to side SS6 or side SS7.

[0056] Now, focusing on the parasitic PMOS transistors of the active cell AC and the inactive cell IAC, we see that the channel length of the parasitic PMOS transistor in the inactive cell IAC is shorter than the channel length of the parasitic PMOS transistor in the active cell AC.

[0057] In other words, as shown in Figures 4 and 5, the distance Diac between the base region PB and the floating region PF in the inactive cell IAC is shorter than the distance Dac between the base region PB and the floating region PF in the active cell AC. Note that distance Diac is the distance along side SS6 or side SS7, and distance Dac is the distance along side SS2 or side SS3. In other words, the depth of the hole barrier region NHB along side SS6 or side SS7 is shallower than the depth of the hole barrier region NHB along side SS2 or side SS3.

[0058] Furthermore, as shown in Figure 5, the impurity concentration in the hole barrier region NHB of the inactive cell IAC, near the boundary between the floating region PF and the hole barrier region NHB, is lower than the impurity concentration in the hole barrier region NHB of the active cell AC at the same depth. In other words, a portion of the channel region of the parasitic PMOS transistor in the inactive cell IAC is in a state where it is easily turned on.

[0059] As described above, the parasitic PMOS transistors of the inactive cell IAC are configured to operate faster than the parasitic PMOS transistors of the active cell AC.

[0060] Therefore, during the transient state of IGBT switching operation, when the parasitic PMOS transistor turns on, the Hall current flowing through the parasitic PMOS transistor of the inactive cell IAC increases, while the Hall current flowing through the parasitic PMOS transistor of the active cell AC decreases.

[0061] Below, we compare the IGBT in Embodiment 1 with the IGBT in the study example using Figures 6, 23, 24, and 25. Figure 23 shows the IGBT in the study example that the present inventors investigated based on Patent Document 1 and other sources. Note that, similar to Figure 4 of Embodiment 1, Figure 23 shows only the trench TR and a part of its surrounding configuration.

[0062] As will be explained in detail later, in Embodiment 1, ion implantation layers NHB1 to NHB3 and ion implantation layers PF1 and PF2 are formed near the region where the floating region PF and hole barrier region NHB are to be formed by high-energy ion implantation. For example, the position of the impurity concentration peak in ion implantation layer PF1 is approximately the same as, or deeper than, the position of the bottom surface BS1 to BS4 of each trench TR. Then, after the trench TR is formed, the floating region PF and hole barrier region NHB are formed by heat treatment at a relatively low temperature, such as 1100°C.

[0063] On the other hand, in the study example, as shown in Figures 24 and 25, ion-implanted layers PF4 and NHB4 are formed by low-energy ion implantation, and then trenches TR are formed. Subsequently, by performing high-temperature and long-duration heat treatment, for example under conditions of 1200°C for 30 minutes, impurities contained in ion-implanted layers PF4 and NHB4 are diffused, forming floating regions PF and hole barrier regions NHB.

[0064] In the example considered, when diffusing impurities, lateral diffusion is easily inhibited by the trenches TR. Therefore, the amount of diffusion of the floating region PF between the pair of trenches TR is approximately the same in the inactive cell IAC and the active cell AC. Furthermore, by strengthening the heat treatment and increasing the amount of diffusion, it is possible to bring the two floating regions PF covering the bottom surface of the pair of trenches TR in the inactive cell IAC into contact.

[0065] In other words, as shown in Figure 23, in the example considered, the distance Diac is approximately the same as the distance Dac. To put it another way, the channel length of the parasitic PMOS transistor of the inactive cell IAC is approximately the same as the channel length of the parasitic PMOS transistor of the active cell AC.

[0066] Figure 6 shows the experimental results of a load short-circuit test using a typical short circuit. In this test, the power supply voltage was set to 400V, and the breakdown withstand voltage was evaluated by applying a voltage of 0 to 15V to the gate electrode GE1. As shown in the graph in Figure 6, it can be seen that the breakdown withstand voltage is improved in Embodiment 1 compared to the example under consideration, in terms of both collector current Ic and collector voltage Vc.

[0067] Furthermore, Table 1 in Figure 6 shows the results of calculating the energy until a load short circuit occurs. Table 2 in Figure 6 shows the results of calculating the Hall current value of the inactive cell IAC and the Hall current value of the active cell AC, and summarizing their ratios. It can be seen that Embodiment 1 has more energy until a load short circuit occurs than the example under consideration, and that the breakdown tolerance is improved. Also, the Hall current value of the inactive cell IAC is higher in Embodiment 1 than in the example under consideration. As a result, latch-up breakdown in the active cell AC is less likely to occur, the concentration of thermal load on the active cell AC is mitigated, and the RBSOA can be improved.

[0068] As described above, according to Embodiment 1, robustness such as load short circuit and RBSOA can be improved, and the performance of the semiconductor device 100 having an IGBT can be improved.

[0069] <Manufacturing method for semiconductor devices> The following describes each manufacturing step included in the manufacturing method of the semiconductor device 100 in Embodiment 1, using Figures 7 to 16.

[0070] As shown in Figure 7, first, an n-type semiconductor substrate SUB having an upper surface and a lower surface is prepared. As mentioned above, in this case, the n-type semiconductor substrate SUB itself constitutes the drift region NV, but the semiconductor substrate SUB may also be a laminate of an n-type silicon substrate and an n-type silicon layer grown on the silicon substrate while introducing phosphorus (P) by epitaxial growth.

[0071] As shown in Figure 8, ion-implanted layers NHB1 to NHB3 are formed in the semiconductor substrate SUB. First, a resist pattern RP1 is formed on the upper surface of the semiconductor substrate SUB. The resist pattern RP1 has a pattern that opens up regions that will later become the hole barrier regions NHB of the active cell AC and inactive cell IAC, respectively. Next, using the resist pattern RP1 as a mask, multiple n-type ion implantations are performed from the upper side of the semiconductor substrate SUB. Here, we illustrate the case where three n-type ion implantations are performed. After the third n-type ion implantation, the resist pattern RP1 is removed by ashing.

[0072] The first n-type ion implantation was performed with phosphorus (P) as the ion species, an energy of 1000 keV, and a dose of 3.0 × 10⁻⁶. 12 / cm 2 This is carried out under the specified conditions. As a result, an ion implantation layer NHB1 is formed in the semiconductor substrate SUB.

[0073] The second n-type ion implantation was performed with phosphorus (P) as the ion species, an energy of 600 keV, and a dose of 3.0 × 10⁻⁶. 12 / cm 2 The process is carried out under these conditions. As a result, an ion-implanted layer NHB2 is formed in the semiconductor substrate SUB. The ion-implanted layer NHB2 is formed in the semiconductor substrate SUB that overlaps with the ion-implanted layer NHB1 in a plan view, and is located above the ion-implanted layer NHB1.

[0074] The third n-type ion implantation was performed with phosphorus (P) as the ion species, an energy of 300 keV, and a dose of 4.0 × 10⁻⁶. 12 / cm 2 The process is carried out under these conditions. As a result, an ion-implanted layer NHB3 is formed in the semiconductor substrate SUB. The ion-implanted layer NHB3 is formed in the semiconductor substrate SUB that overlaps with the ion-implanted layer NHB2 in a plan view, and is located above the ion-implanted layer NHB2.

[0075] Here, the higher the energy, the deeper the ion implantation layer is formed. However, ion implantation generates crystal defects in the semiconductor substrate SUB. If ion implantation layers are formed sequentially from shallow positions, there is a risk that the impurity concentration profile will be disrupted by the crystal defects that have occurred at shallow positions when ion implantation is performed at deeper positions. Therefore, it is preferable to perform ion implantation at deeper positions first.

[0076] In other words, although the energies of the first to third n-type ion implantations are different, it is preferable to perform the n-type ion implantation with the higher energy first. Therefore, it is preferable to perform the first n-type ion implantation first, then the second n-type ion implantation, and then the third n-type ion implantation.

[0077] Furthermore, a higher ion implantation dose increases the probability of crystal defects occurring. Therefore, it is preferable to use a lower dose for the initial ion implantation and a higher dose for the subsequent ion implantation. This minimizes the disruption of the impurity concentration profile due to crystal defects.

[0078] Furthermore, the first to third n-type ion implantations are performed at an angle perpendicular to the top surface of the semiconductor substrate SUB. When ions are implanted at deeper locations, there is a higher probability that each ion will collide with and scatter from one another. Therefore, ion implantation layers formed at deeper locations tend to spread more laterally. Consequently, the width of ion implantation layer NHB1 is wider than the width of ion implantation layer NHB2, and the width of ion implantation layer NHB2 is wider than the width of ion implantation layer NHB3.

[0079] As shown in FIG. 9, ion implantation layers PF1 and PF2 are formed in a semiconductor substrate SUB. First, a resist pattern RP2 is formed on the upper surface of the semiconductor substrate SUB. The resist pattern RP2 has a pattern that opens an area that will later become the floating region PF. Next, using the resist pattern RP2 as a mask, p-type ion implantation is performed multiple times from the upper surface side of the semiconductor substrate SUB. Here, the case of performing p-type ion implantation twice is exemplified. Note that after the second p-type ion implantation, the resist pattern RP2 is removed by an ashing process.

[0080] For the first p-type ion implantation, the ion species is boron (B), the energy is 1250 keV, and the dose amount is 1.25×10 13 / cm 2 under these conditions. Thereby, an ion implantation layer PF1 is formed in the semiconductor substrate SUB.

[0081] For the second p-type ion implantation, the ion species is boron (B), the energy is 300 keV, and the dose amount is 2.75×10 13 / cm 2 under these conditions. Thereby, an ion implantation layer PF2 is formed in the semiconductor substrate SUB. The ion implantation layer PF2 is formed in the semiconductor substrate SUB overlapping the ion implantation layer PF1 in plan view and is located above the ion implantation layer PF1.

[0082] Here too, although the energies of the first and second p-type ion implantations are different respectively, for the same reason as the n-type ion implantations of the first to third times, it is preferable to first perform a p-type ion implantation with a large energy and a low concentration. Therefore, it is preferable to first perform the first p-type ion implantation and then perform the second p-type ion implantation. Also, the first and second p-type ion implantations are performed at an angle perpendicular to the upper surface of the semiconductor substrate SUB. For the same reason as the relationship of the widths of each of the ion implantation layers NHB1 to NHB3, the width of the ion implantation layer PF1 is wider than the width of the ion implantation layer PF2.

[0083] Furthermore, the manufacturing process for forming ion-implanted layers PF1 and PF2 may be carried out before the manufacturing process for forming ion-implanted layers NHB1 to NHB3.

[0084] Next, after forming ion-implanted layers NHB1 to NHB3 and ion-implanted layers PF1 and PF2, the semiconductor substrate SUB is subjected to heat treatment. This heat treatment is carried out in an atmosphere filled with an inert gas such as nitrogen gas, at a temperature of 700°C or higher and 950°C or lower, for a duration of 30 seconds or higher and 150 seconds or lower. More preferably, this heat treatment is carried out at a temperature of 950°C or lower for 30 seconds.

[0085] This heat treatment activates impurities (B) contained in ion-implanted layers PF1 and PF2, respectively, and also activates impurities (P) contained in ion-implanted layers NHB1 to NHB3. Furthermore, this heat treatment restores crystal defects that occurred during ion implantation.

[0086] As shown in Figure 10, trenches TR are formed in the semiconductor substrate SUB on the upper surface side. First, a silicon oxide film is formed on the upper surface of the semiconductor substrate SUB, for example, by CVD. Next, a resist pattern having openings is formed on the silicon oxide film. Next, the silicon oxide film is patterned by anisotropic etching using the resist pattern as a mask, forming a hard mask HM. Finally, the resist pattern is removed by ashing.

[0087] Next, trenches TR are formed in the semiconductor substrate SUB by performing anisotropic etching using the hard mask HM as a mask. Subsequently, the hard mask HM is removed by wet etching using, for example, a solution containing hydrofluoric acid.

[0088] As shown in Figure 11, a sacrificial oxide film IF1 is formed inside the trench TR and on the upper surface of the semiconductor substrate SUB. This removes the damaged layer formed in the semiconductor substrate SUB. Subsequently, the sacrificial oxide film is removed by isotropic etching using, for example, a solution containing hydrofluoric acid.

[0089] The sacrificial oxide film IF1 is formed by heat treatment of the semiconductor substrate SUB. This heat treatment is performed under higher temperatures and for longer periods than the impurity activation heat treatment shown in Figure 9. For example, this heat treatment is performed in an oxygen-filled atmosphere at 1100°C for 30 minutes or more and 60 minutes or less. This diffuses the impurities (B) contained in ion-implanted layers PF1 and PF2, and the impurities (P) contained in ion-implanted layers NHB1 to NHB3, respectively, thereby forming a p-type floating region PF and an n-type hole barrier region NHB.

[0090] In Embodiment 1, before the heat treatment shown in Figure 11, multiple ion implantation processes have formed ion implantation layers NHB1 to NHB3 and ion implantation layers PF1 and PF2 near the region where the floating region PF and hole barrier region NHB are to be formed. In particular, ion implantation layers NHB1 and PF1 are formed to a deep position beforehand. The trenches TR are formed such that the positions of the bottom surfaces BS1 to BS4 of each trench TR are shallower than the position of ion implantation layer PF1. For example, the position of the impurity concentration peak in ion implantation layer PF1 is approximately the same as the position of the bottom surfaces BS1 to BS4 of each trench TR, or deeper than the position of the bottom surfaces BS1 to BS4 of each trench TR. In the study example, heat treatment was performed under high temperature and long duration conditions (1200°C, 30 minutes), but in Embodiment 1, heat treatment can be performed under low temperature conditions.

[0091] Furthermore, as shown in the example, since the diffusion of impurities is not hindered by the trenches TR during the heat treatment in Figure 11, it becomes easier to cover the bottom of each trench TR with each floating region PF. Also, the two floating regions PF become more likely to come into contact between the pair of trenches TR in the inactive cell IAC.

[0092] At this point, the positional relationship between each floating region PF and each trench TR is as shown in Figure 4. That is, each bottom surface BS1 to BS4 is covered by each floating region PF. Also, two floating regions PF are in contact between the pair of trenches TR of the inactive cell IAC. Furthermore, the position of the floating region PF from the top surface of the semiconductor substrate SUB between the pair of trenches TR of the inactive cell IAC is shallower than the position of the floating region PF from the top surface of the semiconductor substrate SUB between the pair of trenches TR of the active cell AC.

[0093] As shown in Figure 12, a gate insulating film GI and a conductive film CF1 are formed inside the trench TR. First, the gate insulating film GI is formed inside the trench TR and on the upper surface of the semiconductor substrate SUB by thermal oxidation. The gate insulating film GI is a silicon oxide film formed by heat treatment using oxygen gas and hydrogen gas under conditions such as 950°C for 60 minutes.

[0094] Next, a conductive film CF1 is formed inside the trench TR and on the upper surface of the semiconductor substrate SUB, for example by CVD, so as to fill the inside of the trench TR via the gate insulating film GI. The conductive film CF1 is, for example, a polycrystalline silicon film into which n-type impurities have been introduced.

[0095] As shown in Figure 13, the gate insulating film GI and gate electrodes GE1 and GE2 are formed inside the trench TR. First, the conductive film CF1 formed outside the trench TR is removed by anisotropic etching. The conductive film CF1 formed inside the trench TR remains as gate electrodes GE1 and GE2. Next, the gate insulating film GI formed outside the trench TR is removed by isotropic etching, anisotropic etching, or a combination of these etching processes.

[0096] As shown in Figure 14, a p-type base region PB is formed on the upper surface of the semiconductor substrate SUB (floating region PF and hole barrier region NHB) within the semiconductor substrate SUB using photolithography and ion implantation techniques. Next, an n-type emitter region NE is selectively formed within the base region PB of the active cell AC using photolithography and ion implantation techniques. Subsequently, a heat treatment is performed to activate the impurities contained in the base region PB and emitter region NE.

[0097] At this point, each floating region PF and each base region PB are formed to have the distance Diac and distance Dac relationships shown in Figure 4. Furthermore, an impurity concentration profile is constructed as shown in Figure 5.

[0098] As shown in Figure 15, first, in the active cell AC and inactive cell IAC, an interlayer insulating film IL is formed on the upper surface of the semiconductor substrate SUB, for example by CVD, so as to cover each trench TR. The interlayer insulating film IL is, for example, a silicon oxide film.

[0099] Next, pores CH are formed in the interlayer insulating film IL, emitter region NE, and base region PB of the active cell AC using photolithography and anisotropic etching. The bottom of the pores CH is located inside the base region PB.

[0100] Here, a pore CH is also formed in the inactive cell IAC, and this pore CH is formed to overlap the gate electrode GE2 in a plan view. Therefore, the pore CH in the inactive cell IAC is formed to be in contact with the gate electrode GE2 and the base region PB. Although not shown in the figures, a pore CH is also formed on a portion of the gate electrode GE1.

[0101] Next, a p-type high-concentration diffusion region PR is selectively formed in the base region PB at the bottom of the pore CH using photolithography and ion implantation techniques. Then, the interlayer insulating film IL is recessed by isotropic etching. As a result, the opening width of the pore CH located on the upper surface of the semiconductor substrate SUB becomes larger than the opening width of the pore CH located inside the semiconductor substrate SUB.

[0102] As shown in Figure 16, a plug PG is formed inside the pore CH. First, a barrier metal film is formed inside the pore CH and on the interlayer insulating film IL. For example, the barrier metal film can be formed by forming a titanium film inside the pore CH and on the interlayer insulating film IL by sputtering, and then forming a titanium nitride film on the titanium film by sputtering. Next, a conductive film, for example, a tungsten film, is formed on the barrier metal film, for example, by CVD, so as to fill the inside of the pore CH. Next, the conductive film and the barrier metal film formed on the outside of the pore CH are removed by anisotropic etching. This forms a plug PG so as to fill the inside of the pore CH.

[0103] Next, an emitter electrode EE is formed on the interlayer insulating film IL. First, a TiW film is formed on the interlayer insulating film IL, for example by sputtering, and then an aluminum alloy film is formed on the TiW film, for example by sputtering. Next, the emitter electrode EE is formed by patterning the TiW film and the aluminum alloy film using photolithography and dry etching. Although not shown in the diagram, the gate wiring GW is also formed on the interlayer insulating film IL in the same process as the process for forming the emitter electrode EE.

[0104] Subsequently, the structure shown in Figure 3 is obtained through the following manufacturing process. First, an n-type field stop region NS and a p-type collector region PC are formed by ion implantation from the underside of the semiconductor substrate SUB. After these ion implantations, laser annealing is performed to activate the impurities contained in the field stop region NS and the collector region PC. Next, a metal film, such as an Au film, Ni film, Ti film, or AlSi film, is formed on the underside of the semiconductor substrate SUB, for example, by sputtering. This metal film becomes the collector electrode CE. The collector electrode CE may be a laminated film formed by appropriately stacking the aforementioned metal films.

[0105] (Embodiment 2) The semiconductor device 100 and its manufacturing method in Embodiment 2 will be described below with reference to Figures 17 to 21. In the following description, the differences from Embodiment 1 will be mainly explained, and points that overlap with Embodiment 1 will not be explained.

[0106] In Embodiment 2, the manufacturing process of the floating region PF is modified to more reliably shorten the channel length of the parasitic PMOS transistor of the inactive cell IAC. As a result, in Embodiment 2, as shown in Figure 17, the position of the floating region PF from the upper surface of the semiconductor substrate SUB between the pair of trenches TR of the inactive cell IAC is shallower than in Embodiment 1. Consequently, the distance Diac, as explained in Figure 4, is shorter than in Embodiment 1.

[0107] The manufacturing process for such a floating region PF is described below using Figures 18 to 20. The manufacturing process in Figures 18 to 20 is performed in place of Figures 8 to 10.

[0108] As shown in Figure 18, multiple ion implantation layers PF1 are formed in the semiconductor substrate SUB. First, a resist pattern RP3 is formed on the upper surface of the semiconductor substrate SUB. The resist pattern RP3 has a pattern that covers the active cell AC and opens the inactive cell IAC.

[0109] Next, using the resist pattern RP3 as a mask, the first p-type ion implantation is performed from the upper side of the semiconductor substrate SUB. This first p-type ion implantation is the same as described in Figure 9. As a result, multiple ion implantation layers PF1 are formed in the semiconductor substrate SUB of the inactive cell IAC. In Embodiment 2, unlike Embodiment 1, the ion implantation layers PF1 are also formed at positions that overlap in a plan view with the positions where the hole barrier region NHB (ion implantation layers NHB1 to NHB3) is formed. After that, the resist pattern RP3 is removed by ashing.

[0110] As shown in Figure 19, multiple ion-implanted layers PF2 are formed in the semiconductor substrate SUB. First, a resist pattern RP2 is formed on the upper surface of the semiconductor substrate SUB. Next, a second p-type ion implantation is performed from the upper side of the semiconductor substrate SUB, using the resist pattern RP2 as a mask. The resist pattern RP2 and the second p-type ion implantation are the same as those described in Figure 9. This forms the ion-implanted layers PF2 in the semiconductor substrate SUB. The ion-implanted layers PF2 are formed in the semiconductor substrate SUB that overlaps with the ion-implanted layer PF1 in a plan view, and are located above the ion-implanted layer PF1. Subsequently, the resist pattern RP2 is removed by an ashing process.

[0111] As shown in Figure 20, after forming ion-implanted layers NHB1 to NHB3 and ion-implanted layers PF1 and PF2, a trench TR is formed to create a sacrificial oxide film IF1. The heat treatment for forming the sacrificial oxide film IF1 is the same as the heat treatment described in Figure 10.

[0112] The heat treatment shown in Figure 20 diffuses impurities (B) contained in ion implantation layers PF1 and PF2, forming a p-type floating region PF, and diffuses impurities (P) contained in ion implantation layers NHB1 to NHB3, forming an n-type hole barrier region NHB.

[0113] In this way, by forming an ion implantation layer PF1 at a position corresponding to the space between the pair of trenches TR of the inactive cell IAC, the floating region PF on the side SS5 and the floating region PF on the side SS8 are ensured to be in contact.

[0114] Furthermore, the ion implantation layer PF1 is formed to a depth that overlaps with a portion of the ion implantation layer NHB3. Therefore, the position of the floating region PF from the upper surface of the semiconductor substrate SUB between the pair of trenches TR of the inactive cell IAC is shallower than in Embodiment 1.

[0115] From the standpoint of ensuring reliable contact between the two floating regions PF, Embodiment 2 is superior to Embodiment 1. However, Embodiment 2 requires the resist pattern RP3, so Embodiment 1 can suppress the increase in manufacturing costs more effectively than Embodiment 2.

[0116] Furthermore, the technology described in Embodiment 2 is also effective in GGEEs structures, but is particularly effective in GGEE structures.

[0117] As shown in Figure 21, in the GGEE structure, the distance Wiac between a pair of trenches TR in the inactive cell IAC is shorter than the distance Wac between a pair of trenches TR in the active cell AC. In other words, the distance Wiac between sides SS6 and SS7 is shorter than the distance Wac between sides SS2 and SS3. On the other hand, in the GGEE structure, the distance Wiac is the same as the distance Wac.

[0118] In the technique described in Embodiment 1, the larger the distance Wiac, the more difficult it becomes to bring the two floating regions PF into contact between the pair of trenches TR of the inactive cell IAC. However, using the technique described in Embodiment 2, even when the distance Wiac is large, such as in a GGEE structure, the two floating regions PF can be brought into contact more reliably.

[0119] (Embodiment 3) The semiconductor device 100 and its manufacturing method in Embodiment 3 will be described below with reference to Figure 22. In the following description, the differences from Embodiments 1 and 2 will be mainly explained, and points that overlap with Embodiments 1 and 2 will not be explained.

[0120] In Embodiment 3, similar to Embodiment 2, improvements have been made to the manufacturing process of the floating region PF to ensure that the channel length of the parasitic PMOS transistor of the inactive cell IAC is more reliably shortened. The final structure of Embodiment 3 is almost the same as the structure shown in Figure 17 of Embodiment 2, so its explanation is omitted. In Embodiment 3 as well, the distance Diac, as explained in Figure 4, is shorter than in Embodiment 1.

[0121] The manufacturing process for such a floating region PF is described below with reference to Figure 22. The manufacturing process in Figure 22 is performed before the heat treatment shown in Figure 10.

[0122] First, ion-implanted layers PF1 and PF2 are formed by two p-type ion implantation processes as described in Figure 9. The manufacturing process shown in Figure 22 is performed before and after the formation of these ion-implanted layers PF1 and PF2.

[0123] As shown in Figure 22, first, a resist pattern RP4 is formed on the upper surface of the semiconductor substrate SUB. The resist pattern RP4 has a pattern that opens up the positions where the hole barrier region NHB (ion implantation layers NHB1 to NHB3) is formed. Next, p-type ion implantation is performed from the upper side of the semiconductor substrate SUB using the resist pattern RP4 as a mask. This forms an ion implantation layer PF3 in the semiconductor substrate SUB. After that, the resist pattern RP4 is removed by ashing.

[0124] The ion-implanted layer PF3 is formed in a location that overlaps, in a plan view, with the locations where the hole barrier region NHB (ion-implanted layers NHB1 to NHB3) is formed. In other words, the ion-implanted layer PF3 is formed in the semiconductor substrate SUB located between the two ion-implanted layers PF1.

[0125] For the p-type ion implantation for the ion implantation layer PF3, the ion species is boron (B), the energy is 1250 keV, and the dose is 1.25 × 10⁻¹⁰. 13 / cm 2 It will be carried out under these conditions.

[0126] Subsequently, a trench TR is formed, and the heat treatment described in Figure 10 is performed to diffuse the impurities (B) contained in each of the ion implantation layers PF1 to PF3, thereby forming a p-type floating region PF, and to diffuse the impurities (P) contained in each of the ion implantation layers NHB1 to NHB3, thereby forming an n-type hole barrier region NHB.

[0127] In this way, by forming the ion implantation layer PF3 at a position corresponding to the pair of trenches TR of the inactive cell IAC, the same effects as in Embodiment 2 can be obtained in Embodiment 3 as in Embodiment 2.

[0128] Furthermore, in terms of ensuring reliable contact between the two floating regions PF, Embodiment 3 is superior to Embodiment 1. However, Embodiment 3 requires the resist pattern RP4, so Embodiment 1 can suppress the increase in manufacturing costs more effectively than Embodiment 3.

[0129] Furthermore, the technique described in Embodiment 3 is effective in GGEEs structures as well as in Embodiment 2, but is particularly effective in GGEE structures. That is, as explained in Figure 21, even when the distance Wiac is large, as in GGEE structures, the two floating regions PF can be brought into contact more reliably.

[0130] Although the present invention has been specifically described above based on embodiments, the present invention is not limited to these embodiments and can be modified in various ways without departing from its essence. [Explanation of Symbols]

[0131] 100 Semiconductor Equipment Area 1A (part of the cell area) AC Active Cell BS1~BS4 Trench bottom CE collector electrode CF1 conductive film CH hole EE emitter electrode EP Emitter Pad GE1, GE2 gate GI gate insulating film GP Gate Pad GW gate wiring HM Hard Mask IAC Inactive Cell IF1 Sacrificial Oxide Film IL interlayer film NE emitter region NHB Hole Barrier Region NHB1~NHB4 Ion Implantation Layer NS Field Stop Area NV drift region PB Base Area PC collector area PF Floating Area PF1-PF4 Ion Implantation Layers PG Plug PR High-concentration diffusion area RP1~RP4 Resist Pattern SS1~SS8 Trench side SUB Semiconductor Substrate TR Trench

Claims

1. A first-type conductive semiconductor substrate having an upper surface and a lower surface, On the upper surface side of the semiconductor substrate, a first trench, a second trench, a third trench, and a fourth trench formed in the semiconductor substrate, A first electrode is formed inside the first trench via a first insulating film and to which a gate potential is supplied, A second electrode is formed inside the second trench via a second insulating film, and to which the gate potential is supplied, A third electrode is formed inside the third trench via a third insulating film and to which an emitter potential is supplied, A fourth electrode is formed inside the fourth trench via a fourth insulating film, and to which the emitter potential is supplied, On the upper surface side of the semiconductor substrate, a first hole barrier region of the first conductivity type formed in the semiconductor substrate between the first trench and the second trench, A first base region of a second conductivity type opposite to the first conductivity type, formed within the first hole barrier region, The emitter region of the first conductivity type formed within the first base region, On the upper surface side of the semiconductor substrate, a second hole barrier region of the first conductivity type formed in the semiconductor substrate between the third trench and the fourth trench, The second base region of the second conductivity type formed within the second hole barrier region, On the upper surface side of the semiconductor substrate, a first floating region of the second conductivity type formed in the semiconductor substrate between the second trench and the third trench, On the upper surface side of the semiconductor substrate, a second floating region of the second conductivity type formed in the semiconductor substrate along the fourth trench, On the upper surface side of the semiconductor substrate, a third floating region of the second conductivity type formed in the semiconductor substrate along the first trench, Equipped with, The first trench has a first side surface, a second side surface facing the first side surface, and a first bottom surface connecting the first side surface and the second side surface. The second trench has a third side surface, a fourth side surface facing the third side surface, and a second bottom surface connecting the third side surface and the fourth side surface. The third trench has a fifth side surface, a sixth side surface facing the fifth side surface, and a third bottom surface connecting the fifth side surface and the sixth side surface. The fourth trench has a seventh side surface, an eighth side surface opposite to the seventh side surface, and a fourth bottom surface connecting the seventh side surface and the eighth side surface. The first trench and the second trench are provided spaced apart such that the second side and the third side are adjacent to each other. The third trench and the fourth trench are provided spaced apart such that the sixth side and the seventh side are adjacent to each other. The first floating region covers the second bottom surface of the second trench, is formed in the semiconductor substrate between the fourth and fifth sides, and covers the third bottom surface so as to extend beyond the sixth side. The third floating region covers the first bottom surface, The second floating region covers the fourth bottom surface so as to extend beyond the seventh side surface. The first floating region and the third floating region are spaced apart from each other. The first floating region and the second floating region are in contact, A semiconductor device wherein the first distance along the sixth side surface between the second base region and the first floating region is shorter than the second distance along the third side surface between the first base region and the first floating region.

2. In the semiconductor device described in claim 1, A semiconductor device wherein the impurity concentration in the second hole barrier region at a first location near the boundary between the first floating region and the second hole barrier region is lower than the impurity concentration in the first hole barrier region at the same depth as the first location.

3. In the semiconductor device described in claim 1, A semiconductor device in which the distance between the sixth side and the seventh side is shorter than the distance between the second side and the third side.

4. In the semiconductor device described in claim 1, A semiconductor device in which the distance between the sixth side and the seventh side is the same as the distance between the second side and the third side.

5. (a) A step of preparing a semiconductor substrate of a first conductivity type having an upper surface and a lower surface, (b) A step of forming a first hole barrier region of the first conductivity type and a second hole barrier region of the first conductivity type in the semiconductor substrate on the upper surface side of the semiconductor substrate. (c) A step of forming a first floating region of a second conductivity type opposite to the first conductivity type in the semiconductor substrate on the upper surface side of the semiconductor substrate. (d) A step of forming a first trench, a second trench, a third trench and a fourth trench in the semiconductor substrate on the upper surface side of the semiconductor substrate. (e) After step (d), a step of forming a first insulating film inside the first trench, a second insulating film inside the second trench, a third insulating film inside the third trench, and a fourth insulating film inside the fourth trench. (f) After step (e), a step of forming a first electrode inside the first trench via the first insulating film, forming a second electrode inside the second trench via the second insulating film, forming a third electrode inside the third trench via the third insulating film, and forming a fourth electrode inside the fourth trench via the fourth insulating film. (g) After step (f), a step of forming a first base region of the second conductivity type within the first hole barrier region and a second base region of the second conductivity type within the second hole barrier region. (h) After step (g), a step of forming an emitter region of the first conductivity type within the first base region, Equipped with, The first trench has a first side surface, a second side surface facing the first side surface, and a first bottom surface connecting the first side surface and the second side surface. The second trench has a third side surface, a fourth side surface facing the third side surface, and a second bottom surface connecting the third side surface and the fourth side surface. The third trench has a fifth side surface, a sixth side surface facing the fifth side surface, and a third bottom surface connecting the fifth side surface and the sixth side surface. The fourth trench has a seventh side surface, an eighth side surface opposite to the seventh side surface, and a fourth bottom surface connecting the seventh side surface and the eighth side surface. The first trench and the second trench are provided spaced apart such that the second side and the third side are adjacent to each other. The third trench and the fourth trench are provided spaced apart such that the sixth side and the seventh side are adjacent to each other. The first hole barrier region is formed in the semiconductor substrate between the second side surface and the third side surface. The second hole barrier region is formed in the semiconductor substrate between the sixth and seventh sides, The first floating region is formed in the semiconductor substrate between the fourth and fifth sides, covers the second bottom surface, and covers the third bottom surface so as to extend beyond the sixth side surface. A gate potential is supplied to the first electrode and the second electrode. The third electrode and the fourth electrode are supplied with emitter potential. In step (c), a second floating region of the second conductivity type is formed in the semiconductor substrate on the eighth side, and a third floating region of the second conductivity type is formed in the semiconductor substrate on the first side. The third floating region covers the first bottom surface, The second floating region covers the fourth bottom surface so as to extend beyond the seventh side surface. The first floating region and the third floating region are spaced apart from each other. The first floating region and the second floating region are in contact, A method for manufacturing a semiconductor device, wherein the first distance between the second base region and the first floating region is shorter than the second distance between the first base region and the first floating region.

6. In the method for manufacturing a semiconductor device according to claim 5, The aforementioned second distance is the distance along the aforementioned third side, A method for manufacturing a semiconductor device, wherein the first distance is the distance along the sixth side surface.

7. In the method for manufacturing a semiconductor device according to claim 5, The above step (c) is, (c1) A step of forming a first resist pattern on the upper surface of the semiconductor substrate, (c2) A step of forming a first ion implantation layer, a second ion implantation layer, and a third ion implantation layer in the semiconductor substrate by performing first ion implantation from the upper surface side of the semiconductor substrate using the first resist pattern as a mask. (c3) Using the first resist pattern as a mask, a second ion implantation is performed from the upper side of the semiconductor substrate to form a fourth ion implantation layer in the semiconductor substrate at a position overlapping with the first ion implantation layer in a plan view, a fifth ion implantation layer in the semiconductor substrate at a position overlapping with the second ion implantation layer in a plan view, and a sixth ion implantation layer in the semiconductor substrate at a position overlapping with the third ion implantation layer in a plan view. (c4) After the steps of (c2) and (c3), a step of removing the first resist pattern, (c5) After step (c4), the semiconductor substrate is subjected to a first heat treatment to diffuse impurities contained in the first ion implantation layer and the fourth ion implantation layer to form the first floating region, diffuse impurities contained in the second ion implantation layer and the fifth ion implantation layer to form the second floating region, and diffuse impurities contained in the third ion implantation layer and the sixth ion implantation layer to form the third floating region. Includes, The energy of the first ion implantation is greater than the energy of the second ion implantation. The (d) step is a method for manufacturing a semiconductor device, performed between the (c4) step and the (c5) step.

8. In the method for manufacturing a semiconductor device according to claim 7, (c6) Between step (c4) and step (d), a step of performing a second heat treatment on the semiconductor substrate to activate impurities contained in each of the first ion implantation layer, the second ion implantation layer, the third ion implantation layer, the fourth ion implantation layer, the fifth ion implantation layer and the sixth ion implantation layer, Furthermore, A method for manufacturing a semiconductor device, wherein the first heat treatment is performed under conditions of higher temperature and longer duration than the second heat treatment.

9. In the method for manufacturing a semiconductor device according to claim 7, The above step (c) is performed before the above step (c5), (c7) A step of forming a second resist pattern on the upper surface of the semiconductor substrate, (c8) A step of forming a seventh ion-implanted layer in the semiconductor substrate located between the first ion-implanted layer and the second ion-implanted layer by performing a third ion implantation from the upper side of the semiconductor substrate using the second resist pattern as a mask. (c9) After step (c8), a step of removing the second resist pattern, It further includes, In step (c5), the impurities contained in the first ion implantation layer, the fourth ion implantation layer and the seventh ion implantation layer are activated to form the first floating region, and the impurities contained in the second ion implantation layer, the fifth ion implantation layer and the seventh ion implantation layer are activated to form the second floating region. The energy of the third ion implantation is greater than the energy of the second ion implantation. The (d) step is a method for manufacturing a semiconductor device, performed between the (c9) step and the (c5) step.

10. In the method for manufacturing a semiconductor device according to claim 5, The above step (c) is, (c10) A step of forming a first resist pattern on the upper surface of the semiconductor substrate, (c11) A step of forming a first ion implantation layer and a third ion implantation layer in the semiconductor substrate by performing first ion implantation from the upper surface side of the semiconductor substrate using the first resist pattern as a mask. (c12) After step (c11), a step of removing the first resist pattern, (c13) A step of forming a second resist pattern on the upper surface of the semiconductor substrate, (c14) Using the second resist pattern as a mask, a second ion implantation is performed from the upper side of the semiconductor substrate to form a fourth ion implantation layer and a fifth ion implantation layer in the semiconductor substrate at a position overlapping with the first ion implantation layer in a plan view, and a sixth ion implantation layer is formed in the semiconductor substrate at a position overlapping with the third ion implantation layer in a plan view. (c15) After step (c14), a step of removing the second resist pattern, (c16) After steps (c12) and (c15), the semiconductor substrate is subjected to a first heat treatment to diffuse impurities contained in the first ion implantation layer and the fourth ion implantation layer to form the first floating region, diffuse impurities contained in the first ion implantation layer and the fifth ion implantation layer to form the second floating region, and diffuse impurities contained in the third ion implantation layer and the sixth ion implantation layer to form the third floating region. Includes, The first ion implantation layer is also formed at a position that overlaps in a plan view with the position where the second hole barrier region is formed. The energy of the first ion implantation is greater than the energy of the second ion implantation. A method for manufacturing a semiconductor device, wherein step (d) is performed after steps (c12) and (c15), and before step (c16).

11. In the method for manufacturing a semiconductor device according to claim 10, (c17) After steps (c12) and (c15), and before step (d), a step of performing a second heat treatment on the semiconductor substrate to activate impurities contained in each of the first ion implantation layer, the third ion implantation layer, the fourth ion implantation layer, the fifth ion implantation layer and the sixth ion implantation layer, Furthermore, A method for manufacturing a semiconductor device, wherein the first heat treatment is performed under conditions of higher temperature and longer duration than the second heat treatment.

12. In the method for manufacturing a semiconductor device according to claim 7, A method for manufacturing a semiconductor device, wherein the distance between the sixth side and the seventh side is shorter than the distance between the second side and the third side.

13. In the method for manufacturing a semiconductor device according to claim 9, A method for manufacturing a semiconductor device, wherein the distance between the sixth side and the seventh side is the same as the distance between the second side and the third side.

14. In the method for manufacturing a semiconductor device according to claim 10, A method for manufacturing a semiconductor device, wherein the distance between the sixth side and the seventh side is the same as the distance between the second side and the third side.

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