Plasma processing using pulsed voltage and high-frequency power

Abstract

To provide an apparatus and method for the plasma processing of a substrate in a processing chamber.SOLUTION: More specifically, embodiments of the present disclosure describe a biasing scheme that is configured to provide a radio frequency (RF) waveform from an RF power supply to one or more electrodes within a processing chamber and provide a pulsed-voltage (PV) waveform delivered from one or more pulsed-voltage (PV) generators to the one or more electrodes within the processing chamber. A plasma process disclosed in the present specification can be used to control the shape of an ion energy distribution function (IEDF) and control the interaction of the plasma with a surface of a substrate during plasma processing.SELECTED DRAWING: Figure 1A

Description

[Technical Field]

[0001] The embodiments described herein generally relate to hardware and processes for semiconductor device manufacturing, and more specifically to apparatus and methods for controlling the supply of power to a plasma formed in a plasma processing chamber used in semiconductor manufacturing. [Background technology]

[0002] Reliably generating high aspect ratio features is one of the key technical challenges for very large-scale integration (VLSI) and ultra-large-scale integration (ULSI) of next-generation semiconductor devices. One method for forming high aspect ratio features is to use plasma-assisted etching processes, such as reactive ion etching (RIE) plasma processes, to form high aspect ratio openings in material layers, such as the dielectric layer of a substrate. In a typical RIE plasma process, plasma is formed in an RIE processing chamber, and ions from the plasma are accelerated toward the substrate surface to form openings in material layers located beneath a mask layer formed on the substrate surface.

[0003] A typical reactive ion etching (RIE) plasma processing chamber includes a radio frequency (RF) bias power supply that provides an RF voltage to a "power electrode" (e.g., a bias electrode), such as a metal plate, positioned adjacent to an "electrostatic chuck" (ESC) assembly, usually referred to as the "cathode." The power electrode may be capacitively coupled to the plasma of the processing system via a thick layer of dielectric material (e.g., ceramic) that is part of the ESC assembly. In capacitively coupled gas discharge, the plasma is generated by using a radio frequency (RF) power supply coupled to the RF electrode ("RF matched") via an RF matching network, which adjusts the apparent load to 50Ω to minimize reflected power and maximize power supply efficiency. When an RF voltage is applied to the power electrode, an electron-donating plasma sheath (also referred to as the "cathode sheath") is formed across the processing surface of the substrate positioned on the substrate support surface of the ESC assembly during processing. The applied RF field is rectified by the nonlinear properties of the plasma sheath, which are similar to those of a diode, resulting in a DC voltage drop, or "self-bias," between the substrate and the plasma, making the substrate potential negative relative to the plasma potential. This voltage drop determines the average energy of the plasma ions accelerated toward the substrate, and therefore the etch anisotropy. More specifically, the ion orientation, feature profile, and etch selectivity relative to the mask and stop layers are controlled by the ion energy distribution function (IEDF). In an RF-biased plasma, the IEDF typically has two non-discrete peaks at low and high energies, and an ion population with energies spanning the range between the two peaks. The presence of an ion population between the two peaks of the IEDF reflects the fact that the voltage drop between the substrate and the plasma oscillates at the RF bias frequency. Using a lower frequency RF bias power supply to achieve a higher self-bias voltage can result in a considerably larger energy difference between these two peaks, and since the etch profile by ions at the lower energy peaks is more isotropic, the walls of the etched features may warp.Low-energy ions cannot reach the corners as effectively as high-energy ions at the bottom of etched features (e.g., due to charging effects), resulting in insufficient sputtering of the mask material. This is important in high-aspect-ratio etching applications such as hard mask apertures or derivative type etching. As feature sizes continue to decrease and aspect ratios increase, while the requirements for controlling feature profiles become more stringent, it is increasingly desirable to obtain well-controlled IEDF on the substrate surface during processing.

[0004] In other conventional plasma process and processing chamber designs, it has been found that a wide variety of RF frequencies can be supplied to one or more electrodes within the plasma processing chamber to control various plasma properties such as plasma density, ion energy, and / or plasma chemistry. However, it has been found that supplying multiple conventional sinusoidal waveforms from two or more RF sources, each configured to supply a different RF frequency, fails to properly or desirablely control the sheath characteristics, resulting in undesirable arc generation problems. Furthermore, due to direct or capacitive coupling between RF sources during processing, each RF source may induce an RF current, which is supplied to the output of other connected RF sources (often referred to as "crosstalk"), causing power to deviate from the intended load (plasma) and, in some cases, damage each of the RF sources.

[0005] Therefore, in this field, there is a need for novel, robust, and reliable plasma treatment and biasing methods that, by maintaining a nearly constant sheath voltage, generate repeatable and desirable IEDFs on the substrate surface, enabling precise control over the shape of the IEDFs, and in some cases even allowing the formation of etch profiles of features on the substrate surface. [Overview of the project]

[0006] This disclosure generally includes a plasma processing chamber with a substrate support assembly, a pulsed voltage waveform generator, a first filter assembly, a radio frequency (RF) power supply, and a second filter assembly. The substrate support assembly includes a substrate support surface, a support base, and a bias electrode disposed between the support base and the substrate support surface, wherein a first dielectric layer is disposed between the support base and the bias electrode, and a second dielectric layer is disposed between the bias electrode and the substrate surface. A pulsed voltage waveform generator, configured to generate a pulsed voltage signal including a pulsed voltage waveform, is electrically coupled to the bias electrode. The first filter assembly is electrically coupled between the pulsed voltage waveform generator and the bias electrode. The radio frequency (RF) power supply is configured to generate an RF signal including a high-frequency waveform and is electrically coupled to the support base or the bias electrode. The second filter assembly is electrically coupled between the radio frequency power supply and the support base or the bias electrode. In some configurations, the second filter assembly is electrically coupled between the radio frequency power supply and the radio frequency matching, and the radio frequency matching is electrically coupled between the radio frequency power supply and the support base or the bias electrode. In some other configurations, the high-frequency matching is located between the second filter assembly and the support base or bias electrode.

[0007] Embodiments of the present disclosure may further provide a method for processing a substrate in a plasma processing chamber, the method comprising supplying a high-frequency signal to a support base disposed inside a substrate support assembly using a high-frequency power supply electrically coupled to the support base via a pulsed voltage filter assembly, and establishing a first pulsed voltage waveform on a bias electrode disposed inside the substrate support assembly using a first pulsed voltage waveform generator electrically coupled to a bias electrode via a first high-frequency filter assembly. The bias electrode is disposed between the support base and the substrate support surface of the substrate support assembly. A first dielectric layer is disposed between the support base and the bias electrode, and a second dielectric layer is disposed between the bias electrode and the substrate support surface.

[0008] Embodiments of the present disclosure may further provide a method for processing a substrate in a plasma processing chamber, the method comprising: supplying a high-frequency signal to a support base disposed inside a substrate support assembly using a high-frequency power supply electrically coupled to the support base via a pulsed voltage filter assembly; establishing a first pulsed voltage waveform on a bias electrode disposed inside the substrate support assembly using a first pulsed voltage waveform generator electrically coupled to a bias electrode via a first high-frequency filter assembly; and establishing a second pulsed voltage waveform on an edge control electrode disposed inside the substrate support assembly using a second pulsed voltage waveform generator electrically coupled to an edge control electrode via a second high-frequency filter assembly. The bias electrode is disposed between the support base and the substrate support surface of the substrate support assembly. A first dielectric layer is disposed between the support base and the bias electrode, and a second dielectric layer is disposed between the bias electrode and the substrate support surface, with the edge control electrode surrounding at least a portion of the bias electrode.

[0009] Embodiments of the present disclosure may further provide a plasma processing chamber comprising a substrate support assembly, a pulse voltage waveform generator, a high-frequency filter assembly, a high-frequency power supply, and a pulse voltage filter assembly. The substrate support assembly comprises a substrate support surface, a support base, and a first bias electrode disposed between the support base and the substrate support surface, wherein a first dielectric layer is disposed between the support base and the first bias electrode, and a second dielectric layer is disposed between the first bias electrode and the substrate support surface. The pulse voltage waveform generator is configured to establish a pulse voltage waveform on the first bias electrode and is electrically coupled to the first bias electrode via a first conductor. The high-frequency filter assembly is electrically coupled to the pulse voltage waveform generator and the first conductor. The high-frequency power supply is configured to establish a high-frequency voltage waveform on the support base or the first bias electrode and is electrically coupled to the support base or the first bias electrode via a second conductor. The pulse voltage filter assembly is electrically coupled to the high-frequency power supply and the second conductor.

[0010] Embodiments of the present disclosure may further provide a plasma processing chamber comprising a substrate support assembly, a first pulse voltage waveform generator, a first high-frequency filter assembly, a second pulse voltage waveform generator, a second high-frequency filter assembly, a high-frequency power supply, and a pulse voltage filter assembly. The substrate support assembly comprises a substrate support surface, a support base, a first bias electrode disposed between the support base and the substrate support surface, and an edge control electrode, wherein a first dielectric layer is disposed between the support base and the first bias electrode, and a second dielectric layer is disposed between the first bias electrode and the substrate support surface. The first pulse voltage waveform generator is configured to establish a pulse voltage signal waveform at the first bias electrode and is electrically coupled to the first bias electrode via a first conductor. The first high-frequency filter assembly is electrically coupled to the first pulse voltage waveform generator and the first conductor. The second pulse voltage waveform generator is configured to establish a pulse voltage waveform at the edge control electrode and is electrically coupled to the edge control electrode via a second conductor. A second high-frequency filter assembly is electrically coupled between a second pulse voltage waveform generator and a second conductor. A high-frequency power supply is configured to establish a high-frequency waveform on a support base or a first bias electrode and is electrically coupled to the support base or the first bias electrode via a third conductor. A pulse voltage filter assembly is electrically coupled between the high-frequency power supply and the third conductor.

[0011] Embodiments of the present disclosure may provide a pulse voltage subsystem assembly comprising a pulse voltage generation unit housing and a junction box housing. The pulse voltage generation unit housing may include a first pulse voltage waveform generator electrically coupled to a first generator output coupling assembly. The junction box housing may include a first bias compensation module compartment and a high-frequency filter compartment. The first bias compensation module compartment includes a first blocking capacitor electrically coupled between the output coupling assembly of the first bias compensation module compartment and the first generator output coupling assembly, and a first DC power supply having positive and negative terminals electrically coupled to the output coupling assembly of the first bias compensation module compartment. The high-frequency filter compartment includes a first high-frequency filter assembly electrically coupled between the first high-frequency filter output coupling assembly and the output coupling assembly of the first bias compensation module compartment. The pulse voltage subsystem assembly is configured to be coupled to a plasma processing chamber. The first high-frequency filter output coupling assembly is configured to be electrically coupled to a first electrode disposed within the plasma processing chamber.

[0012] Embodiments of the present disclosure may further provide a pulse voltage subsystem assembly including a pulse voltage generation unit housing and a junction box housing. The pulse voltage generation unit housing includes a first pulse voltage waveform generator electrically coupled to a first generator output coupling assembly and a second pulse voltage waveform generator electrically coupled to a second generator output coupling assembly. The junction box housing includes a first bias compensation module compartment, a second bias compensation module compartment and a high-frequency filter compartment. The first bias compensation module compartment includes a first blocking capacitor electrically coupled between the output coupling assembly of the first bias compensation module compartment and the first generator output coupling assembly, and the first DC power supply has positive and negative terminals electrically coupled to the output coupling assembly of the first bias compensation module compartment. The second bias compensation module compartment includes a second blocking capacitor electrically coupled between the output coupling assembly of the second bias compensation module compartment and the second generator output coupling assembly, and the second DC power supply has positive and negative terminals electrically coupled to the output coupling assembly of the second bias compensation module compartment. The high-frequency filter section includes a first high-frequency filter assembly electrically coupled between a first high-frequency filter output coupling assembly and the output coupling assembly of a first bias compensation module section, and a second high-frequency filter assembly electrically coupled between a second high-frequency filter output coupling assembly and the output coupling assembly of a second bias compensation module section. The pulse voltage subsystem assembly is configured to be coupled to the plasma processing chamber. The first high-frequency filter output coupling assembly is configured to be electrically coupled to a first electrode and a second electrode disposed within the plasma processing chamber.

[0013] A more detailed description of the disclosure, which is briefly summarized above, can be obtained by referring to the embodiments, some of which are shown in the accompanying drawings, so that the features of the disclosure listed above may be understood in detail. However, it should be noted that the accompanying drawings are illustrative embodiments only and should not be considered to limit the scope of the exemplary embodiments, leaving room for other equally effective embodiments. [Brief explanation of the drawing]

[0014] [Figure 1A] This is a schematic cross-sectional view of a processing chamber configured to carry out the method described herein according to one embodiment. [Figure 1B] This is a schematic cross-sectional view of a processing chamber configured to carry out the method described herein according to one embodiment. [Figure 1C] This is a schematic cross-sectional view of a packaging assembly coupled to a processing chamber according to one embodiment. [Figure 1D] This is a schematic cross-sectional view of an alternative version of a packaging assembly coupled to a processing chamber, according to one embodiment. [Figure 2] This is a simplified schematic diagram of a bias scheme that can be used with the processing chamber shown in Figure 1A or Figure 1B, according to one embodiment. [Figure 3A] This is a functional equivalent circuit diagram of a negative pulse bias scheme that can be executed in the processing chamber shown in Figure 1A or Figure 1B, according to one embodiment. [Figure 3B] This is a functional equivalent circuit diagram of a positive pulse bias scheme that can be executed in the processing chamber shown in Figure 1A or Figure 1B, according to one embodiment. [Figure 3C] This is a functional equivalent circuit diagram of a Coulomb electrostatic chuck (ESC) that can be used in the processing chamber shown in Figure 1A or Figure 1B, according to one embodiment. [Figure 3D] This is a functional equivalent circuit diagram of a Johnsen-Rahbek type ESC that can be used in the processing chamber shown in Figure 1A or Figure 1B, according to one embodiment. [Figure 4A] This figure shows an example of a negative pulse voltage (PV) waveform established on the bias electrode and substrate according to one embodiment. [Figure 4B] This figure shows an example of a series of pulsed voltage (PV) waveform bursts according to one or more embodiments. [Figure 4C] This figure shows an example of a series of pulsed voltage (PV) waveform bursts according to one or more embodiments. [Figure 4D] This figure shows an example of an ion energy distribution function (IEDF) formed by a series of pulsed voltage (PV) waveform bursts according to one or more embodiments. [Figure 5A] This figure shows an example of a negative pulse voltage (PV) waveform established at a bias electrode according to one embodiment. [Figure 5B] This figure shows an example of a shaped pulse voltage (PV) waveform established at a bias electrode according to one embodiment. [Figure 5C] This figure shows an example of a positive pulse voltage (PV) waveform established at the bias electrode according to one embodiment. [Figure 5D] This figure shows a comparison of negative pulse voltage (PV) waveforms and positive pulse voltage (PV) waveforms established on the substrate during processing, according to one embodiment. [Figure 6A] This figure shows an example of a high-frequency (RF) waveform according to one embodiment. [Figure 6B] This figure shows an example of a pulsed radio frequency (RF) waveform according to one embodiment. [Figure 6C] This figure shows examples of radio frequency (RF) waveforms and pulsed voltage (PV) waveforms that can be supplied to one or more electrodes according to one or more embodiments. [Figure 6D] This figure shows examples of radio frequency (RF) waveforms and pulsed voltage (PV) waveforms that can be supplied to one or more electrodes according to one or more embodiments. [Figure 6E] This figure shows examples of radio frequency (RF) waveforms and pulsed voltage (PV) waveforms that can be supplied to one or more electrodes according to one or more embodiments. [Figure 6F] This figure shows examples of radio frequency (RF) waveforms and pulsed voltage (PV) waveforms that can be supplied to one or more electrodes according to one or more embodiments. [Figure 6G] This figure shows examples of radio frequency (RF) waveforms and pulsed voltage (PV) waveforms that can be supplied to one or more electrodes according to one or more embodiments. [Figure 6H] This figure shows examples of radio frequency (RF) waveforms and pulsed voltage (PV) waveforms that can be supplied to one or more electrodes according to one or more embodiments. [Modes for carrying out the invention]

[0015] For ease of understanding, the same reference numerals are used where possible to indicate identical elements common to each figure. It is intended that elements and features of one embodiment can be usefully incorporated into other embodiments without further detail.

[0016] Embodiments of the disclosure provided herein include apparatus and methods for plasma processing a substrate in a processing chamber. More specifically, embodiments of the disclosure describe bias schemes configured to supply a radio frequency (RF) waveform from an RF power supply to one or more electrodes in the processing chamber and a pulsed voltage (PV) waveform supplied from one or more pulsed voltage (PV) generators to one or more electrodes in the processing chamber. Generally, the generated RF waveform is configured to establish and maintain plasma inside the processing chamber, and the supplied PV waveform is configured to establish a substantially constant sheath voltage across the surface of the substrate, so that a desired ion energy distribution function (IEDF) is brought to the surface of the substrate during one or more plasma processing steps performed in the processing chamber. The plasma processes disclosed herein can be used to control the shape of the IEDF during processing to control the interaction between the surface of the substrate and the plasma. In some configurations, the plasma processes disclosed herein are used to control the profile of features formed on the surface of the substrate during processing. In some embodiments, the pulsed voltage waveform is established by a PV power supply electrically coupled to bias electrodes disposed in a substrate support assembly disposed in the plasma processing chamber.

[0017] During some semiconductor plasma processes, ions are intentionally accelerated toward a substrate by a voltage drop across an electron-donating sheath that occurs over the substrate placed on top of a substrate support assembly 136 (Figures 1A-1C). Without intending to limit the scope of the disclosure provided herein, the substrate support assembly 136 is referred to herein, in most cases, as the “cathode assembly” or “cathode.” In some embodiments, the substrate support assembly 136 includes a substrate support 105 and a support base 107. The substrate support 105 may include an electrostatic chuck (ESC) assembly configured to chucking (e.g., holding) a substrate on a substrate receiving surface 105A.

[0018] In some embodiments of the disclosure provided herein, the processing chamber is configured to bring about a capacitively coupled gas discharge so that plasma is generated by using an RF power supply assembly which includes an RF power supply coupled to an RF electrode via an RF matching network ("RF matching"). The RF matching network is configured to adjust the apparent load to 50Ω in order to minimize reflected power and maximize power supply efficiency. In some embodiments, the RF electrode includes a metal plate positioned parallel to the plasma-facing surface of the substrate.

[0019] In addition, during the plasma processing methods disclosed herein, a sheath of the ion-accelerating cathode is generally formed during plasma processing by using a pulse voltage (PV) generator configured to establish a pulse voltage waveform on one or more bias electrodes 104 (Figures 1A-1B) disposed within a substrate support assembly 136. In some embodiments, one or more bias electrodes 104 include a chucking electrode separated from the substrate by a thin layer of dielectric material formed within the substrate support assembly 136 (e.g., an electrostatic chuck (ESC) assembly), and an optional edge control electrode disposed within or below an edge ring 114 surrounding the substrate 103 when the substrate 103 is disposed on the substrate support surface 105A of the substrate support assembly 136. This pulsed voltage waveform (PVWF) may be configured such that a nearly constant sheath voltage (e.g., the difference between the plasma potential and the substrate potential) is formed for a substantial portion of the pulse period of the PV waveform, as will be discussed further below. This substantial portion corresponds to a single (narrow) peak containing the ion energy distribution function (IEDF) of ions reaching the substrate during this portion of the pulse period, which is also referred to herein as the "ion current phase."

[0020] However, as described above, due to direct or capacitive coupling between the RF power supply assembly and the PV generator assembly during processing, the interaction between the output from the RF power supply and the output from the PV generator causes the power to deviate not only from the intended (plasma) load but may also damage each of the RF and PV sources, even without using the filtering schemes and / or processing methods disclosed herein. Therefore, the apparatus and methods disclosed herein are configured to provide a method for combining RF power and PV power to one or more electrodes (e.g., cathodes) of a plasma processing chamber by coupling each generator to its respective electrode via one or more waveform-dependent filter assemblies, such that at least one or more waveform-dependent filter assemblies do not significantly interfere with the power supply from each RF power supply and PV generator to the plasma.

[0021] Example of a plasma processing chamber Figure 1A is a schematic cross-sectional view of a processing chamber 100 in which a composite load 130 (Figures 3A-3B) is formed during plasma processing. Figures 3A-3B are examples of simplified electrical circuits 140 of pulse voltage and RF bias schemes that can be implemented using the components of the processing chamber 100. The processing chamber 100 is configured to implement one or more of the bias schemes according to one or more embodiments proposed herein. In one embodiment, the processing chamber is a plasma processing chamber, such as a reactive ion etch (RIE) plasma chamber. In some other embodiments, the processing chamber is a plasma-assisted deposition chamber, such as a plasma-assisted chemical vapor deposition (PECVD) chamber, a plasma-assisted physical vapor deposition (PEPVD) chamber, or a plasma-assisted atomic layer deposition (PEALD) chamber. In some other embodiments, the processing chamber is a plasma processing chamber, or a plasma-based ion implantation chamber, such as a plasma doping (PLAD) chamber. In some embodiments, the plasma source is a capacitively coupled plasma (CCP) source including electrodes (e.g., a chamber lid 123) disposed within the processing volume facing the substrate support assembly 136. As shown in Figure 1A, the opposing electrodes, such as the chamber lid 123 located on the opposite side of the substrate support assembly 136, are electrically grounded. However, in other alternative embodiments, the opposing electrodes are electrically coupled to a radio frequency power supply, as shown in Figure 1B. In yet another embodiment, the processing chamber includes, as an alternative or in addition, an inductively coupled plasma (ICP) source electrically coupled to a radio frequency (RF) power supply.

[0022] The processing chamber 100 also includes a chamber body 113, including a chamber lid 123, one or more side walls 122, and a chamber base 124, which define the processing volume 129. The one or more side walls 122 and the chamber base 124 generally consist of a material sized and molded to form structural support for the elements of the processing chamber 100, and are configured to withstand the pressure and energy applied to them while plasma 101 is generated in a vacuum environment maintained within the processing volume 129 of the processing chamber 100 during processing. In one example, the one or more side walls 122 and the chamber base 124 are formed from a metal such as aluminum, an aluminum alloy, or stainless steel. A gas inlet 128, disposed through the chamber lid 123, is used to supply one or more processing gases to the processing volume 129 from a processing gas source 119 fluidly coupled thereto. The substrate 103 is moved in and out of the processing volume 129 through an opening (not shown) in one or more side walls 122, and the opening is sealed by a slit valve (not shown) during plasma processing of the substrate 103. Here, the substrate 103 is moved between the substrate receiving surface 105A of the ESC substrate support 105 using a lift pin system (not shown).

[0023] In some embodiments, the high-frequency power supply assembly 160 is configured to supply RF power to a support base 107 disposed within the substrate support assembly 136 in close proximity to the ESC substrate support 105. The RF power supplied to the support base 107 is configured to ignite and maintain a processing plasma 101 formed using a processing gas distributed within the processing volume 129. In some embodiments, the support base 107 is an RF electrode electrically coupled to the high-frequency power supply 118 via an RF matching circuit 161 and a first filter assembly 162, both disposed within the high-frequency power supply assembly 160. In some embodiments, the plasma generator assembly 160 and the high-frequency power supply 118 are used to ignite and maintain the processing plasma 101 using a field generated by the processing gas distributed within the processing volume 129 and the RF power supplied to the support base 107 by the high-frequency power supply 118. The processing volume 129 is fluidly connected to one or more dedicated vacuum pumps via a vacuum suction port 120, so that the processing gas and / or other gases are evacuated and maintained under reduced pressure. The substrate support assembly 136, located within the processing volume 129, is positioned on a grounded support shaft 138 that extends through the chamber base 124. However, in some embodiments, the high-frequency power supply assembly 160 is configured to supply RF power to the support base 107 to a bias electrode 104 located within the substrate support 105.

[0024] The substrate support assembly 136 generally includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107, as briefly discussed above. In some embodiments, the substrate support assembly 136 may further include an insulating plate 111 and a grounding plate 112, as will be further discussed below. The substrate support 105 is disposed on and thermally coupled to the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature between the substrate support 105 and the substrate 103 disposed on the substrate support 105 during substrate processing. In some embodiments, one or more cooling channels (not shown) disposed inside the support base 107 are fluidly connected to a cooling source (not shown), such as a water source, which has relatively high electrical resistance. In some embodiments, a heater (not shown), such as a resistive heating element, is embedded in the dielectric material of the substrate support 105. Here, the support base 107 is formed from a corrosion-resistant thermal conductive material such as a corrosion-resistant metal such as aluminum, an aluminum alloy, or stainless steel, and is bonded to the substrate support using an adhesive or by mechanical means.

[0025] The support base 107 is electrically insulated from the chamber base 124 by an insulating plate 111, with a grounding plate 112 inserted between the insulating plate 111 and the chamber base 124. In some embodiments, the processing chamber 100 further includes a quartz pipe 110 or collar that at least partially surrounds a portion of the substrate support assembly 136 to prevent the ESC substrate support 105 and / or the support base 107 from coming into contact with corrosive processing gases or plasma, cleaning gases or plasma, or their byproducts, so as not to corrode them. Typically, the quartz pipe 110, insulating plate 111, and grounding plate 112 are surrounded by a liner 108, where a plasma screen 109 is located substantially coplanar with the substrate receiving surface of the ESC substrate support 105 to prevent plasma formation in the volume between the liner 108 and one or more side walls 122.

[0026] The substrate support 105 is generally formed from dielectric materials such as bulk sintered ceramic materials, corrosion-resistant metal oxides or metal nitride materials such as aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof. In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded within these dielectric materials. In one configuration, the bias electrode 104 is a chucking electrode used to fix (chuck) the substrate 103 to the substrate receiving surface 105A of the substrate support 105, also referred herein as the ESC substrate support, and to bias the substrate 103 to the processing plasma 101 using one or more of the pulse voltage biasing methods described herein. Generally, the bias electrode 104 is formed from one or more conductive components such as one or more metal meshes, foils, plates, or combinations thereof. In some embodiments, the bias electrode 104 is electrically coupled to a chucking module 116, from which a chucking voltage, such as a static DC voltage of about -5000V to about 5000V, is supplied using a conductor such as a coaxial transmission line 106 (e.g., a coaxial cable). As will be discussed further below, the chucking module 116 includes a bias compensation circuit element 116A (Figures 3A-3B), a DC power supply 155, and a blocking capacitor 153. A chucking module blocking capacitor, also referred to herein as the blocking capacitor 153, is positioned between the output of the pulse voltage waveform generator (PVWG) 150 and the bias electrode 104.

[0027] The bias electrode 104 is spaced from the substrate receiving surface 105A of the substrate support 105 by a layer of dielectric material of the substrate support 105, and thus is spaced from the substrate 103. The effective circuit elements used to model the electrical coupling of the bias electrode 104 to the plasma 101 will vary depending on the type of electrostatic chuck method such as the Coulomb ESC or the Johnsen-Rahbek type ESC utilized within the substrate support 105 to hold the substrate 103 during processing. FIGS. 3C and 3D show the effective circuit elements 191 generated when the Coulomb ESC or the Johnsen-Rahbek type ESC is utilized during plasma processing. Generally, a parallel-plate-like structure formed by the bias electrode 104 and the layer of dielectric material generally has an effective capacitance C E that can be on the order of about 5 nF to about 50 nF. Generally, the thickness of the layer of dielectric material (such as aluminum nitride (AlN), aluminum oxide (Al2O3), etc.) is on the order of about 0.1 mm to about 1 mm, such as about 0.1 mm to about 0.5 mm, for example about 0.3 mm. Here, the bias electrode 104 is electrically coupled to the output of a pulse voltage waveform generator (PVWG) 150 using an external conductor such as a transmission line 106 disposed within a support shaft 138. In some embodiments, the dielectric material and layer thickness are selected such that the chuck capacitance C ESC of the layer of dielectric material is on the order of about 5 nF to about 50 nF, such as about 7 to about 10 nF for example.

[0028] In the more complex Johnsen-Rahbek type ESC model shown in FIG. 3D, the circuit model, as shown, includes a combination of the chuck capacitance C ESC of the ESC dielectric material, the resistance R CER of the ESC dielectric material, the capacitance C abt of the gap, the capacitance C sub of the substrate, and the resistance R sub of the substrate. The capacitance C abt of the gap generally consists of the gas-containing spaces above and below the substrate disposed on the substrate support 105. The capacitance C abtThis is the chuck capacitance C ESC It is expected to have the same capacitance range as [the other component].

[0029] In some applications, the substrate 103 is typically made of a thin layer of semiconductor and / or dielectric material, and therefore can be electrically considered as part of the ESC dielectric layer disposed between the bias electrode 104 and the substrate receiving surface 105A. Thus, in some applications, the chuck capacitance C ESC This is the difference between ESC capacitance and substrate capacitance (i.e., substrate capacitance C). sub It is approximated by the series capacitance of the combination of ). However, in the case of a Coulomb chuck, the substrate capacitance C sub Since this is generally very large (>10nF) or the substrate may be conductive (infinite capacitance), the series capacitance is mainly capacitance C. ESC Determined by [the following]. In this case, the effective capacitance C E As shown in Figure 3C, the actual chuck capacitance C ESC It is equal to . In the case of a "Johnsen-Rahbek type ESC," the ESC dielectric layer is not a perfect insulator and is "leaky" in the sense that it has some conductivity, for example, because the dielectric material can be doped aluminum nitride (AlN) with a dielectric constant (ε) of about 9. However, the effective capacitance of a Johnsen-Rahbek type ESC should be similar to that of a Coulomb-chuck. In one example, the volume resistivity of the dielectric layer in a Johnsen-Rahbek type ESC is about 10 12 Less than ohms-cm (Ω-cm), or about 10 10 Less than Ω-cm, and even 10 8 Ω-cm~10 12 It could be Ω-cm.

[0030] The edge control electrode 115, further included in the substrate support assembly 136, is located beneath the edge ring 114 and surrounds the bias electrode 104. When biased, depending on its position relative to the substrate 103, it can affect or alter a portion of the generated plasma 101, either on or outside the edge of the substrate 103. The edge control electrode 115 is biased using a pulsed voltage waveform generator (PVWG) 150 separate from the pulsed voltage waveform generator (PVWG) 150 used to bias the bias electrode 104. In one configuration, the first PV waveform generator 150 of the first PV source assembly 196 is configured to bias the bias electrode 104, and the second PV waveform generator 150 of the second PV source assembly 197 is configured to bias the edge control electrode 115. In one embodiment, the edge control electrode 115 is located within the region of the substrate support 105, as shown in Figure 1A. Generally, for a processing chamber 100 configured to process a circular substrate, the edge control electrode 115 is annular, fabricated from a conductive material, and configured to surround at least a portion of the bias electrode 104, as shown in Figures 1A and 1B. In some embodiments, the edge control electrode 115 includes a conductive mesh, foil, or plate disposed from the surface 105A of the substrate support 105 at a similar distance (i.e., in the Z direction) from the bias electrode 104, as shown in Figure 1A. In some other embodiments, the edge control electrode 115 includes a conductive mesh, foil, or plate disposed on or within a region of a dielectric pipe 110 (e.g., AlN or Al2O3), the dielectric pipe 110 surrounding at least a portion of the bias electrode 104 and / or the substrate support 105, as shown in Figure 1B. Alternatively, in some other embodiments, the edge control electrode 115 is located inside or coupled to an edge ring 114 disposed adjacent to the substrate support 105. In this configuration, the edge ring 114 is formed from a semiconductor or dielectric material (e.g., AlN, Al2O3, etc.).

[0031] Referring to Figure 1B, in some embodiments, a secondary electrode 104L (e.g., a metal mesh, foil, or plate) further included in the substrate support 105 is electrically coupled to the bias electrode 104 using a plurality of conductive vias 114V. One or more of the vias 114V have a first end electrically in contact with the bias electrode 104 and a second end electrically in contact with the secondary electrode 104L. The secondary electrode 104L, positioned beneath the bias electrode 104, is dimensionally sized, positioned, and aligned to improve control of the plasma sheath and / or plasma uniformity across the surface of the substrate 103 during processing. In some configurations, as shown in Figure 1B, when the bias electrode 104, the secondary electrode 114L, and the edge control electrode 115 are used in combination, the edge control electrode 115 is positioned adjacent to the secondary electrode 104L to desirablely alter the generated plasma 101 at or outside the edge of the substrate 103.

[0032] Referring to Figures 1A and 1B, the support base 107 is spaced from the bias electrode 104 by a portion of dielectric material. In some configurations, the portion of dielectric material is the dielectric material used to form the substrate support 105, extending from the back side of the substrate support 105 to the bias electrode 104. The portion of dielectric material of the substrate support 105 provides the support base capacitance C CL It has an ESC capacitance C, which is schematically shown in Figures 3A and 3B. E It is connected in series with the support base 107. In some embodiments, a portion of the dielectric material disposed between the support base 107 and the bias electrode 104 is thicker than the dielectric material disposed between the bias electrode 104 and the substrate 103, and these dielectric materials are the same material as the substrate support 105 and / or form part of the substrate support 105. In one example, the thickness of a portion of the dielectric material (e.g., Al2O3 or AlN) of the substrate support 105 disposed between the support base 107 and the bias electrode 104 is greater than 1 mm, such as about 1.5 mm to about 20 mm.

[0033] Generally, when low pressure is formed in the processing volume 129 of the processing chamber 100, heat conduction between the surfaces of hardware components, such as between the dielectric material of the substrate support 105 and the substrate 103 disposed on the substrate receiving surface of the substrate support 105, deteriorates, reducing the efficiency of the substrate support in heating and cooling the substrate 103. Therefore, in some processes, a thermally conductive inert heat transfer gas, typically helium, is introduced into a volume (not shown) disposed therein to improve heat transfer between the non-device side of the substrate 103 and the substrate receiving surface 105A of the substrate support 105. The heat transfer gas supplied by a heat transfer gas source (not shown) flows to the back volume through a gas transfer path (not shown) disposed via a support base 107, and is further distributed through the substrate support 105.

[0034] The processing chamber 100 further includes a controller 126, also referred to herein as a processing chamber controller, where the controller 126 includes a central processing unit (CPU) 133, memory 134, and support circuitry 135. The controller 126 is used to control the processing sequence used to process the substrate 103, including the substrate biasing method described herein. The CPU 133 is a general-purpose computer processor and associated subprocessors configured for use in industrial settings for controlling the processing chamber. The memory 134 described herein is generally non-volatile memory and may include random-access memory, read-only memory, floppy disk drives or hard disk drives, or other suitable forms of local or remote digital storage. The support circuitry 135 is conventionally coupled to the CPU 133 and includes a cache, clock circuitry, input / output subsystems, power supplies and similar, and combinations thereof. Software instructions (programs) and data may be encoded and stored in memory 134 for instructing the processor in the CPU 133. A software program (or computer instruction) readable by the CPU 133 in the controller 126 determines the tasks that can be performed by the components of the processing chamber 100. Preferably, the code contained in the program readable by the CPU 133 in the controller 126, when executed by the processor (CPU 133), performs tasks related to monitoring and executing the electrode bias scheme described herein. This program will include instructions used to perform various processing tasks and various processing sequences used to control various hardware and electrical components in the processing chamber 100 to implement the electrode bias scheme described herein.

[0035] During processing, the PV generators 314 inside the PV waveform generators 150 of the first PV source assembly 196 and the second PV source assembly 197 establish pulse voltage waveforms on a load (e.g., composite load 130) disposed with the processing chamber 100. To simplify the discussion without limiting it to the disclosures provided herein, Figures 3A and 3B do not show schematics of the internal components of the second PV source assembly 197 used to bias the edge control electrode 115. The supply of PV waveforms from each of the PV waveform generators 150 is controlled overall using signals supplied from the controller 126. In one embodiment, the PV waveform generator 150A is configured to maintain a substantially constant predetermined positive voltage at its output (i.e., output to ground) by repeatedly opening and closing its internal switch S1 at a predetermined rate over a time interval of a predetermined length that is periodically repeated, as shown in Figure 3A. Alternatively, in one embodiment, the PV waveform generator 150B maintains a substantially constant predetermined negative voltage at its output (i.e., output to ground) by repeatedly opening and closing its internal switch S1 at a predetermined rate over a time interval of a predetermined length that is periodically repeated, as shown in Figure 3B. In Figures 3A and 3B, the PV waveform generators 150A and 150B are summarized into a minimal combination of components important for understanding their role in establishing the desired pulsed voltage waveform at the bias electrode 104. As schematically shown in Figures 3A and 3B, each PV waveform generator 150 would include a PV generator 314 (e.g., a DC power supply) configured to supply a PV waveform to the output 350, and one or more electrical components such as a high repetition rate switch, a capacitor (not shown), an inductor (not shown), a flyback diode (not shown), a power transistor (not shown), and / or a resistor (not shown). Actual PV waveform generators 150 can be obtained based on more complex electrical circuits than those shown in Figures 3A and 3B, and may include any number of internal components to be configured as nanosecond pulse generators.The schematic diagrams in Figures 3A and 3B provide only functional equivalent representations of the components and electrical circuits of the PV waveform generator 150 to the extent necessary to explain the basic operating principle of the PV waveform generator 150, its interaction with the plasma in the processing volume, and its role in establishing pulse voltage waveforms such as input pulse voltage waveforms 401, 431, and 441 (Figures 4A and 4C) at the bias electrode 104. As can be inferred from the schematic diagrams shown in Figures 3A and 3B, when the switch S1 moves from the open (off) position to the closed (on) position, it connects the output of the PV waveform generator 150 to the PV generator 314, which produces a substantially constant output voltage. The PV waveform generator 150 can be used primarily as a charge injector (current source) rather than a constant voltage power supply, and therefore, since the output voltage can change over time even when the switch is closed (on), strict requirements for output voltage stability are not necessary. Furthermore, in some configurations, the PV generator 314 is essentially a source source rather than a sink source, in that it only allows current to flow in one direction (for example, its output can charge a capacitor but cannot discharge it). In addition, when switch S1 remains in the open (off) position, the voltage (V0) across the output of the PV waveform generator 150 is determined not by the PV generator 314, but by the interaction of the internal components of the PV waveform generator 150 with other circuit elements.

[0036] The current feedback output stage 314A is connected at one end to ground and at the other end to the output connection point of the PV waveform generator 150 (i.e., one side of the generator output coupling assembly (not shown)). The current feedback output stage 314A may include elements such as a resistor, a series connection of a resistor and an inductor, a switch S2, and / or a parallel capacitor that allows a positive current flow toward ground.

[0037] A transmission line 131, which forms part of the PV transmission line 157 (Figures 1A-1B), electrically connects the output 350 of the PV waveform generator 150 to the second filter assembly 151. The following discussion will mainly focus on the PV transmission line 157 of the first PV source assembly 196, which is used to couple the PV waveform generator 150 to the bias electrode 104, but the PV transmission line 158 of the second PV source assembly 197 will also contain the same or similar components to the edge control electrode 115 that couples the PV waveform generator 150. Thus, generally, the output 350 of the PV waveform generator 150 is the end, and the output of the PV pulse generator 314 is connected to the output 350 of the PV waveform generator 150 and the current feedback output stage 314A by an internal conductor. The transmission line 131 connects the generator output coupling assembly 181 (Figure 1C), which is located at the output 350 of the PV waveform generator 150, to the second filter assembly 151. The conductors inside the various components of the PV transmission lines 157, 158 may include (a) a coaxial transmission line (e.g., coaxial line 106) which may include a flexible coaxial cable connected in series with a rigid coaxial transmission line, (b) an insulated high-voltage corona-resistant hookup wire, (c) a bare wire, (d) a metal rod, (e) an electrical connector, or (f) any combination of the electrical elements of (a) to (e). The portion of the PV transmission line 157 inside the support shaft 138 and the external conductor portion of the PV transmission line 157 (e.g., the first conductor), such as the bias electrode 104, have some combination of stray capacitance C relative to ground. stray (Figures 3A-3B) should have some combined stray capacitance C to ground. Although not shown in the figures, the outer conductor portion of the PV transmission line 158 (e.g., the second conductor) and the edge control electrode 115 also have some combined stray capacitance C to ground. strayIt should have the following. The internal conductors of the PV waveform generator 150 may include the same basic elements as the external conductors. In the most practical applications, the transmission line 131 should include a line inductance 159, which may include the portion generated by the internal components of the PV waveform generator 150 (i.e., the left side of the generator output coupling assembly 181 (Figures 3A-3B)) and / or the portion that connects the PV waveform generator 150 to the second filter assembly 151 (i.e., the right side of the generator output coupling assembly 181), generated by the external line / cable.

[0038] Returning to Figure 1A, the processing chamber 100 includes a grounded chamber lid 123. In this configuration, which differs overall from conventional plasma processing chamber designs, RF power is supplied instead through a substrate support. Thus, by coupling the RF power supply 118 to the support base 107, the upper electrode can be grounded by the entire ESC, which is functionally part of the cathode assembly, and the current feedback region can be maximized. For plasma processes utilizing RF power supply and PV waveform supply, maximizing the current feedback region by maximizing the grounded area inside the plasma processing chamber minimizes plasma potential jumps during the ESC recharge / sheath collapse phase of the PV waveform cycle generated by the output of the PV waveform generator 150, which will be discussed further below. Thus, the apparatus and methods provided herein improve plasma processing efficiency by minimizing power loss to the chamber walls. The RF power and PV pulse waveform supply methods described herein also provide benefits for certain processes, as they influence and enable improved control of plasma characteristics and radical generation. However, as mentioned above, there is strong capacitive coupling between the support base 107 and the bias electrode 104 via the ESC ceramic layer, and also strong capacitive coupling between the RF transmission line 167 and the PV transmission line 157. Therefore, when both types of power are supplied through the substrate support assembly 136 (i.e., the cathode assembly), each generator induces a current through the other, not only diverting power from the intended (plasma) load but also damaging both generators.

[0039] In another alternative chamber lid 123 configuration, which may be used in conjunction with one or more of the other embodiments disclosed herein, the chamber lid 123 (i.e., the opposing electrodes) is electrically isolated from one or more side walls 122, as shown in Figure 1B, and electrically coupled to a high-frequency power supply 118 via a plasma generator assembly 160. In this configuration, the chamber lid 123 may be driven by the high-frequency power supply 118 to ignite and maintain a processing plasma 101 inside the processing volume 129. In one example, the high-frequency power supply 118 is configured to supply the chamber lid 123 with an RF signal at an RF frequency higher than approximately 300 kHz, such as approximately 300 kHz to 60 MHz, and even approximately 2 MHz to approximately 40 MHz.

[0040] Bias subsystem assembly Figure 1C is a schematic diagram of a processing chamber 100 that includes a bias subsystem assembly 170 configured to separately isolate various electrical components used to generate and control high-frequency and pulsed voltage waveforms and supply them to one or more electrodes, such as a substrate support assembly 136, inside the processing chamber 100. At least due to the configuration and positioning of the bias subsystem assembly 170 inside the processing chamber 100, more repeatable and efficient supply of the generated RF and PV waveforms can be achieved during processing. Using a bias subsystem assembly 170 inside each of several similarly configured processing chambers is thought to help reduce the variability in processing results seen in substrate processing facilities containing many processing chambers and in other substrate processing facilities around the world that contain many processing chambers.

[0041] The bias subsystem assembly 170 will generally include a pulse voltage generation unit housing 172 and a junction box housing 169. The bias subsystem assembly 170 will generally include an electrical circuit containing active power supplies and voltage sources, as well as passive components. The active power supplies may include one or more pulse voltage waveform generators, one or more high-frequency power supplies, and / or one or more DC power supplies. The passive components inside the electrical circuit may include resistors, capacitors, inductors, and diodes. In use, the bias subsystem assembly 170 may be used to combine these power supplies so that the outputs of various types of power supplies can be applied to the same load (e.g., a composite load 130). The load may include a plasma 101 formed in the processing chamber 100, a cathode sheath, a cathode and its power supply system (e.g., a transmission line), as well as stray inductive and capacitive elements.

[0042] In some embodiments, the junction box housing 169 includes one or more bias compensation module compartments 171 and a high-frequency (RF) filter compartment 173. In some embodiments, the bias subsystem assembly 170 also includes an RF supply housing 174. Each of the compartments 171, 172, and 173 and the RF supply housing 174 includes one or more walls 171A, 172A, 173A, and 174A, each of which is at least partially configured to surround internal electrical components and to isolate and insulate them from electrical components inside adjacent housings or from electrical components in the environment outside the processing chamber 100. Generally, only one wall is used to insulate adjacent compartments from each other. As schematically shown in Figures 1C and 1D, in some areas two walls are arranged in a directly adjacent relationship, but a single wall may be used instead of two separate adjacent walls, and this is not intended to limit the scope of the disclosure provided herein. The bias subsystem assembly 170 is positioned or coupled to one or more walls of the processing chamber 100, such as the base 124, to be firmly mounted, to repeatedly define the distance between it and its components, and to avoid strain on any connections between the bias subsystem assembly 170 and other components in the processing chamber 100 (e.g., connections with the substrate support assembly 136). In some embodiments, the surface of the bias subsystem assembly 170 (e.g., the exposed surface of wall 173A) is positioned adjacent to one or more walls of the processing chamber 100 (e.g., the base 124). In some embodiments, the exposed surface of the bias subsystem assembly 170 (e.g., the surface of wall 173A) is positioned at a distance of less than 24 inches 124A (Figure 1C) from the base 124, such as less than 12 inches, or even less than 6 inches. In one example, the exposed surface of wall 173A is coupled directly to the lower surface of the base 124.It is believed that stray inductance and stray capacitance formed in each of these areas of the system can be minimized by optimizing the path selection of current carrier elements interconnecting electrical components within sections 171, 172, and 173 of the bias subsystem assembly 170 and / or the RF supply housing 174, such as the connections between components of the bias compensation section and components of the high-frequency filter section 173, thereby minimizing the connection length. In practice, the bias subsystem assembly 170 can be used to significantly reduce fluctuations in the generated and established waveforms, and thus improve the integrity and repeatability of high-voltage signals supplied to electrodes inside the processing chamber 100, such as electrodes inside the substrate support assembly 136.

[0043] The pulse voltage generation unit housing 172 includes at least one PV waveform generator 150 isolated from electrical components such as the high-frequency filter compartment 173 and the RF supply housing 174 within the bias compensation module compartment 171 by at least a wall 172A. The wall 172A may include a metal sheet box (e.g., an aluminum or SST box) that supports one or more PV waveform generators 150 and is grounded and configured to isolate from any electromagnetic interference generated by internal components of the RF supply housing 174 and / or external components of the processing chamber 100. At the interface between the pulse voltage generation unit housing 172 and the bias compensation module compartment 171, a generator output coupling assembly 181 is used to connect the output 350 of the PV waveform generator 150 to a first portion of the transmission line 131 and electrical components (e.g., a blocking capacitor 153) located within the bias compensation module compartment 171. As used herein, the term “coupling assembly” generally refers to one or more electrical components, such as one or more electrical connectors, individual electrical elements (e.g., capacitors, inductors, and resistors), and / or conductive elements, configured to connect current-carrying elements that electrically couple two or more electrical components.

[0044] One or more bias compensation module compartments 171 include bias compensation circuit elements 116A (Figures 3A-3B) and blocking capacitors 153, which are isolated by at least a wall 171A from electrical components in the pulse voltage generation unit housing 172, the high-frequency filter compartment 173, and the RF supply housing 174. In one embodiment, the bias compensation circuit element 116A is coupled to an externally located DC power supply 155 using a DC power supply coupling assembly 185 of the bias compensation module compartment formed in the wall 171A. Alternatively, in one embodiment (not shown), both the bias compensation circuit element 116A and the DC power supply 155 are located inside the bias compensation module compartment 171 and enclosed by the wall 171A. The wall 171A may include a grounded metal sheet box configured to isolate the components inside the bias compensation module compartment 171 from components inside the pulse voltage generation unit housing 172, any electromagnetic interference generated by the RF supply housing 174, and / or electromagnetic interference outside the processing chamber 100. At the interface between the bias compensation module section 171 and the high-frequency filter section 173, the output coupling assembly 182 of the bias compensation module section is used to connect the bias compensation circuit element 116A, the DC power supply 155, and the blocking capacitor 153 to a second portion of the transmission line 131 and electrical components (e.g., a second filter assembly 151) located within the high-frequency filter section 173.

[0045] The high-frequency filter compartment 173 includes one or more second filter assemblies 151 and chamber interconnection components, isolated by at least a wall 173A from the electrical components within the pulse voltage generation unit housing 172, one or more bias compensation module housings 171, and the RF supply housing 174. The wall 173A may include a grounded metal sheet box configured to isolate the internal components of the high-frequency filter compartment 173 from the internal components of the pulse voltage generation unit housing 172, any electromagnetic interference generated by the RF supply housing 174, and / or electromagnetic interference outside the processing chamber 100. At the interface between the high-frequency filter compartment 173 and the base 124 of the processing chamber 100, a cathode coupling assembly 183 is used to connect the output connection point of the high-frequency filter compartment 173 to a portion of the PV transmission lines 157, 158, which electrically connect the bias subsystem assembly 170 to one of the internal electrodes of the processing chamber 100, such as an electrode inside the substrate support assembly 136.

[0046] The RF supply housing 174 includes an RF matching circuit 161, a first filter assembly 162, an optional high-frequency power supply 118, and other chamber interconnection components, isolated by at least a wall 174A from the electrical components in the pulse voltage generation unit housing 172 and one or more bias compensation module housings 171. The wall 174A may include a grounded metal sheet box configured to isolate the internal components of the RF supply housing 174 from any electromagnetic interference generated by the internal components of the pulse voltage generation unit housing 172 and / or external electromagnetic interference from the processing chamber 100. At the interface between the RF supply housing 174 and the base 124 of the processing chamber 100, a cathode coupling assembly 184 is used to connect the output connection point of the RF supply housing 174 to a portion of the RF transmission line 167, which electrically connects the RF supply housing 174 of the bias subsystem assembly 170 to one of the internal electrodes of the processing chamber 100, such as an electrode inside the substrate support assembly 136. A portion of the RF transmission line 167 inside the support shaft 138 and an external conductor portion of the RF transmission line 167 (e.g., a third conductor), such as the support base 107, have some combined stray capacitance C relative to ground. stray It should have

[0047] Figure 1D is a schematic diagram of the processing chamber 100 including an alternative version of the bias subsystem assembly 170 shown in Figure 1C. As shown in Figure 1D, the first filter assembly 162 is removed from the RF supply housing 174 and relocated within the high-frequency filter compartment 173. In this configuration, the high-frequency power supply 118 is configured to supply the RF waveform to the electrodes having the substrate support assembly 136 through the RF matching circuit 161, cathode coupling assembly 184, first RF coupling assembly 186, first filter assembly 162, second RF coupling assembly 187, and RF transmission line 167. In this configuration, the high-frequency filter compartment 173 includes one or more second filter assemblies 151, the first filter assembly 162, and other chamber interconnection components.

[0048] Plasma processing bias method and process Figure 2 is a simplified schematic diagram of a biasing scheme that may be used with the processing chamber shown in Figure 1A or Figure 1B. As shown in Figure 2, the high-frequency power supply 118 and the PV waveform generator 150 are configured to supply an RF waveform and a pulsed voltage waveform, respectively, to one or more electrodes disposed within the chamber body 113 of the processing chamber 100. In one embodiment, the high-frequency power supply 118 and the PV waveform generator 150 are configured to simultaneously supply an RF waveform and a pulsed voltage waveform to one or more electrodes disposed within the substrate support assembly 136. In one non-limiting example, as discussed above, the high-frequency power supply 118 and the PV waveform generator 150 are configured to supply an RF waveform and a pulsed voltage waveform to a support base 107 and a bias electrode 104, both disposed within the substrate support assembly 136. In another example, the high-frequency power supply 118, the first PV waveform generator 150, and the second PV waveform generator 150 are configured to supply the RF waveform, the first pulse voltage waveform, and the second pulse voltage waveform, respectively, to the support base 107, bias electrode 104, and edge control electrode 115, all of which are located within the substrate support assembly 136.

[0049] As shown in Figure 2, the high-frequency power supply 118 is configured to supply a sinusoidal RF waveform to one or more electrodes disposed within the chamber body 113 by supplying an RF signal including a sinusoidal RF waveform 601 (Figures 6A to 6G) through a plasma generator assembly 160 which includes an RF matching circuit 161 and a first filter assembly 162. In addition, each of the PV waveform generators 150 is configured to supply a PV waveform, generally including a series of voltage pulses (e.g., nanosecond voltage pulses), to one or more electrodes disposed within the chamber body 113 by establishing a PV waveform 401 (Figures 4A, 5A), 441 (Figure 5B), or 431 (Figure 5C) to the bias electrode 104 via a second filter assembly 151. Internal components of the chucking module 116 may optionally be placed between each PV waveform generator 150 and the second filter assembly 151.

[0050] As briefly discussed above, Figures 3A and 3B are functionally equivalent simplified examples of the pulsed voltage electrical circuit 140 and RF bias scheme proposed herein, respectively, and also include representations of the plasma within the processing volume. Figure 3A represents a simplified pulsed voltage electrical circuit 140 and RF bias scheme that utilizes a PV waveform generator 150 inside a first PV source assembly 196 configured to supply a positive voltage during part of the process of establishing a PV waveform such as PV waveform 431 (Figure 5C) to the bias electrode 104. Figure 3B represents a simplified pulsed voltage electrical circuit 140 and RF bias scheme that utilizes a PV waveform generator 150 inside a first PV source assembly 196 configured to supply a negative voltage during part of the process of establishing a PV waveform such as PV waveform 401 (Figures 4A and 5A) to the bias electrode 104. These circuits illustrate a simplified model of the interaction between the pulse voltage waveform generator 150 of the first PV source assembly 196 and the high-frequency power supply 118 inside the processing chamber 100, and illustrate the basic elements used during the operation of the processing chamber 100. For clarity, the following definitions are used throughout this disclosure: (1) Unless a reference is specified, all potentials refer to ground. (2) The voltage at any physical point (such as the substrate or bias electrode) is similarly defined as the potential at that point relative to ground (the zero potential point). (3) The cathode sheath refers to the electron-donating ion-accelerating sheath corresponding to the negative substrate potential relative to the plasma. (4) Sheath voltage (sometimes referred to as "sheath voltage drop") V sh (5) The substrate potential is the potential at the substrate surface facing the plasma.

[0051] The composite load 130 shown in Figures 3A and 3B is presented as a standard electrical plasma model that represents the processing plasma 101 as three series elements. The first element is an electron-donating cathode sheath (sometimes referred to as the "plasma sheath" or simply the "sheath") adjacent to the substrate 103. In Figures 3A and 3B, the cathode sheath is represented by (a) a diode D that represents sheath decay when open. SH (b) A current source I that represents the ionic current flowing through the substrate in the presence of the sheath. i (c) Capacitor C representing the sheath related to the main part of the bias cycle in which ion acceleration and etching occur (i.e., the ionic current phase of the PV waveform) SH It is represented by a conventional three-part circuit element, which includes (for example, about 100-300pF). The second element is a single resistor R plasma This is the bulk plasma represented by (for example, resistor 146 = approximately 5-10 Ω). The third element is the electron-donating wall sheath formed on the chamber wall. This wall sheath is similar to (a) diode D in Figure 3. wall (b) Current source I that represents the ionic current to the wall iwall (c) Capacitor C that primarily represents the wall sheath in the ESC recharge phase (explained later in the text) of the PV waveform. wall It is represented by having a circuit element consisting of three parts (for example, about 5-10 nF). The inner surface of the grounded metal wall is also a large capacitor C in Figure 3. coat It can be considered to be coated with a thin layer of dielectric material expressed by (for example, approximately 300-1000 nF).

[0052] As shown in Figures 3A and 3B, the high-frequency power supply 118 converts the RF signal to the generated RF power, which is then filtered into the first filter assembly 162, the RF matching circuit 161, and the line inductance L Line , support base capacitance C CL , and effective capacitance C EIt is configured to supply power to the support base 107 by supplying power via and ultimately to the composite load 130. In one embodiment, the RF matching circuit 161 is configured to supply power to a series inductance element L SER And an adjustable series capacitance element C that can be controlled by input from controller 126. SER and adjustable shunt capacitance element C Shunt This includes the following. In some embodiments, the RF matching circuit 161 may be formed using alternative configurations of other circuit elements, such as L-shaped networks, π-networks, or transformer matching circuits. As previously stated, the RF matching circuit 161 is generally configured to adjust the apparent load to 50Ω in order to maximize its power supply efficiency by minimizing reflected power generated by supplying RF signals from the high-frequency power supply 118. In some embodiments, the RF matching circuit 161 is optional, and in these cases, other RF signal matching techniques (e.g., variable frequency tuning) may be used during the plasma treatment of the substrate to avoid inefficient supply of RF power to the composite load 130.

[0053] The first filter assembly 162, also referred to herein as a pulse voltage filter assembly, includes one or more electrical elements configured to substantially prevent current generated by the output of the PV waveform generator 150 from flowing through the RF transmission line 167 and damaging the high-frequency power supply 118. The first filter assembly 162 acts as a high impedance (e.g., high Z) to the PV signal generated from the PV pulse generator 314 inside the PV waveform generator 150, and thus suppresses the flow of current to the high-frequency power supply 118. In one embodiment, the first filter assembly 162 includes a blocking capacitor C disposed between the RF matching circuit 161 and the high-frequency power supply 118. BC This configuration includes the RF matching element 161 adjusting the apparent load on the high-frequency power supply 118, blocking capacitor C BCIt is configured to compensate for the capacitance. In one example, to prevent nanosecond PV waveforms (e.g., pulse period 10 to 100 nanoseconds) supplied from the PV waveform generator 150 from damaging the high-frequency power supply 118, the first filter assembly 162 includes a capacitor of 35 to 100 pF. In another example, the first filter assembly 162 includes a blocking capacitor C with capacitance less than 50 pF. BC Includes.

[0054] In some embodiments, it would be desirable to utilize two or more sets of high-frequency power supplies 118 and RF plasma generator assemblies 160, each configured to independently supply RF power of different RF frequencies to other electrodes inside the support base 107 or substrate support assembly 136. In one example, a first high-frequency power supply 118A (not shown) and a first RF plasma generator assembly 160A (not shown) are configured to supply RF signals with RF frequencies of approximately 300 kHz to 13.56 MHz to the support base 107, and a second high-frequency power supply 118B (not shown) and a second RF plasma generator assembly 160B (not shown) are configured to supply RF signals with RF frequencies of approximately 40 MHz or higher to the support base 107. In this example, each of the high-frequency power supply assemblies 160A and 160B is similarly configured with a first filter assembly 162 (e.g., capacitance C) adapted to prevent current generated by the output of the PV waveform generator 150 from flowing into their respective transmission lines and damaging their respective high-frequency power supplies. BCThis will include a blocking capacitor. In addition, each of the high-frequency power supply assemblies 160A and 160B may also include a separate RF filter assembly, such as a second filter assembly 151 connected in series with each high-frequency power supply assembly, configured to block other RF frequencies supplied from the other high-frequency power supply assembly, in order to further prevent RF currents generated by the output of the other high-frequency power supply from flowing into the transmission line and damaging the respective high-frequency power supply. In this configuration, the separate RF filter assembly may include a low-pass filter, a notch filter, or a high-pass filter that can allow the generated RF waveform to pass through but block RF waveforms generated by the other high-frequency power supply.

[0055] In some embodiments, it would also be desirable to utilize two or more sets of PV generators, each configured to supply a separate PV waveform to the bias electrode 104 and / or edge control electrode 115. In this example, each of the PV waveform generators 150 (only one is shown in Figure 3A or Figure 3B) is fitted with a PV filter assembly (for example, with capacitance C) to prevent current generated by the output of other PV generators from flowing into their respective PV transmission lines 157 and damaging their respective PV generators. BC This will include a blocking capacitor. In addition, each of the PV waveform generators 150 will also include an RF filter assembly, such as a second filter assembly 151 connected in series with each PV waveform generator and configured to block RF frequencies supplied from other PV waveform generators.

[0056] In some embodiments, as shown in Figures 1A to 3B, each of the PV waveform generators 150 outputs the generated pulse voltage waveform to a blocking capacitor 153 of a chucking module 116, a second filter assembly 151, and a high-voltage line inductance L HV And, effective capacitance C EBy supplying through the system, a pulsed voltage waveform signal is supplied to the bias electrode 104 and ultimately to the composite load 130. In this case, the system optionally includes a chucking module 116 used for chucking the substrate, such as "electrical clamping" the substrate receiving surface of the ESC substrate support. When the substrate is chucking, helium gas (He) can be filled into this gap to allow temperature control of the substrate by providing good thermal contact between the substrate receiving surface and the non-device side of the substrate, thereby regulating the temperature of the ESC substrate support. When the pulsed voltage generated by the PV waveform generator 150 and the DC chucking voltage generated by the chucking module 116 are combined at the bias electrode 104, the additional voltage offset of the pulsed voltage waveform becomes equal to the DC chucking voltage generated by the chucking module. The additional voltage offset can be added to / subtracted from the offset ΔV shown in Figures 4A and 5A-5B. The influence of the chucking module 116 on the operation of the PV pulse generator 314 of the PV waveform generator 150 can be ignored by appropriately selecting a large blocking capacitor 153 and blocking resistor 154. Blocking resistor 154 schematically represents a resistor placed inside the component that connects the chucking module 116 to a point inside the transmission line 131. The main function of the blocking capacitor 153 in the simplified electrical circuit is to protect the PV pulse generator 314 from the DC voltage generated by the DC power supply 155, so that this DC voltage is reduced across the blocking capacitor 153 and does not disturb the output of the PV waveform generator. The value of the blocking capacitor 153 is selected so that it blocks only the DC voltage and does not become a load on the pulse voltage output of the pulse bias generator. By selecting a sufficiently large capacitance (e.g., 10-80 nF), the blocking capacitor 153 is much larger than any other relevant capacitance in the system, and the voltage drop across it is greater than the chuck capacitance C E or sheath capacitance C SHIn terms of voltage drop being very small compared to other related capacitors, such as the PV waveform generator 150, it becomes almost transparent to a 400 kHz PV waveform signal generated by the PV waveform generator 150. In addition, in some embodiments, the capacitance of the blocking capacitor 153 is such that the blocking capacitor C in the first filter assembly 162 is nearly transparent. BC It is significantly larger than the capacitance of the first filter assembly 162. In some embodiments, the capacitance of the blocking capacitor 153 is greater than that of the blocking capacitor C in the first filter assembly 162. BC It is at least 10 times, or at least 100 times, or at least about 1000 times, greater than the capacitance of C. BC The capacitance of is approximately 38pF, and the capacitance of the blocking capacitor 153 is approximately 40nF.

[0057] Referring to Figures 3A and 3B, the purpose of the blocking resistor 154 in the chucking module 116 is to block the voltage of the high-frequency pulse bias generator, thereby minimizing the current induced by it in the DC voltage power supply 155. This blocking resistor 154 is set large enough to efficiently minimize the current passing through it. For example, a resistor of 1 MΩ or more is used to make the 400 kHz current from the PV waveform generator 150 to the chucking module 116 negligibly small. In one example, the blocking resistor has a resistance value greater than approximately 500 kΩ. The resulting average induced current of approximately 0.5 to 1 mA is actually much smaller than the typical limit for the chucking module power supply, which is approximately 5 mA of DC current. The components of the bias compensation circuit element 116A, namely the capacitance 155B, diode 155C, resistor 155A, and blocking resistor 154, together form a current suppression / filtering circuit for the pulse voltage, so that the pulse voltage does not induce current through the chucking module 116. The blocking resistor 154 is positioned between the DC power supply 155 and the output 350 and / or the generator output coupling assembly 181 (Figure 1C). In some embodiments, the diode 155C is connected in parallel with the blocking resistor 154, with its anode side connected to the PV transmission line 157.

[0058] The second filter assembly 151 includes one or more electrical elements configured to prevent current generated by the output of the high-frequency power supply 118 from flowing into the PV transmission line 157 and damaging the PV pulse generator 314 of the PV waveform generator 150. As discussed above, the PV transmission line 157 is an assembly including the coaxial transmission line 106 and the transmission line 131. In one embodiment, the second filter assembly 151 has a capacitance of C FC The filter capacitor 151A is connected in parallel with it and is located in the transmission line 157 between the PV pulse generator 314 and the bias electrode 104, with an inductance of L FLThis includes a filter inductor 151B. In some configurations, the second filter assembly 151 is positioned between the blocking capacitor 153 and the bias electrode 104 of the chucking module 116. The second filter assembly 151 acts as a high impedance (e.g., high Z) to the RF signal generated from the high-frequency power supply 118 and thus suppresses the flow of current to the PV pulse generator 314. In some embodiments, the capacitance C of the filter capacitor 151A FC This is significantly smaller, at most less than 1 / 10, at most less than 1 / 100, or at most less than 1 / 1000 of the capacitance of the blocking capacitor 153. For example, the capacitance C of the filter capacitor 151A FC The capacitance of the first capacitor is approximately 51pF, and the capacitance of the blocking capacitor 153 is approximately 40nF.

[0059] As discussed above, the second filter assembly 151 is configured to prevent RF signals and any associated harmonics from flowing into the PV pulse generator 314. In some embodiments, the RF signals generated by the high-frequency power supply are configured to supply RF frequencies higher than 400 kHz, such as RF frequencies of 1 MHz or higher, 2 MHz or higher, 13.56 MHz or higher, or 40 MHz or higher. In some embodiments, to prevent RF power supplied from the high-frequency power supply 118 from damaging the PV pulse generator 314, the second filter assembly 151 includes a filter capacitor 151A with a capacitance of approximately 25 pF to 100 pF and a filter inductor 151B with an inductance of approximately 0.1 to 1 μH. In one example, to prevent 40 MHz RF power supplied from a high-frequency power supply 118 from damaging the PV pulse generator 314, the second filter assembly 151 includes a filter capacitor 151A with a capacitance of approximately 51 pF and a filter inductor 151B with an inductance of approximately 311 nH. In some embodiments, the blocking capacitor C of the first filter assembly 162 is also included. BCThe capacitance value is within 10 times the capacitance value of the filter capacitor 151A of the second filter assembly 151.

[0060] In some embodiments, as shown in Figures 3A to 3B, the second filter assembly 151 further includes a second filter inductor 151C with inductance L2 and a second filter capacitor 151E with capacitance C2, coupled between the transmission line 157 and ground, and a third filter inductor 151D with inductance L3 and a third filter capacitor 151F with capacitance C3, also coupled between the transmission line 157 and ground. In some configurations, the inductances of the second filter inductor 151C and the third filter inductor 151D may be approximately 0.1 to 1 μH, and the capacitances of the second filter capacitor 151E and the third filter capacitor 151F may be approximately 25 pF to 100 pF.

[0061] Example of a pulse waveform As described above, the novel substrate biasing methods provided by embodiments of this disclosure enable the maintenance of a substantially constant sheath voltage during processing and thus the generation of a desired IEDF on the substrate surface, while also providing the ability to independently control the mode of plasma formed within the processing volume of the plasma processing chamber by using one or more RF source assemblies. In some embodiments, a single-peak (single-energy) IEDF can be formed on the substrate surface during processing by using the novel substrate biasing apparatus and methods disclosed herein. In other embodiments, a double-peak (dual-energy) IEDF can be formed on the substrate surface during processing by using one or more of the novel substrate biasing apparatus and methods disclosed herein, as shown in Figure 4D. In some configurations of the apparatus disclosed herein, such as that shown in Figure 1A, it is also possible to maximize the area of ​​grounded surfaces inside the plasma processing chamber and thus minimize power loss to the chamber walls to improve plasma processing efficiency.

[0062] As will be discussed further below in relation to Figures 4A-4C and 5A-5C, a novel substrate biasing method that enables the maintenance of a substantially constant sheath voltage during plasma processing involves supplying a series of pulses and / or bursts of pulses during a plasma processing sequence performed on a substrate during a plasma process performed in a plasma processing chamber. Embodiments of the disclosure provided herein involve supplying pulses having a desired pulsed voltage waveform (PVWF), each comprising a plurality of distinct phases. As will be discussed further below, each PV waveform comprises at least one phase of a plurality of phases controlled by supplying a voltage signal or optionally a constant current signal from a PV waveform generator 150. Generally, for the purposes of discussion, each pulse of the PV waveform may be segmented into two main regions, including a first region 405 and a second region 406, as shown in Figures 5A-5C. Generally, each PV waveform has an amplitude (V out ), offset (e.g., ΔV), pulse period (T P ), and pulse repetition frequency (F P = 1 / T P This will include ).

[0063] Figure 4A shows a negative pulse bias type PV waveform that can be established on the bias electrode 104 and / or edge control electrode 115 by using a PV waveform generator 150 inside the PV source assembly. In some embodiments, the PV waveform shown in Figure 4A is established separately on the bias electrode 104 and edge control electrode 115, respectively, using the PV waveform generator 150 of the first PV source assembly 196 and the PV waveform generator 150 of the second PV source assembly 197. Figure 5A shows a negative pulse bias type pulse voltage waveform, where the PV waveform generator 150 is configured to control the generation of a sequence 550 of polyphase negative pulse waveforms 401 to establish a PV waveform on the bias electrode 104 or edge control electrode 115. In some embodiments, the polyphase negative pulse waveform 401 includes a series of repeating periods, and the waveform in each cycle has a first portion occurring during a first time interval and a second portion occurring during a second time interval. The multiphase negative pulse waveform 401 will contain positive voltage pulses that are present only for at least a portion of the first time interval, and the pulse voltage waveform will remain substantially constant throughout at least a portion of the second time interval. The output of the PV waveform generator 150 is connected to a negative voltage source for at least a portion of the second time interval.

[0064] The substrate PV waveform 425 is a series of PV waveforms established on the substrate by PV waveforms formed and established on the bias electrode 104 or edge control electrode 115 by the PV waveform generator 150, as shown in Figure 4A. The substrate PV waveform 425 is established on the surface of the substrate during processing and includes a sheath collapse and ESC recharge phase 450 (or sheath collapse phase 450 for simplicity of discussion) extending between points 420 and 421 of the exemplary substrate PV waveform 425, a sheath formation phase 451 extending between points 421 and 422, and an ion current phase 452 extending from point 422 to the starting point 420 of the next pulse voltage waveform which is established consecutively. As shown in Figures 4A to 4C, the plasma potential curve 433 shows the local plasma potential during the supply of negative pulse waveforms 401 established on the bias electrode 104 and / or edge control electrode 115 using one or more PV waveform generators 150.

[0065] In some embodiments, during processing in the processing chamber 100, a PV waveform generator 150 supplies and controls a negative voltage through two of the phases of the established multiphase negative pulse waveform 401, such as the negative portion of the PV waveform and / or the portion that is maintained at a negative voltage level (e.g., the ion current phase), thereby forming a multiphase negative pulse waveform 401. For example, these portions of the negative pulse waveform 401 that contain negative voltage are, by analogy, associated with the sheath formation phase 451 and the ion current phase 452 shown in Figure 4A with respect to the substrate PV waveform 425. In this case, with respect to the multiphase negative pulse waveform 401, the supply of negative voltage from the PV waveform generator 150 occurs in the second phase 406, as shown in Figure 4A, and extends from point 411 (i.e., the peak of the multiphase negative pulse waveform 401) to point 413, which coincides with the start of the sheath breakdown phase 450 of the substrate PV waveform. In some embodiments, the PV waveform generator 150 applies a constant negative voltage (e.g., V) during the ion current phase 452, which matches the portion of the multiphase negative pulse waveform 401 established between points 412 and 413. OUT It is configured to supply ) to the ion current phase 452. For example, in the ion current phase 452, the ion current (I iAs the ions accumulate positive charge on the substrate surface, the voltage on the substrate surface increases over time, as seen in the upward-sloping line between points 422 and 420 (Figure 4A). This increase in voltage on the substrate surface over time causes the sheath voltage to decrease and the ion energy to diffuse. Therefore, in order to minimize the effects of the decrease in sheath voltage and the divergence of ion energy, at least the frequency (1 / T) of the PV waveform should be reduced. PD . T PD It is desirable to control and set the period of the PV waveform (Figure 5A).

[0066] Figure 5B shows a PV waveform of the molded pulse bias type, where the PV waveform generator 150 is configured to control the generation of a sequence 551 of multiphase molded pulse waveforms 441 established on the bias electrode 104 and / or edge control electrode 115. In some embodiments, the PV waveform generator 150 forming the multiphase molded pulse waveforms 441 is configured to use one or more internal switches and a DC power supply to supply a positive voltage between one or more phases of the voltage pulse (e.g., a first region 405) and a negative voltage between one or more phases of the voltage pulse (e.g., a second region 406).

[0067] In some embodiments, the PV waveform generator 150 is configured to supply a sequence 552 of polyphase positive pulse waveforms 431, as shown in Figure 5C, to the bias electrode 104 and the edge control electrode 115. Each positive pulse phase in the positive pulse waveform 431 may include multiple phases, such as a sheath collapse phase, an ESC recharge phase, a sheath formation phase, and an ion current phase. In this example, the first region 405 generally includes the sheath collapse phase and the ESC recharge phase. The second region 406 generally includes the sheath formation phase and the ion current phase. In some embodiments, the polyphase positive pulse waveform 431 includes a series of repeating periods, and the waveform in each cycle has a first portion occurring during a first time interval and a second portion occurring during a second time interval. The polyphase positive pulse waveform 431 will include positive voltage pulses that are present only for at least a portion of the first time interval and are substantially constant for at least a portion of the second time interval. The output of the PV waveform generator 150 is connected to a positive voltage source for at least a portion of the first time interval.

[0068] The various pulse voltage waveforms 401, 441, and 431 shown in Figures 5A, 5B, and 5C, respectively, represent pulse voltage waveforms supplied to the input of the chucking module 116 and may therefore differ from the pulse voltage waveforms established at the bias electrode 104 and edge control electrode 115, as shown in Figure 4A. The DC offset of ΔV in each PV waveform depends on the various characteristics of the configuration of the PV waveform generator 150 used to establish the PV waveform.

[0069] In the processing method shown in Figure 4B, a series of pulsed voltage waveform bursts 462 are established on the bias electrode 104 and / or edge control electrode 115 and established on the substrate surface. In the example shown in Figure 4B, multiple pulses 461 within each burst 462 include a series of negative pulse waveforms 401 established on the bias electrode 104 and / or edge control electrode 115. In this example, each burst 462 has a consistent pulsed voltage shape PV waveform (for example, a constant voltage amplitude is supplied between parts of each PV waveform 401) and an invariant burst supply period T between burst 462 and another burst. ON And, a certain period of burst pause T OFF Includes pulse 461 having the following: Burst pause period T OFF This is the burst supply period T ON It is formed by stopping the supply of the PV waveform that was supplied inside. In this example, the length of time during which multiple pulses are supplied during the burst (i.e., burst supply period T) ON ) and the duration of the burst period (i.e., T BD =T ON +T OFF The duty cycle of burst 462, which is the ratio to ), is also constant. In other processing methods, it will be understood that multiple pulses 461 may include negative pulse waveforms 401, shaped pulse waveforms 441 or positive pulse waveforms 431, or a combination thereof. As shown in Figure 4B, burst pause period T OFF In this case, the bias electrode potential curve 436 is primarily controlled by the chucking voltage applied and controlled by the chucking module 116, and can therefore be at a voltage level different from the plasma potential.

[0070] In the processing method shown in Figure 4C, bursts of multiple pulses, such as bursts 462 and 463, configured in different ways, are established on the bias electrode 104 and / or edge control electrode 115 and established on the substrate surface. Figure 4D shows a graph of the IEDF resulting from performing the processing method shown in Figure 4C during plasma processing. By performing the processing method shown in Figure 4C, it is considered possible to control the distribution of ion energy to form an IEDF that includes two or more discrete IEDF peaks, such as the two discrete IEDF peaks shown in Figure 4D, by controlling the supply of multiple bursts configured in different ways within the range of the repetition period. In contrast, in conventional plasma processes utilizing RF biasing methods, the IEDF generally has two peaks, which are formed at low and high energies and in several ion populations with energies between the two peaks, and therefore will not form the desired discrete IEDF peaks. An example of a conventionally formed IEDF curve is shown in Figure 1B of U.S. Patent No. 10,555,412, the entire patent of which is incorporated herein by reference. In these conventional biasing methods, the applied RF voltage (having a waveform such as that shown in Figure 6A) modulates the cathode sheath throughout the RF period, thus excessively varying the sheath voltage drop over time and resulting in a dual-peak IEDF. As discussed above, the range of ion energies between the two IEDF peaks formed during conventional processing (i.e., the formation of non-discrete IEDF peaks) affects the profile of the etched feature walls formed within the substrate surface during plasma processing.

[0071] In some embodiments of the method shown in Figure 4C, multiple bursts configured in different ways have a repeating period length (T) configured in different ways. TrainThe burst 462 and burst 463 include a repeating period of bursts having a different pulse voltage amplitude (e.g., different V). Each of bursts 462 and 463 includes a plurality of pulses 461 which may include a negative pulse waveform 401, a shaped pulse waveform 441, or a positive pulse waveform 431, or a combination thereof. In some embodiments, the plurality of bursts configured in different ways includes at least two bursts configured in different ways such that the characteristics of the plurality of pulses 461 formed between at least two of the bursts in the plurality of bursts configured in different ways are different. In one example, as shown in Figure 4C, the characteristics of the plurality of pulses 461 having burst 462 are different from the plurality of pulses 461 having burst 463 (e.g., different V). OUT ) has and therefore can form two IEDF peaks with different peak heights (Figure 4D). In some embodiments, pulse 461 has a pulse voltage amplitude (V) from about 1 kilovolt (kV) to about 10 kV. OUT ) has. In some embodiments, the characteristics of multiple pulses 461 that differ between at least two bursts in the repetition period include different individual PV waveform periods, different pulse voltage amplitudes, different shapes (e.g., voltage amplitude, slope (dV / dt)), or other PV waveform characteristics of at least a portion of the PV waveform within the range of a first region 405 and a second region 406. Each of bursts 462 and 463 has a burst supply period T ON and burst pause period T OFF It has a burst period that includes T. BD and burst duty cycle (for example T ON / T BD ) is the burst supply period T ON and burst period T BD Based on. In some embodiments, the burst supply period T ON The burst duration is approximately 50 μs to 50 milliseconds (ms), such as approximately 200 μs to 5 milliseconds, and the burst duty cycle is approximately 5% to 100%, such as approximately 50% to 95%. For example, the burst supply period T ONis about 800 μs, and the duty cycle of the burst is about 80% for both burst 462 and burst 463. More specifically, FIG. 4C includes an example of a plurality of bursts of an input pulse voltage waveform (each containing a plurality of waveform cycles) originating from the generator end of the generator output coupling assembly 181, and the termination of the generator output coupling assembly 181 is disposed at the output of the PV waveform generator 150 that is supplied to the bias electrode 104 of the substrate support assembly 136. The plurality of bursts configured in different ways have offsets (ΔV), burst periods (T BD ), burst frequencies (fB = 1 / T BD ), and / or duty cycles of the burst (Duty = T on / T BD ) that can be characterized as such. Thus, by varying the characteristics of the plurality of pulses 461 between two or more bursts configured in different ways, two or more discrete IEDF peaks can be formed to adjust or vary the plasma processing results achieved on the substrate during processing.

[0072] FIG. 5D shows a series of PV waveforms formed on the substrate by establishing a positive pulse waveform 431 (not shown) or a negative pulse waveform 401 (not shown) on the bias electrode 104 and / or the edge control electrode 115 using one or more PV waveform generators 150 during processing. The PV waveforms formed on the substrate include a substrate PV waveform 425 formed by establishing the negative pulse waveform 401, or a substrate PV waveform 531 formed by establishing the positive pulse waveform 431. In some embodiments, the negative pulse waveform 401 has a time T N1 and a time T N2It is formed by establishing a negative voltage between the bias electrode 104 and / or the edge control electrode 115. In some embodiments, the negative voltage supplied to the output 350 of the PV waveform generator 150 is supplied to the bias electrode 104 and / or the edge control electrode 115 and is substantially constant throughout at least a portion of the second region 406 of the negative pulse waveform 401. In one example, the negative voltage supplied to the output 350 of the PV waveform generator 150 is substantially constant throughout the entire second region 406, except for any voltage oscillations or transitions associated with some switching at the start and / or end of the second region 406. Referring to FIG. 3B, between time T N1 and time T N2 a negative voltage is supplied by keeping switch S1 closed and switch S2 open. During other periods from T N2 to T N1 switch S1 will be kept open and switch S2 will be kept closed.

[0073] In some embodiments, the positive pulse waveform 431 is formed by establishing a positive voltage between the bias electrode 104 and / or the edge control electrode 115 between time T P1 and time T P2 Referring to FIG. 3A, between time T P1 and time T P2 a positive voltage is supplied by keeping switch S1 closed and switch S2 open. During other periods from T P2 to T P1 switch S1 will be kept open and switch S2 will be kept closed. In some embodiments, the positive voltage supplied to the output 350 of the PV waveform generator 150 is supplied to the bias electrode 104 and / or the edge control electrode 115 and is substantially constant throughout at least a portion of the first region 405 of the positive pulse waveform 431.

[0074] As shown in Figure 5D, the process of establishing a negative pulse waveform 401 or a positive pulse waveform 431 on the bias electrode 104 and / or edge control electrode 115 will result in the formation of a substrate PV waveform 425 or a substrate PV waveform 531, which may have different waveform characteristics. In one example, when using the negative pulsing process, a longer period (T) of the waveform cycle is used in which there is no sheath (i.e., a sheath formed during the ESC recharge phase 560). NNSH It is desirable to form a substrate PV waveform 425 that includes ), and in contrast, during the positive pulsing process, a shorter period (T) of the waveform cycle is present in which there is no sheath (i.e., the sheath formed during the ESC recharge phase 570). PNSH It is desirable to form a substrate PV waveform 531 that includes ). In this example, there is a period T in the negative PV waveform during which no sheath exists. NNSH This can be approximately 175 nanoseconds (ns), in contrast to the period T in which there is no sheath present in the positive PV waveform. PNSH This could be approximately 80 nanoseconds.

[0075] In any process of establishing a pulse voltage waveform, such as establishing a negative pulse waveform 401, a shaping pulse waveform 441, or a positive pulse waveform 431 on the bias electrode 104 and / or edge control electrode 115, it may be possible to keep the sheath voltage nearly constant for a large proportion of the substrate processing time (e.g., 85% to 90%) during the plasma process. The waveforms shown in Figures 4A to 5D are intended only to show simplified schematic diagrams of pulse voltage waveforms that may be used with one of the methods that may be used during plasma processing of the substrate described herein. The actual waveforms generated by the PV waveform generator 150 may be much more complex and may contain several fine-scale characteristics (e.g., high-frequency oscillations due to the presence of inductive elements) that are not shown in Figures 3A to 3B. However, these fine-scale characteristics are not essential for understanding the fundamental physical phenomena that determine the overall shape of the actual pulse voltage waveforms generated by the pulse voltage bias schemes and control methods proposed herein.

[0076] Pulse voltage waveform phase Generally, pulse voltage waveforms such as the established negative pulse waveform 401, shaped pulse waveform 441, or positive pulse waveform 431 have a period T above the voltage offset (ΔV). PD It includes a series of short pulses with a repeating periodicity. For example, period T PD The intervals are approximately 1 μs to 5 μs, such as approximately 2.5 μs. The waveforms within each period (repetition period) include the following:

[0077] (1) Sheath capacitor C sh (Figures 3A-3B) discharges, and the substrate potential becomes the level of the local plasma potential (e.g., plasma potential curve 433 in Figure 4A) in the sheath collapse phase. Due to the sheath collapse phase, during the ESC recharge phase of (2) below, electrons supplied from the plasma create a chuck capacitor C E This will enable rapid recharging.

[0078] (2) By rapidly injecting or accumulating an amount of charge of opposite polarity to the total charge accumulated on the substrate surface during the subsequent ionic current phase of (4), a chuck capacitor C is introduced into the ESC recharge phase. E Recharging. During the ESC recharging phase, a plasma current is also induced by electrons. That is, electrons reach the substrate without a cathode sheath, and therefore capacitor C E Construct a surface charge that charges the surface.

[0079] (3) Jump to a negative voltage to discharge the stray capacitor in the processing chamber. Reform the sheath during the sheath formation phase to create a sheath voltage (V SH Set the value of ). Sheath formation (C sh The start of charging can be clearly identified as the point at which the substrate potential begins to drop below the local plasma potential.

[0080] (4) An overall long ion current phase (longer than 50%, e.g., about 80-90% of the PV waveform cycle period T) in which positive charge accumulates on the substrate surface due to the ion current, the sheath capacitor and chuck capacitor gradually discharge, the sheath voltage slowly decreases and the substrate potential approaches 0. This results in a voltage droop in the substrate voltage waveforms 425 (Figure 4A) and 531 (Figure 5D). It is because of the sheath voltage droop that occurs here that a pulse waveform is required to transition to the next cycle as described in (1) to (3) above.

[0081] As discussed above, in some embodiments, the processing chamber 100 includes at least one or more high-frequency power supplies 118 and associated first filter assemblies 162, and one or more PV generators 314 and associated second filter assemblies 151, which together are configured to supply a desired waveform to one or more electrodes disposed inside the substrate support assembly 136. The memory of the controller 126 stores software instructions configured to generate RF waveforms configured to establish, maintain, and control one or more aspects of the plasma formed inside the processing chamber. The one or more aspects of the plasma to be controlled may include, but are not limited to, the plasma density, plasma chemistry, and ion energy of the plasma formed in the processing volume 129.

[0082] Figure 6A shows the frequency supplied from the high-frequency power supply 118 (i.e., 1 / T). RF The image shows a typical sinusoidal RF waveform 601 having ). Generally, one or more embodiments of the plasma select a desired RF frequency and RF power, and optionally a duty cycle of the pulsed RF signal (i.e., the time the sinusoidal RF signal is "on" (T). RFON The ratio of the time (T) in which the sinusoidal RF signal is "off" versus the time in which the sinusoidal RF signal is "off" RFOFFThe ratio of the RF frequency can also be controlled by selecting the desired RF frequency. The selection of the desired RF frequency is generally performed by selecting a high-frequency power supply (e.g., a 2 MHz, 13.56 MHz, or 40 MHz high-frequency power supply) configured to supply varying amounts of RF power at one or more frequencies within a selected narrow RF frequency range.

[0083] Figure 6B shows a pulsed RF waveform 602 that can be supplied from the high-frequency power supply 118 during the plasma process. The formed pulsed RF waveform 602 is the period T of the RF pulses within the RF pulsed RF sequence. RFP Then, the "on" time (i.e., T) during which the sinusoidal RF waveform 601 is supplied by the high-frequency power supply 118. RFON ) and the "off" time when it is not supplied (i.e., T RFOFF ) may have both.

[0084] Figure 6C illustrates how pulsed RF waveforms 602 supplied from a high-frequency power supply 118 and a series of bursts 612, 622, or 632 supplied to bias electrodes 104 and / or edge control electrodes 115 are synchronized using one or more PV waveform generators 150 and a controller 126. Each of the bursts 615, 625, and 635 in the series of bursts 612, 622, and 632 includes a single burst of a consistent type (i.e., pulses 461 have identical pulse characteristics), as shown in Figure 6C, and each of the bursts in the series of bursts generated by one or more PV waveform generators 150 may include bursts configured in different ways, such as bursts 462 and 463 in Figure 4C. Similarly, in some embodiments, the RF pulses in RF waveform 602 may include a series of RF pulses configured in different ways. Bursts 615, 625, or 635 each include a plurality of pulses 461, which may include a negative pulse waveform 401, a shaping pulse waveform 441, or a positive pulse waveform 431, or a combination thereof, and these may be established on either or both of the bias electrode 104 and the edge control electrode 115.

[0085] In one example, during processing, a series of bursts 612, including multiple bursts 615, are supplied to the bias electrode 104 and / or edge control electrode 115 and synchronized with the supply of the pulsed RF waveform 602. In this example, the burst supply period, burst pause period, and burst period of each of the multiple bursts 615 correspond to the RF pulse supply period T of the RF pulse in the pulsed RF waveform 602, respectively. RFON RF pulse pause period T RFOFF , and RF pulse period T RFP It is identical to [the other one].

[0086] In another example, during processing, a series of bursts 622, including multiple bursts 625, are supplied to the bias electrode 104 and / or edge control electrode 115, synchronized with the supply of the pulsed RF waveform 602. In this example, the burst supply period, burst pause period, and burst period of each of the multiple bursts 625 correspond to the RF pulse supply period T of the RF pulse in the pulsed RF waveform 602, respectively. RFON RF pulse pause period T RFOFF , and RF pulse period T RFP This is identical. However, in this example, a delay period T, also referred to herein as a positive delay period, is introduced such that each burst 625 begins some time after at least a portion of each RF pulse in the pulse RF waveform 602 has been supplied. DE This is given. Alternatively, it would be desirable to delay the supply of RF pulses relative to the supply of burst 625 (i.e., a negative delay period) so that the RF pulses are supplied after at least a portion of the burst 625 has been supplied.

[0087] In another example, during processing, a series of bursts 632, including multiple bursts 635, are supplied to the bias electrode 104 and / or edge control electrode 115, synchronized with the supply of a pulsed RF waveform 602. In this example, each of the multiple bursts 635 has the same burst period as the RF pulse in the pulsed RF waveform 602. However, in this example, the burst supply period and burst pause period are different from the RF pulse in the pulsed RF waveform 602. As shown in Figure 6C, the burst supply period of each burst 635 is the RF pulse supply period T RFON Period T DS It's just longer. In this case, the duty cycle for supplying burst 635 and the duty cycle for supplying pulse RF waveform 602 are different.

[0088] The series of bursts 612, 622, and 632 shown in Figure 6C each contain a constant burst supply period and duty cycle, although the burst supply period and / or duty cycle in the series of bursts are intended to change over time. Furthermore, the series of bursts 622 shown in Figure 6C each contain a constant delay period T DE Although it includes a constant burst supply period and a constant delay period, the burst supply period in the series of bursts is intended to change over time, and / or it would be desirable to delay the supply of RF pulses relative to the supply of burst 625.

[0089] In another example, as shown in Figure 6D, during processing, a series of bursts 642, including multiple bursts 645, are supplied to the bias electrode 104 and / or edge control electrode 115, synchronized with the supply of the pulsed RF waveform 602. In this example, the burst supply period, burst pause period, and burst period of each of the multiple bursts 645 correspond to the RF pulse supply period T of the RF pulse in the pulsed RF waveform 602, respectively. RFON , and RF pulse pause period T RFOFFThis is different. In this example, the start delay period T is set so that each burst 645 begins a certain time after at least a portion of each RF pulse in the pulse RF waveform 602 has been supplied. DE Given, and also the RF pulse period T RFP The termination delay period T is set so that each burst 645 ends before the end of the other burst 645. ED Given this, in this example, the duty cycle of each burst 645 is smaller than that of the RF pulse.

[0090] In another example, as shown in Figure 6E, during processing, a series of bursts 652, including multiple bursts 655 and 656, are supplied to the bias electrode 104 and / or edge control electrode 115 and synchronized with the supply of a multilevel pulsed RF waveform 603. The multilevel pulsed RF waveform 603 includes multiple RF pulsed power levels 604 and 605 formed by supplying sinusoidal RF waveforms 601 of different power levels using a high-frequency power supply. In this example, each of the multiple bursts 655 and 656 is synchronized with the changes in the RF pulsed power levels 604 and 605. Multiple negative pulse waveforms 401, included in each of the multiple bursts 655 and 656, are supplied at different voltage levels, indicated by the difference in the respective negative levels of the voltage level peaks applied to each of the bursts 655 and 656. In some embodiments, as shown in Figure 6E, the transitions between bursts 655 and 656 and / or between RF pulsed power levels 604 and 605 are each accompanied by a burst pause period T OFF Time or RF pulse pause period T RFOFF It is not separated by time.

[0091] Figure 6F schematically shows a TTL signal waveform used to synchronize the supply of the series of bursts 652 and multilevel pulsed RF waveforms 603, as shown in Figure 6E. In some embodiments, the controller 126 supplies the TTL signal waveform to each PV waveform generator 150 and the high-frequency power supply 118 so that the supply of the series of bursts 652 and multilevel pulsed RF waveforms 603 can be synchronized. In other embodiments, the master high-frequency power supply 118 supplies the TTL signal waveform to each PV waveform generator 150 so that the supply of the series of bursts 652 and the multilevel pulsed RF waveforms 603 supplied from the master high-frequency power supply 118 can be synchronized. The TTL signal waveform may include a multilevel pulse containing one or more signal characteristics that each PV waveform generator 150 and / or high-frequency power supply 118 uses to determine the desired PV waveform characteristics or RF signal waveform characteristics to supply. In one example, the amplitude (e.g., voltage level) of the signal waveform at various time points during the processing sequence is used by each PV waveform generator 150 to determine the desired PV waveform output voltage level, and by the high-frequency power supply 118 to determine the desired RF power level to be supplied.

[0092] In another example, as shown in Figure 6G, during processing, a series of bursts 662, including multiple bursts 665 and 667, are supplied to the bias electrode 104 and / or edge control electrode 115 and synchronized with the supply of a multilevel pulsed RF waveform 606. The multilevel pulsed RF waveform 606 includes multiple RF pulse power levels 607 and 608 formed by supplying sinusoidal RF waveforms 601 of different power levels using a high-frequency power supply. The multilevel pulsed RF waveform 606 is coupled with an RF pulse pause period T, indicated by an RF pause time 609. RFOFF This may include a time interval between the transition from the first power level 607 to the second power level 608. In some embodiments, the RF pulse pause period T may also be included. RFOFFThe time lies in the respective transitions between RF pulse power levels 607 and 608. The transitions between each of the multiple bursts 665 and 667 are synchronized with the changes in RF pulse power levels 607 and 608. The multiple negative pulse waveforms 401 contained in each of the multiple bursts 665 and 667 are supplied at different voltage levels, as indicated by the difference in the respective negative levels of the peaks for each of the bursts 665 and 667. In some embodiments, the transition from burst 667 to burst 665 is during a burst pause period T OFF Although separated by time, the transition from burst 665 to burst 667 is during the burst pause period T OFF It is not separated by time. However, in some embodiments, the transition from burst 665 to burst 667 is a burst pause period T OFF Although separated by time, the transition from burst 667 to burst 665 is during the burst pause period T OFF The transitions from burst 665 to burst 667 and from burst 667 to burst 665 are not separated by time. OFF It can be separated by time.

[0093] Figure 6G also shows a TTL signal waveform that can be used to help synchronize the supply of a series of bursts 662 and multilevel pulsed RF waveforms 606. As similarly discussed above, the TTL signal waveform is supplied by the controller 126 to each PV waveform generator 150 and the high-frequency power supply 118, or supplied from the master high-frequency power supply 118 to each PV waveform generator 150, so that the supply of a series of bursts 662 and the multilevel pulsed RF waveforms 606 can be synchronized. As shown in Figure 6G, the amplitude of the signal waveform at various times in the processing sequence is used by each PV waveform generator 150 to determine the voltage level of the desired PV waveform output and by the high-frequency power supply 118 to determine the desired RF power level. In some configurations, information provided by one or more levels of the TTL signal waveform, such as the LS2 level in Figure 6G, is used to determine the desired duty cycle, number of pulses in the burst, and / or pulse amplitude for one or more of bursts 665 and 667, such as burst 667, and / or the duty cycle and / or RF pulse amplitude of RF waveform 606 are determined from the characteristics of the TTL signal waveform.

[0094] Figure 6H shows an alternative version of the pulse sequence shown in Figure 6G. Hereinafter, the pulse configuration shown in Figure 6H is referred to as the L-to-H (LH) PV pulse sequence, in contrast to the H-to-L (HL) PV pulse sequence shown in Figure 6G. As shown in Figure 6H, bursts 665 and 667 of the series of bursts 662, and RF pulse power levels 607 and 608 of the multilevel pulsed RF waveform 606, are arranged sequentially at separate times. In this configuration, bursts 665 and 667 and RF pulse power levels 607 and 608 are reordered in time such that burst 667 precedes the supply of burst 665, and RF pulse power level 607 precedes the supply of RF pulse power level 608.

[0095] In some embodiments, one or more PV waveform generators 150 and controllers 126 are used to synchronize and supply separately to the bias electrode 104 and the edge control electrode 115 a series of bursts, such as a series of bursts 612, 622, or 632. In addition, as discussed above, the pulsed RF waveform 602 can be synchronized with a series of bursts 612, 622, or 632 that can be supplied to the bias electrode 104 and the edge control electrode 115 using one or more PV waveform generators 150 and controllers 126. In one example, a series of bursts 612 are supplied to the bias electrode 104 from the PV waveform generator 150 of a first PV source assembly 196, and a series of bursts 612 are supplied to the edge control electrode 115 from the PV waveform generator 150 of a second PV source assembly 197, these of which are synchronized with the supply of pulsed RF waveform 602.

[0096] In some embodiments, the bursts and / or series of bursts supplied to the bias electrode 104 and the bursts and / or series of bursts supplied to the edge control electrode have one or more different characteristics. In one example, the pulse voltage waveform of the burst supplied to the bias electrode 104 is different from the pulse voltage waveform of the burst supplied to the edge control electrode 115 at the same time. In another example, the bursts in the series of bursts supplied to the bias electrode 104 (e.g., burst 615) and the bursts in the series of bursts supplied to the edge control electrode 115 (e.g., burst 635) have different burst supply periods. In yet another example, the bursts in the series of bursts supplied to the bias electrode 104 are time-shifted from the bursts in the series of bursts supplied to the edge control electrode 115. In this example, burst 615 of a series of bursts 612 is supplied to the bias electrode 104, and burst 625 of a series of bursts 622 is supplied to the edge control electrode 115. Therefore, the timing of the burst supply to the bias electrode 104, the edge control electrode, and the pulse RF waveform 602 can be adjusted independently of each other.

[0097] In some embodiments, the PV waveform supplied to the bias electrode 104 and the PV waveform supplied to the edge control electrode 115 may be synchronized and identical in shape, but the amplitude of the individual pulses supplied to each electrode may differ. The different PV waveform amplitudes applied to the bias electrode 104 and the edge control electrode 115 may be used to control the "edge slope" of etched features formed on the substrate. In one example, the PV waveforms in a first burst supplied to the bias electrode 104 and the edge control electrode 115 are synchronized and identical in shape, and the PV waveform applied to the edge control electrode 115 has a higher peak-to-peak voltage than the PV waveform applied to the bias electrode 104. In another example, the PV waveforms in a second burst supplied to the bias electrode 104 and the edge control electrode 115 are synchronized and identical in shape, and the PV waveform applied to the edge control electrode 115 has a lower peak-to-peak voltage than the PV waveform applied to the bias electrode 104.

[0098] In some embodiments, software instructions stored in the memory of the controller 126 are configured to generate pulsed voltage (PV) waveforms and / or bursts of pulsed voltage (PV) waveforms, which are used to establish a nearly constant sheath voltage during plasma processing in the processing chamber to generate a desired IEDF on the substrate surface. Controlling pulsed voltage (PV) waveforms and / or bursts of pulsed voltage (PV) waveforms allows for more precise control over the shape of the IEDF and the number of peaks having the IEDF, resulting in better control over the profile of features formed on the substrate surface. Controlling pulsed voltage (PV) waveforms and / or bursts of pulsed voltage (PV) waveforms typically involves supplying a desired voltage signal during one or more of the pulsed voltage (PV) waveform phases, and then controlling the waveform period T PDThis should include allowing the shape of the remaining phases of the pulsed voltage (PV) waveform to evolve naturally through the remainder. The software stored in the controller 126's memory should also include instructions used to execute various process tasks and process sequences necessary to control various hardware and electrical components inside the processing chamber 100 and the processing system in which the processing chamber 100 is installed, in order to synchronize the supply of RF waveforms, pulsed voltage (PV) waveforms and / or bursts of pulsed voltage (PV) waveforms to one or more electrodes inside the processing chamber 100.

[0099] While the foregoing applies to embodiments of the present disclosure, other embodiments and further embodiments of the present disclosure may be conceived without departing from the basic scope of the invention, the scope of which is determined by the following claims.

Claims

1. A plasma processing chamber, A substrate support assembly comprising a substrate support surface, a support base, and a first bias electrode disposed between the support base and the substrate support surface, A first dielectric layer disposed between the support base and the first bias electrode, A second dielectric layer is disposed between the first bias electrode and the substrate support surface, A pulse voltage waveform generator configured to be electrically coupled to the first bias electrode via a first conductor and to establish a pulse voltage waveform at the first bias electrode, A high-frequency filter assembly electrically coupled between the pulse voltage waveform generator and the first conductor, A high-frequency power supply configured to be electrically coupled to the support base or the first bias electrode via a second conductor, and to establish a high-frequency voltage waveform at the support base or the first bias electrode, A pulse voltage filter assembly electrically coupled between the high-frequency power supply and the second conductor, A plasma processing chamber equipped with the following features.

2. The plasma processing chamber according to claim 1, further comprising a parallel plate structure having an effective capacitance between 3 nF and 50 nF, comprising the first bias electrode and the second dielectric layer.

3. The plasma processing chamber according to claim 2, wherein the second dielectric layer comprises a material having a finite resistivity.

4. The plasma processing chamber according to claim 1, wherein the thickness of the second dielectric layer is 0.1 mm to 2 mm.

5. A filter coupling assembly configured to electrically couple the filter end of the first conductor to the high-frequency filter assembly, An electrode coupling assembly configured to electrically couple the second end of the first conductor to the first bias electrode, A generator output coupling assembly configured to electrically couple a pulse voltage generator to the high-frequency filter assembly, Chucking assembly and The chucking assembly further comprises, A chucking power supply electrically coupled to the generator output coupling assembly, A blocking resistor having a resistivity exceeding 500 k ohms is disposed between the chucking power supply and the generator output coupling assembly. A plasma processing chamber according to claim 1, comprising:

6. The plasma processing chamber according to claim 1, wherein the pulse voltage filter assembly includes a blocking capacitor.

7. The plasma processing chamber according to claim 6, further comprising an RF matching circuit electrically coupled between the pulse voltage filter assembly and the support base.

8. The aforementioned substrate support assembly further, A second bias electrode is disposed between the support base and the first bias electrode, One or more vias having a first end that electrically contacts the first bias electrode and a second end that electrically contacts the second bias electrode. A plasma processing chamber according to claim 1, comprising:

9. A plasma processing chamber, A substrate support assembly comprising a substrate support surface, a support base, and a first bias electrode disposed between the support base and the substrate support surface, A first dielectric layer disposed between the support base and the first bias electrode, A second dielectric layer is disposed between the first bias electrode and the substrate support surface, Edge control electrode, A first pulse voltage waveform generator is electrically coupled to the first bias electrode via a first conductor and configured to establish a pulse voltage signal waveform at the first bias electrode, A first high-frequency filter assembly electrically coupled between the first pulse voltage waveform generator and the first conductor, A second pulse voltage waveform generator is electrically coupled to the edge control electrode via a second conductor and configured to establish a pulse voltage waveform at the edge control electrode, A second high-frequency filter assembly electrically coupled between the second pulse voltage waveform generator and the second conductor, A high-frequency power supply configured to be electrically coupled to the support base or the first bias electrode via a third conductor, and to establish a high-frequency waveform at the support base or the first bias electrode, A pulse voltage filter assembly electrically coupled between the high-frequency power supply and the third conductor, A plasma processing chamber equipped with the following features.

10. The plasma processing chamber according to claim 9, further comprising a parallel plate structure having an effective capacitance of 3 nF to 50 nF, comprising the first bias electrode and the second dielectric layer.

11. The plasma processing chamber according to claim 9, wherein the thickness of the second dielectric layer is 0.1 mm to 1 mm.

12. A first filter coupling assembly configured to electrically couple the filter end of the first conductor to the first high-frequency filter assembly, A first electrode coupling assembly configured to electrically couple the second end of the first conductor to the first bias electrode, A first generator output coupling assembly configured to electrically couple the first pulse voltage waveform generator to the first high-frequency filter assembly, A chucking assembly comprising a first chucking power supply electrically coupled to the high-frequency filter terminal of the first generator output coupling assembly, The plasma processing chamber according to claim 9, further comprising:

13. A second filter coupling assembly configured to electrically couple the filter end of the second conductor to the second high-frequency filter assembly, A second electrode coupling assembly configured to electrically couple the second end of the second conductor to the edge control electrode, A second generator output coupling assembly configured to electrically couple a pulse voltage generator to the second high-frequency filter assembly, The chucking assembly comprises a second chucking power supply electrically coupled to the high-frequency filter terminal of the second generator output coupling assembly, The plasma processing chamber according to claim 12, further comprising:

14. A blocking resistor having a resistivity exceeding 500 k ohms, disposed between the first chucking power supply and the high-frequency filter terminal of the first generator output coupling assembly, A diode connected in parallel with the aforementioned blocking resistor, The plasma processing chamber according to claim 13, further comprising:

15. The plasma processing chamber according to claim 9, wherein the pulse voltage filter assembly comprises a blocking capacitor.

16. The plasma processing chamber according to claim 15, further comprising an RF matching circuit electrically coupled between the pulse voltage filter assembly and the support base.

17. The substrate support assembly is A second bias electrode is disposed between the support base and the first bias electrode, One or more vias having a first end that electrically contacts the first bias electrode and a second end that electrically contacts the second bias electrode, The plasma processing chamber according to claim 9, further comprising:

18. The plasma processing chamber according to claim 5, wherein the chucking assembly comprises a first end of a bias compensation circuit element and a second end of the bias compensation circuit element.

19. The plasma processing chamber according to claim 18, wherein the high-frequency filter assembly is coupled to the first end of the bias compensation circuit element, and the chucking power supply is electrically coupled to the second end of the bias compensation circuit element.

20. The plasma processing chamber according to claim 19, wherein the blocking resistor is disposed between the chucking power supply and the generator output coupling assembly, and the generator output coupling assembly is coupled to the first end of the bias compensation circuit element.

Images