Synchronous reverse-blocking switch for soft-switching current source converters, and soft-switching current source converters including the same

Abstract

A synchronous reverse blocking switch for a soft-switching current source converter (SSCSC), comprising: a first controlled switch; a second controlled switch connected in series with the first controlled switch; and a delay generation circuit configured to control the second controlled switch to turn on after a delay (t_dON) after the first controlled switch turns on, and to control the second controlled switch to turn off after a delay (t_dOFF) after the first controlled switch turns off.

Description

Technical Field

[0001] (Cross - Reference to Related Applications)

[0002] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 041,632, filed on June 19, 2020, entitled "Synchronous Reverse Blocking Switch for Soft - Switching Current Source Converters", which is hereby incorporated by reference in its entirety.

[0003] (Technical Field) The present disclosure relates to power converters, and more particularly, to reverse blocking switches for soft - switching current source converters.

Background Art

[0004] Current - Sourced Converters (CSC) require a reverse blocking (RB) switch as a main semiconductor device. Conventionally, CSCs have larger conversion losses than voltage - sourced ones, so they are mainly used in high - power applications and operate at low switching frequencies. In that case, reverse blocking switches such as thyristors, GTOs, and IGCTs were essentially appropriate choices.

[0005] In related technologies, a soft-switching CSC (SSCSC) topology, named Soft-Switching Solid-State Transformer (S4T), has been proposed, which has the potential to significantly reduce or substantially eliminate semiconductor switching losses through zero-voltage switching (ZVS) operation and dramatically increase switching frequencies. This new family of modular power converters features flexible input / output interfaces with DC, single-phase, or multi-phase AC power sources and loads, high-frequency isolation, fast control dynamics, low dv / dt, good failure modes, and high conversion efficiency. A description of S4T may be found in PCT application PCT / US2019 / 042969 dated July 23, 2019, and PCT application PCT / US2017 / 033186 dated May 17, 2017, and their entire disclosures are incorporated herein as if they were fully described below by reference. Another family of soft-switching CSC topologies, named Soft-Switching Current Source Inverters (SSCSI), has been proposed in related technologies and can also benefit from the synchronous reverse-blocking switches disclosed herein. A description of SSCSI may be found in PCT application PCT / US2020 / 047882, the entire disclosure of which is incorporated herein as if it were fully described below by reference.

[0006] As a non-limiting example, the S4T topology is suitable for industrial power electronics applications at 480VAC and >600VDC, and can be extended to medium voltage AC (MVAC) and medium voltage DC (MVDC) by stacking multiple modules in series. To achieve the high-frequency operation potential of the topology, related RB switches may consist of a series connection of diodes with high-speed switching control elements such as MOSFETs or IGBTs. This allows for a simple and robust switch structure that offers a good balance of cost and efficiency for most applications.

[0007] Furthermore, the S4T topology can be used to interface with touch-safe 48VDC power supplies (such as lithium batteries and solar panels) in high-current, low-voltage applications, and to address future low-voltage power conversion needs. Examples include 48VDC hybrid vehicle systems, intrinsically safe explosion-proof low-voltage modular electric vehicle (EV) powertrains, power supply to 5G wireless access points and data centers, and high-speed deployment AC power supplies used after grid failures or in modular microgrids. In these applications, the related RB technology can include ultra-low resistance silicon MOSFETs or gallium nitride HEMTs in series with the diodes to limit the voltage drop between active elements. However, the inventors have found that the forward voltage drop of the series low-voltage diode remains similar to that of the high-voltage class diodes used in the related S4T technology, and accounts for a significant portion of the conduction losses at the switch position. For example, the inventors have found that 92% of the 5.3% efficiency loss in a 48VDC bridge may be attributable to the diodes.

[0008] A similar observation holds true in SSCSC applications of related technologies, where the voltage drop across the series-connected diodes is considerably higher than the voltage drop across the series-connected control switches.

[0009] Therefore, it is desirable to improve the efficiency of the converter by improving or replacing the RB configuration. Aspects of this disclosure relate to these and additional issues. [Overview of the project]

[0010] This disclosure relates to synchronous reverse blocking switches (SRBS) for soft-switching current source converters. An example of an embodiment of this disclosure provides a synchronous reverse blocking switch for a soft-switching current source converter (SSCSC), the switch comprising: a first controlled switch; a second controlled switch connected in series with the first controlled switch; and a delay generating circuit configured to control the second controlled switch to turn on after a delay (t_dON) after the first controlled switch is turned on, and to control the second controlled switch to turn off after a delay (t_dOFF) after the first controlled switch is turned off.

[0011] An example of an embodiment of the present disclosure provides a Soft-Switching Current Source Converter (SSCSC), the SSCSC comprising: a first SSCSC bridge comprising at least one leg having two synchronous reverse-blocking switches connected in series, each of the synchronous reverse-blocking switches including a first controlled switch, a second controlled switch connected in series with the first controlled switch, and a delay generating circuit that controls the second controlled switch to turn on after a delay (t_dON) after the first controlled switch is turned on, and the second controlled switch to turn off after a delay (t_dOFF) after the first controlled switch is turned off; a second SSCSC bridge; and an inductive element connected between the first and second SSCSC bridges.

[0012] One embodiment of the present disclosure provides a synchronous reverse-blocking switch package for a soft-switching current source converter (SSCSC), the switch package comprising: a first controlled switch; a second controlled switch connected in series with the first controlled switch; and a delay generation circuit configured to control the second controlled switch to turn on after a delay (t_dON) after the first controlled switch turns on, and to control the second controlled switch to turn off after a delay (t_dOFF) after the first controlled switch turns off.

[0013] One embodiment of the present disclosure provides a synchronous reverse blocking switch (SRBS) package for a soft-switching current source converter (SSCSC), the SRBS package comprising a plurality of SRBS modules, each of which comprises a first controlled switch, a second controlled switch connected in series with the first controlled switch, and a delay generation circuit configured to control the second controlled switch to turn on after a delay (t_dON) after the first controlled switch turns on, and to control the second controlled switch to turn off after a delay (t_dOFF) after the first controlled switch turns off.

[0014] These and other aspects of the Disclosure are described below in the detailed description and accompanying drawings. Other aspects and features of the embodiments will become apparent to those skilled in the art by considering the following descriptions of specific and exemplary embodiments in conjunction with the drawings. Features of the Disclosure may be discussed in relation to specific embodiments and drawings, but all embodiments of the Disclosure may include one or more of the features discussed herein. Furthermore, one or more embodiments may be discussed as having particular advantageous features, and one or more such features may be used in conjunction with the various embodiments discussed herein. Similarly, exemplary embodiments may be described below as embodiments of apparatus, systems, or methods, but it should be understood that such exemplary embodiments can be implemented as various apparatus, systems, and methods of the Disclosure.

[0015] The following detailed description of specific embodiments of this disclosure will be better understood in conjunction with the accompanying drawings. Specific embodiments are shown in the drawings for illustrative purposes of this disclosure. However, it should be understood that this disclosure is not limited to the exact arrangement or means of the embodiments shown in the drawings. [Brief explanation of the drawing]

[0016] [Figure 1A] Figure 1A shows a soft-switching current source converter using related technology. [Figure 1B] Figure 1B shows an RB switch assembly for a soft-switching current source converter using related technology. [Figure 2A] Figure 2A shows a synchronous RB switch for a soft-switching current source converter according to an embodiment of the present disclosure. [Figure 2B] Figure 2B shows a synchronous RB switch for a soft-switching current source converter according to an embodiment of the present disclosure. [Figure 3] Figure 3 shows a soft-switching current source converter using an example of a synchronous RB switch according to one embodiment of the present disclosure. [Figure 4]Figure 4 shows an example of the gate sequence waveform of a synchronous RB switch in a soft-switching current source converter DC bridge according to one embodiment of the present disclosure. [Figure 5A] Figure 5A shows the switching state of a soft-switching current source converter DC bridge according to one embodiment of the present disclosure. [Figure 5B] Figure 5B shows the switching state of a soft-switching current source converter DC bridge according to one embodiment of the present disclosure. [Figure 5C] Figure 5C shows the switching state of a soft-switching current source converter DC bridge according to one embodiment of the present disclosure. [Figure 5D] Figure 5D shows the switching state of a soft-switching current source converter DC bridge according to one embodiment of the present disclosure. [Figure 5E] Figure 5E shows the switching state of a soft-switching current source converter DC bridge according to one embodiment of the present disclosure. [Figure 6A] Figure 6A shows a synchronous reverse blocking switch according to an embodiment of the present disclosure. [Figure 6B] Figure 6B shows a synchronous reverse blocking switch according to an embodiment of the present disclosure. [Figure 7] Figure 7 shows a switch package having a synchronous RB switch according to one embodiment of the present disclosure. [Modes for carrying out the invention]

[0017] To facilitate an understanding of the principles and features of the present invention, various exemplary embodiments will be described below. The components, steps, and materials described below as constituting the various elements of the embodiments disclosed herein are for purposes of illustration and not intended to be limiting. It is intended that many suitable components, steps, and materials performing the same or similar functions as the components, steps, and materials described herein be included within the scope of the present disclosure. Such other components, steps, and materials not described herein may include, but are not limited to, similar components or steps developed after the development of the embodiments disclosed herein. The present disclosure relates to a synchronous reverse blocking switch for a soft switching current source converter.

[0018] Figure 1 shows an example of a soft-switching current source converter topology 100 using related technology. The isolated converter 100 includes four elements: (1) a high-frequency (HF) transformer 110 (e.g., a multi-winding HF transformer) that provides galvanic isolation and a certain amount of energy storage; (2) a current source converter (CSC) bridge 130 that serves as the interface between the current source and the load; (3) a terminal LC filter 140 for suppressing harmonics; and (4) an auxiliary resonant circuit 120 that provides a zero-voltage switching (ZVS) state to all main components. The CSC bridge 130 is configured with a reverse-blocking switch 132 (e.g., a reverse-blocking switch 132) in the phase leg that conducts current in one direction but blocks voltage in both directions. As shown in Figure 1B, the switch 132 can be a switch assembly including a reverse-conducting controlled switch (e.g., a functionally equivalent element such as an IGBT 192a, MOSFET 192b, or a High-Electron-Mobility Transistor (HEMT)) connected in series with the diode 194. The controlled switch may have gate-controlled ON and gate-controlled OFF states. This allows the SSCSC to potentially take advantage of the high-frequency operation potential of the topology. The controlled switch and / or diode can be formed from silicon, silicon carbide, and / or wide-bandgap semiconductors. The auxiliary resonant circuit 120 includes active elements Sr 122 (e.g., a reverse-blocking switch or reverse-blocking switch assembly), inductor 124 (e.g., a resonant inductor 124), capacitor 126 (e.g., a resonant capacitor 126), and diode 128 (e.g., a damping diode 128) arranged within the auxiliary resonant circuit 120 between capacitor 126 and transformer 110. The active element Sr122 can be used in the form of an IGBT in series with a diode, an RB-IGBT, a thyristor, etc.Due to the leakage inductance of the transformer, two auxiliary resonant circuits 120 may be required to provide ZVS transitions to the elements of the input and output CSC bridges 130, respectively. FIG. 1 shows a topology applicable to a three-phase to three-phase converter, and those skilled in the art will recognize, in light of the present disclosure, that aspects of the present disclosure are applicable to alternative configurations (e.g., single-phase versions, VAR compensators, DC-AC, DC-DC, and non-insulated topologies, etc.).

[0019] However, as described above, soft-switching isolated converter topologies in the related art may suffer from large efficiency losses from the diodes of the RB switch assembly 132. Therefore, there is a need to provide an alternative solution to improve circuit efficiency.

[0020] FIGS. 2A and 2B show synchronous reverse blocking switches (SRBS) 232a, 232b according to aspects of the present disclosure. As shown in FIG. 2A, SRBS 232a includes a first controlled switch 292 (e.g., an active switch or S_A), a second controlled switch 294 (e.g., a rectifier switch or S_R), and a passive delay generation circuit 298a configured to passively delay the activation / deactivation signal of S_R 294, connected in series via each reference pin (e.g., the source pin of a MOSFET and the emitter pin of an IGBT). S_A 292 and S_R 294 may be N-channel MOSFETs, but this is merely an example. S_R 294 replaces the diode 194 of switch 132b. The reverse conduction path 295 (e.g., body diode 295 or anti-parallel diode 295) of S_R 294 functions as the series diode 194 of RB switch 132b when S_R 294 turns off. Therefore, to reduce the conduction loss of SRBS 232a, it is desirable to turn on the channel of switch S_R 294 to minimize the conduction time of the reverse conduction path 295.

[0021] The gate driver 296a controls the combination 260a of S_A292, S_R294, and delay circuit 298a by receiving a single gate reference connection from the combination using a single gate output. Furthermore, the gate driver 296a may receive a single gate control signal from the control system of the soft-switching current source converter. Thus, the combination 260a of S_A292, S_R294, and delay circuit 298a can be fully compatible with the reverse-blocking switches 132a and 132b in related technologies, and the gate driver 296a may be a standard gate driver used in soft-switching current source converters in related technologies.

[0022] As shown in Figure 2B, the SRBS232b includes a first controlled switch 292 (e.g., an active switch or S_A) and a second controlled switch 294 (e.g., a rectifier switch or S_R) connected in a manner similar to that described with reference to Figure 2A. However, the delay circuit 298b is included within the gate driver 296b and may be implemented using an active circuit. Thus, the gate driver 296b may be a dedicated gate driver 296b configured to implement a delay function (and / or additional functions) in addition to the functions commonly available in the related art. Furthermore, the gate driver 296b may receive a single gate control signal from the control system of the soft-switching current source converter.

[0023] SRBS232a and 232b may utilize methodologies that take advantage of the operating principles and switching environments of soft-switching current source converter topologies such as S4T topologies, thereby taking advantage of the reduced conduction losses of dual-switch structures while mitigating the related technical problems regarding sensitivity to reverse recovery and shoot-through faults, which are typical in this type of structure.

[0024] In particular, the unique switching environment of the soft-switching current source converter, combined with appropriate gate driver 296b circuits and / or delay circuits 298a, 298b and control, eliminates the reverse recovery phenomenon of the reverse conduction path 295. Furthermore, under normal operation, there is no risk of a shoot-through condition. These represent a significant improvement over the dual-switch structure of related technologies in conventional converters, which require complex monitoring and gating strategies that limit the use of switch channel conduction, as shoot-through conditions and fault modes can occur with each switching cycle. Moreover, in some applications of related technologies, these undesirable events can only be avoided by precisely timed multi-step gate sequences that are prone to catastrophic failures and rely on advanced, high-speed, and accurate sensing techniques. Additionally, or alternatively, related technologies often cannot avoid the reverse recovery effect unless broadbandgap technology is used in the switch, which is not always possible or feasible in all situations.

[0025] Figures 1 and 3 show a current source converter having an HF transformer 110, but those skilled in the art will recognize, in light of this disclosure, that various alternative inductive elements may be included as energy storage in various configurations within the previously disclosed soft-switching current source converters without departing from the scope of this disclosure. Non-limiting examples include shunt inductors or series inductors, both of which have a suitable resonant circuit.

[0026] Figure 3 shows an example of an S4T 300 utilizing a synchronous reverse-blocking switch 232. As can be seen from the figure, the DC bridge 310 utilizes the reverse-blocking switch 232, and the AC bridge 320 utilizes the reverse-blocking switch 132. Figure 3 shows a 1kW 48VDC to 240VAC S4T. Those skilled in the art will understand in light of this disclosure that this is merely an example and that the synchronous reverse-blocking switch 232 may be used in various additional or alternative S4T implementations.

[0027] Figure 4 shows an example of the gate sequence waveform 400 of the DC bridge 310, where power is circulated over the battery port. Figures 5A to 5E show the various switching states of the DC bridge 310. Initially (t0), the DC bridge 310 is set to state 1 (Figure 5B), with S_A292 (S1_A) of S1 and S_A292 (S4_A) of S4 being turned on. After a turn-on delay (t_dON), S_R294 (S1_R) of S1 and S_R294 (S4_R) of S4 are turned on at t1. Next, the DC bridge 310 switches to state 0 (Figure 5A) (t2), with S_A292 (S1_A) of S1 being turned off and S_A292 (S3_A) of S3 being turned on. After another delay time (t_dOFF), S1's S_R294 (S1_R) is turned off at t3. At t4, the ZVS transition is completed and DC bridge 310 switches to state 2 (Figure 5C). At t5, S3's S_R294 (S3_R) is turned on.

[0028] At t6, the DC bridge 310 transitions back to state 0. S_A292 (S4_A) of S4 is turned off, and S_A292 (S6_A) of S6 is turned on. At t7, S_R294 (S4_R) of S4 is turned off after a delay (t_dOFF). The DC bridge 310 switches to state 3 (Figure 5D) at t8. At t9, S_R294 (S6_R) of S6 is turned on. At t10, both S_A292 (S3_A) of S3 and S_A292 (S6_A) of S6 are turned off, and the DC bridge 310 transitions back to its original state 0, and then at t11, S_R294 (S3_R) of S3 and S_R294 (S6_R) of S6 are turned off. As will be understood by those skilled in the art in light of this disclosure, S_R294(S3_R) of S3 and S_R294(S6_R) of S6 may be turned off at different times. In some cases, one or both of S_R294(S3_R) of S3 and S_R294(S6_R) of S6 may be turned off at any point after t10 and before t13. At t12, switch Sres is turned on, bridge 310 transitions to state 4 (Figure 5E), and the polarity of the resonant capacitor voltage reverses between t12 and t14. DC bridge 310 transitions back to state 0 before the cycle restarts at t15 / t0.

[0029] t_dON may be a fixed time such that t_dON is greater than the ZVS transition time t_S0 of the DC bridge 310 in order to avoid undesirable hard switching behavior. All switches S1-S6 can have the same t_dON. However, this is just an example, and in some cases, at least one switch S1-S6 may be designed to have a different t_dON, and a catastrophic failure will not occur if at least one switch S1-S6 has a t_dON less than the transition time t_S0.

[0030] t_dOFF may be a fixed time such that t_dOFF is shorter than the period (t_2R) between the switch to state 0 at t10 and the start of the resonant capacitor voltage polarity reversal where the voltage across at least one of the second controlled switches S_R294 (e.g., S1_R for S1, S3_R for S3, or S6_R for S6) becomes positive at t13 (e.g., the minimum resonant time of the DC bridge 310). This allows all switches S1-S6 to have the same t_dOFF and is protected from a possible shoot-through condition. However, this is merely an example, and as will be understood by those skilled in the art in light of this disclosure, each S_R294 should be turned off by the time the resonant capacitor voltage matches the voltage of the most negative vector at t13. Earlier switching in a cycle can take advantage of a longer t_dOFF than later switching in a cycle. Furthermore, in light of this disclosure, it will be understood by those skilled in the art that this delayed turn-off of each S_R294 minimizes and / or prevents the reverse recovery problem. It will also be understood in light of this disclosure that this delayed turn-off of each S_R294 is made possible by the inherent switching environment of the SSCSC.

[0031] t_dON and t_dOFF may be controlled by a gate driver 296 having a dedicated delay generation circuit and / or passive delay circuit. For example, in Figure 6A, SRBS600a includes a gate driver 296a (e.g., a standard gate driver) and a switch module 650a. The gate driver 296a includes a digital isolator 605, an isolated power supply 610, a gate driver integrated circuit 615a, and enable logic 620 (e.g., hardware and / or software enable logic) for activating the gate driver integrated circuit 615a. The gate driver integrated circuit 615a provides a single activate and / or deactivate signal for the combination of S_A292 and S_R294. The delay generation circuit 690a may passively generate t_dON and t_dOFF from this single signal.

[0032] In some cases, the switch module 650a may be a standalone package including a rectifier switch, an active switch, and a passive delay generation circuit 690a. One gate control input pin and a reference voltage pin may be exposed to the gate driver. Therefore, since the gate driver does not control the active switch and the rectifier switch independently, the gate driver may not be able to distinguish between a package containing the switch module 650a and a package containing a conventional switch. Thus, the switch module 650a may operate without special high-level control (i.e., control of the gate driver or the entire circuit) and may function as a fully compatible reverse-blocking switch in a soft-switching current source converter in related technology.

[0033] As will be understood by those skilled in the art in light of this disclosure, multiple switch modules 650a may be incorporated into a single package, with each switch module 650a providing its own gate control input pins and reference voltage pins. For example, four (or six) switch modules 650a may be incorporated into a single package. In such a case, the package may have four (or six) gate control input pins and four (or six) reference voltage pins corresponding to each switch module 650a. Figure 7 shows a switch package 700 having six switch modules 650a according to an aspect of this disclosure. Each switch module 650a has its own gate control pins (GS1 to GS6) and reference voltage pins (SS1 to SS6). Furthermore, the switch package may have phase terminals A, B, and C, and positive and negative DC current terminals.

[0034] In Figure 6B, SRBS600b includes a gate driver 296b and a switch module 650b. The gate driver 296b includes a digital isolator 605, an isolated power supply 610, a gate driver integrated circuit 615b, and enable logic 620 (e.g., hardware and / or software enable logic) for activating the gate driver integrated circuit 615b. In this implementation, the gate driver 296b may further include a precision voltage reference 625 and a delay generation circuit 690b. The delay generation circuit 690b may be implemented in hardware, software, or a combination of hardware and software. Because the delay generation circuit 232b is included in the gate driver 296b, the gate driver integrated circuit 615b can activate / deactivate S_A292 and S_R294, respectively.

[0035] Furthermore, the gate driver 296b may also measure the voltage across S_R294 using, for example, a drain-source voltage detection circuit 630 (e.g., a voltage divider). On the other hand, fault protection logic 635 (e.g., fault protection circuit, comparator circuit) may receive the voltage measurement from the detection circuit 630 and prevent activation and / or deactivation, or send an activation / deactivation signal to S_R294 (e.g., via an AND gate 640). For example, if the voltage across S_R294 is positive (e.g., measured for the reference terminal voltages of S_R294 and S_A292, the measured voltage corresponds to the drain-source voltage if S_R294 is implemented using a MOSFET or HEMT), fault protection logic 635 may prevent S_R294 from being turned on / activated. In other words, to eliminate the possibility of shoot-through under abnormal operating conditions, SRBS600b uses gate control that detects the drain-source voltage of switch S_R294, preventing the element from being gate-on if the reverse conduction path 295 of S_R294 is reverse-biased (e.g., the drain-source voltage is positive). An additional benefit of this protection mechanism is that the switching transition (e.g., zero-voltage switching) is reliably completed even if the condition t_dON is shorter than the ZVS transition time t_S0, and generally the timing constraints described above for t_dON and t_dOFF are relaxed. In another example, if the voltage across S_R294 exceeds a threshold, fault protection logic 635 may force S_R294 to be turned off / deactivated.

[0036] In some cases, the SRBS600a or 600b may be a standalone solution including a rectifier switch, an active switch, and a gate driver. One gate signal and one enable signal may be supplied to the package from the power converter control system. Therefore, since the power converter control system does not control the active switch and the rectifier switch independently, the power converter control system may not be able to distinguish between implementations including the switch assembly SRBS600a / 600b and implementations including switches in related technologies. Thus, the switch assembly SRBS600a / 600b may operate without special high-level control (i.e., control from the power converter control system).

[0037] As those skilled in the art will understand, the proposed SRBS232 / 600 described herein may have several advantages. In no particular order, firstly, the SRBS232 / 600 can reduce conduction losses in SSCSC applications by up to an order of magnitude, depending on the application. Furthermore, these savings are achieved without being plagued by reverse recovery problems or complex fault modes, or without relying on the complex / advanced gating patterns required in related technological solutions.

[0038] Secondly, a simple control technique that can fix the on and off gating delays (t_dON and t_dOFF) of S_R294 allows for leveraging a unique SSCSC switching environment to minimize or eliminate reverse recovery and improve conduction losses, regardless of the semiconductor technology used and even when standard silicon elements are employed.

[0039] Thirdly, by utilizing a unique SSCSC switching environment, the operating range of t_dON and t_dOFF is significantly wider than the timing control required by related technological solutions. This can be achieved without compromising efficiency or safe operation. In other words, t_dON and t_dOFF can be set to a wide range of values, without requiring precise repeatability without affecting the operation of SRBS or soft-switching current source converters including them.

[0040] Fourth, using a gate driver with integrated delay generation (e.g., 298b) or a module with a gate driver (e.g., 296a) and passive delay generation circuitry (e.g., 650a) can abstract away the complexity of controlling two switches S_A292 and S_R294 from a high-level power converter control system. That is, the main controller only needs to send one turn-on / turn-off signal per switch position, and the SRBS232 / 600 appropriately derives the appropriate gate sequence for driving the physical switches S_A292 and S_R294.

[0041] Furthermore, a relatively simple fault protection mechanism may be implemented at the gate driver level by detecting the drain-source voltage of the S_R294 switch and preventing the switch position from turning on and / or forcibly turning it off if the polarity of the drain-source voltage is positive (e.g., the body diode is reverse-biased) and / or exceeds a threshold. This can provide a robust and durable structure even under abnormal conditions, including converter transients and failures.

[0042] Furthermore, the SRBS232 / 650a can be integrated into standard power module designs by implementing an S_R delay generation circuit using passive components, requiring only one gate pin per SRBS switch position, and simplifying integration with related technologies such as S4T and SSCSI variations, standard gate drivers, and system controllers.

[0043] Furthermore, the SRBS232 / 600b can be integrated into standard power module designs by implementing S_R delay generation using a dedicated gate driver circuit, which requires only one gate control connection per SRBS switch position, simplifying integration with related S4T and SSCSI variations and system controllers.

[0044] The additional features of the synchronous reverse-blocking switch in S4T applications are described by the inventors A. Marellapudi, MJ Mauger, P. Kandula and D. Divan, "Enabling High Efficiency in Low-Voltage Soft-Switching Current Source Converters," 2020 IEEE Energy Conversion Congress and Exposition (ECCE), 2020, pp. 3456-3463, doi:10.1109 / ECCE44975.2020.9235719, and by reference, the entirety of that disclosure is incorporated herein as if it were described below.

[0045] One embodiment of this disclosure can be carried out in accordance with at least the following:

[0046] Item 1: A synchronous reverse blocking switch for a soft-switching current source converter (SSCSC), comprising: a first controlled switch; a second controlled switch connected in series with the first controlled switch; and a delay generation circuit configured to control the second controlled switch to turn on after a delay (t_dON) after the first controlled switch turns on, and to control the second controlled switch to turn off after a delay (t_dOFF) after the first controlled switch turns off.

[0047] Item 2: t_dON is a predetermined duration, a synchronous reverse blocking switch as described in Item 1.

[0048] Item 3: t_dON is a fixed duration synchronous reverse blocking switch as described in Item 1 or Item 2.

[0049] Item 4: t_dOFF is a predetermined duration, a synchronous reverse blocking switch as described in any of Items 1 to 3.

[0050] Item 5: t_dOFF is a fixed duration, a synchronous reverse blocking switch as described in any of Items 1 to 4.

[0051] Item 6: A synchronous reverse-blocking switch as described in any of Items 1 through 6, further comprising a gate driver.

[0052] Item 7: The gate driver is a synchronous reverse-blocking switch as described in Item 6, including the delay generation circuit.

[0053] Item 8: The synchronous reverse-blocking switch according to any one of Items 1 to 7, wherein the delay generation circuit includes a delay circuit configured to delay the turn-on control signal for the second controlled switch by the delay t_dON and the turn-off control signal by the delay t_dOFF.

[0054] Item 9: A synchronous reverse blocking switch according to any one of Items 6 to 8, wherein the gate driver controls both the first controlled switch and the second controlled switch by transmitting a single activation signal and a single deactivation signal, and the delay generating circuit is located between the second controlled switch and the gate driver, and the delay generating circuit controls the second controlled switch to turn on after a delay t_dON and turn off after a delay t_dOFF.

[0055] Item 10: The delay generation circuit includes a passive delay circuit, and is a synchronous reverse-blocking switch as described in any of Items 1 to 9.

[0056] Item 11: A synchronous reverse-blocking switch according to any one of Items 1 to 10, wherein the passive delay circuit is integrated within a package including the first and second controlled switches, and has a single gate control interface for controlling both the first and second controlled switches externally.

[0057] Item 12: A synchronous reverse-blocking switch according to any one of items 1 to 11, further comprising a gate driver having a detection circuit configured to measure the voltage across the second controlled switch.

[0058] Item 13: The gate driver further comprises a fault protection circuit configured to prevent the second controlled switch from being turned on / activated in response to the detection circuit indicating that the voltage across the second controlled switch is positive, wherein the voltage across the second controlled switch is measured such that the voltage is positive when the second controlled switch interrupts the current, a synchronous reverse blocking switch as described in any of Items 6 to 12.

[0059] Item 14: A synchronous reverse-blocking switch according to any one of items 1 to 13, wherein at least one of the first controlled switch and the second controlled switch is a silicon switch.

[0060] Item 15: A synchronous reverse blocking switch according to any one of items 1 to 14, wherein at least one of the first controlled switch and the second controlled switch includes a silicon carbide switch or a gallium nitride switch.

[0061] Item 16: A synchronous reverse blocking switch according to any of items 1 to 15, wherein at least one of the first controlled switch and the second controlled switch is a metal-oxide-semiconductor field-effect transistor (MOSFET).

[0062] Item 17: The synchronous reverse-blocking switch according to Item 16, wherein the second controlled switch is connected in series with the first controlled switch via the source pin of the at least one MOSFET.

[0063] Item 18: A synchronous reverse-blocking switch as described in Item 16 or Item 17, wherein the first controlled switch and the second controlled switch are each MOSFETs, and the second controlled switch is connected in series with the first controlled switch via their respective source pins.

[0064] Item 19: A synchronous reverse-blocking switch according to any one of items 1 to 17, wherein at least one of the first controlled switch and the second controlled switch is a high-electron-mobility transistor (HEMT).

[0065] Item 20: The synchronous reverse-blocking switch according to Item 19, wherein the second controlled switch is connected in series with the first controlled switch via at least one high-electron-mobility transistor (HEMT).

[0066] Item 21: A synchronous reverse-blocking switch as described in Item 19 or Item 20, wherein the first controlled switch and the second controlled switch are each HEMT, and the second controlled switch is connected in series with the first controlled switch via their respective source pins.

[0067] Item 22: A synchronous reverse-blocking switch according to any of items 1 to 7, 19, and 20, wherein at least one of the first controlled switch and the second controlled switch is an insulated-gate bipolar transistor (IGBT).

[0068] Item 23: The synchronous reverse-blocking switch according to Item 22, wherein the second controlled switch is connected in series with the first controlled switch via the emitter pin of the at least one IGBT.

[0069] Item 24: A synchronous reverse-blocking switch as described in Item 22 or Item 23, wherein the first controlled switch and the second controlled switch are each IGBTs, and the second controlled switch is connected in series with the first controlled switch via their respective emitter pins.

[0070] Item 25: A synchronous reverse-blocking switch according to any one of Items 6 to 24, wherein the gate driver is configured to receive a single gate control signal from the main controller of a soft-switching current source converter and to control the first controlled switch and the second controlled switch.

[0071] Item 26: The gate driver is a synchronous reverse-blocking switch as described in any of Items 6 to 25, which is independent of the control method or modulation method of the soft-switching current source converter in which the synchronous reverse-blocking switch is used.

[0072] Item 27: A synchronous reverse-blocking switch as described in any of Items 1 to 26, wherein the individual control of the first controlled switch and the second controlled switch is not performed by the controller of the soft-switching current source converter in which the synchronous reverse-blocking switch is used.

[0073] Item 28: A synchronous reverse-blocking switch according to any one of Items 1 to 27, wherein the delay generation circuit is configured to control the first and second controlled switches such that the synchronous reverse-blocking switch is configured to minimize reverse recovery regardless of the switching technology used.

[0074] Item 29: A synchronous reverse-blocking switch according to any one of Items 1 to 28, wherein the delay generation circuit is configured to control the first and second controlled switches such that the synchronous reverse-blocking switch is configured to have no reverse recovery regardless of the switching technology used.

[0075] Item 30: t_dON is a synchronous reverse-blocking switch as described in any of items 1 to 29, wherein t_dON is greater than the zero-voltage switching (ZVS) transition time of the SSCSC bridge in which the synchronous reverse-blocking switch is used.

[0076] Item 31: t_dOFF is a synchronous reverse-blocking switch described in any of Items 1 to 30, which has a minimum resonant time less than that of the SSCSC bridge in which the synchronous reverse-blocking switch is used.

[0077] Item 32: The first controlled switch and the second controlled switch are different types of controlled switches, synchronous reverse blocking switches as described in any of Items 1 to 31.

[0078] Item 33: The second controlled switch is a synchronous reverse-blocking switch as described in any of Items 1 to 32, connected in series with the first controlled switch via its respective reference pins.

[0079] Item 34: A synchronous reverse blocking switch as described in any of Items 1 to 33, wherein the first controlled switch and the second controlled switch are connected in series in the opposite direction of current interruption.

[0080] Item 35: A synchronous reverse blocking switch according to any one of Items 1 to 34, wherein the first controlled switch and the second controlled switch are arranged to interrupt the current in the direction toward the series connection.

[0081] Item 36: A synchronous reverse blocking switch according to any one of Items 1 to 35, wherein the delay generation circuit is configured to receive a control signal for the first controlled switch, delay the control signal, and transmit the delayed control signal to the second controlled switch, thereby controlling the second controlled switch to be turned on after t_dON when the first controlled switch is turned on, and controlling the second controlled switch to be turned off after t_dOFF when the first control switch is turned off.

[0082] Item 37: A synchronous reverse blocking switch according to any one of items 6 to 36, wherein the gate driver further comprises a fault protection circuit configured to forcibly turn off / deactivate the second controlled switch in response to the detection circuit indicating that the voltage across the second controlled switch exceeds a threshold.

[0083] Item 38: A soft-switching current source converter (SSCSC) comprising: a first SSCSC bridge having at least one leg having two synchronous reverse-blocking switches as described in any of Items 1 to 37; a second SSCSC bridge; and an inductive element connected between the first and second SSCSC bridges.

[0084] Item 39: The SSCSC as described in Item 38, wherein the inductive element includes at least one of a high-frequency transformer, a series inductor, and a shunt inductor.

[0085] Item 40: A synchronous reverse-blocking switch package for a soft-switching current source converter (SSCSC), comprising the components described in any of items 1 through 37.

[0086] Item 41: A synchronous reverse blocking switch (SRBS) package for a soft-switching current source converter (SSCSC), comprising a synchronous reverse blocking switch as described in any of items 1 through 37.

[0087] Item 42: The SRBS package described in Item 41, further comprising a single gate control pin for each of the switch modules.

[0088] Item 43: An SRBS package as described in Item 42, comprising multiple pairs of SRBS modules.

[0089] Item 44: The SRBS package described in Item 43, further comprising phase terminals corresponding to each of the plurality of pairs of SRBS modules.

[0090] It should be understood that the embodiments and claims disclosed herein are not limited to their application to the details of the configuration and arrangement of the components shown in the description and drawings. Rather, the description and drawings provide examples of conceivable embodiments. The embodiments and claims disclosed herein are further possible and can be practiced and implemented in various ways. It should also be understood that the words and terms used herein are for illustrative purposes only and should not be considered as limiting the scope of the claims.

[0091] Therefore, those skilled in the art will understand that the concepts underlying the present application and claims can be readily used as a basis for designing other structures, methods, and systems to accomplish some of the embodiments and objectives of the claims presented herein. It is therefore important to consider the claims as encompassing such equivalent configurations.

[0092] Furthermore, the purpose of the above abstract is to enable the United States Patent and Trademark Office and the general public, especially those skilled in the art who are not familiar with patent or legal terminology, to quickly grasp the nature and essence of the technical disclosure of this application at a glance. The abstract does not define, nor does it limit, the claims of this application.

Claims

1. A synchronous reverse-blocking switch for a Soft-Switching Current Source Converter (SSCSC), The first controlled switch, A second controlled switch connected in series with the first controlled switch, A delay generation circuit, The second controlled switch is controlled to turn on after a delay (t_dON) after the first controlled switch is turned on. The second controlled switch is controlled to turn off after a delay (t_dOFF) after the first controlled switch is turned off. The first and second controlled switches are controlled so that both are turned on simultaneously during the overlap period. A delay generation circuit configured as follows, A detection circuit configured to measure the voltage across the second controlled switch, A fault protection circuit configured to prevent the second controlled switch from being turned on / activated in response to the detection circuit indicating that the voltage across the second controlled switch is positive, A gate driver having, A synchronous reverse blocking switch, wherein the voltage across the second controlled switch is measured such that the voltage becomes positive when the second controlled switch interrupts the current.

2. The synchronous reverse blocking switch according to claim 1, wherein the gate driver includes the delay generation circuit.

3. The synchronous reverse blocking switch according to claim 2, wherein the delay generation circuit is further configured to delay the turn-on control signal for the second controlled switch by the delay t_dON and the turn-off control signal by the delay t_dOFF.

4. The gate driver is configured to control both the first controlled switch and the second controlled switch by transmitting a single activation signal and a single deactivation signal, The delay generation circuit is located between the second controlled switch and the gate driver. The synchronous reverse blocking switch according to claim 1, wherein the delay generation circuit is further configured to control the second controlled switch so that it turns on after a delay t_d ON and turns off after a delay t_d OFF.

5. The synchronous reverse blocking switch according to claim 1, wherein the delay generation circuit includes a passive delay circuit having a single gate control interface configured to control both the first and second controlled switches externally, and is integrated within a package including the first and second controlled switches.

6. The synchronous reverse blocking switch according to claim 1, further comprising a fault protection circuit configured to forcibly turn off / deactivate the second controlled switch in response to the detection circuit indicating that the voltage across the second controlled switch exceeds a threshold.

7. The synchronous reverse blocking switch according to claim 1, wherein at least one of the first controlled switch and the second controlled switch is selected from the group consisting of a silicon switch, a silicon carbide switch, and a gallium nitride switch.

8. The synchronous reverse blocking switch according to claim 1, wherein at least one of the first controlled switch and the second controlled switch is selected from the group consisting of a metal-oxide-semiconductor field-effect transistor (MOSFET), a high-electron-mobility transistor (HEMT), and an insulated-gate bipolar transistor (IGBT).

9. The second controlled switch is connected to the first controlled switch, Through the source pin of at least one MOSFET, via the source pin of at least one HEMT, or Through the emitter pin of at least one IGBT, A synchronous reverse blocking switch according to claim 8, connected in series.

10. (i) The first controlled switch and the second controlled switch are each MOSFETs, The second controlled switch is connected in series with the first controlled switch via the respective source pins of the MOSFETs. (ii) The first controlled switch and the second controlled switch are each HEMT, The second controlled switch is connected in series with the first controlled switch via the respective source pins of the HEMT, or (iii) The first controlled switch and the second controlled switch are each IGBTs, The synchronous reverse blocking switch according to claim 1, wherein the second controlled switch is connected in series with the first controlled switch via the respective emitter pins of the IGBT.

11. The gate driver is configured to receive a single gate control signal from the main controller of the SSCSC and to control the first controlled switch and the second controlled switch, or The gate driver is independent of the control method and modulation method of the SSCSC in which the synchronous reverse-blocking switch is used. A synchronous reverse blocking switch according to claim 1, which is at least one of the following:

12. A synchronous reverse blocking switch for a Soft-Switching Current Source Converter (SSCSC), The first controlled switch, A second controlled switch connected in series with the first controlled switch, A delay generation circuit, The second controlled switch is controlled to turn on after a delay (t_dON) after the first controlled switch is turned on. The second controlled switch is controlled to turn off after a delay (t_dOFF) after the first controlled switch is turned off. The first and second controlled switches are controlled so that both are turned on simultaneously during the overlap period. A delay generation circuit configured to such an extent is provided, The individual control of the first controlled switch and the second controlled switch is not performed by the controller of the soft-switching current source converter in which the synchronous reverse-blocking switch is used. The delay generation circuit is configured to control the first and second controlled switches such that the synchronous reverse-blocking switch is configured to minimize reverse recovery regardless of the switching technology used. The delay generation circuit is configured to control the first and second controlled switches such that the synchronous reverse-blocking switch is configured to prevent reverse recovery regardless of the switching technology used. t_dON is greater than the zero-voltage switching (ZVS) transition time of the SSCSC bridge in which the synchronous reverse-blocking switch is used. t_dOFF is smaller than the minimum resonant time of the SSCSC bridge in which the synchronous reverse-blocking switch is used. The first controlled switch and the second controlled switch are different types of controlled switches. The second controlled switch is connected in series with the first controlled switch via their respective reference pins. The first controlled switch and the second controlled switch are connected in series in opposite current blocking directions. The first controlled switch and the second controlled switch are arranged in a direction that interrupts the current in the direction toward the series connection, or The aforementioned delay generation circuit is Upon receiving the control signal for the first controlled switch, The aforementioned control signal is delayed, By transmitting the delayed control signal to the second controlled switch, The system is configured to control the second controlled switch to be turned on after t_dON following the first controlled switch being turned on, and to control the second controlled switch to be turned off after t_dOFF following the first controlled switch being turned off. One of these is a synchronous reverse-blocking switch.

13. A detection circuit configured to measure the voltage across the second controlled switch, The gate driver further comprises a fault protection circuit configured to prevent the second controlled switch from being turned on / activated in response to the detection circuit indicating that the voltage across the second controlled switch is positive, The synchronous reverse blocking switch according to claim 12, wherein the voltage across the second controlled switch is measured such that the voltage becomes positive when the second controlled switch interrupts the current.

14. A synchronous reverse-blocking switch for a Soft-Switching Current Source Converter (SSCSC), The first controlled switch, A second controlled switch connected in series with the first controlled switch, A delay generation circuit, The second controlled switch is controlled to turn on after a delay (t_dON) after the first controlled switch is turned on. The second controlled switch is controlled to turn off after a delay (t_dOFF) following the first controlled switch has turned off. A delay generation circuit configured to such an extent is provided, The delay generation circuit is configured to control the first and second controlled switches such that the synchronous reverse-blocking switch is configured to minimize reverse recovery regardless of the switching technology used. The delay generation circuit is configured to control the first and second controlled switches such that the synchronous reverse-blocking switch is configured to prevent reverse recovery regardless of the switching technology used. t_dON is greater than the zero-voltage switching (ZVS) transition time of the SSCSC bridge in which the synchronous reverse-blocking switch is used, or t_dOFF is smaller than the minimum resonant time of the SSCSC bridge in which the synchronous reverse-blocking switch is used. One of these is a synchronous reverse-blocking switch.

15. A synchronous reverse-blocking switch for a Soft-Switching Current Source Converter (SSCSC), The first controlled switch, A second controlled switch connected in series with the first controlled switch, A delay generation circuit, The second controlled switch is controlled to turn on after a delay (t_dON) after the first controlled switch is turned on. The second controlled switch is controlled to turn off after a delay (t_dOFF) following the first controlled switch has turned off. A delay generation circuit configured as follows, A detection circuit configured to measure the voltage across the second controlled switch, A fault protection circuit configured to prevent the second controlled switch from being turned on / activated in response to the detection circuit indicating that the voltage across the second controlled switch is positive, A gate driver having, A synchronous reverse blocking switch, wherein the voltage across the second controlled switch is measured such that the voltage becomes positive when the second controlled switch interrupts the current.

16. The synchronous reverse blocking switch according to claim 15, wherein the gate driver includes the delay generation circuit.

17. The synchronous reverse blocking switch according to claim 16, wherein the delay generation circuit is further configured to delay the turn-on control signal for the second controlled switch by the delay t_dON and the turn-off control signal by the delay t_dOFF.

18. The gate driver is configured to control both the first controlled switch and the second controlled switch by transmitting a single activation signal and a single deactivation signal, The delay generation circuit is located between the second controlled switch and the gate driver. The synchronous reverse blocking switch according to claim 15, wherein the delay generation circuit is further configured to control the second controlled switch so that it turns on after a delay t_d ON and turns off after a delay t_d OFF.

19. The synchronous reverse blocking switch according to claim 15, wherein the delay generation circuit includes a passive delay circuit having a single gate control interface configured to control both the first and second controlled switches externally, and is integrated within a package including the first and second controlled switches.

20. The synchronous reverse blocking switch according to claim 15, wherein the gate driver further comprises a fault protection circuit configured to forcibly turn off / deactivate the second controlled switch in response to the detection circuit indicating that the voltage across the second controlled switch exceeds a threshold.

21. The synchronous reverse blocking switch according to claim 15, wherein at least one of the first controlled switch and the second controlled switch is selected from the group consisting of a silicon switch, a silicon carbide switch, and a gallium nitride switch.

22. The synchronous reverse blocking switch according to claim 15, wherein at least one of the first controlled switch and the second controlled switch is selected from the group consisting of a metal-oxide-semiconductor field-effect transistor (MOSFET), a high-electron-mobility transistor (HEMT), and an insulated-gate bipolar transistor (IGBT).

23. The second controlled switch is connected to the first controlled switch, Through the source pin of at least one MOSFET, via the source pin of at least one HEMT, or Through the emitter pin of at least one IGBT, A synchronous reverse blocking switch according to claim 22, connected in series.

24. (i) The first controlled switch and the second controlled switch are each MOSFETs, The second controlled switch is connected in series with the first controlled switch via the respective source pins of the MOSFETs. (ii) The first controlled switch and the second controlled switch are each HEMT, The second controlled switch is connected in series with the first controlled switch via the respective source pins of the HEMT, or (iii) The first controlled switch and the second controlled switch are each IGBTs, The synchronous reverse blocking switch according to claim 15, wherein the second controlled switch is connected in series with the first controlled switch via the respective emitter pins of the IGBT.

25. The gate driver is configured to receive a single gate control signal from the main controller of the SSCSC and to control the first controlled switch and the second controlled switch, or The gate driver is independent of the control method and modulation method of the SSCSC in which the synchronous reverse-blocking switch is used. A synchronous reverse blocking switch according to claim 15, which is at least one of the above.

26. The individual control of the first controlled switch and the second controlled switch is not performed by the controller of the soft-switching current source converter in which the synchronous reverse-blocking switch is used. The delay generation circuit is configured to control the first and second controlled switches such that the synchronous reverse-blocking switch is configured to minimize reverse recovery regardless of the switching technology used. The delay generation circuit is configured to control the first and second controlled switches such that the synchronous reverse-blocking switch is configured to prevent reverse recovery regardless of the switching technology used. t_dON is greater than the zero-voltage switching (ZVS) transition time of the SSCSC bridge in which the synchronous reverse-blocking switch is used. t_dOFF is smaller than the minimum resonant time of the SSCSC bridge in which the synchronous reverse-blocking switch is used. The first controlled switch and the second controlled switch are different types of controlled switches. The second controlled switch is connected in series with the first controlled switch via their respective reference pins. The first controlled switch and the second controlled switch are connected in series in opposite current blocking directions. The first controlled switch and the second controlled switch are arranged in a direction that interrupts the current in the direction toward the series connection, or The aforementioned delay generation circuit is Upon receiving the control signal for the first controlled switch, The aforementioned control signal is delayed, By transmitting the delayed control signal to the second controlled switch, The system is configured to control the second controlled switch to be turned on after t_dON following the first controlled switch being turned on, and to control the second controlled switch to be turned off after t_dOFF following the first controlled switch being turned off. A synchronous reverse blocking switch according to claim 15, which is at least one of the above.

27. A soft-switching current source converter (SSCSC), The first SSCSC bridge, The second SSCSC bridge, The system comprises an induction element connected between the first and second SSCSC bridges, The first SSCSC bridge comprises at least one leg having two synchronous reverse-blocking switches according to any one of claims 1 to 26, connected in series.

28. The SSCSC according to claim 27, wherein the inductive element includes at least one of a high-frequency transformer, a series inductor, and a shunt inductor.

29. A synchronous reverse-blocking switch package for a soft-switching current source converter (SSCSC), wherein the switch package includes a synchronous reverse-blocking switch according to any one of claims 1 to 26.

30. A synchronous reverse blocking switch (SRBS) package for a soft-switching current source converter (SSCSC), An SRBS package comprising a plurality of SRBS modules, each of which includes a synchronous reverse-blocking switch as described in any one of claims 1 to 26.

31. The SRBS package according to claim 30, further comprising a single gate control pin for each of the aforementioned SRBS modules.

32. The SRBS package according to claim 30, comprising a plurality of pairs of SRBS modules.

33. The SRBS package according to claim 32, further comprising phase terminals corresponding to each of the plurality of pairs of SRBS modules.

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