Indication device

Abstract

SOLUTION: A display device according to one embodiment comprises: a substrate in which a plurality of spaced pixel regions and a plurality of transmissive regions arranged between the pixel regions are defined, where each of the pixel regions includes a plurality of sub-pixels; and a plurality of signal lines that extend in a first direction on the substrate. The sub-pixels include a plurality of pixel circuits. The signal lines do not overlap the transmissive regions but overlap a region where the pixel circuits are arranged.EFFECT: Accordingly, the pixel regions and the signal lines are formed in the same region to reduce the area of an opaque region in the entire display device and enlarge the area of the transmissive regions to enable a transparent display device to materialize.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This specification relates to a transparent display device, and more particularly to a transparent display device using LEDs (Light Emitting Diodes).

Background Art

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light emitting display devices (Organic Light Emitting Display; OLED) that emit light by themselves, and liquid crystal display devices (Liquid Crystal Display; LCD) that require a separate light source, etc.

[0003] The application range of display devices is diverse not only in computer monitors and TVs but also in personal mobile devices, and research is underway on display devices that have a reduced volume and weight while having a large display area.

[0004] In recent years, display devices including LEDs have attracted attention as next-generation display devices. Since LEDs are made of inorganic substances that are not organic substances, they are excellent in reliability and have a longer lifespan than liquid crystal display devices and organic light emitting display devices. In addition, LEDs not only have a fast lighting speed but also have excellent luminous efficiency, strong impact resistance, excellent stability, and can display high-brightness images.

Summary of the Invention

Problems to be Solved by the Invention

[0005] The problem to be solved by this specification is to provide a transparent display device with a high transmittance.

[0006] Another problem to be solved by this specification is to provide a display device in which an opaque pixel region and a plurality of wirings are overlapped to maximize the area of the transmission region.

[0007] Another problem that this specification seeks to solve is to provide a display device that minimizes interference between the pixel area drive transistors and multiple data wirings.

[0008] Another problem that this specification seeks to solve is to provide a display device that minimizes fluctuations in the voltage and drive current of the drive transistor due to data routing.

[0009] Another problem that this specification seeks to solve is to provide a display device that improves display quality by minimizing the coupling between data wiring and drive transistors.

[0010] The problems described herein are not limited to those mentioned above, and other problems not mentioned can be clearly understood by those skilled in the art from the following description. [Means for solving the problem]

[0011] A display device according to one embodiment of this specification includes a substrate in which multiple pixel regions and multiple transparent regions arranged between the multiple pixel regions are defined, each spaced apart from the others, and multiple signal lines extending in a first direction on the substrate, wherein the multiple subpixels include multiple pixel circuits, and the multiple signal lines do not overlap the multiple transparent regions but overlap the regions in which the multiple pixel circuits are arranged. Therefore, by forming multiple pixel regions and multiple signal lines in the same region, the area of ​​opaque regions in the entire display device can be reduced, and the area of ​​transparent regions can be increased to realize a transparent display device.

[0012] Specific details of other embodiments are included in the detailed description and drawings. [Effects of the Invention]

[0013] This specification can realize a transparent display device with improved light transmittance.

[0014] This specification describes how opaque components of a display device can be superimposed on each other to maximize the area of ​​the transparent region in the display device.

[0015] This specification makes it possible to minimize voltage fluctuations in the drive transistor and the resulting drive current fluctuations caused by the coupling of data wiring and the drive transistor.

[0016] This specification can minimize crosstalk and brightness changes caused by the coupling of data wiring and drive transistors.

[0017] The effects described herein are not limited to those exemplified above, and a wider variety of effects are included within this specification. [Brief explanation of the drawing]

[0018] [Figure 1] This is a schematic diagram of a display device according to one embodiment of this specification. [Figure 2a] This is a partial cross-sectional view of a display device according to one embodiment of this specification. [Figure 2b] This is a perspective view of a tiling display device according to one embodiment of this specification. [Figure 3] This is a schematic enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. [Figure 4] This is an enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. [Figure 5] This is a cross-sectional view of a subpixel of a display device according to one embodiment of this specification. [Figure 6] This is a simulation result measuring the crosstalk level based on the thickness of the insulating layer. [Figure 7] This is an enlarged plan view of a display device according to another embodiment of this specification. [Figure 8] This is a cross-sectional view of a subpixel of a display device according to another embodiment of this specification. [Figure 9a] This graph shows the voltage and drive current of the drive gate electrode measured by the data voltage in the comparative example display device. [Figure 9b] This is a graph obtained by measuring the voltage and drive current of a driving gate electrode with a data voltage in a display device according to another embodiment of the present specification.

Embodiments for Carrying Out the Invention

[0019] The advantages and features of the present specification, and the methods for achieving them, will become clear by referring to the embodiments described in detail below together with the accompanying drawings. However, the present specification is not limited to the embodiments disclosed below, and is embodied in various different forms. Merely, these embodiments are provided so that the disclosure of the present specification becomes complete, and to fully inform those having ordinary knowledge in the technical field to which the present specification pertains of the scope of the invention.

[0020] The shapes, areas, ratios, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present specification are exemplary, so the present specification is not limited to the matters illustrated. Throughout the specification, the same reference numerals refer to the same components. Also, in explaining the present specification, when it is determined that a detailed description of related known technologies may muddy the gist of the present specification, the detailed description thereof is omitted. When terms such as "including", "having", "being made", etc. mentioned in the present specification are used, unless "only" is used, other parts may be added. When a component is expressed in the singular, it includes the case of including a plurality unless otherwise explicitly stated.

[0021] In interpreting a component, it is interpreted as including an error range even without a separate explicit description.

[0022] When explaining a positional relationship, for example, when a positional relationship between two parts is described such as "on ~", "above ~", "below ~", "next to ~", etc., unless "immediately" or "directly" is used, one or more other parts may be located between the two parts.

[0023] When an element or layer is referred to as "on" another element or layer, this includes cases where another layer or other element is interposed immediately above or between the other element.

[0024] Furthermore, while terms such as "first," "second," etc., are used to describe a variety of components, these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0025] Throughout the specification, the same reference numeral refers to the same component.

[0026] The area and thickness of each component shown in the drawings are provided for illustrative purposes only, and this specification is not necessarily limited to the area and thickness of the components shown.

[0027] The features of each of the various embodiments described herein can be combined or combined with one another, either partially or as a whole, enabling a variety of technically diverse interoperability and drive, and each embodiment may be implemented independently of the others or together in relation to one another.

[0028] In the following, this specification will be described with reference to the drawings.

[0029] Figure 1 is a schematic diagram of a display device according to one embodiment of this specification. In Figure 1, for the sake of explanation, only the display panel PN, gate drive unit GD, data drive unit DD, and timing controller TC are shown among the various components of the display device 100.

[0030] Referring to Figure 1, the display device 100 includes a display panel PN containing a plurality of subpixels SP, a gate drive unit GD and a data drive unit DD that supply various signals to the display panel PN, and a timing controller TC that controls the gate drive unit GD and the data drive unit DD.

[0031] The gate drive unit GD supplies multiple scan signals to multiple scan wirings SL based on multiple gate control signals provided by the timing controller TC. In Figure 1, one gate drive unit GD is shown spaced apart on one side of the display panel PN, but the number and arrangement of gate drive units GD are not limited to this.

[0032] The data drive unit DD supplies data voltages to multiple data lines DL based on multiple data control signals and video data provided by the timing controller TC. The data drive unit DD can convert video data into data voltages using a reference gamma voltage and supply the converted data voltages to the multiple data lines DL.

[0033] The timing controller TC aligns the video data input from an external source and supplies it to the data drive unit DD. The timing controller TC can generate gate control signals and data control signals using synchronization signals input from an external source, such as a dot clock signal, a data enable signal, and horizontal / vertical synchronization signals. The timing controller TC can then control the gate drive unit GD and the data drive unit DD by supplying the generated gate control signals and data control signals to the gate drive unit GD and the data drive unit DD, respectively.

[0034] The display panel PN is a configuration for displaying images to the user and includes multiple sub-pixels SP. Multiple scan lines SL and multiple data lines DL intersect each other in the display panel PN, and multiple sub-pixels SP may be formed at the intersection points of the scan lines SL and data lines DL.

[0035] The display panel PN may have a display area AA and a non-display area NA defined.

[0036] Display area AA is the area where the image is displayed on the display device 100. Display area AA may contain multiple subpixels SP that constitute multiple pixels PX, and pixel circuits for driving the multiple subpixels SP. Multiple subpixels SP are the smallest units that constitute display area AA, and n subpixels SP can form one pixel PX. Each of the multiple subpixels SP may contain a thin-film transistor or the like for driving multiple light-emitting elements 120. Multiple light-emitting elements 120 may be defined differently depending on the type of display panel PN. For example, if the display panel PN is an inorganic light-emitting display panel, the light-emitting elements 120 may be LEDs (Light-emitting Diodes) or micro-LEDs (Micro Light-emitting Diodes).

[0037] Multiple signal lines are arranged in the display area AA to transmit various signals to multiple sub-pixels SP. For example, the multiple signal lines may include multiple data lines DL that supply data voltage to each of the multiple sub-pixels SP, and multiple scan lines SL that supply scan signals to each of the multiple sub-pixels SP. Multiple scan lines SL may extend from the display area AA in one direction and be connected to the multiple sub-pixels SP, and multiple data lines DL may extend from the display area AA in directions other than one direction and be connected to the multiple sub-pixels SP. In addition, low-potential power supply lines, high-potential power supply lines, etc., may be further arranged in the display area AA, but are not limited to these.

[0038] The non-display area NA is an area where the image is not displayed, and can be defined as an area extending from the display area AA. Link wiring and pad electrodes for transmitting signals to the subpixels SP of the display area AA, as well as drive ICs such as gate driver ICs and data driver ICs, may be placed in the non-display area NA.

[0039] On the other hand, the non-display area NA may be located on the back of the display panel PN, i.e., on the side without subpixels SP, or it may be omitted, and is not limited to what is shown in the drawing.

[0040] On the other hand, drive units such as the gate drive unit GD, data drive unit DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gate drive unit GD may be implemented in the non-display area NA using the GIP (Gate In Panel) method, or it may be implemented in the display area AA between multiple sub-pixels SP using the GIA (Gate In Active Area) method.

[0041] For example, the data drive unit DD and timing controller TC are formed on separate flexible film and printed circuit boards, and the display panel PN and the data drive unit DD and timing controller TC can be electrically connected by bonding the flexible film and printed circuit board to pad electrodes formed in the non-display area NA of the display panel PN.

[0042] To give another example, when the gate drive unit GD is implemented inside the display area AA using the GIA method, and side wiring SRL is formed to connect the signal wiring on the front of the display panel PN to the pad electrodes on the back of the display panel PN, and a flexible film and printed circuit board are bonded to the back of the display panel PN, the non-display area NA on the front of the display panel PN can be minimized. Therefore, when the gate drive unit GD, data drive unit DD, and timing controller TC are connected to the display panel PN in the manner described above, it may be possible to realize a zero bezel where there is virtually no bezel, and for a more detailed explanation, please refer to Figures 2a and 2b.

[0043] Figure 2a is a partial cross-sectional view of a display device according to one embodiment of this specification. Figure 2b is a perspective view of a tiling display device according to one embodiment of this specification.

[0044] Multiple pad electrodes are arranged in the non-display area NA of the display panel PN to transmit various signals to multiple sub-pixels SP. For example, a first pad electrode PAD1 that transmits signals to multiple sub-pixels SP is arranged in the non-display area NA on the front of the display panel PN, and a second pad electrode PAD2 that is electrically connected to drive components such as flexible film and printed circuit boards is arranged in the non-display area NA on the back of the display panel PN.

[0045] In this case, although not shown in the drawing, various signal wirings connected to multiple sub-pixels SP, such as scan wiring SL and data wiring DL, can extend from the display area AA to the non-display area NA and be electrically connected to the first pad electrode PAD1.

[0046] Then, a side wiring SRL is positioned along the side of the display panel PN. The side wiring SRL can electrically connect the first pad electrode PAD1 on the front of the display panel PN and the second pad electrode PAD2 on the back of the display panel PN. Thus, signals from the drive components on the back of the display panel PN can be transmitted to multiple subpixels SP through the second pad electrode PAD2, the side wiring SRL, and the first pad electrode PAD1. Consequently, by positioning the drive components on the back of the display panel PN and forming a signal transmission path between the front and back of the display panel PN, the area of ​​the non-display region NA on the front of the display panel PN can be minimized.

[0047] Referring to Figure 2b, a tiling display device TD with a large screen can be realized by connecting multiple display devices 100. In this case, as shown in Figure 2a, when the tiling display device TD is realized using display devices 100 with minimized bezels, the seam area between the display devices 100 where images are not displayed can be minimized, which can improve display quality.

[0048] For example, a single pixel PX can contain multiple sub-pixels SP, and the spacing D1 between the outermost pixel PX of one display device 100 and the outermost pixel PX of another adjacent display device 100 can be identical to the spacing D1 between pixels PX within one display device 100. Thus, the spacing between pixels PX can be configured to be constant between display devices 100, minimizing the seam area.

[0049] However, Figures 2a and 2b are illustrative examples, and the display device 100 according to one embodiment of this specification may be a general display device with a bezel, and is not limited thereto.

[0050] In the following, the display panel PN of the display device 100 according to one embodiment of this specification will be described in more detail with reference to Figures 3 to 6.

[0051] Figure 3 is a schematic enlarged plan view of the pixel PX portion of the display area of ​​a display device according to one embodiment of this specification. Figure 4 is an enlarged plan view of the display area of ​​a display device according to one embodiment of this specification. Figure 5 is a cross-sectional view of a subpixel of a display device according to one embodiment of this specification. Figure 6 is a simulation result of measuring the crosstalk level due to the thickness of the insulating layer. In Figure 3, for the sake of explanation, only the scan wiring SL and data wiring DL are shown among the multiple wirings, and only one pixel area UPA and the multiple transparent areas TA surrounding one pixel area UPA are shown among the multiple pixel areas UPA.

[0052] Referring to Figure 3, the display area AA has a pixel area UPA on which a pixel PX is formed, and a transparent area TA surrounding the pixel area UPA. In the pixel PX of the display area AA, a pixel circuit including a driving element and a light-emitting element 120 driven by the pixel circuit are formed. As a result, the multiple pixel areas UPA on which pixel PX is formed may be substantially opaque regions, and the multiple transparent areas TA on which pixel PX is not formed may be substantially transparent regions. In this case, the pixel area UPA defined as having a pixel PX can also be defined as a light-emitting region because it is the region where the light emitted by the light-emitting element 120 is displayed. Furthermore, the pixel area UPA defined as having a pixel PX can also be defined as a circuit region because it is the region on which a pixel circuit including a driving element is formed.

[0053] Multiple pixel regions UPA are formed in the display region AA. These multiple pixel regions UPA are areas where driving elements and light-emitting elements 120 are arranged to display an image. The multiple pixel regions UPA may be arranged spaced apart from each other, separated by multiple transparent regions TA. For example, the multiple pixel regions UPA may be arranged in multiple rows and multiple columns.

[0054] Multiple subpixels SP are arranged in each of the multiple pixel regions UPA. Each of the multiple subpixels SP includes a light-emitting element 120 and a pixel circuit and can emit light independently. For example, the multiple subpixels SP may include a first subpixel SP1, a second subpixel SP2, and a third subpixel SP3 that emit light of different hues. For example, the first subpixel SP1 may be a red subpixel, the second subpixel SP2 may be a green subpixel, and the third subpixel SP3 may be a blue subpixel, but is not limited to this.

[0055] In the following explanation, we will assume that one pixel PX contains two first subpixels SP1, two second subpixels SP2, and two third subpixels SP3, i.e., two red subpixels, two green subpixels, and two blue subpixels. However, the configuration of pixel PX is not limited to this.

[0056] On the other hand, each of the pair of first subpixels SP1, the pair of second subpixels SP2, and the pair of third subpixels SP3 can be used as a main subpixel SP and a redundant subpixel SP. For example, one of the pair of first subpixels SP1, one of the pair of second subpixels SP2, and one of the pair of third subpixels SP3 may be the main subpixel SP that is basically used when the display device 100 is driven. When displaying an image, the main subpixel SP can be used preferentially. The remaining of the pair of first subpixels SP1, the remaining of the pair of second subpixels SP2, and the remaining of the pair of third subpixels SP3 can become redundant subpixel SPs, and if the main subpixel SP is faulty, the redundant subpixel SPs can be used instead.

[0057] Furthermore, the arrangement order of the main subpixels SP can be configured in the same way as the arrangement order of the redundant subpixels SP. For example, the subpixels SP that make up the main subpixels SP may be arranged in the order of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, and the subpixels SP that make up the redundant subpixels SP may also be arranged in the order of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3.

[0058] However, the pair of first subpixels SP1, the pair of second subpixels SP2, and the pair of third subpixels SP3 are not limited to the main subpixels SP and redundant subpixels SP, and all of them can always be used when the display device 100 is driven, and the arrangement order of the subpixels SP is also not limited thereto.

[0059] The pixel region UPA can be superimposed on wiring that extends in the column direction among multiple wirings, for example, data wiring DL and reference wiring RL. By forming the pixel region UPA in a region where multiple opaque wirings are arranged, the area of ​​the transparent region TA can be secured across the entire display region AA. Specifically, the pixel region UPA, where multiple sub-pixels SP are arranged, may have low transparency and be substantially opaque due to the configuration of the pixel circuits and light-emitting elements 120 arranged on the multiple sub-pixels SP. Therefore, the multiple sub-pixels SP of the pixel region UPA can be arranged to overlap with opaque wiring that extends in the column direction, for example, data wiring DL, reference wiring RL, low-potential power supply wiring VSS, and high-potential power supply wiring VDD. Thus, by arranging the multiple sub-pixels SP of the pixel region UPA to overlap with multiple wirings, the area of ​​the opaque region can be reduced across the entire display region AA, and the area of ​​the transparent region TA can be maximized.

[0060] Multiple subpixels SP arranged in a single pixel region UPA can be rectangular or L-shaped. For example, one first subpixel SP1, one second subpixel SP2, and one third subpixel SP3 may be arranged on one side of a scan wiring SL, and one first subpixel SP1, one second subpixel SP2, and one third subpixel SP3 may be arranged on the other side of the scan wiring SL. On both sides of the scan wiring SL, the first subpixel SP1 may be arranged in a rectangular region, and the second subpixel SP2 may be arranged in an L-shaped region surrounding two adjacent sides of the first subpixel SP1. The third subpixel SP3 may be arranged in an L-shaped region surrounding the outer part of the L-shaped second subpixel SP2. Thus, a single pixel region UPA composed of the rectangular first subpixel SP1 and the L-shaped second and third subpixels SP2 and SP3 can be formed in a rectangular shape.

[0061] Multiple transparent regions TA are areas within the display area AA excluding the areas where multiple wirings and multiple pixel areas UPA are arranged, and have relatively high transmittance. Light is transmitted through the transparent regions TA, allowing the background located on the rear side of the display device 100 to be seen from the front of the display device 100. Multiple transparent regions TA may be arranged spaced apart, flanking multiple wirings and multiple pixel areas UPA. Multiple transparent regions TA may be arranged to surround multiple pixel areas UPA. Therefore, the display device 100 according to one embodiment of this specification can be embodied as a transparent display device 100, including multiple transparent regions TA.

[0062] Referring to Figures 3 to 5, each of the multiple sub-pixels SP includes a pixel circuit and one or more light-emitting elements 120. The pixel circuit includes multiple transistors T1, T2, DT and a storage capacitor Cst, which can supply drive current to the light-emitting elements 120. For example, the pixel circuit may include a first transistor T1, a second transistor T2, a drive transistor DT and a storage capacitor Cst. The multiple sub-pixels SP arranged in a single pixel region UPA can be connected to scan wiring SL, multiple data wiring DL, reference wiring RL, high-potential power wiring VDD and low-potential power wiring VSS to receive various signals.

[0063] First, the substrate 110 is a structure for supporting the various components included in the display device 100, and may be made of an insulating material. For example, the substrate 110 may be made of glass or resin. Furthermore, the substrate 110 may contain polymers or plastics, and may be made of a flexible material.

[0064] A light-shielding layer LS is placed on each of the multiple subpixels SP on the substrate 110. The light-shielding layer LS blocks the light incident on the drive active layer DACT of the drive transistor DT, which will be described later, at the bottom of the substrate 110. By blocking the light incident on the drive active layer DACT of the drive transistor DT with the light-shielding layer LS, leakage current can be minimized.

[0065] A buffer layer 111 is placed on the substrate 110 and the light-shielding layer LS. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. The buffer layer 111 may, but is not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx). However, the buffer layer 111 may, but is not limited to, be omitted depending on the type of substrate 110 or the type of transistor.

[0066] On the buffer layer 111, a drive transistor DT, a first transistor T1, and a second transistor T2 are arranged for each of the multiple subpixels SP.

[0067] The driving transistor DT, the first transistor T1, and the second transistor T2 for each of the multiple sub-pixels SP may be P-type thin-film transistors or N-type thin-film transistors. For example, in a P-type thin-film transistor, holes move from the source electrode to the drain electrode, so current can flow from the source electrode to the drain electrode. In an N-type thin-film transistor, electrons move from the source electrode to the drain electrode, so current can flow from the drain electrode to the source electrode. In the following explanation, we will assume that the driving transistor DT, the first transistor T1, and the second transistor T2 are P-type thin-film transistors that allow current to flow from the source electrode to the drain electrode, but we are not limited to this.

[0068] First, a drive transistor DT is placed for each of the multiple sub-pixels SP on the buffer layer 111. The drive transistor DT is a transistor for controlling the drive current supplied to the light-emitting element 120. In a single pixel region UPA, the drive transistors DT for each of the multiple sub-pixels SP may be arranged in a line along the column direction. Multiple drive transistors DT for multiple sub-pixels SP may be arranged in a line superimposed on the region where the reference wiring RL and data wiring DL are located.

[0069] The drive transistor DT includes a drive active layer DACT, a drive gate electrode DGE, a drive source electrode DSE, and a drive drain electrode DDE.

[0070] A driving active layer DACT is placed on the buffer layer 111. The driving active layer DACT may, but is not limited to, a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon.

[0071] A gate insulating layer 112 is placed on the drive active layer DACT. The gate insulating layer 112 is an insulating layer for insulating the drive active layer DACT from the drive gate electrode DGE, and may, but is not limited to, a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx).

[0072] A drive gate electrode DGE is positioned on the gate insulating layer 112. The drive gate electrode DGE may be composed of one or more layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0073] A first interlayer insulating layer 113a is disposed on the drive gate electrode DGE. The first interlayer insulating layer 113a has contact holes formed therein for the drive source electrode DSE to connect to the drive active layer DACT. The first interlayer insulating layer 113a is an insulating layer for protecting the structure below the first interlayer insulating layer 113a and may consist of a single or multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0074] A drive source electrode DSE is placed on the first interlayer insulating layer 113a. The drive source electrode DSE is electrically connected to the drive active layer DACT through a contact hole formed in the first interlayer insulating layer 113a. The drive source electrode DSE can then be electrically connected to the second transistor T2. The drive source electrode DSE may be composed of one or more layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0075] A second interlayer insulating layer 113b is placed on the drive source electrode DSE. The second interlayer insulating layer 113b is an insulating layer for protecting the structure below the second interlayer insulating layer 113b and may consist of a single layer or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0076] A first passivation layer 114a is placed on the second interlayer insulating layer 113b. The first passivation layer 114a is an insulating layer for protecting the structure below the first passivation layer 114a and may consist of a single or multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx), but is not limited thereto.

[0077] A drive drain electrode DDE is positioned on the first passivation layer 114a. The drive drain electrode DDE is electrically connected to the drive active layer DACT through contact holes formed in the first passivation layer 114a, the first interlayer insulating layer 113a, and the second interlayer insulating layer 113b. The drive drain electrode DDE may also be electrically connected to the low-potential power supply wiring VSS through a contact hole formed in the first passivation layer 114a. The drive drain electrode DDE may be composed of one or more layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0078] Next, a first transistor T1 is placed on each of the multiple subpixels SP on the buffer layer 111. The first transistor T1 is a transistor that transmits the data voltage Vdata to the gate electrode of the drive transistor DT, and can be called a switching transistor. In this case, in a single pixel region UPA, the multiple first transistors T1 of the multiple subpixels SP may be arranged so as to overlap the scan wiring SL and the protruding portion of the scan wiring SL, and may be arranged in a line along the row direction.

[0079] Specifically, the scan wiring SL may extend in the row direction on the gate insulating layer 112 and be arranged across multiple pixel regions UPA. In this case, the scan wiring SL may include portions that protrude on both sides toward multiple sub-pixels SP in the region overlapping with the multiple pixel regions UPA. The portion protruding on one side of the scan wiring SL may include portions that extend in the column direction and portions that extend in the row direction from the end of the portion that extends in the column direction. The scan wiring SL may further include protruding portions that protrude from the scan wiring SL, with at least a portion extending in the row direction. That is, the protruding portion that protrudes from one side of the scan wiring SL may be "L" shaped. The portion protruding from the other side of the scan wiring SL may include portions that extend in the column direction.

[0080] Furthermore, the first transistors T1 of multiple sub-pixels SP on one side of the scan wiring SL can be arranged in a line along the portion of the scan wiring SL that extends in the row direction. Similarly, the first transistors T1 of multiple sub-pixels SP on the other side of the scan wiring SL can be arranged in a line along the scan wiring SL that extends in the row direction. Thus, the multiple first transistors T1 on one side of the scan wiring SL can be arranged in a line along the row direction on the protruding portion of the scan wiring SL, and the multiple first transistors T1 on the other side of the scan wiring SL can be arranged in a line along the row direction on the scan wiring SL. While the scan wiring SL is split and formed in two branches within a single pixel region UPA, the first transistors T1 of the main sub-pixels SP and the first transistors T1 of the redundant sub-pixels SP can be easily separated and formed. Therefore, the main sub-pixels SP and the redundant sub-pixels SP can be connected to and driven by different first transistors T1.

[0081] The first transistor T1 includes a first active layer ACT1, a first gate electrode GE1, a first source electrode SE1, and a first drain electrode DE1.

[0082] A first active layer ACT1 is placed on the buffer layer 111. The first active layer ACT1 may, but is not limited to, a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon.

[0083] A first gate electrode GE1 is positioned on the gate insulating layer 112. The first gate electrode GE1 can be electrically coupled to the scan wiring SL. For example, the first gate electrode GE1 can be integrated with the scan wiring SL. The first gate electrode GE1 can be composed of one or more layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, and is not limited thereto.

[0084] A first drain electrode DE1 is positioned between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The first drain electrode DE1 is electrically connected to the first active layer ACT1 through contact holes formed in the first interlayer insulating layer 113a and the gate insulating layer 112. The first drain electrode DE1 can also be electrically connected to the second gate electrode GE2 of the second transistor T2 through a contact hole in the first interlayer insulating layer 113a. The first drain electrode DE1 may be composed of one or more layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0085] A first source electrode SE1 is placed on a first passivation layer 114a. The first source electrode SE1 is electrically connected to a first active layer ACT1 through contact holes in the first passivation layer 114a, the second interlayer insulating layer 113b, and the first interlayer insulating layer 113a. The first source electrode SE1 can also be electrically connected to a data trace DL. For example, the first source electrode SE1 can be integrated with the data trace DL. The first source electrode SE1 may be composed of one or more layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0086] Next, a second transistor T2 is placed on each of the multiple subpixels SP on the buffer layer 111. The second transistor T2 is a transistor for compensating the threshold voltage of the drive transistor DT and may be called a sensing transistor. The second transistors T2 of the multiple subpixels SP may be arranged in a line along the portion of the scan wiring SL that extends in the column direction. For example, the second transistors T2 of the multiple subpixels SP on one side of the scan wiring SL may be placed corresponding to the portion of the scan wiring SL that extends in the column direction, and the second transistors T2 of the multiple subpixels SP on the other side of the scan wiring SL may be placed corresponding to the portion of the scan wiring SL that extends in the column direction. Thus, the multiple second transistors T2 placed in a single pixel region UPA may be arranged in a line along the column direction.

[0087] The second transistor T2 includes a second active layer ACT2, a second gate electrode GE2, a second source electrode SE2, and a second drain electrode DE2.

[0088] A second active layer ACT2 is positioned between the buffer layer 111 and the gate insulating layer 112. The second active layer ACT2 may, but is not limited to, a semiconductor material such as an oxide semiconductor, amorphous silicon, or polysilicon.

[0089] In this case, the second active layer ACT2 of multiple adjacent subpixels SP can be connected to one another. For example, the second active layer ACT2 of the first subpixel SP1, second subpixel SP2, and third subpixel SP3 located on one side of the scan wiring SL can extend in the column direction and be connected to one another, and can be connected together to the second drain electrode DE2 located on the first subpixel SP1. Similarly, the second active layer ACT2 of the first subpixel SP1, second subpixel SP2, and third subpixel SP3 located on the other side of the scan wiring SL can also extend in the column direction and be connected to one another, and can be connected together to the second drain electrode DE2 located on the first subpixel SP1. That is, the connecting portion of the second active layer ACT2 of multiple subpixels SP that connects the channel region and the reference wiring RL can be made of a transparent second active layer ACT2 material instead of an opaque conductive material, and the transmittance can be improved at the outermost edge of the pixel region UPA. Furthermore, the connecting portion that links the channel region of the second active layer ACT2 of multiple subpixels SP to the reference wiring RL can be made of the same material as the second active layer ACT2, eliminating the need for contact holes and simplifying the structure of the pixel region UPA.

[0090] A second gate electrode GE2 is positioned between the gate insulating layer 112 and the first interlayer insulating layer 113a. The second gate electrode GE2 can be electrically coupled to the scan trace SL. For example, the second gate electrode GE2 can be integrated with a protruding portion of the scan trace SL and electrically coupled to it. The second gate electrode GE2 may be composed of one or more layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0091] A second source electrode SE2 is positioned between the first interlayer insulating layer 113a and the second interlayer insulating layer 113b. The second source electrode SE2 is electrically connected to the second active layer ACT2 through contact holes in the first interlayer insulating layer 113a and the gate insulating layer 112. The second source electrode SE2 can be integrated with the drive source electrode DSE and electrically connected to the drive source electrode DSE. The second source electrode SE2 may be composed of one or more layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0092] A second drain electrode DE2 is positioned between the first passivation layer 114a and the second passivation layer 114b. The second drain electrode DE2 is electrically connected to the second active layer ACT2 through contact holes formed in the first passivation layer 114a, the second interlayer insulating layer 113b, the first interlayer insulating layer 113a, and the gate insulating layer 112. The second drain electrode DE2 may be integrated with the reference wiring RL and electrically connected to the reference wiring RL. The second drain electrode DE2 may be composed of one or more layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0093] Next, a storage capacitor Cst is placed on the gate insulating layer 112. The storage capacitor Cst can store the potential difference between the drive gate electrode DGE and the drive source electrode DSE of the drive transistor DT while the light-emitting element 120 is emitting light, so that a constant drive current is supplied to the light-emitting element 120. The storage capacitor Cst includes a first capacitor electrode C1 electrically connected to the drive gate electrode DGE and a second capacitor electrode C2 electrically connected to the drive source electrode DSE, and can maintain a constant voltage between the drive gate electrode DGE and the drive source electrode DSE.

[0094] Specifically, a first capacitor electrode C1 is placed on the gate insulating layer 112. The first capacitor electrode C1 may be integrated with the drive gate electrode DGE. A second capacitor electrode C2 is placed on the first interlayer insulating layer 113a. The first capacitor electrode C1 and the second capacitor electrode C2 may be arranged so as to overlap with the first interlayer insulating layer 113a in between. In this case, the second capacitor electrode C2 may be integrated with the drive source electrode DSE. The first capacitor electrode C1 and the second capacitor electrode C2 may be composed of one or more layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but are not limited thereto.

[0095] Next, an auxiliary electrode AE ​​is placed on the first passivation layer 114a. The auxiliary electrode AE ​​is an electrode for electrically connecting the driving source electrode DSE and the first reflective electrode RE1. The driving source electrode DSE and the first reflective electrode RE1 can be electrically connected to each other through the auxiliary electrode AE. The auxiliary electrode AE ​​may be composed of one or more layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof, but is not limited thereto.

[0096] A low-potential power supply wiring VSS is arranged on the second interlayer insulating layer 113b. The low-potential power supply wiring VSS is arranged along the column direction and may be superimposed on multiple pixel regions UPA. The low-potential power supply wiring VSS may be electrically connected to the drive drain electrode DDE. The low-potential power supply wiring VSS may consist of one or more layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof.

[0097] A reference trace RL is positioned on the first passivation layer 114a. The reference trace RL is positioned along the column direction and may superimpose on multiple pixel regions UPA. The reference trace RL is positioned adjacent to the protruding portions of the scan trace SL and may be electrically coupled to multiple second transistors T2 positioned on the protruding portions of the scan trace SL. The reference trace RL may consist of one or more layers of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof.

[0098] Multiple data paths DL are arranged on the first passivation layer 114a. The multiple data paths DL may extend in the column direction and overlap multiple pixel regions UPA. The multiple data paths DL may include data paths DL connected to the first transistor T1 of multiple first subpixels SP1, data paths DL connected to the first transistor T1 of multiple second subpixels SP2, and data paths DL connected to the first transistor T1 of multiple third subpixels SP3.

[0099] Next, a second passivation layer 114b is placed on the drive transistor DT, the first transistor T1, the second transistor T2, the storage capacitor Cst, the reference wiring RL, and the data wiring DL. The second passivation layer 114b is an insulating layer for protecting the underlying structure and may, but is not limited to, a single or multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx).

[0100] A first planarization layer 115a is placed on the second passivation layer 114b. The first planarization layer 115a can planarize the upper part of the substrate 110 on which multiple transistors and storage capacitors Cst are arranged. The first planarization layer 115a may consist of a single layer or multiple layers, and may, for example, be made of a photoresist or an acrylic-based organic material, but is not limited thereto.

[0101] On the other hand, although not shown in the drawings, further passivation layers may be placed on the first planarization layer 115a. For example, a passivation layer consisting of a single or multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx) can be formed on the first planarization layer 115a to protect the structure below the passivation layer.

[0102] Next, a plurality of first reflective electrodes RE1 are arranged on the first planarization layer 115a. The plurality of first reflective electrodes RE1 are arranged in each of the plurality of subpixels SP, electrically connecting the drive transistor DT and the light-emitting element 120, and at the same time reflecting the light emitted by the light-emitting element 120 to the outside of the display device 100. The plurality of first reflective electrodes RE1 may be arranged adjacent to the drive source electrode DSE in each of the plurality of subpixels SP. The plurality of first reflective electrodes RE1 may, but are not limited to, opaque conductive materials with high reflectivity such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof.

[0103] A second reflective electrode RE2, which is a high-potential power supply wiring VDD, is placed on the first planarization layer 115a. The second reflective electrode RE2 and the high-potential power supply wiring VDD are integrated, and while supplying a high-potential power supply voltage to the light-emitting element 120, the light emitted by the light-emitting element 120 can be reflected to the outside of the display device 100. The second reflective electrode RE2 of each of the multiple subpixels SP can be connected to each other and integrated. The second reflective electrode RE2 and the high-potential power supply wiring VDD can be arranged to extend in the column direction and superimpose on the light-emitting element 120. The second reflective electrode RE2 and the high-potential power supply wiring VDD can be arranged to superimpose on multiple data wiring DL, reference wiring RL and low-potential power supply wiring VSS. The second reflective electrode RE2 and the high-potential power supply wiring VDD may, but are not limited to, opaque conductive materials with high reflectivity such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof.

[0104] A third passivation layer 114c is arranged on multiple first reflective electrodes RE1 and second reflective electrodes RE2. The third passivation layer 114c is an insulating layer for protecting the underlying structure of the third passivation layer 114c and may, but is not limited to, a single or multiple layer of silicon oxide (SiOx) or silicon nitride (SiNx).

[0105] An adhesive layer AD is placed on the third passivation layer 114c. The adhesive layer AD is formed on the front surface of the substrate 110 and can fix the light-emitting element 120 placed on the adhesive layer AD. The adhesive layer AD may consist of a photocurable adhesive material that can be cured by light. For example, the adhesive layer AD may be selected from, but is not limited to, adhesive polymer, epoxy resist, UV resin, polyimide series, acrylate series, urethane series, or polydimethylsiloxane (PDMS).

[0106] Multiple light-emitting elements 120 are arranged on each of the multiple subpixels SP on the adhesive layer AD. The light-emitting elements 120 are elements that emit light in response to an electric current, and can include red light-emitting elements 120R that emit red light, green light-emitting elements 120G that emit green light, and blue light-emitting elements 120B that emit blue light. By combining these, a variety of hues of light, including white, can be realized. For example, the light-emitting elements 120 may be LEDs (Light Emitting Diodes) or microLEDs, but are not limited to these.

[0107] A red light-emitting element 120R may be placed in the first subpixel SP1, a green light-emitting element 120G may be placed in the second subpixel SP2, and a blue light-emitting element 120B may be placed in the third subpixel SP3. Multiple light-emitting elements 120 placed in a single pixel region UPA may be arranged in a single row along the column direction. Furthermore, the multiple light-emitting elements 120 may be arranged so as to overlap the second reflective electrode RE2 in each of the multiple subpixels SP.

[0108] On the other hand, if multiple subpixels SP are divided into main subpixels SP and redundant subpixels SP as described above, then multiple light-emitting elements 120 can also be divided into main light-emitting elements 120 and redundant light-emitting elements 120. For example, one of a pair of first subpixels SP1, one of a pair of second subpixels SP2, and one of a pair of third subpixels SP3 are main subpixels SP, and the red light-emitting element 120R, green light-emitting element 120G, and blue light-emitting element 120B arranged in the main subpixels SP may be the main light-emitting elements 120. Then, the remaining of a pair of first subpixels SP1, the remaining of a pair of second subpixels SP2, and the remaining of a pair of third subpixels SP3 are redundant subpixels SP, and the red light-emitting element 120R, green light-emitting element 120G, and blue light-emitting element 120B arranged in the redundant subpixels SP may be the redundant light-emitting elements 120.

[0109] Each of the multiple light-emitting elements 120 includes a first semiconductor layer 121, a light-emitting layer 122, a second semiconductor layer 123, a first electrode 124, a second electrode 125, and a sealing film 126.

[0110] A first semiconductor layer 121 is placed on an adhesive layer AD, and a second semiconductor layer 123 is placed on the first semiconductor layer 121. The first semiconductor layer 121 and the second semiconductor layer 123 may be layers formed by doping specific materials with n-type and p-type impurities. For example, the first semiconductor layer 121 and the second semiconductor layer 123 may each be layers doped with n-type and p-type impurities in materials such as gallium nitride (GaN), indium aluminum phosphide (InAlP), gallium arsenide (GaAs), etc. The p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc., and the n-type impurity may be silicon (Si), germanium, tin (Sn), etc., but is not limited to these.

[0111] A light-emitting layer 122 is disposed between a first semiconductor layer 121 and a second semiconductor layer 123. The light-emitting layer 122 can emit light by receiving holes and electrons from the first semiconductor layer 121 and the second semiconductor layer 123. The light-emitting layer 122 can be a single layer or a multi-quantum well (MQW) structure, and may be made of, for example, indium gallium nitride (InGaN) or gallium nitride (GaN), but is not limited thereto.

[0112] A first electrode 124 is placed on the first semiconductor layer 121. The first electrode 124 is an electrode for electrically connecting the drive transistor DT and the first semiconductor layer 121. In this case, the first semiconductor layer 121 is a semiconductor layer doped with n-type impurities, and the first electrode 124 may be a cathode. The first electrode 124 may be placed on the upper surface of the first semiconductor layer 121 exposed from the light-emitting layer 122 and the second semiconductor layer 123. The first electrode 124 may be made of a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0113] A second electrode 125 is placed on the second semiconductor layer 123. The second electrode 125 may be placed on the upper surface of the second semiconductor layer 123. The second electrode 125 is an electrode for electrically connecting the high-potential power supply wiring VDD to the second semiconductor layer 123. In this case, the second semiconductor layer 123 is a semiconductor layer doped with p-type impurities, and the second electrode 125 may be an anode. The second electrode 125 may be made of a conductive material, such as a transparent conductive material like ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), or an opaque conductive material like titanium (Ti), gold (Au), silver (Ag), copper (Cu), or alloys thereof, but is not limited thereto.

[0114] Next, a sealing film 126 is placed surrounding the first semiconductor layer 121, the light-emitting layer 122, the second semiconductor layer 123, the first electrode 124, and the second electrode 125. The sealing film 126 is made of an insulating material and can protect the first semiconductor layer 121, the light-emitting layer 122, and the second semiconductor layer 123. Contact holes are formed in the sealing film 126 to expose the first electrode 124 and the second electrode 125, so that the first connecting electrode CE1 and the second connecting electrode CE2 can be electrically connected to the first electrode 124 and the second electrode 125.

[0115] On the other hand, a portion of the side surface of the first semiconductor layer 121 may be exposed from the sealing film 126. The light-emitting element 120 manufactured on the wafer can be separated from the wafer and transferred to the display panel PN. However, a portion of the sealing film 126 may be peeled off during the process of separating the light-emitting element 120 from the wafer. For example, a portion of the sealing film 126 adjacent to the lower edge of the first semiconductor layer 121 of the light-emitting element 120 may be peeled off during the separation process of the light-emitting element 120 from the wafer, exposing a portion of the lower side surface of the first semiconductor layer 121 to the outside. Even if the lower portion of the light-emitting element 120 is exposed from the sealing film 126, the first connecting electrode CE1 and the second connecting electrode CE2 are formed after the second planarization layer 115b and the third planarization layer 115c covering the side surface of the first semiconductor layer 121, so short-circuit defects can be reduced.

[0116] Next, the second planarization layer 115b and the third planarization layer 115c are placed on the adhesive layer AD and the light-emitting element 120.

[0117] The second planarization layer 115b can be superimposed on a portion of the side surface of the multiple light-emitting elements 120 to fix and protect the multiple light-emitting elements 120. The portion where the sealing film 126 protecting the side surface of the first semiconductor layer 121 of the light-emitting elements 120 has been peeled off can be covered with the second planarization layer 115b. This prevents contact and short-circuit defects between the connecting electrodes and the first semiconductor layer 121 later on.

[0118] The third planarization layer 115c is formed to cover the second planarization layer 115b and the upper portion of the light-emitting element 120. Contact holes may be formed in the third planarization layer 115c, exposing the first electrode 124 and the second electrode 125 of the light-emitting element 120. Although the first electrode 124 and the second electrode 125 of the light-emitting element 120 are exposed from the third planarization layer 115c, the third planarization layer 115c can be partially positioned in the region between the first electrode 124 and the second electrode 125 to reduce short-circuit defects. The second planarization layer 115b and the third planarization layer 115c may be single-layer or multi-layer, and may, for example, be made of photoresist or acrylic-based organic material, but are not limited thereto.

[0119] The first connecting electrode CE1 and the second connecting electrode CE2 are placed on the third planarization layer 115c.

[0120] The first connecting electrode CE1 is an electrode that electrically connects the first electrode 124 of the light-emitting element 120 to the drive transistor DT. The first connecting electrode CE1 is electrically connected to the first electrode 124 exposed from the third planarization layer 115c, and at the same time can be electrically connected to the first reflective electrode RE1 through contact holes formed in the third planarization layer 115c, the second planarization layer 115b, and the third passivation layer 114c. Thus, the first electrode 124 and the drive source electrode DSE can be electrically connected through the first connecting electrode CE1, the first reflective electrode RE1, and the auxiliary electrode AE.

[0121] The second connecting electrode CE2 is an electrode that electrically connects the second electrode 125 of the light-emitting element 120 to the high-potential power supply wiring VDD. The second connecting electrode CE2 is electrically connected to the second electrode 125 exposed from the third planarization layer 115c, and can also be electrically connected to the second reflective electrode RE2, which is the high-potential power supply wiring VDD, through contact holes formed in the third planarization layer 115c, the second planarization layer 115b, and the third passivation layer 114c. Therefore, the second electrode 125 and the high-potential power supply wiring VDD can be electrically connected through the second connecting electrode CE2.

[0122] The first connecting electrode CE1 and the second connecting electrode CE2 may be made of a transparent conductive material such as ITO (Indium Tin Oxide) or IZO (Indium Zinc Oxide), but are not limited thereto.

[0123] On the other hand, although the drawing shows that the drive source electrode DSE of the drive transistor DT and the first electrode 124 of the light-emitting element 120 are electrically connected, the drawing is not limited to this, and the drive drain electrode DDE of the drive transistor DT and the second electrode 125 of the light-emitting element 120 may also be electrically connected, depending on the type of drive transistor DT and the design of the pixel circuit.

[0124] Next, a bank BB is placed on the third planarization layer 115c, the first connecting electrode CE1, and the second connecting electrode CE2 in the pixel region UPA. The bank BB may be placed at a certain distance from the light-emitting element 120. The bank BB may be placed at the boundary between multiple sub-pixels SP and may cover a portion of the first connecting electrode CE1 and the second connecting electrode CE2. The bank BB may be placed at a distance from the transmission region TA. The bank BB may be made of an opaque material to reduce color mixing between multiple sub-pixels SP, for example, black resin, but is not limited to this.

[0125] A protective layer 116 is placed on the first connecting electrode CE1, the second connecting electrode CE2, and the bank BB. The protective layer 116 is a layer for protecting the components beneath it. The protective layer 116 may consist of a single layer or multiple layers and may, but is not limited to, benzocyclobutene, translucent epoxy, photoresist, or acrylic organic material, or inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx).

[0126] On the other hand, in order to secure the area of ​​the transparent region TA, multiple sub-pixels SP may be arranged so as to overlap with multiple wirings. In this case, some wirings may cause fluctuations in the drive current of each of the multiple sub-pixels SP. For example, the drive transistor DT and storage capacitor Cst of each of the multiple sub-pixels SP may be superimposed on and coupled with the data wiring DL. In this case, the voltage of the drive gate electrode DGE may fluctuate due to the data wiring DL to which a different voltage is applied for each frame. As the voltage of the drive gate electrode DGE fluctuates, the drive current flowing to the light-emitting element 120 may fluctuate, and brightness changes due to crosstalk may occur, potentially degrading the display quality.

[0127] Therefore, in the display device 100 according to one embodiment of this specification, the voltage fluctuation of the drive gate electrode DGE due to the data wiring DL can be reduced by adjusting the thickness of the insulating layer, taking into consideration the dielectric constant of the insulating layer disposed between the storage capacitor Cst and the drive transistor DT and the data wiring DL. For example, an inorganic insulating film disposed on the substrate 110, i.e., insulating layers such as the buffer layer 111, gate insulating layer 112, first interlayer insulating layer 113a and second passivation layer 114b, can be formed to a thickness of several thousand angstroms (Å). However, the thickness of the first passivation layer 114a and the second interlayer insulating layer 113b, which are insulating layers disposed between the data wiring DL and the storage capacitor Cst, is formed to a thickness of at least several micrometers (μm), unlike the other insulating layers, so that the voltage fluctuation of the drive transistor DT due to the data wiring DL can be minimized. Therefore, the thickness of the insulating layer between the data wiring DL and the storage capacitor Cst may be greater than the thickness of the buffer layer 111, the thickness of the gate insulating layer 112, the thickness of the first interlayer insulating layer 113a, and the thickness of the second passivation layer 114b.

[0128] Referring to Figure 6, when the width of the data wiring DL is 1 μm, the thickness of the insulating layer can be determined by the material and dielectric constant of the insulating layer placed beneath the data wiring DL. As the thickness of the insulating layer increases, the level of brightness change due to crosstalk can decrease. In this case, if the insulating layer is made of silicon nitride (SiNx) with a dielectric constant of approximately 6.69 and the target crosstalk is 2%, the brightness change level due to crosstalk can be controlled to 2% or less by forming the insulating layer thickness to approximately 16.55 μm or more. If the insulating layer is made of silicon oxide (SiOx) with a dielectric constant of approximately 4.3 and the target crosstalk is 2%, the brightness change level due to crosstalk can be controlled to 2% or less by forming the insulating layer thickness to approximately 10.64 μm or more. Therefore, when the width of the data wiring DL is 1 μm, the overall thickness of the first passivation layer 114a and the second interlayer insulating layer 113b can be made to at least 10.64 μm to minimize the voltage fluctuation of the drive transistor DT and the storage capacitor Cst connected to the drive transistor DT due to the data wiring DL. Furthermore, as the width of the data wiring (DL) increases, an even thicker insulating layer may be required to achieve the same level of crosstalk.

[0129] Therefore, the overall thickness of the first passivation layer 114a and the second interlayer insulating layer 113b can be determined by considering the width of the data wiring DL, the dielectric constant of the first passivation layer 114a and the second interlayer insulating layer 113b, and the target crosstalk level, thereby minimizing interference between the data wiring DL and the drive transistor DT and the storage capacitor Cst connected to the drive transistor DT while maintaining a constant drive current.

[0130] In one embodiment of the display device 100 described herein, the area of ​​the transparent area TA can be maximized by arranging a plurality of pixel areas UPA in an area where a plurality of wirings extending in the column direction are arranged. By arranging substantially opaque pixel areas UPA containing pixel circuits and light-emitting elements 120 together with opaque wiring, the area of ​​opaque regions in the entire display area AA can be reduced. Therefore, the area of ​​the transparent area TA can be maximized, improving the overall transmittance of the display device 100, and a transparent display device 100 can be realized.

[0131] In one embodiment of the display device 100 described herein, voltage fluctuations of the drive transistor DT due to data wiring DL can be minimized. When data wiring DL and pixel area UPA are superimposed to secure the area of ​​the transparent area TA, the configurations of data wiring DL and pixel area UPA are coupled, which can cause voltage fluctuations. For example, data wiring DL may be superimposed on the drive transistor DT and storage capacitor Cst and coupled with them, causing voltage fluctuations of the drive transistor DT and storage capacitor Cst, which can lead to brightness fluctuations and a decrease in display quality. Therefore, the influence of data wiring DL can be minimized by forming a thicker insulating layer between data wiring DL and the drive transistor DT and storage capacitor Cst. In this case, the thickness of the insulating layer can be determined by considering the dielectric constant of the insulating layer, the width of data wiring DL, the target level of crosstalk, etc. Accordingly, in one embodiment of the display device 100 described herein, the thickness of the insulating layer between data wiring DL and drive transistor DT can be made relatively thicker among the multiple insulating layers to minimize drive current fluctuations due to data wiring DL and improve display quality.

[0132] Figure 7 is an enlarged plan view of a display device according to another embodiment of this specification. Figure 8 is a cross-sectional view of a subpixel of a display device according to another embodiment of this specification. Figure 9a is a graph showing the voltage and drive current of the drive gate electrode due to the data voltage measured in a display device according to a comparative example. Figure 9b is a graph showing the voltage and drive current of the drive gate electrode due to the data voltage measured in a display device according to another embodiment of this specification. The display panel PN' in Figures 7 and 8 is substantially the same as the display panel PN in Figures 1 to 5 except for the low-potential power supply wiring VSS, so redundant explanations are omitted.

[0133] Referring to Figures 7 and 8, a low-potential power supply wiring VSS is arranged between the second interlayer insulating layer 113b and the first passivation layer 114a so as to overlap with multiple data wirings DL. The low-potential power supply wiring VSS can overlap the region where multiple data wirings DL are arranged. The low-potential power supply wiring VSS has a relatively wide width, and one low-potential power supply wiring VSS can overlap with multiple data wirings DL. The low-potential power supply wiring VSS can cover the storage capacitors Cst and drive transistors DT of multiple sub-pixels SP'. Since only the low-potential power supply wiring VSS is arranged between the second interlayer insulating layer 113b and the first passivation layer 114a, the low-potential power supply wiring VSS can be easily formed in the remaining region excluding the region where contact holes are located.

[0134] The low-potential power supply wiring VSS may have openings formed inside that overlap with contact holes. For example, the low-potential power supply wiring VSS may have openings formed that overlap with contact holes connecting the first source electrode SE1 and the first active layer ACT1, and with contact holes connecting the drive drain electrode DDE and the drive active layer DACT. The first source electrode SE1 and the drive drain electrode DDE are placed on the low-potential power supply wiring VSS, while the first active layer ACT1 and the drive active layer DACT are placed below the low-potential power supply wiring VSS. Thus, by forming openings in the low-potential power supply wiring VSS, configurations connected to the upper and lower parts of the low-potential power supply wiring VSS can be easily connected.

[0135] The low-potential power supply wiring VSS is placed between the storage capacitor Cst and the drive transistor DT and multiple data wiring DLs, and can function as a shielding film to block voltage fluctuations of the drive transistor DT caused by the data wiring DLs. The low-potential power supply wiring VSS, to which a constant voltage is applied, is placed between the storage capacitor Cst and the drive transistor DT and the data wiring DLs, and can prevent coupling between the data wiring DLs and the storage capacitor Cst and the drive transistor DTs. The low-potential power supply wiring VSS is positioned to cover at least the drive gate electrode DGE of the drive transistor DTs, and can protect the voltage DTG of the drive gate electrode DGE from fluctuations caused by the data wiring DLs.

[0136] In the following section, the effects of extending and arranging the low-potential power supply wiring (VSS) will be explained with reference to Figures 9a and 9b.

[0137] Referring to Figure 9a, the display device 10 in the comparative example has a structure in which a low-potential power supply wiring VSS is not placed between the data wiring DL and the drive transistor DT. In the display panel 10 in the comparative example, no separate shielding film is placed between the data wiring DL and the drive transistor DT, and it can be confirmed that the voltage DTG of the drive gate electrode DGE fluctuates due to voltage fluctuations in the data wiring DL. Furthermore, it can be confirmed that the drive current ILED flowing to the light-emitting element 120 also fluctuates as the voltage DTG of the drive gate electrode DGE fluctuates. In such a case, the brightness may fluctuate and the display quality may deteriorate.

[0138] Referring to Figure 9b, in another embodiment of this specification, the display panel PN' has a low-potential power supply wiring VSS positioned between the data wiring DL and the drive transistor DT, and between the data wiring DL and the storage capacitor Cst, acting as a barrier film. Therefore, even if the voltage of the data wiring DL fluctuates, the voltage DTG of the drive gate electrode DGE and the drive current ILED can be kept constant. Consequently, the brightness can be kept constant, and the display quality can be improved.

[0139] In other embodiments of this specification, a low-potential power supply wiring VSS can be formed between the data wiring DL and the drive transistor DT to minimize voltage fluctuations of the drive transistor DT caused by the data wiring DL. The low-potential power supply wiring VSS may be positioned to cover the drive transistor DT and storage capacitor Cst beneath multiple data wiring DLs. The low-potential power supply wiring VSS, which maintains a constant voltage, can block interference between the multiple data wiring DLs and the drive transistor DT and storage capacitor Cst. In this case, the voltage DTG of the drive gate electrode DGE and the drive current ILED can be kept constant without increasing the thickness of the insulating layer between the multiple data wiring DLs and the drive transistor DT and storage capacitor Cst. Furthermore, instead of forming a separate shielding film, the size of the existing low-potential power supply wiring VSS can be extended to correspond to the area where multiple data wiring DLs are arranged, and the low-potential power supply wiring VSS can be used as a shielding film, simplifying the manufacturing process of the display panel PN'. Therefore, in the display panel PN' according to other embodiments of this specification, the size of the low-potential power supply wiring VSS can be expanded to superimpose on all of the multiple data wiring DLs, thereby stably maintaining the drive current ILED of the sub-pixel SP' at a constant level and improving the reliability of the display panel PN'.

[0140] On the other hand, existing designs have both a main light-emitting element and a redundant light-emitting element arranged in a single subpixel, with the main and redundant light-emitting elements connected in parallel to a single pixel circuit. In this case, the first and second electrodes of the main light-emitting element and the first and second electrodes of the redundant light-emitting element can be connected to the same node, i.e., the same electrode. If a short circuit occurs in the light-emitting element or pixel circuit in such a structure, a failure may occur where both the main and redundant light-emitting elements, which are connected in parallel and share a specific electrode, become dark, making it difficult to isolate and repair only the defective light-emitting element.

[0141] In contrast, in the display panels PN and PN' according to various embodiments of this specification, as described above, the multiple sub-pixels SP and SP' can be divided and used as main sub-pixels SP and SP' including a main light-emitting element 120, and redundant sub-pixels SP and SP' including redundant light-emitting elements 120. The main light-emitting elements 120 of the main sub-pixels SP and SP' and the redundant light-emitting elements 120 of the redundant sub-pixels SP and SP' can be driven independently. That is, a pixel circuit for driving the main light-emitting element 120 and a pixel circuit for driving the redundant light-emitting elements 120 can be formed separately. For example, by further forming an "L"-shaped projection on a scan wiring SL extending in the row direction, one of the first transistors T1 for driving the main light-emitting element 120 and the first transistor T1 for driving the redundant light-emitting element 120 can be formed on the scan wiring SL, and the other can be formed on the "L"-shaped projection, thereby separating the formation of the first transistor T1 for driving the main light-emitting element 120 and the first transistor T1 for driving the redundant light-emitting element 120. Therefore, by further forming a projection on the scan wiring SL, the first transistor T1 for the main light-emitting element 120 and the first transistor T1 for the redundant light-emitting element 120 can be formed individually, and the main light-emitting element 120 and the redundant light-emitting element 120 can be driven independently. Therefore, in the display panels PN and PN' according to the various embodiments of this specification, the main light-emitting element 120 and the redundant light-emitting elements 120 are connected to different pixel circuits. As a result, a defect in a specific sub-pixel SP or SP' does not affect other sub-pixels SP or SP', and only the defective sub-pixel SP or SP' can be easily detected and repaired.

[0142] The various embodiments of this specification may be described as follows.

[0143] A display device according to one embodiment of this specification includes a substrate in which a plurality of pixel regions and a plurality of transparent regions arranged between the plurality of pixel regions are defined, each spaced apart from the others, and a plurality of signal lines extending in a first direction on the substrate, wherein the plurality of subpixels include a plurality of pixel circuits, and the plurality of signal lines do not overlap the plurality of transparent regions but overlap the regions in which the plurality of pixel circuits are arranged.

[0144] According to other features of this specification, the scan wiring further includes a scan wiring extending in a second direction, which is different from the first direction, across a plurality of pixel regions on a substrate, wherein each plurality of subpixels in the plurality of pixel regions includes a first main subpixel, a second main subpixel, and a third main subpixel located on one side of the scan wiring, and a first redundant subpixel, a second redundant subpixel, and a third redundant subpixel located on the other side of the scan wiring, wherein the first main subpixel and the first redundant subpixel emit light of a first hue, the second main subpixel and the second redundant subpixel emit light of a second hue, and the third main subpixel and the third redundant subpixel emit light of a third hue.

[0145] According to other features of this specification, a plurality of signal lines may include at least one of a plurality of data lines and a plurality of reference lines.

[0146] According to other features of this specification, each of the plurality of subpixels may further include a first transistor positioned between one of the plurality of data wirings and the substrate and electrically connected to the plurality of data wirings, a drive transistor positioned between one of the data wirings and the substrate and electrically connected to the first transistor, a second transistor positioned between one of the data wirings and the substrate and electrically connected to the drive transistor, a storage capacitor positioned between one of the data wirings and the drive transistor and electrically connected to the gate electrode of the drive transistor, and a light-emitting element positioned on one of the data wirings and electrically connected to the drive transistor.

[0147] According to other features of this specification, in one of a plurality of pixel regions, the first transistors of the first main subpixel, the second main subpixel, and the third main subpixel may be arranged in a line along a second direction which is different from the first direction, and in one of a plurality of pixel regions, the first transistors of the first redundant subpixel, the second redundant subpixel, and the third redundant subpixel may be arranged in a line along the second direction.

[0148] According to other features of this specification, in one of a plurality of pixel regions, the scan trace includes a protruding portion that projects from the scan trace in a first direction and includes at least a portion that extends in a second direction, and the first transistors of each of the first main subpixel, second main subpixel and third main subpixel located on one side of the scan trace are located on the protruding portion of the scan trace, and the first transistors of each of the first redundant subpixel, second redundant subpixel and third redundant subpixel located on the other side of the scan trace are located on the scan trace.

[0149] According to other features of this specification, in one of a plurality of pixel regions, the second transistors of the first main subpixel, the second main subpixel, and the third main subpixel may be arranged in a line along the first direction, and in one of a plurality of pixel regions, the second transistors of the first redundant subpixel, the second redundant subpixel, and the third redundant subpixel may be arranged in a line along the first direction.

[0150] According to other features of this specification, in one of a plurality of pixel regions, the drive transistors for the first main subpixel, the second main subpixel, and the third main subpixel may be arranged in a line along the first direction, and in one of a plurality of pixel regions, the drive transistors for the first redundant subpixel, the second redundant subpixel, and the third redundant subpixel may be arranged in a line along the first direction.

[0151] According to other features of this specification, in one of a plurality of pixel regions, the light-emitting elements of the first main subpixel, the second main subpixel, and the third main subpixel may be arranged in a line along a first direction, and in one of a plurality of pixel regions, the light-emitting elements of the first redundant subpixel, the second redundant subpixel, and the third redundant subpixel may be arranged in a line along a first direction.

[0152] According to other features of this specification, multiple signal lines may be arranged on and superimposed on the drive transistors and storage capacitors.

[0153] According to other features of this specification, the invention further includes a buffer layer disposed between a substrate and a drive transistor, a gate insulating layer disposed on the buffer layer between the drive gate electrode and the drive active layer of the drive transistor, a first interlayer insulating layer covering the drive transistor, and one or more insulating layers covering a storage capacitor on the first interlayer insulating layer, wherein a plurality of signal lines are disposed on one or more insulating layers, and the thickness of one or more insulating layers may be greater than the thickness of the buffer layer, the thickness of the gate insulating layer and the thickness of the first interlayer insulating layer.

[0154] According to other features of this specification, power supply wiring may be further included between the storage capacitor and the multiple signal wiring, the power supply wiring may be superimposed on the multiple signal wiring.

[0155] According to other features of this specification, power wiring may include low-potential power wiring or high-potential power wiring.

[0156] According to other features of this specification, power supply wiring may be superimposed on the drive transistors and storage capacitors.

[0157] According to other features of this specification, the drive active layer of the drive transistor and the first active layer of the first transistor are located beneath the power supply wiring, the drive drain electrode of the drive transistor and the first source electrode of the first transistor are located on the power supply wiring, and the low-potential power supply wiring may include a plurality of openings superimposed on the contact holes connecting the drive active layer and the drive drain electrode, and the contact holes connecting the first active layer and the first source electrode, respectively.

[0158] According to other features of this specification, multiple reference lines may be electrically connected to a second transistor, and multiple reference lines may be located on the same layer as multiple data lines.

[0159] According to other features of this specification, multiple reference lines may be formed integrally with the second drain electrode of the second transistor.

[0160] According to other features of this specification, the subpixels include a first subpixel which is rectangular in shape on a plane, a second subpixel which surrounds two adjacent sides of the first subpixel on a plane, and a third subpixel which surrounds the outer portion of the second subpixel on a plane, and the first subpixel, second subpixel and third subpixel can form a single rectangle.

[0161] Other embodiments of this specification include a substrate including a pixel region and a light-transmitting region more transparent than the pixel region, a drive transistor disposed in the pixel region, power supply wiring disposed on the drive transistor in the pixel region, signal wiring disposed on the power supply wiring in the pixel region, and a light-emitting element disposed in the pixel region and electrically connected to the drive transistor.

[0162] According to other features of this specification, in cross-section, signal wiring may be positioned between the drive transistor and the power supply wiring, and may be superimposed on the drive transistor and the power supply wiring.

[0163] Although embodiments of this specification have been described in more detail above with reference to the attached drawings, this specification is not necessarily limited to these embodiments and can be modified and implemented in various ways within the scope of the technical concept of this specification. Accordingly, the embodiments disclosed herein are for illustrative purposes only, not to limit the technical concept of this specification, and the scope of the technical concept of this specification is not limited by such embodiments. Therefore, the embodiments described above should be understood in all respects as illustrative and not restrictive.

Claims

1. A substrate comprising multiple pixel regions arranged at a distance from each other, each containing multiple subpixels, and multiple transparent regions arranged between the multiple pixel regions, and A display device including a plurality of signal lines extending in a first direction on the substrate, The plurality of subpixels include a plurality of pixel circuits, and the plurality of signal lines do not overlap the plurality of transparent regions, but overlap the region where the plurality of pixel circuits are arranged. The display device further includes scan wiring extending across the plurality of pixel regions on the substrate in a second direction different from the first direction, Each of the plurality of subpixels in the plurality of pixel regions includes a first main subpixel, a second main subpixel, and a third main subpixel arranged on one side of the scan wiring, and a first redundant subpixel, a second redundant subpixel, and a third redundant subpixel arranged on the other side of the scan wiring. The first main subpixel and the first redundant subpixel emit light of the first hue, the second main subpixel and the second redundant subpixel emit light of the second hue, and the third main subpixel and the third redundant subpixel emit light of the third hue. The aforementioned plurality of signal lines include a plurality of data lines, Each of the aforementioned subpixels is, A first transistor is positioned between one of the plurality of data lines and the substrate, and is electrically connected to the plurality of data lines. A drive transistor is placed between the one data wiring and the substrate and is electrically connected to the first transistor. A second transistor is positioned between the aforementioned data wiring and the substrate and is electrically connected to the drive transistor. A storage capacitor is placed between the data wiring and the drive transistor and is electrically connected to the gate electrode of the drive transistor, and A display device further comprising a light-emitting diode arranged on one of the data lines and electrically connected to the drive transistor.

2. The display device according to claim 1, wherein the plurality of signal wirings include a plurality of reference wirings.

3. In one of the plurality of pixel regions, the first transistors of the first main subpixel, the second main subpixel, and the third main subpixel are arranged in a line along a second direction different from the first direction. The display device according to claim 1, wherein in one of the plurality of pixel regions, the first transistors of the first redundant subpixel, the second redundant subpixel, and the third redundant subpixel are arranged in a line along the second direction.

4. In the aforementioned pixel region, the scan wiring includes a protruding portion that extends from the scan wiring toward the first direction and at least a portion of it extends toward the second direction. The display device according to claim 3, wherein the first transistors of the first main subpixel, the second main subpixel, and the third main subpixel, each located on one side of the scan wiring, are arranged on the protruding portion of the scan wiring, and the first transistors of the first redundant subpixel, the second redundant subpixel, and the third redundant subpixel, each located on the other side of the scan wiring, are arranged on the scan wiring.

5. In one of the plurality of pixel regions, the second transistors of the first main subpixel, the second main subpixel, and the third main subpixel are arranged in a line along the first direction. The display device according to claim 1, wherein in one of the plurality of pixel regions, the second transistors of the first redundant subpixel, the second redundant subpixel, and the third redundant subpixel are arranged in a line along the first direction.

6. In one of the plurality of pixel regions, the drive transistors for the first main subpixel, the second main subpixel, and the third main subpixel are arranged in a line along the first direction. The display device according to claim 1, wherein in one of the plurality of pixel regions, the drive transistors for the first redundant subpixel, the second redundant subpixel, and the third redundant subpixel are arranged in a line along the first direction.

7. In one of the plurality of pixel regions, the light-emitting diodes of the first main subpixel, the second main subpixel, and the third main subpixel are arranged in a line along the first direction. The display device according to claim 1, wherein in one of the plurality of pixel regions, the light-emitting diodes of the first redundant subpixel, the second redundant subpixel, and the third redundant subpixel are arranged in a line along the first direction.

8. The display device according to claim 1, wherein the plurality of signal wirings are arranged on and superimposed on the drive transistor and the storage capacitor.

9. A buffer layer disposed between the substrate and the drive transistor, A gate insulating layer is disposed on the buffer layer between the drive gate electrode and the drive active layer of the drive transistor. The first interlayer insulating layer covering the drive gate electrode, and The first interlayer insulating layer further includes one or more insulating layers covering the storage capacitor, The plurality of signal wirings are arranged on one or more insulating layers. The display device according to claim 1, wherein the thickness of the one or more insulating layers is greater than the thickness of the buffer layer, the thickness of the gate insulating layer, and the thickness of the first interlayer insulating layer.

10. The system further includes power supply wiring positioned between the storage capacitor and the plurality of signal wirings, The display device according to claim 1, wherein the power supply wiring is superimposed on the plurality of signal wiring.

11. The display device according to claim 10, wherein the power supply wiring includes low-potential power supply wiring.

12. The display device according to claim 10, wherein the power supply wiring is superimposed on the drive transistor and the storage capacitor.

13. The drive active layer of the drive transistor and the first active layer of the first transistor are located below the power supply wiring. The drive drain electrode of the drive transistor and the first source electrode of the first transistor are arranged on the power supply wiring. The display device according to claim 11, wherein the low-potential power supply wiring includes a plurality of openings superimposed on the contact hole connecting the drive active layer and the drive drain electrode, and the contact hole connecting the first active layer and the first source electrode.

14. The plurality of reference wires are electrically connected to the second transistor. The display device according to claim 2, wherein the plurality of reference wirings are arranged on the same layer as the plurality of data wirings.

15. The display device according to claim 14, wherein the plurality of reference wirings are formed integrally with the second drain electrode of the second transistor.

16. The aforementioned multiple subpixels are, In plan view, the first subpixel is rectangular. In a plan view, the second subpixel enclosing two adjacent sides of the first subpixel, and In a plan view, it includes a third subpixel that surrounds the outer portion of the second subpixel, The display device according to claim 1, wherein the first subpixel, the second subpixel, and the third subpixel together form a single rectangular shape.

17. A substrate including a pixel region containing subpixels and a light-transmitting region that is more transparent than the pixel region, A drive transistor arranged in the aforementioned pixel region, Power supply wiring arranged on the drive transistor in the aforementioned pixel region, A signal wiring positioned above the power wiring in the aforementioned pixel region and extending in a first direction, A light-emitting element arranged in the pixel region and electrically connected to the drive transistor, and The substrate includes scan wiring that extends in a second direction different from the first direction, crossing a plurality of the pixel regions, Each of the multiple subpixels in the multiple pixel regions includes a first main subpixel, a second main subpixel, and a third main subpixel arranged on one side of the scan wiring, and a first redundant subpixel, a second redundant subpixel, and a third redundant subpixel arranged on the other side of the scan wiring. A display device in which the first main subpixel and the first redundant subpixel emit light of a first hue, the second main subpixel and the second redundant subpixel emit light of a second hue, and the third main subpixel and the third redundant subpixel emit light of a third hue.

18. A substrate including a pixel region containing subpixels and a light-transmitting region that is more transparent than the pixel region, A drive transistor arranged in the aforementioned pixel region, Power supply wiring arranged on the drive transistor in the aforementioned pixel region, In a cross-sectional view, a signal wire extending in a first direction is positioned between the drive transistor and the power supply wiring, and superimposed on the drive transistor and the power supply wiring in the pixel region. A light-emitting element arranged in the pixel region and electrically connected to the drive transistor, and The substrate includes scan wiring that extends in a second direction different from the first direction, crossing a plurality of the pixel regions, Each of the multiple subpixels in the multiple pixel regions includes a first main subpixel, a second main subpixel, and a third main subpixel arranged on one side of the scan wiring, and a first redundant subpixel, a second redundant subpixel, and a third redundant subpixel arranged on the other side of the scan wiring. A display device in which the first main subpixel and the first redundant subpixel emit light of a first hue, the second main subpixel and the second redundant subpixel emit light of a second hue, and the third main subpixel and the third redundant subpixel emit light of a third hue.

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