Method for cleaning plasma chambers and chamber components

Abstract

To provide a plasma processing system and a method for processing plasma for preferentially cleaning a desired surface of a substrate supporting assembly by manipulating at least one characteristic of an on-site plasma.SOLUTION: The method for processing plasma includes the steps of: generating plasma in a processing region defined by a chamber lid and a substrate support assembly; exposing an edge ring and a substrate support surface to the plasma; and establishing a pulse voltage (PV) waveform in an edge control electrode.SELECTED DRAWING: Figure 7A

Description

[Technical Field]

[0001]

[0001] Embodiments described herein relate to plasma generation gas or vapor-electric space discharge devices used in semiconductor device manufacturing, particularly processing chambers configured to generate capacitively coupled or inductively coupled plasma of a gas or vapor material supplied into a chamber space and to process a semiconductor substrate therein. [Background technology]

[0002]

[0002] Electrostatic chucks (ESCs) are commonly used in semiconductor device manufacturing processes where vacuum chucks are impractical and mechanical clamping is undesirable, such as for supporting and securing substrates in the low-pressure environment of a processing chamber. A typical ESC is formed of one or more layers of dielectric material that provide a surface for supporting the substrate (e.g., a substrate support surface), and further includes chucking electrodes embedded in or positioned between one or more layers of dielectric material. The substrate is secured to the ESC by creating a potential difference between the substrate and the chuck electrodes, thereby generating an electrostatic attraction force between them.

[0003]

[0003] The ESC is often part of an assembly configured to control a form of plasma-assisted process performed within a processing chamber, such as a plasma-assisted etching process in which ions are collided with the material surface of the substrate through openings in a mask layer formed on the substrate surface. In a typical plasma-assisted etching process, the substrate is placed on the ESC, plasma is formed on the substrate, and ions are accelerated from the plasma toward the substrate across a plasma sheath, i.e., an electron-depleted region formed between the plasma and the substrate surface.

[0004]

[0004] The ESC assembly may include an edge ring used to improve the uniformity of plasma processing near the substrate edge by reducing electrical and thermal discontinuities between the substrate edge and the portion of the ESC assembly positioned outward from the substrate edge. Typically, the edge ring is positioned to surround the substrate and is sized to allow at least some tolerance for positioning the substrate on the ESC such that the inward surface of the edge ring and the outer edge of the substrate define a gap region between them.

[0005]

[0005] Generally, processing byproducts from plasma-assisted processes accumulate on the chamber surface, including the surface of the ESC assembly. Conventional methods for cleaning such byproducts involve exposing the chamber surface to active species of a cleaning gas, which may be formed using a remote plasma source and introduced into the processing chamber, or by introducing the cleaning gas into the chamber to form an in-situ plasma. The active species of the cleaning gas react with the processing byproducts formed on the chamber surface to form volatile species, which are discharged from the processing chamber through exhaust. Generally, it is best to minimize the number and / or duration of chamber cleaning processes due to downtime and surface damage to chamber components resulting from repeated exposure to activated cleaning gas.

[0006]

[0006] Unfortunately, undesirable processing by-products often accumulate in parts of the ESC assembly, for example, in the gap between the outer edge of the substrate and the inward portion of the edge ring, well before the chamber cleaning process is required for other processing components located there. Processing by-products accumulated in the gap can be transferred to the bevel edge of the substrate and / or cause plasma instability that leads to undesirable arc discharges between the substrate and the edge ring. Surface defects and / or arc discharge-related damage at the substrate edge caused by transferred processing by-products can lead to reliability issues or failures of devices formed on the substrate, potentially reducing the yield of usable devices formed on the substrate. Particles induced by arc discharges can also increase chamber contamination and increase chamber downtime for cleaning and maintenance, thus reducing system uptime and production capacity. Frequent use of conventional chamber cleaning methods to clean the gaps in the ESC reduces system uptime and production capacity, and also has the problem of potentially damaging other surfaces of the ESC, such as the substrate support surface, and reducing its service life.

[0007]

[0007] Therefore, what is needed in the art is a system and a method to solve the above problem. [Overview of the project]

[0008]

[0008] Embodiments provided herein generally include plasma treatment systems and associated methods configured to preferentially clean a desired surface of a substrate support assembly by manipulating one or more properties of an in-situ plasma.

[0009]

[0009] In one embodiment, the plasma processing method includes (a) generating plasma in a processing area defined by a chamber lid and a substrate support assembly, wherein the substrate support assembly includes a first portion of dielectric material forming a substrate support surface, an edge ring surrounding the substrate support surface which may include a plasma-facing surface and one or more edge pocket surfaces positioned inward from the plasma-facing surface, a bias electrode positioned at a distance from the substrate support surface by the first portion of dielectric material, and an edge control electrode positioned at a distance from the center of the bias electrode, which is electrically connected to a first pulse voltage waveform generator configured to establish a first pulse voltage (PV) waveform at the bias electrode, wherein the edge control electrode is electrically connected to a second bias generator configured to establish a second pulse voltage (PV) waveform at the edge control electrode, and (b) exposing the edge ring and the substrate support surface to the plasma, and (c) simultaneously with (b), establishing a second pulse voltage (PV) waveform at the edge control electrode.

[0010] In another embodiment, the plasma processing method comprises: (a) igniting and maintaining a plasma within a processing region of a processing chamber, the plasma including a first portion disposed between a substrate support surface of a substrate support assembly and a chamber lid, and a second portion disposed between an edge ring and the chamber lid, the substrate support assembly including a first portion of a dielectric material forming the substrate support surface, a bias electrode spaced from the substrate support surface by the first portion of the dielectric material, the bias electrode being electrically connected to a first pulse voltage (PV) waveform generator configured to establish a first pulse voltage (PV) waveform at the bias electrode, an edge control electrode disposed at a distance from the center of the bias electrode and electrically connected to a second pulse voltage (PV) waveform generator, and an edge ring surrounding the substrate support surface and including one or more edge pocket surfaces that may define an edge pocket region by a substrate that is at least partially lifted above the substrate support surface, and igniting and maintaining the plasma; (b) using the second pulse voltage (PV) waveform generator to establish a second pulse voltage (PV) waveform at the edge control electrode; and (c) exposing the at least partially lifted substrate to the plasma.

[0011]

[0011] In another embodiment, the processing method is (a) igniting and maintaining a plasma from a gas or vapor supplied to a processing area, the processing area being defined by a chamber lid and a substrate support assembly facing the chamber lid, the substrate support assembly comprising: a first portion of dielectric material forming a substrate support surface; a first electrode positioned at a distance from the substrate support surface by the first portion of dielectric material; an edge ring surrounding the substrate support surface, the edge ring having one or more edge pocket surfaces defining an edge pocket region by the outer peripheral edge of a substrate that is at least partially lifted and positioned on the substrate support surface; and a second portion of dielectric material positioned at a distance from the edge ring (b) Ignition and maintenance of plasma, comprising: (a) exposure of one or more edge pocket surfaces to plasma, wherein a second electrode is positioned such that the substrate support assembly is electrically connected to an RF generator that supplies a high-frequency (RF) signal used to ignite and maintain the plasma, the RF signal establishing a first RF waveform at the first electrode and a second RF waveform at the second electrode, the second electrode being electrically connected to an edge tuning circuit configured to control the uniformity of plasma density within a processing area by tuning one or more characteristics of the second RF waveform relative to the first RF waveform, the second electrode having at least one characteristic different from the characteristics of the first RF waveform; and (b) exposure of one or more edge pocket surfaces to the plasma.

[0012]

[0012] In another embodiment, the plasma chamber includes a chamber body that defines a processing space and a chamber lid, and the substrate support assembly is disposed within the processing space facing the chamber lid. The substrate support assembly may include a support base and a substrate support disposed on the support base. The substrate support may include a dielectric material that forms a substrate support surface, a bias electrode disposed within the dielectric material and spaced from the substrate support surface and the support base by portions of the dielectric material, and an edge control electrode disposed at a distance from the center of the bias electrode. The chamber may also include an edge tuning circuit electrically connected to the edge control electrode and a non-transitory computer-readable medium having instructions for performing the method, the method including: a) generating a plasma from a gas or vapor supplied to the processing space by using a radio frequency (RF) signal supplied to the support base, the RF signal being supplied to the support base by an RF signal generator, the RF signal establishing a first RF waveform at the bias electrode and a second RF waveform at the edge control electrode; and b) adjusting one or more characteristics of the second RF waveform relative to the first RF waveform by using the edge tuning circuit.

[0013]

[0013] Other embodiments include corresponding computer systems, devices, and computer programs recorded on one or more computer storage devices, each configured to perform the operations of the method.

[0014]

[0014] Note, however, that the accompanying drawings show only exemplary embodiments and should not be considered as limiting the scope of the present disclosure, which may admit other equally effective embodiments. Note, however, that the accompanying drawings show only exemplary embodiments and should not be considered as limiting the scope of the present disclosure, which may admit other equally effective embodiments.

Brief Description of the Drawings

[0015] [Figure 1A]

[0015] This is a schematic cross-sectional view of one or more embodiments of a processing system configured to carry out the methods described herein. [Figure 1B] This is a schematic cross-sectional view of one or more embodiments of a processing system configured to perform the methods described herein. [Figure 1C]

[0016] This is a close schematic cross-sectional view of a portion of the substrate support assembly shown in Figure 1A, according to one embodiment. [Figure 1D] This is a close schematic cross-sectional view of a portion of the substrate support assembly shown in Figure 1A, according to one embodiment. [Figure 2]

[0017] This is a simplified schematic diagram of a biasing and edge control scheme that can be used with one or both of the processing systems shown in Figures 1A-1B, according to one or more embodiments. [Figure 3A]

[0018] An exemplary edge tuning circuit, which can be used with one or both of the processing systems shown in Figures 1A-1B, according to one or more embodiments, is schematically shown. [Figure 3B] An exemplary edge tuning circuit, which can be used with one or both of the processing systems shown in Figures 1A-1B, according to one or more embodiments, is schematically shown. [Figure 3C] An exemplary edge tuning circuit, which can be used with one or both of the processing systems shown in Figures 1A-1B, according to one or more embodiments, is schematically shown. [Figure 3D]

[0019] These are functionally equivalent circuit diagrams of different electrostatic chuck (ESC) types that can be used with one or both of the processing systems shown in Figures 1A and 1B. [Figure 3E] These are functionally equivalent circuit diagrams of different electrostatic chuck (ESC) types that can be used with one or both of the processing systems shown in Figures 1A and 1B. [Figure 4]

[0020] Examples of pulse voltage (PV) waveforms that can be established using the embodiments described herein are shown. [Figure 5]

[0021] A and B show exemplary radio frequency (RF) waveforms that can be established using the embodiments described herein. [Figure 6]

[0022] Figures A through D are graphs showing simulation results using exemplary edge-tuned circuit configurations according to embodiments of this specification. [Figure 7A]

[0023] This figure shows a method that can be carried out using the embodiments described herein. [Figure 7B] This figure shows a method that can be carried out using the embodiments described herein. [Figure 7C] This figure shows a method that can be carried out using the embodiments described herein. [Figure 8A]

[0024] These are schematic cross-sectional views of the edge portion of a substrate support assembly, showing an embodiment of the method described in Figures 7A to 7C according to the embodiments of this specification. [Figure 8B] These are schematic cross-sectional views of the edge portion of a substrate support assembly, showing an embodiment of the method described in Figures 7A to 7C according to the embodiments of this specification. [Figure 8C] These are schematic cross-sectional views of the edge portion of a substrate support assembly, showing an embodiment of the method described in Figures 7A to 7C according to the embodiments of this specification. [Modes for carrying out the invention]

[0016]

[0025] The embodiments provided herein relate to processing systems and related methods used in semiconductor device manufacturing processes. In particular, the embodiments herein provide cleaning of portions of substrate support assemblies using plasma formed in a processing chamber, such as in-situ cleaning plasma. For example, in some embodiments, the systems and methods are preferentially used to clean accumulated processing byproducts from portions of substrate support assemblies that define gap regions formed when a substrate is placed on the substrate support assembly. Thus, the methods described herein can be used to beneficially in-situ plasma cleaning of gap region surfaces of substrate support assemblies while reducing plasma damage to other surfaces, such as substrate support surfaces, and extending their useful life.

[0017]

[0026] In some embodiments, the processing system is configured for a plasma-assisted etching process in which plasma-generated ions are used to collide with the material surface of the substrate through openings formed in a patterned mask layer formed on the substrate surface. In a typical plasma-assisted etching process, the substrate is placed on the substrate receiving surface of a substrate support assembly, and a plasma is formed on the substrate using radio frequency (RF) power, and ions are accelerated from the plasma toward the substrate across the plasma sheath. The plasma sheath generally exhibits properties similar to a nonlinear diode, resulting in the rectification of the applied RF field and a DC voltage drop (i.e., self-bias) between the substrate and the plasma.

[0018]

[0027] In some embodiments, the processing system is configured to control the characteristics of the plasma sheath using pulsed voltage (PV) waveforms supplied from one or more pulsed voltage (PV) generators to bias electrodes and edge control electrodes. In some embodiments, an RF waveform is supplied from a radio frequency (RF) generator to one or more power electrodes in the processing chamber, generating RF to establish and maintain the plasma within the processing chamber, while one or more PV waveforms supplied from one or more PV generators are configured to establish a substantially constant sheath voltage (e.g., a constant difference between the plasma potential and the substrate potential) across the substrate surface and the adjacent substrate support assembly. The established substantially constant sheath voltage provides a desired ion energy distribution function (IEDF) at the substrate surface during one or more plasma processing steps performed in the processing chamber.

[0019]

[0028] Some embodiments of the present disclosure include apparatus and methods for controlling plasma uniformity by controlling, for example, the electron density in a bulk plasma across the peripheral edge region of a substrate and adjacent surfaces of a substrate support assembly with respect to the center of the substrate. In some embodiments, plasma uniformity is controlled using an edge tuning circuit to control one or a combination of the voltage amplitude ratio between an RF waveform established at an edge control electrode and an RF waveform established at a bias electrode (e.g., a chucking electrode), the current amplitude ratio between the RF waveforms at the edge control electrode and the bias electrode, and the phase difference between the RF waveforms at each electrode.

[0020]

[0029] In some embodiments, ion energy and directionality are controlled by biasing the substrate and the surrounding edge ring separately using a pulsed voltage (PV) waveform. The PV waveform can be established at electrodes located in parts of the substrate support assembly that form part of the substrate support assembly and are generally located beneath the substrate (bias electrode) and the edge ring (edge ​​control electrode), respectively. As described later, the shape of the plasma sheath boundary can be manipulated using the PV waveform to focus ions accelerated across the sheath toward a desired area of ​​the surface beneath. In some embodiments, a chamber component cleaning method uses focused ions to target the gap region between the substrate edge and / or the substrate support surface and the surrounding edge ring, removing undesirable processing byproducts, such as polymers, formed on the surface of the edge pocket region during a reactive ion etching (RIE) plasma process.

[0021]

[0030] In some embodiments, ion flux (plasma density uniformity) is controlled by using an edge tuning circuit to adjust one or more characteristics of the RF waveforms established at the edge control electrode to one or more characteristics of the RF waveforms established at the bias electrode. For example, the edge tuning circuit can be used to adjust the voltage amplitude ratio or current amplitude ratio between the RF waveforms established at the edge control electrode and the bias electrode. The voltage and / or current amplitude ratio can be used to adjust the plasma distribution (plasma density) on the substrate support assembly, increasing the plasma density on the edge ring relative to the plasma density on the central region of the substrate support assembly, or vice versa.

[0022]

[0031] In some embodiments, an edge tuning circuit is used to introduce a desired phase difference between RF waveforms established by a bias electrode and an edge control electrode. By adjusting the phase difference, the electric field generated between the two electrodes can be amplified. The amplification of the electric field can be manipulated to increase the concentration of ions and reactive neutral species in the gap region located between the substrate edge and the inward surface of the edge ring. In some embodiments, the phase difference between the RF waveforms is controlled to concentrate the plasma between the bias electrode and the edge control electrode, and thus concentrate the plasma in the gap region.

[0023]

[0032] In some embodiments, pulsed voltage (PV) waveforms and / or edge tuning circuits are used alone or in combination with a substrate chucking method to preferentially clean gap regions while protecting the dielectric substrate support surface from ion-induced damage. For example, in some embodiments, the method includes focusing ions toward a gap region and / or concentrating plasma in the gap region while the substrate is partially lifted from the substrate support surface.

[0024]

[0033] Beneficially, the apparatus and method described herein, individually or in combination, provide individual process tuning knobs for controlling the uniformity of ion energy and directionality, which can be used to individually control the uniformity of ion flux and / or reactive neutral species across the surface of the substrate support assembly and / or the substrate placed thereon. For example, in some embodiments, the uniformity of ion energy and directionality can be controlled by adjusting the PV waveforms established at the edge control electrode and bias electrode, respectively, to control the thickness profile of the plasma sheath and the shape of the sheath boundary (between the plasma sheath and the plasma) formed over the gap region of the substrate support assembly. The uniformity of ion flux and / or reactive neutral species concentration can be individually controlled by adjusting the RF waveforms established at each electrode. Thus, the apparatus and method described herein facilitate targeted cleaning of the gap region of the substrate support assembly by controlling the ion energy, ion directionality, and / or the concentration of ions and reactive neutral species. Exemplary processing systems that can be used to carry out the method are shown in Figures 1A to 1D.

[0025] Examples of plasma processing systems

[0034] Figures 1A and 1B are schematic cross-sectional views of processing systems 10A and 10B, respectively, configured to perform one or more of the plasma processing methods specified herein. Figure 1C is a close-up view of a portion of the substrate support assembly 136 shown in Figure 1A. Figure 2 is a simplified schematic diagram of a processing scheme that can be used with one or both of processing systems 10A and 10B. Figures 3A-3B are examples of edge tuning circuits 170 that can be used with one or both of processing systems 10A and 10B to control and adjust plasma uniformity.

[0026]

[0035] In some embodiments, the processing systems 10A and 10B shown in Figures 1A and 1B are configured for plasma-assisted etching processes such as reactive ion etching (RIE) plasma processing. However, it should be noted that some embodiments described herein may also be used in conjunction with processing systems configured for use in other plasma-assisted processes, such as plasma deposition processes, e.g., plasma-enhanced chemical vapor deposition (PECVD), plasma-enhanced physical vapor deposition (PEPVD), plasma-enhanced atomic layer deposition (PEALD), plasma processing processes, or plasma-based ion implantation processes (e.g., plasma doping (PLAD) processes).

[0027]

[0036] As shown in Figures 1A-1B, processing systems 10A-10B are configured to form a capacitively coupled plasma (CCP), and the processing chamber 100 includes an upper electrode (e.g., a chamber lid 123) located within the processing space 129, and this upper space faces a lower electrode (e.g., a substrate support assembly 136) also located within the processing space 129. In a typical capacitively coupled plasma (CCP) processing system, a radio frequency (RF) source (e.g., an RF generator 118) is electrically connected to either the upper or lower electrode and supplies an RF signal configured to ignite and maintain the plasma (e.g., plasma 101), which is capacitively coupled to the upper and lower electrodes and placed in the processing area between them. Typically, one of the opposing upper or lower electrodes is connected to ground or a second RF power source. In Figures 1A-1B, one or more components of the substrate support assembly 136, such as the support base 107, are electrically connected to the plasma generator assembly 163, which includes the RF generator 118, and the chamber lid 123 is electrically connected to ground.

[0028]

[0037] As shown in Figures 1A and 1B, each of the processing systems 10A and 10B includes a processing chamber 100, a substrate support assembly 136, a system controller 126, and a plasma control scheme 188. In the embodiments described herein, one or a combination of features, configurations, and / or structural components of the processing system 10A, such as the structural components of the substrate support assembly 136 and / or the electrical components of the plasma control scheme 188, may be used in the processing system 10B, and vice versa.

[0029]

[0038] The processing chamber 100 typically includes a chamber body 113, which comprises a chamber lid 123, one or more side walls 122, and a chamber base 124, collectively defining a processing space 129. The one or more side walls 122 and the chamber base 124 generally include a material sized and molded to form structural supports for the elements of the processing chamber 100, and configured to withstand the pressure and further energy applied to them. Meanwhile, the plasma 101 is generated in a vacuum environment maintained within the processing space 129 of the processing chamber 100 during processing. In one embodiment, the one or more side walls 122 and the chamber base 124 are formed from a metal such as aluminum, an aluminum alloy, or a stainless steel alloy.

[0030]

[0039] A gas inlet 128, positioned through the chamber lid 123, is used to supply one or more processing gases to the processing space 129 from a processing gas source 119, to which it is fluidly connected. In some embodiments, the gas is supplied through a showerhead (not shown). In other embodiments, the gas is supplied through a side wall 122 (not shown). The substrate 103 is brought into and out of the processing space 129 through an opening (not shown) in one of the side walls 122, which is sealed by a slit valve (not shown) during the plasma processing of the substrate 103.

[0031]

[0040] In some embodiments, a plurality of lift pins 20, movably positioned through an opening formed in the substrate support assembly 136, facilitate the transfer of the substrate to and from the substrate support surface 105A. In some embodiments, the plurality of lift pins 20 are connected to and / or engageable with a lift pin hoop (not shown) positioned above and located within a processing space 129. The lift pin hoop may be connected to a shaft (not shown) that extends in a sealed manner through the chamber base 124. The shaft may be connected to an actuator (not shown) used to raise and lower the lift pin hoop. When the lift pin hoop is in the raised position, it engages with the plurality of lift pins 20 to raise the upper surface of the lift pins above the substrate support surface 105A, lifting the substrate 103 from there and allowing a robot handler (not shown) to access the inactive (back) side of the substrate 103. When the lift pin hoop is in the lowered position, the multiple lift pins 20 are either coplanar with the substrate support surface 105A or recessed below the substrate support surface 105A, and the substrate 103 is placed on top of them.

[0032]

[0041] The system controller 126, also referred to herein as the processing chamber controller, includes a central processing unit (CPU) 133, memory 134, and support circuitry 135. The system controller 126 is used to control the process sequence (including the substrate biasing method described herein) used to process the substrate 103. The CPU 133 is a general-purpose computer processor configured for use in industrial settings to control the processing chamber and the subprocessors associated with the processing chamber. The memory 134 described herein is generally non-volatile memory and may include random-access memory, read-only memory, floppy or hard disk drives, or other suitable forms of digital storage (local or remote). The support circuitry 135 is conventionally connected to the CPU 133 and includes a cache, clock circuitry, input / output subsystems, power supply, and combinations thereof. Software instructions (programs) and data may be encoded and stored in memory 134 for instructing the processor in the CPU 133. A software program (or computer instruction) readable by the CPU 133 in the system controller 126 identifies which tasks can be performed by components in the processing system 10A and / or 10B.

[0033]

[0042] Typically, the program is readable by the CPU 133 in the system controller 126 and contains code. When executed by the processor (CPU 133), this code performs tasks related to the plasma processing scheme described herein. The program may also contain instructions. These instructions are used to control various hardware and electrical components within the processing system 10A and / or 10B. This is used to perform various process tasks and various process sequences used to implement the methods described herein. In one embodiment, the program contains instructions used to perform one or more of the operations described later in relation to Figures 7 and 8A-8C.

[0034]

[0043] The plasma control scheme 188 illustrated in Figures 1A-1B generally includes a plasma generator assembly 163, a first bias generator 196 for establishing a first PV waveform at the bias electrode 104, and a second bias generator 197 for establishing a second PV waveform at the edge control electrode 115. In some embodiments, the plasma generator assembly 163 supplies an RF signal to a support base 107 (e.g., a power electrode or cathode), which may be used to generate (maintain and / or ignite) plasma 101 in a processing area located between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF generator 118 is configured to supply an RF signal having a frequency greater than 400 kHz, such as an RF frequency of about 1 MHz or more, or about 2 MHz or more, e.g., about 13.56 MHz or more, about 27 MHz or more, or about 40 MHz or more.

[0035]

[0044] In some embodiments, the plasma control scheme 188 further includes an edge tuning circuit 170, which may be used to adjust one or more characteristics of the plasma 101 formed between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the edge tuning circuit 170 may be used to adjust the density of a portion of the plasma 101 formed on the outer peripheral edge of the substrate 103 placed on the substrate support assembly 136 relative to the density of a portion of the plasma 101 formed on the central surface of the substrate 103.

[0036]

[0045] Generally, as used herein, plasma density is the number of free electrons in bulk plasma per unit volume (e.g., number of free electrons / cm³). 3 ) refers to, which in some embodiments is about 10 8 cm -3 ~about 10 11 cm -3This may be within the range. The edge tuning circuit 170 allows manipulation of one or more characteristics of the RF power used to maintain the plasma 101 in the region on the edge of the substrate support assembly 136, with respect to the RF power used to maintain the plasma 101 in the region on the central portion of the substrate support assembly 136. For example, the edge tuning circuit 170 may be used to adjust one or more of the voltage, current, and / or phase of the RF power at the edge of the substrate support assembly 136, with respect to the RF power in the central region 103A of the substrate support assembly 136.

[0037]

[0046] As will be further described later, the edge tuning circuit 170 may be electrically connected to the edge control electrode 115 located in the substrate support assembly 136. In some embodiments, the RF signal used to ignite and / or maintain the plasma 101 is supplied from the plasma generator assembly 163 to the support base 107, which is capacitively coupled to the edge control electrode 115 via a layer of dielectric material placed between them. The edge tuning circuit 170 may be used to adjust one or more characteristics of the RF power used to maintain the plasma within a region on the edge control electrode 115, for example, by adjusting the voltage, current, and / or phase of the RF power at the edge control electrode 115 with respect to the RF power supplied to the support base 107.

[0038]

[0047] In some embodiments, the difference between the voltage, current, and / or phase of the RF power used to ignite and / or maintain the plasma in the region on the edge control electrode 115 and the bias electrode 104 is determined and / or monitored by measuring or determining the respective voltage, current, and / or phase of the RF power at the edge control electrode 115 and / or the bias electrode 104. In some embodiments, one or more characteristics of the RF power at the edge control electrode 115 and / or the bias electrode 104 are measured and / or determined using the signal detection module 187 described below.

[0039]

[0048] As described above, in some embodiments, the plasma generator assembly 163, including the RF generator 118 and RF generator assembly 160, is generally configured to supply a desired amount of continuous wave (CW) or pulsed RF power at a desired substantially fixed sinusoidal frequency to the support base 107 of the substrate support assembly 136, based on a control signal supplied from the system controller 126. During processing, the plasma generator assembly 163 is configured to supply RF power (e.g., an RF signal) to the support base 107, which is located in close proximity to the substrate support 105 and within the substrate support assembly 136. The RF power supplied to the support base 107 is configured to ignite and maintain the processing plasma 101 of the processing gas located within the processing space 129.

[0040]

[0049] In some embodiments, the support base 107 is an RF electrode electrically connected to the RF generator 118 via an RF matching circuit 162 and a first filter assembly 161, both of which are located within the RF generator assembly 160. The first filter assembly 161 includes one or more electrical elements configured to substantially prevent current generated by the output of the PV waveform generator 150 from flowing through the RF power supply line 167 and damaging the RF generator 118. The first filter assembly 161 acts as a high impedance (e.g., high Z) to the PV signal generated from the PV pulse generator P1 in the PV waveform generator 150, thereby suppressing the flow of current to the RF matching circuit 162 and the RF generator 118.

[0041]

[0050] In some embodiments, an RF generator assembly 160 and an RF generator 118 are used to ignite and maintain a processing plasma 101 using a processing gas placed in a processing space 129 and an electric field generated by RF power (RF signal) supplied to a support base 107 by the RF generator 118. The processing space 129 is fluidly connected to one or more dedicated vacuum pumps through a vacuum outlet 120. One or more dedicated vacuum pumps maintain the processing space 129 at near-atmospheric pressure and exhaust the processing gas and / or other gases from the processing space 129. In some embodiments, a substrate support assembly 136 placed in the processing space 129 is grounded and positioned on a support shaft 138 extending through a chamber base 124. However, in some embodiments, the RF generator assembly 160 is configured to supply RF power to a bias electrode 104 located in a substrate support 105 relative to the support base 107.

[0042]

[0051] In some embodiments, the edge tuning circuit 170 is used to control and / or adjust one or more characteristics of the RF waveform established on the edge control electrode 115 (e.g., the second RF waveform 502 shown in Figure 5) to one or more characteristics of the RF waveform established on the bias electrode 104 (e.g., the first RF waveform 501 shown in Figure 5). In some embodiments, such as those shown in Figures 1A and 2, the edge tuning circuit 170 is electrically connected between the edge control electrode 115 and ground. In other embodiments, such as those shown in Figure 1B and the dotted line in Figure 2, the edge tuning circuit 170 may be electrically connected between the edge control electrode 115 and the plasma generator assembly 163, and therefore electrically connected between the edge control electrode 115 and the support base 107.

[0043]

[0052] As briefly described above, the substrate support assembly 136 generally includes a substrate support 105 (e.g., an ESC substrate support) and a support base 107. In some embodiments, the substrate support assembly 136 may further include an insulating plate 111 and a grounding plate 112, which will be described further below. The support base 107 is electrically insulated from the chamber base 124 by the insulating plate 111, and the grounding plate 112 is inserted between the insulating plate 111 and the chamber base 124. The substrate support 105 is thermally coupled to the support base 107 and is positioned on the support base 107. In some embodiments, the support base 107 is configured to regulate the temperature of the substrate support 105 and the substrate 103 positioned on the substrate support 105 during substrate processing.

[0044]

[0053] In some embodiments, the support base 107 includes one or more cooling channels (not shown) disposed internally. One or more cooling channels are fluidly connected to and fluidly coupled to a coolant source (not shown), such as a refrigerant source or water source having relatively high electrical resistance. In some embodiments, the substrate support 105 includes a heater (not shown), such as a resistance heating element embedded in the dielectric material of the substrate support 105. Here, the support base 107 is formed of a corrosion-resistant thermal conductive material such as a corrosion-resistant metal (e.g., aluminum, aluminum alloy, or stainless steel) and is connected to the substrate support by adhesive or mechanical means.

[0045]

[0054] Typically, the substrate support 105 is formed of a dielectric material, such as a bulk sintered ceramic material (corrosion-resistant metal oxide or metal nitride material, such as aluminum oxide (Al2O3), aluminum nitride (AlN), titanium oxide (TiO), titanium nitride (TiN), yttrium oxide (Y2O3), mixtures thereof, or combinations thereof). In embodiments herein, the substrate support 105 further includes a bias electrode 104 embedded in its dielectric material. In some embodiments, one or more characteristics of the RF power used to maintain the plasma 101 in the processing area on the bias electrode 104 are determined and / or monitored by measuring an RF waveform established at the bias electrode 104 (e.g., the first RF waveform 501 in Figure 5). Typically, the first RF waveform 501 is established by supplying an RF signal from the plasma generator assembly 163 to the substrate support 105, and the substrate support 105 is capacitively coupled to the bias electrode 104 through a dielectric material layer 105C (Figure 1C) placed between them.

[0046]

[0055] In one configuration, the bias electrode 104 is a chucking pole used to fix (i.e., chuck or electrostatically clamp) the substrate 103 to the substrate support surface 105A of the substrate support 105 and to bias the substrate 103 to the processing plasma 101 using one or more of the pulse voltage bias schemes described herein. Typically, the bias electrode 104 is formed of one or more conductive components, such as one or more metal meshes, foils, plates, or combinations thereof.

[0047]

[0056] In some embodiments, the bias electrode 104 is electrically connected to a clamping network 116. The clamping network 116 supplies a chucking voltage to the bias electrode 104, such as a static DC voltage between approximately -5000V and approximately 5000V, using an electrical conductor such as a coaxial power supply line 106 (e.g., a coaxial cable). As will be further discussed below, the clamping network 116 includes a bias compensation circuit element 116A, a DC power supply source 155, and a bias compensation module blocking capacitor. The bias compensation module blocking capacitor is also referred to herein as the blocking capacitor C5. The blocking capacitor C5 is positioned between the output of the pulse voltage (PV) waveform generator 150 and the bias electrode 104.

[0048]

[0057] Referring to Figures 1A and 1B, the substrate support assembly 136 may further include an edge control electrode 115. The edge control electrode 115 is positioned below the edge ring 114, surrounding the bias electrode 104, and / or at a distance from the center of the bias electrode 104. Generally, in a processing chamber 100 configured to process a circuit board, the edge control electrode 115 is ring-shaped, made from a conductive material, and configured to surround at least a portion of the bias electrode 104. In some embodiments, such as shown in Figure 1A, the edge control electrode 115 is positioned within the region of the substrate support 105. In some embodiments, as shown in Figure 1A, the edge control electrode 115 includes a conductive mesh, foil, and / or plate positioned from the edge ring 114 at a similar distance (i.e., in the Z direction) from the substrate support surface 105A of the substrate support 105 to the bias electrode 104. In some other embodiments, such as those shown in Figure 1B, the edge control electrode 115 includes a conductive mesh, foil, and / or plate positioned on or within the region of the dielectric tube 110. The dielectric tube 110 surrounds at least a portion of the bias electrode 104 and / or the substrate support 105. The dielectric tube 110 can be made of various insulators such as aluminum oxide, aluminum nitride, and quartz. In some embodiments, the dielectric tube 110 may include several components made of the same or different materials. Alternatively, in some other embodiments (not shown), the edge control electrode 115 is positioned within or connected to an edge ring 114 positioned adjacent to the substrate support 105.

[0049]

[0058] Figure 1D is a close-up view of a portion of the substrate support assembly 136 shown in Figure 1A. As shown, the edge ring 114 is positioned on the substrate support 105 and surrounds the substrate 103. The edge ring 114 may be used to protect the edges of the substrate support 105 and, in some cases, to minimize electrical and / or thermal discontinuities formed in the substrate and substrate support edges. The edge ring 114 includes one or more inner surfaces 114A that face a portion of the substrate support 105 and the outer (beveled) edge of the substrate 103 placed thereon. The inner surfaces 114A of the edge ring 114 may include a ledge portion 114B that is spaced apart from the substrate support 105 and the substrate 103 placed thereon, defining one or more gaps 117A-B and positioned below the beveled substrate edge when the substrate 103 is placed on the substrate support 105.

[0050]

[0059] In a typical etching process, ions collide with the upper plasma-facing surface of the edge ring 114 (e.g., surface 114C) during processing, resulting in ion-induced erosion of the dielectric material forming the edge ring 114. Unfortunately, the surface of the edge ring 114 defining the gap regions 117A-B is less exposed to the plasma 101, and therefore tends to accumulate processing etching byproducts. These byproducts, unless removed, can cause undesirable plasma arcs and / or particle migration between the edge ring 114 and the substrate 103 surface. Therefore, in some embodiments, bias and plasma control methods used to improve processing non-uniformity at the substrate edge may also be used to preferentially clean the surface defining the edge pocket region 117.

[0051]

[0060] As described later, the edge ring 114 can be biased using a pulsed voltage (PV) waveform to control the shape of the plasma sheath boundary 11 that extends beyond the substrate edge and the edge ring 114 so as to span the edge pocket region 117. The shape of the plasma sheath boundary 11 affects the energy and directionality of ions accelerated across the plasma sheath. For example, as described later and shown in Figures 9A-9C, the difference in height between a portion of the sheath boundary 11 formed on the substrate 103 (part 11A) and a portion of the sheath boundary formed on the edge ring 114 (part 11C) will cause the sheath boundary to bend in the portion of the sheath boundary that spans the edge pocket region 117 (bent portion 11B). The sheath thickness and the change in the bending of the sheath boundary affect the ionic energy and ionic directionality of ions that collide with the surface of the substrate 103 and the edge ring 114 located beneath it, respectively. Thus, control over the plasma sheath boundary 11 across the edge pocket region 117 allows for adjustment of the ion energy and ion orientation on the surface of the substrate edge region 103B. This can be used to improve the uniformity of the substrate processing. The improved control over the plasma sheath boundary 11 can also be used to perform the in-plasma cleaning method described herein, targeting the surfaces 114A-B of the edge ring 114 to clean away undesirable processing byproducts.

[0052]

[0061] The edge control electrode 115, when used with the edge tuning circuit 170 and / or biased using the pulse bias scheme 140 (Figures 1A-1B), is positioned such that, due to its position relative to the substrate 103, it can influence or alter a portion of the generated plasma 101 located on or outside the outer peripheral edge of the substrate 103. In some embodiments, bias generators 196, 197 may be used to control the shape of the sheath boundary 11 on the plasma-facing surface of the substrate support assembly 136. For example, due to repeated ion collisions, the edge ring 114 is typically subjected to plasma-based erosion, reducing its thickness over its service life. If the thickness of the plasma sheath formed on the edge ring 114 remained constant, the wear of the edge ring 114 would eventually lead to bending of the plasma sheath boundary, resulting in uneven processing at the substrate edge. Therefore, in some embodiments, one or more characteristics of the pulse voltage (PV) waveform established by the bias electrode 104 and / or edge control electrode 115 may be adjusted to compensate for changes in the height of the edge ring 114 over the lifespan of the edge ring in order to maintain a substantially uniform sheath boundary 11 across the edge of the substrate 103.

[0053]

[0062] In some embodiments, an edge tuning circuit 170 electrically connected to the edge control electrode 115 can be used to manipulate one or more characteristics of the RF power used to ignite and / or maintain the plasma in the processing area 129A above the edge control electrode 115. For example, in some embodiments, the edge tuning circuit 170 can be used to adjust and / or manipulate one or more of the voltage, current, and / or phase of the RF power used to ignite and / or maintain the plasma 101 in the processing area located between the edge control electrode 115 and the chamber lid 123.

[0054]

[0063] In some embodiments, one or more characteristics of the RF power used to maintain the plasma 101 in the processing area on the edge control electrode 115 are determined and / or monitored by measuring one or more differences between a second RF waveform 502 and a first RF waveform 501 established at the edge control electrode 115 and the bias electrode 104, respectively. In some embodiments, the difference in characteristics of one or more of the second RF waveform 502 and the first RF waveform 501 can be manipulated by using an edge tuning circuit 170 to adjust the plasma density in the area on the outer peripheral edge of the substrate 103 and / or in the area spanning the edge pocket area 117.

[0055]

[0064] In some embodiments, the difference in characteristics between the second RF waveform 502 and the first RF waveform 501 can be utilized to preferentially form plasma between the edge ring 114 and the edge of the substrate 103, effectively concentrating the plasma in the edge pocket region 117 and removing undesirable processing byproducts from the surface within it. Thus, the edge tuning circuit 170 is advantageously used to control the generation of active species in the bulk plasma, thereby enabling fine control of the ion and / or radical flux at the edge of the substrate 103 (edge ​​region 103B) relative to the central region 103A of the substrate 103, and / or the plasma concentration in the edge pocket region 117.

[0056]

[0065] The edge control electrode 115 can be energized using a PV waveform generator 150 different from the PV waveform generator 150 used to energize the bias electrode 104. In some embodiments, the edge control electrode 115 can be energized by using a PV waveform generator 150 that is also used to energize the bias electrode 104 by sharing a portion of the power with the edge control electrode 115. In one configuration, the first PV waveform generator 150 of the first bias generator 196 is configured to energize the bias electrode 104, and the second PV waveform generator 150 of the bias generator 197 is configured to energize the edge control electrode 115.

[0057]

[0066] In some embodiments, a signal detection module 187, communicatively connected to a system controller 126, is used to measure and / or determine one or more characteristics of the generated RF power. The signal detection module 187 is generally configured to receive electrical signals from various components within the processing systems 10A and 10B, for example, electrical signal traces (not shown) electrically connected to node N. The signal detection module 187 may include a plurality of input channels 172, each configured to receive electrical signals from a corresponding electrical signal trace, and a data acquisition module 169. The received electrical signals may include, but are not limited to, one or more characteristics of the RF signal supplied to the support base 107, the RF waveform established on one or both of the bias electrode 104 and the edge control electrode 115, the pulse voltage (PV) waveform established on one or both of the bias electrode 104 and the edge control electrode 115, and the chucking voltage supplied to one or both of the bias electrode 104 and the edge control electrode 115.

[0058]

[0067] In some embodiments, the data acquisition module 169 is configured to generate control signals used to automatically control one or more characteristics of the RF signal, RF waveform, PV waveform, and / or chucking voltage during substrate processing. In some embodiments, a desired change in one or more characteristics is transmitted by the system controller 126 to the signal detection module 187, and the data acquisition module 169 may be used to implement the desired change.

[0059]

[0068] Referring to Figures 1A and 1B, the second bias generator 197 includes a clamping network 116 such that the bias applied to the edge control electrode 115 is configured similarly to the bias applied to the bias electrode 104 by the clamping network 116 connected within the first bias generator 196.

[0060]

[0069] In some embodiments, the processing chamber 100 further includes a dielectric tube 110 or collar that at least partially surrounds a portion of the substrate support assembly 136 as a dielectric barrier between the RF high-temperature substrate support assembly 136 and the grounding liner 108, and also prevents the substrate support 105 and / or support base 107 from coming into contact with corrosive processing gases or plasma, cleaning gases or plasma, or their by-products. Typically, the liner 108 is in contact with the dielectric tube 110, the insulating plate 111, and the grounding plate 112. In some embodiments, a plasma screen 109 is positioned between the cathode liner 108 and the sidewalls 122 to prevent plasma from being generated in the space below the plasma screen 109 between the liner 108 and one or more sidewalls 122.

[0061] Configuration of the substrate support assembly

[0070] Figure 1C is a close-up view of a portion of the substrate support assembly 136 shown in Figure 1A, and includes a simplified electrical schematic diagram of the electrical properties of various structural elements in one or more embodiments of the substrate support assembly 136. The simplified electrical schematic diagram shown in Figure 1C is equally applicable to the corresponding structural elements of the substrate support assembly 136 depicted in Figure 1B. Here, the substrate support assembly 136 is configured as an electrostatic chuck (ESC), and can be either a Coulombic type ESC or a Johnsen-Rahbek type ESC. Simplified equivalent circuit models 191 of the Coulombic type ESC and the Johnsen-Rahbek type ESC are shown in Figures 3D and 3E, respectively, and will be discussed later. In general, in any ESC configuration of the substrate support assembly 136, the substrate 103 is fixed to the substrate support 105 by applying a potential between the substrate 103 and the bias electrode 104, resulting in an electrostatic attraction force between them. In one embodiment, the bias electrode 104 is also used to facilitate the biasing scheme of the pulse voltage (PV) waveform described herein.

[0062]

[0071] The substrate support 105 is formed of a dielectric material and provides a substrate support surface 105A including a bias electrode 104 embedded in the dielectric material. The bias electrode 104 is spaced apart from the substrate support surface 105A and thus from the substrate 103 by a first dielectric material layer 105B, and from the support base 107 by a second dielectric material layer 105C.

[0063]

[0072] In some embodiments, the ESC configuration may be used to fix the substrate 103 to the substrate support 105 in a relatively low-pressure (e.g., ultra-high vacuum) processing environment. In some embodiments, it may be desirable to heat and / or cool the substrate 103 during processing to maintain the substrate at a desired processing temperature. In these embodiments, the substrate support assembly 136 may be configured to maintain the substrate 103 at a desired temperature by heating or cooling the substrate support 105 and, consequently, the substrate 103 placed thereon. Often, in these embodiments, the substrate support surface 105A is patterned to have a raised portion (e.g., a mesa) that contacts the substrate 103 and a recess that defines a back space 105D between the substrate 103 and the substrate 103. During substrate processing, a gas source 173 fluidly connected to the substrate support assembly 136 may be used to supply an inert gas, such as helium, to the back space 105D to increase heat transfer between the substrate support surface 105A and the substrate 103 placed thereon. In some embodiments, the gas source 173 is used to supply an inert gas to a region located between the edge ring 114 and the surface of the substrate support assembly 136 positioned beneath it.

[0064]

[0073] The bias electrode 104 is electrically connected to a DC power supply 155 (described above in FIGS. 1A - 1B), and this DC power supply 155 is configured to apply a potential between the substrate 103 and the bias electrode 104, and as a result, an electrostatic attraction force (chucking force) is generated therebetween. The substrate support assembly 136 can be configured as either a Coulomb-type ESC or a Johnson-Rahbek-type ESC. The Johnson-Rahbek-type ESC can provide a higher chucking force and use a lower chucking voltage compared to the Coulomb-type ESC. In the Coulomb-type ESC, the dielectric material selected for the first dielectric material layer 105B will typically have a higher electrical resistance than the dielectric material selected for the Johnson-Rahbek-type ESC. As a result, there are differences in the simplified functional equivalent circuit models 191 shown in FIGS. 3D and 3E, respectively.

[0065]

[0074] In the simplest case (e.g., the circuit model 191 of the Coulomb-type ESC shown in FIG. 3D), the first dielectric layer 105B is formed of a dielectric material (e.g., having an infinite resistance R JR assumed to function as an insulator). Thus, the functionally equivalent circuit model 191 includes a direct capacitance C1 between the bias electrode 104 and the substrate 103 through the first dielectric layer 105B. In some embodiments of the Coulomb-type ESC, the dielectric material and thickness T DL1 of the first dielectric material layer 105B are selected such that the capacitance C1 is between about 5 nF and about 100 nF, for example, between about 7 nF and about 20 nF. For example, the dielectric material layer 105B is formed of a ceramic material (e.g., aluminum oxide (Al2O3), etc.) and can have a thickness T DL1 between about 0.1 mm and about 1 mm, for example, between about 0.1 mm and about 0.5 mm, for example, about 0.3 mm.

[0066]

[0075] In a more complex case, as shown in the circuit model 191 of the Johnson-Rahbek-type ESC shown in FIG. 3E, the circuit model 191 includes a dielectric material resistance R JR and a gap capacitance C JRThis includes a capacitance C1 connected in parallel with the diode. Typically, in a Johnsen-Lahbeck type ESC, the dielectric material layer 105B is considered "leaky" in the sense that it is not a perfect insulator but has some conductivity. For example, the dielectric material can be doped aluminum nitride (AlN) with a dielectric constant (ε) of about 9. Similar to the circuit model 191 of the Coulomb type ESC shown in Figure 3D, capacitance C1 exists directly between the bias electrode 104 and the substrate 103 through the dielectric material layer 105B and the helium-filled back space 105D. The volume resistance of the dielectric layer in a Johnsen-Lahbeck type ESC is about 10 12 Less than ohms·cm (Ω·cm), or approximately 10 10 Less than Ω·cm, and even 10 8 Ω·cm and 10 12 It is within the range of Ω·cm. Therefore, the dielectric material layer 105B is 10 6 Ω and 10 11 Dielectric material resistance R in the range of Ω JR It may have. In Model 191 of Figure 3E, in order to consider the gas-containing back space 105D between the substrate 103 and the substrate support surface 105A, the gap volume C JR This is used. Gap volume C JR It is expected to have a capacity slightly larger than capacity C1.

[0067]

[0076] Returning to Figure 1C, the schematic electrical diagram of the circuit formed within the substrate support assembly 136 includes the support base dielectric layer capacitance C2, which represents the capacitance of the second dielectric material layer 105C. In some embodiments, the thickness of the portion of the second dielectric material layer 105C is greater than the thickness of the first dielectric material layer 105B. In some embodiments, the dielectric material used to form the dielectric layers on both sides of the bias electrode is the same material and forms the structural body of the substrate support 105. In one example, the thickness of the second dielectric material layer 105C (e.g., Al2O3 or AlN), measured in the direction extending between the support base 107 and the bias electrode 104, is greater than 1 mm, such as having a thickness between about 1.5 mm and about 100 mm. The support base dielectric layer capacitance C2 typically has a capacitance between about 0.5 nanofarads (nF) and about 10 nF.

[0068]

[0077] As shown in Figure 1C, the schematic electrical diagram of the circuit formed within the substrate support assembly 136 is also shown, along with the support base resistor R. P , insulating plate capacitance C3, and grounding plate resistance R connected to ground at one end. G This includes the support base 107 and the grounding plate 112, which are typically made of metal material, and the support base resistance R P and ground plate resistor R G This is very low, such as less than a few milliohms. The insulator plate capacitance C3 represents the capacitance of the dielectric layer located between the bottom surface of the support base 107 and the top surface of the grounding plate 112. In one example, the insulator plate capacitance C3 has a capacitance between approximately 0.1 nF and approximately 1 nF.

[0069] Bias and edge control scheme

[0078] Figure 2 is a simplified schematic diagram of a bias and edge control scheme that can be used with one or both of the processing systems 10A to 10B shown in Figures 1A and 1B. As shown in Figure 2, the RF generator 118 and the PV waveform generator 150 are configured to supply an RF waveform and a pulsed voltage waveform, respectively, to one or more electrodes located in the processing space 129 of the processing chamber 100. In one embodiment, the RF generator 118 and the PV waveform generator 150 are configured to supply an RF waveform and a pulsed voltage waveform simultaneously to one or more electrodes located in the substrate support assembly 136.

[0070]

[0079] As described above, the edge tuning circuit 170 is generally configured to control the uniformity of the plasma formed between the chamber lid 123 and the substrate support assembly 136, for example, by controlling the plasma density (i.e., the free electron density in the bulk plasma) across the outer edge of the substrate 103. In some embodiments, as shown in Figures 1A and 2, the edge tuning circuit 170 is electrically connected between the edge control electrode 115 (edge ​​bias electrode) and ground. In other embodiments, as shown by the dotted lines in Figures 1B and 2, the edge tuning circuit 170 is electrically connected between the edge control electrode 115 and the plasma generator assembly 163, for example, between the edge control electrode 115 and the RF generator 118.

[0071]

[0080] In some embodiments, the edge tuning circuit 170 is configured as a resonant circuit including an inductor and a capacitor (e.g., an LC circuit) that can be used to adjust the voltage, current, and / or phase of the RF power used to maintain plasma in the region on the edge control electrode. Exemplary electrical circuits 170a, 170b, and 170c that can be used as the edge tuning circuit 170 in any one of the embodiments described herein are illustrated in Figures 3A–3C. As illustrated, the edge tuning circuits 170a and 170b are each electrically connected between the power supply line 158 and ground (i.e., between the edge control electrode 115 and ground). However, each of the exemplary edge tuning circuits 170a and 170b may also be electrically connected between the power supply line 158 and the plasma generator assembly 163 (i.e., between the edge control electrode 115 and the RF generator 118), as shown in Figure 1B. In some other embodiments, the edge tuning circuit 170 may be electrically connected to the power supply line 158, the plasma generator assembly 163, and ground simultaneously, as shown for the exemplary edge tuning circuit 170c in Figure 3C.

[0072]

[0081] In one embodiment shown in Figure 3A, the edge tuning circuit 170a includes an inductor L2 and a variable capacitor C7 arranged in parallel (i.e., a parallel LC resonant circuit). In another embodiment shown in Figure 3B, the edge tuning circuit 170b includes an inductor L2 and a variable capacitor C7 arranged in series (i.e., a series LC resonant circuit). In another embodiment shown in Figure 3C, the edge tuning circuit 170c includes an inductor L2 and a variable capacitor C8 arranged in series between the edge control electrode 115 and the plasma generator assembly 163 (i.e., between the edge control electrode 115 and the RF generator 118) (i.e., a series LC resonant circuit), and a second variable capacitor C7 connected to a node located between the inductor L2 and variable capacitor C8 and ground in the power supply line 158.

[0073]

[0082] In some embodiments, one or both of the variable capacitors C7 and C8 are adjustable from at least about 50 pF to at least about 200 pF, for example, from at least about 20 pF to at least about 250 pF.

[0074]

[0083] The type of LC resonant circuit selected for the edge tuning circuit 170, such as parallel, series, or other configurations, may depend on the mechanical dimensions of the substrate support assembly 136 and the resulting electrical connections between conductive components or electrodes such as the edge ring 114, edge control electrode 115, support base 107, bias electrode 104, substrate 103, and ground plate 112.

[0075]

[0084] In some embodiments, the type of LC resonant circuit can be selected based on the desired ability to control the plasma density distribution, which can be achieved by tuning one or more parameters of the LC resonant circuit so that one or more characteristics of the second RF waveform 502 (Figures 5A-5B) established at the edge control electrode 115 can be tuned to one or more characteristics of the first RF waveform 501 established at the bias electrode 104. Simulation results of various control characteristics that can be achieved for an exemplary edge tuning circuit 170 are described below in Figures 6A-6D.

[0076]

[0085] Returning to Figure 2, in a non-limiting example, the RF generator 118 and the PV waveform generator 150 are configured to supply the RF waveform and pulse voltage waveform to the support base 107 and bias electrode 104 located in the substrate support assembly 136, respectively. In another embodiment, the RF generator 118, the first PV waveform generator 150, and the second PV waveform generator 150 are configured to supply the RF waveform, the first pulse voltage waveform, and the second pulse voltage waveform to the support base 107, bias electrode 104, and edge control electrode 115 located in the substrate support assembly 136, respectively.

[0077]

[0086] As shown in Figure 2, the RF generator 118 is configured to supply an RF signal to one or more electrodes located within the chamber body 113 by supplying a sinusoidal RF waveform (RF signal), including sinusoidal RF waveforms, here RF waveforms 501, 502 (Figures 5A-5B), through an RF (plasma) generator assembly 160, which includes an RF matching circuit 162 and a first filter assembly 161. Furthermore, each of the PV waveform generators 150 is configured to supply a PV waveform, typically including a series of voltage pulses (e.g., nanosecond voltage pulses), to one or more electrodes located within the chamber body 113 by establishing a PV waveform at the bias electrode 104 through a second filter assembly 151. Components within the clamping network 116 may optionally be placed between each PV waveform generator 150 and the second filter assembly 151.

[0078]

[0087] During processing, a PV waveform is supplied to the bias electrode 104 by the PV waveform generator 150 of the first bias generator 196, and a PV waveform is supplied to the edge control electrode 115 by the PV waveform generator 150 of the second bias generator 197. The PV waveform is supplied to a load located within the processing chamber 100 (for example, the composite load 130 shown in Figures 3D-3E). The PV waveform generators 150 are connected to the bias electrode 104 and the edge control electrode 115 through their respective power supply lines 157 and 158. The supply of PV waveforms from each of the PV waveform generators 150 is controlled using signals supplied by the system controller 126.

[0079]

[0088] In one embodiment, the PV waveform generator 150 is configured to output a periodic voltage function at predetermined time intervals, using a signal from, for example, a transistor-to-transistor logic (TTL) source (not shown). The periodic voltage function generated by the transistor-to-transistor logic (TTL) source may be two-state DC pulses between a predetermined negative or positive voltage and zero. In one embodiment, the PV waveform generator 150 is configured to maintain a predetermined substantially constant negative voltage across its output (i.e., relative to ground) while predetermined time intervals are periodically repeated, by repeatedly opening and closing one or more switches at a predetermined rate. In one embodiment, a first switch is used to connect a high-voltage power supply to the bias electrode 104 during a first phase of the pulse interval, and a second switch is used to connect the bias electrode 104 to ground during a second phase of the pulse interval. In another embodiment, the PV waveform generator 150 is configured to maintain a predetermined substantially constant positive voltage across its output (i.e., relative to ground) for a predetermined period of time intervals of a predetermined length by repeatedly opening and closing its internal switch (not shown) at a predetermined rate.

[0080]

[0089] In one configuration, a first switch is used to connect the bias electrode 104 to ground during the first phase of the pulse interval, and a second switch is used to connect the high-voltage power supply to the bias electrode 104 during the second phase of the pulse interval. In another configuration, during the first phase of the pulse interval, the bias electrode 104 is disconnected from the high-voltage power supply and the first switch is positioned open so that the bias electrode 104 is coupled to ground through an impedance network (e.g., an inductor and resistor connected in series). Then, during the second phase of the pulse interval, the first switch is positioned closed to connect the high-voltage source to the bias electrode 104, while the bias electrode 104 remains connected to ground through the impedance network.

[0081]

[0090] The PV waveform generator 150 may include, but is not limited to, a PV generator and one or more electrical components such as a high-repetition-rate switch (not shown), a capacitor (not shown), an inductor (not shown), a flyback diode (not shown), a power transistor (not shown), and / or a resistor (not shown) configured to supply the PV waveform to the output. An actual PV waveform generator 150 that can be configured as a nanosecond pulse generator may include any number of internal components.

[0082]

[0091] The power supply line 157 electrically connects the output of the PV waveform generator 150 of the first bias generator 196 to the optional filter assembly 151 and bias electrode 104. The following discussion will primarily describe the power supply line 157 of the first bias generator 196 used to connect the PV waveform generator 150 to the bias electrode 104, but the power supply line 158 of the second bias generator 197, which connects the PV waveform generator 150 to the edge control electrode 115, will also contain the same or similar components. One or more electrical conductors in the various parts of the power supply line 157 may include: (a) one or a combination of coaxial cables, such as a flexible coaxial cable connected in series with a rigid coaxial cable; (b) an insulated high-voltage corona-resistant hookup wire; (c) bare wire; (d) a metal rod; (e) an electrical connector; or (f) any combination of the electrical elements of (a) to (e). The optional filter assembly 151 includes one or more electrical elements configured to substantially prevent current generated by the output of the RF generator 118 from flowing through the power supply line 157 and damaging the PV waveform generator 150. The optional filter assembly 151 acts as a high impedance (e.g., high Z) to the RF signal generated by the RF generator 118, thereby suppressing the flow of current to the PV waveform generator 150.

[0083]

[0092] In some embodiments, as shown in Figures 1A-1B, the PV waveform generator 150 of the first bias generator 196 is configured to supply a pulsed voltage (PV) waveform signal to the bias electrode 104 and, consequently, the composite load 130 (Figures 3D-3E) by supplying the generated pulsed voltage (PV) waveform through a blocking capacitor C5, a filter assembly 151, a power supply line 157, and a capacitance C1 (Figure 1C). In some embodiments, the plasma control scheme 188 may further include a blocking resistor (not shown) located within a component connecting the clamping network 116 to a point in the power supply line 157. The primary function of the blocking capacitor C5 is to protect the PV waveform generator 150 from the DC voltage generated by the DC power supply 155, which drops across the blocking capacitor C5 and does not disturb the output of the PV waveform generator 150. The purpose of the blocking resistors in the clamping network 116 is to block the pulse voltage generated by the PV waveform generator 150 to a degree sufficient to minimize the current induced in the DC power supply 155.

[0084] Waveform example

[0093] Figure 4 shows an example of a PV waveform 402 established on the substrate 103 by a PV waveform 401 established on the bias electrode 104. Here, the PV waveform 401 is established on the bias electrode 104 and / or edge control electrode 115 by using the PV waveform generator 150 in the respective bias generators 196, 197 and the DC voltage source 155 of the corresponding clamping network 116.

[0085]

[0094] Generally, the output of the PV waveform generator 150, which can be controlled by the plasma processing recipe settings stored in the memory of the controller 126, forms a PV waveform 401 that includes a peak-to-peak voltage VPP, also known as the pulse voltage level Vpp.

[0086]

[0095] Waveform period T PThe PV waveform 402 having the above characteristics is the waveform seen by the substrate 103 for supplying the PV waveform 401 to the bias electrode 104, and is characterized as including a sheath collapse and recharge phase 450 (or, for simplicity of discussion, a sheath collapse phase 450) extending between points 420 and 421, a sheath formation phase 451 extending between points 421 and 422, and an ion current phase 452 extending between point 422 and the starting point of point 420 of the subsequently established pulse voltage waveform. The sheath collapse phase 450 generally includes a period in which the capacitance of the sheath is discharged and the substrate potential is brought to the level of the local plasma potential 433.

[0087]

[0096] Depending on the desired plasma processing conditions, the PV waveform frequency (1 / T) may be necessary to obtain the desired plasma processing results on the substrate. P It may be desirable to control and set at least the PV waveform characteristics, such as the pulse voltage level Vpp, pulse voltage on time, and / or other parameters of the PV waveform 401. In one embodiment, the pulse voltage (PV) on time is defined as the ratio of the ion current period (e.g., the time between point 422 and the next point 420 in Figure 4) to the waveform period Tp, and is greater than 50% or greater than 70%, for example, between 80% and 95%. In some embodiments, the PV waveform generator 150 is configured to supply a constant voltage during the ion current phase 452, as shown in Figure 4. In some embodiments, the PV waveform generator 150 is configured to provide a shaped pulse voltage waveform (not shown) with a non-zero slope during the ion current phase 452 by using one or more internal switches and a DC power supply. In some embodiments, the PV waveform generator 150 is configured to supply a constant positive voltage (not shown) during one of the phases of the voltage pulse, such as only during the sheath collapse phase 450. Generally, the DC offset ΔV observed in each PV waveform of the bias electrode depends on the bias applied by the DC power supply 155 of the clamping network 116 and the various characteristics of the configuration of the PV waveform generator 150 used to establish the PV waveform 401.

[0088]

[0097] In some embodiments, during the ion current phase 452, the ion current (Ii) deposits a positive charge on the substrate surface, so the voltage on the substrate surface increases over time, as seen by the positive slope of the line between points 422 and 420. This voltage increase over time on the substrate surface will decrease the sheath voltage and lead to a broadening of the ion energy distribution. Therefore, at least the PV waveform frequency (1 / T) PD ) controls and sets (where T PD (where is the PV waveform period), it is desirable to minimize the effects of sheath voltage reduction and ion energy distribution broadening.

[0089]

[0098] Figures 5A–5B show a first RF waveform 501 established at the bias electrode 104 and a second RF waveform 502 established at the edge control electrode 115, resulting from the capacitive coupling of the RF signal supplied to the support base 107 by the RF generator 118 in the plasma generator assembly 163. The waveform characteristics of the first RF waveform 501 and the second RF waveform 502 are controlled by using an edge tuning circuit 170 configuration, such as one of the configurations illustrated in Figure 3A (parallel LC resonant circuit), Figure 3B (series resonant circuit), and Figure 3C (more complex resonant circuit). The exemplary waveforms shown in Figures 5A–5B and the simulation results shown in Figures 6A–6D below are provided for the sake of simplicity of discussion and are not intended to limit the scope of the disclosure provided herein.

[0090]

[0099] Generally, the RF signals supplied to the support base 107 have relatively high frequencies, so the first RF waveform 501 and the second RF waveform 502 have corresponding high frequencies (1 / T) of about 1 MHz or more, for example, between about 30 MHz and about 60 MHz. RFThe edge tuning circuit 170, as described in various embodiments disclosed herein, may be used to tune one or more characteristics of a second RF waveform 502 established at the edge control electrode 115 to one or more characteristics of a first RF waveform 501 established at the bias electrode 104. In some embodiments, one or more relative characteristics are the RF waveform amplitude ratio (e.g., voltage amplitude ratio V) between the second RF waveform 502 and the first RF waveform 501. RF2 / V RF1 The RF current amplitude ratio between the second RF waveform 502 and the first RF waveform 501 (e.g., the current amplitude ratio is not shown), the phase difference (ΔΦ) between the second RF waveform 502 and the first RF waveform 501, and / or the RF supply power ratio between the second RF waveform 502 and the first RF waveform 501 (e.g., the supply power ratio is not shown).

[0091]

[0100] One or more characteristics of the second RF waveform 502 relative to the first RF waveform 501 can be determined and / or monitored by measuring the respective voltage, current, phase, and / or power of the RF waveforms established at the edge control electrode 115 and the bias electrode 104. The measured characteristics of the second RF waveform 502 and the first RF waveform 501 correspond to characteristics of the bulk plasma in the portion formed above the edge control electrode 115 and the bias electrode 104, such as plasma density. The difference determined between the second RF waveform 502 and the first RF waveform 501 can be used to monitor and control the difference between the electron density of the portion of bulk plasma formed on the edge ring 114 and the electron density of the portion of bulk plasma formed on the central portion of the substrate 103. The uniformity and / or distribution of plasma density can be controlled and / or adjusted to achieve the desired processing result by using the edge tuning circuit 170, such as by using the system controller 126 to adjust the variable capacitor C7.

[0092]

[0101] Figures 6A-6B show non-limiting simulation results for the edge tuning circuit 170 shown in Figures 3A and 3B, and Figures 6C-6D show simulation results for the edge tuning circuit 170 combining the series and parallel configurations shown in Figure 3C. In Figures 6A and 6C, the simulation results are obtained by changing the capacitance over a range of approximately 20pF to approximately 250pF (for example, the variable capacitor C of each edge tuning circuit 170 configuration). 7を (To adjust) the voltage amplitude ratio between the second RF waveform 502 and the first RF waveform 501 (for example, V RF2 / V RF1 This provides an example of an LC circuit tuning curve showing the effect on the second RF waveform 502 and the first RF waveform 501 (e.g., Φ). In Figures 6B and 6D, the simulation results show that changing the capacitance of C7 affects the phase difference (e.g., Φ) between the second RF waveform 502 and the first RF waveform 501. RF2 -Φ RF1 This provides an example of an LC circuit adjustment curve that shows the effect on ( ).

[0093]

[0102] As shown in Figure 6A, the variable capacitance C7 of the edge tuning circuit 170 (configuration shown in Figure 3A), which has a value of approximately 170 pF, corresponds to a voltage amplitude ratio (V) of approximately 1.5. RF2 / V RF1 ) has. As shown in Figure 6B, the phase difference corresponding to the 170pF capacitance of the edge tuning circuit 170, which has the same configuration as in Figure 6A, is relatively small, for example, less than 5 degrees. Therefore, as shown in Figure 6A, amplification of the second RF waveform 502 relative to the first RF waveform 501 occurs, and a small phase difference (ΔΦ) occurs between them.

[0094]

[0103] In Figures 6C-6D, the variable capacitance C7 of the edge tuning circuit 170 (configuration as shown in Figure 3C) can be set to a value of approximately 25pF. As a result, the voltage amplitude ratio (V RF2 / V RF1 ) is approximately equal to 0.5 (Figure 6C), and the phase difference (ΔΦ) is approximately zero (about null), as shown in Figure 6D.

[0095]

[0104] As shown in Figure 6A, the simulation results based on the configuration of the edge tuning circuit 170 in Figure 3A (e.g., a parallel LC resonant circuit) show resonance peaks at approximately 100pF and 120pF. In Figure 6D, the simulation results for the edge tuning circuit 170 (configuration in Figure 3C) show resonance phase transitions at 60pF and 250pF. In some embodiments, it may be desirable to operate each edge tuning circuit 170 on either side of the resonance during the period in which the RF plasma is maintained. In some embodiments, the edge tuning circuit 170 may be configured to allow switching operation of the edge tuning circuit 170 between either side of a resonance peak without crossing the resonance region, for example, by using a variable capacitor combining parallel and series LC circuits. As stated above, the simulation results shown in Figures 6A to 6D are not intended to be limiting, because the voltage amplitude ratio (V RF2 / V RF1 Other configurations of the edge tuning circuit 170 may be used to provide other desired operating ranges for amplifying, reducing, and / or equalizing the current amplitude ratio and / or the phase difference between the second RF waveform 502 and the first RF waveform 501.

[0096]

[0105] In some embodiments, it may be desirable to select a tuning circuit configuration and / or variable capacitor C7 that creates a phase difference between the respective RF waveforms, thereby amplifying the electric field between the edge control electrode 115 and the bias electrode 104. The amplified electric field results in a corresponding increase in plasma density in the portion of the plasma 101 formed on the substrate support assembly 136 at a certain distance between the two electrodes. In some embodiments, it may be desirable to select a tuning circuit configuration and / or variable capacitor C7 that does not create a phase difference between the RF waveforms established at each electrode, so that the plasma density remains substantially uniform over the region extending to the edge of the substrate 103.

[0097]

[0106] Beneficially, the edge tuning circuit 170 may be configured to provide a wide range of desired plasma processing conditions in order to control and / or adjust the plasma density distribution at different points between the center and edges of the substrate 103. The characteristics of the edge tuning circuit 170, and thus the position of the system on the tuning curve (Figures 6A-6D), may be controlled by adjusting one or more variable capacitors C7 using the system controller 126. Controlled adjustment of the characteristics of the edge tuning circuit by the system controller 126 will make it possible to change plasma processing conditions relatively easily within a single substrate plasma process, between successive substrate plasma processes, and / or for different types of substrates, without the need to manually change hardware-related configurations. In some embodiments, one or both of the bias generators 196, 197, the edge tuning circuit 170, or a combination thereof may be used to preferentially clean the surface of the substrate support assembly 136 within the edge pocket region 117 during field plasma cleaning methods such as those described below in relation to Figures 7A-7C and 8A-8C.

[0098]

[0107] In some embodiments, the edge tuning circuit 170 is automatically adjusted to maintain desired processing conditions, such as taking into account plasma uniformity drift due to changes in the shape dimensions and / or material of various components of the processing chamber 100 over time. For example, this method may be used to automatically adjust the tuning circuit by changing the capacitance C7, for example, to account for changes in the thickness of the edge ring 114 that may be caused by erosion of the dielectric material from the edge ring 114 due to ion collisions. For example, in some embodiments, the system controller 126 may be configured to use a signal detection module 187 to detect signals of one or more electrical parameters at corresponding nodes N of the processing systems 10A, 10B, and to determine whether the processing systems 10A, 10B are operating within desired processing conditions by comparing the characteristics of the detected signals with one or more control limits, and to adjust one or more components of the edge tuning circuit 170 if the electrical signal characteristics are outside the control limits. Some embodiments include automatically adjusting the edge tuning circuit, such as adjusting the capacitance C7, to maintain a desired RF voltage amplitude ratio, RF current amplitude ratio, and / or RF phase difference between different RF waveforms at the edge control electrode 115 and the bias electrode 104.

[0099]

[0108] In some embodiments, the system controller 126 is configured to compare one or more processing conditions and / or RF waveforms with predetermined limits, such as control limits, and to automatically adjust the edge tuning circuit 170 based on desired processing conditions and / or desired characteristics between the RF waveforms of the edge control electrode 115 and the bias electrode 104 by changing one or more setpoints, such as the capacitance C7 of the edge tuning circuit 170, based on an algorithm or lookup table stored in the memory 134 of the system controller 126.

[0100]

[0109] In some embodiments, the edge tuning circuit 170 may be manually tuned and / or controlled by adjusting one or more components of the edge tuning circuit 170 to a desired setpoint and / or within a desired control limit. A list of desired setpoints and / or control limits is selected by the user and stored in the instructions used to control the processing systems 10A, 10B. For example, the capacitance C7 of the edge tuning circuit 170 may be determined by the user and controlled to a desired capacitance stored in the memory of the system controller 126.

[0101]

[0110] Generally, pulse voltage (PV) waveforms established on electrodes 104 and 115, such as negative pulse waveform 401, shaped pulse waveform 441, or positive pulse waveform 431, have a voltage offset (ΔV) and a period T. PD It includes a periodic series of pulse voltage (PV) waveforms that repeat over time. In one example, the period T of the PV waveform is PD This can be between approximately 1 μs and approximately 5 μs, for example, approximately 2.5 μs, for example, between approximately 200 kHz and approximately 1 MHz, or approximately 400 kHz, for example, approximately 1 MHz or less, or approximately 500 kHz or less.

[0102]

[0111] As described above, in some embodiments, the processing chamber 100 includes at least one or more RF generators 118 and a first filter assembly 161 associated therewith, and one or more PV generators 314 and a second filter assembly 151 associated therewith, which together are configured to supply a desired waveform to one or more electrodes located within a substrate support assembly 136. Software instructions stored in the memory of the system controller 126 are configured to generate RF waveforms configured to establish, maintain, and control one or more aspects of the plasma formed within the processing chamber. One or more aspects of the controlled plasma may include, but are not limited to, the plasma density, plasma chemistry, and ion energy in the plasma formed within the processing space 129.

[0103] Examples of processing methods

[0112] Figures 7A–7C are process flow diagrams illustrating the respective methods that can be used to clean processing by-products from the surface of a substrate support assembly. Figures 8A–8C are close-up views of a substrate support assembly 136 used to illustrate embodiments of the methods described in Figures 7A–7C. In Figures 8A–8C, a portion of the substrate support assembly 136 is configured as shown in Figure 1B, with the edge control electrode 115 positioned in or on the material of the dielectric tube 110 surrounding the substrate support 105. However, the methods described below are intended to be used with any one or a combination of the substrate support assembly configurations described herein, such as when the edge control electrode 115 is positioned in the dielectric material of the substrate support 105 (Figures 1A, 1D), or within the edge ring 114, and / or connected to the edge ring 114.

[0104]

[0113] Figure 7A is a process flow diagram showing a method 700 for preferentially cleaning the surface defining the edge pocket region 117 of a substrate support assembly 136, according to one embodiment. Figures 1A-1D and 8A are referenced in the following description to illustrate aspects of method 700, but are not intended to limit them, for method 700 is intended to be performed in other processing systems configured to bias the substrate and edge ring separately. Generally, method 700 uses in-situ plasma (plasma formed in the processing chamber 100) to remove processing by-products accumulated from the edge ring 114 and / or adjacent portions of the substrate support surface 105A. Method 700 is used to manipulate the shape of the plasma sheath boundary 11 (Figure 8A) formed on the substrate support assembly 136 by increasing or decreasing the voltage between the edge ring 114 and the plasma relative to the voltage between the substrate support surface 105A and the plasma 101. The voltage difference creates a corresponding difference in ion energy at surfaces 114A-C and 105A, resulting in a bend in the plasma sheath boundary, which in some embodiments can be advantageously used to preferentially direct plasma-generated ions toward a desired portion of the substrate support assembly 136. For example, as shown in Figure 8A, the difference in height between a portion 11A of the sheath boundary 11 formed on the substrate support surface 105A and a portion 11C of the sheath boundary 11 formed on the edge ring 114 causes the sheath boundary to bend in the portion spanning the edge pocket region 117 (bent portion 11B).

[0105]

[0114] In step 702, method 700 includes generating a first plasma in a processing area of ​​a processing chamber, the processing chamber 100 may include any one or a combination of the features illustrated in Figures 1A to 1D, where the processing area 129A is defined by a chamber lid 123 and a substrate support assembly 136. Referring here to Figure 8A, the substrate support assembly 136 generally includes a first portion of dielectric material 105B that forms a substrate support surface 105A and an edge ring 114 that surrounds the substrate 103 (shown by a dotted line) when the substrate 103 is placed on the substrate support surface 105A. One or more edge pocket surfaces 114A, B of the edge ring 114 and the outer peripheral edge of the first portion 105B of the dielectric material define an edge pocket area 117 where the edge pocket surfaces 114A, B are located inside the chamber lid-facing surface 114C.

[0106]

[0115] In some embodiments, the substrate support assembly 136 further includes a bias electrode 104 positioned at a distance from the substrate support surface 105A by a first portion 105B of dielectric material, and an edge control electrode 115 positioned at a distance from the center of the bias electrode 104. Generally, the edge control electrode 115 is positioned at a distance from the bias electrode 104 by the dielectric material of the substrate support assembly 136, which may include the dielectric material of the substrate support 105, the dielectric material used to form the dielectric tube 110, the dielectric material of the edge ring 114 in which the edge control electrode 115 is embedded, or a combination thereof. Here, the bias electrode 104 is electrically connected to a first bias generator 196 configured to establish a first pulse voltage (PV) waveform at the bias electrode 104. The edge control electrode 115 is electrically connected to a second bias generator 197 configured to establish a second pulse voltage (PV) waveform at the edge control electrode 115.

[0107]

[0116] In some embodiments, the first plasma generated in step 702 is a capacitively coupled plasma (CCP) generated using a high-frequency (RF) signal from an RF waveform generator 163 electrically connected to a substrate support assembly 136, such as being electrically connected to a support base 107, in which case the chamber lid 123 is electrically connected to ground (as shown) or to a second RF generator. In other embodiments (not shown), the first plasma may be a CCP formed using an RF generator electrically connected to the chamber lid 123, in which case the substrate support assembly 136 is electrically connected to ground. In other embodiments, the first plasma may be an inductively coupled plasma (ICP) formed using an RF generator electrically connected to one or more ICP coils (not shown) located on the chamber lid 123.

[0108]

[0117] In some embodiments, the RF signal used to generate the first plasma has a frequency greater than about 400 kHz, for example, about 1 MHz or more, or about 2 MHz or more, for example, about 13.56 MHz or more, about 27 MHz or more, about 40 MHz or more, or for example, between about 30 MHz and about 200 MHz, for example, between about 30 MHz and about 160 MHz, between about 30 MHz and about 120 MHz, or between about 30 MHz and about 60 MHz.

[0109]

[0118] In step 704, the method includes exposing the edge ring 114 and the substrate support surface 105A to a first plasma. In some embodiments, the first plasma is formed from an oxygen-containing gas, a hydrogen-containing gas, a halogen-containing gas such as a fluorine and / or chlorine-based gas, or a combination thereof. In some embodiments, radical species generated in the plasma react with processing byproducts accumulated on surfaces in the processing space 129, such as the surfaces 114A-C of the edge ring 114. The reaction forms volatile substances which are discharged from the processing space 129 through a vacuum outlet 120. In some embodiments, the first time with the RF plasma can be about 1 second or more, for example, about 5 seconds or more, or about 10 seconds or more.

[0110]

[0119] In step 706 of method 700, the plasma sheath boundary of the first plasma over the edge pocket region is adjusted by tuning the variable capacitors C7 and / or C8 in the edge tuning circuit 170 and / or by establishing a pulse voltage (PV) waveform at the edge control electrode 115 to supply a voltage greater than that between the bulk plasma and the substrate support surface 105A between the bulk plasma and the edge ring 114.

[0111]

[0120] In some embodiments, the second pulse voltage (PV) waveform established at the edge control electrode during step 706 comprises a series of repeating cycles in which the voltage waveform within each cycle has a first portion occurring during a first time interval (e.g., sheath collapse phase 452) and a second portion occurring during a second time interval (e.g., sheath formation phase 451 and ion current phase 452). Generally, the voltage during the first interval is different from the voltage during the second interval, and the difference between these voltages determines the energy of the ions accelerated across the sheath to the edge ring 114.

[0112]

[0121] In some embodiments, the voltage established on the bias electrode by the first pulsed voltage (PV) waveform generator 150 (here, the bias voltage) is maintained at zero volts VPP (e.g., about 0 volts ± 1 volt (zero (null) volt)) for at least several repeating cycles of the second PV waveform established on the edge control electrode 115 in step 704. For example, in some embodiments, the second PV waveform may be established on the edge control electrode 115 at a non-zero VPP. The pulsed voltage VPP established on the bias electrode using the first PV waveform generator may be maintained at zero volts (e.g., about 0 volts ± 1 volt (zero (null) volt)) for about 1 second or longer, for example, about 5 seconds or longer, or about 10 seconds or longer. In some embodiments, the bias electrode 104 is connected to ground for the first period by using a switch connected between the power supply line 157 and ground. In another embodiment, the bias voltage may be driven to zero volts (null volt) using the PV waveform generator 150 or another driver (not shown).

[0113]

[0122] In some embodiments, as shown in Figure 8A, steps 702, 704, and 706 are performed without the substrate 103 (shown by the dotted line) so that the substrate support surface 105A is exposed to the first plasma. Beneficially, the plasma sheath boundary 11 bends at portion 11B due to the potential difference between the portion of plasma formed on the substrate support surface 105A and the portion of plasma formed on the edge ring 114. The shape of the plasma sheath boundary shown in Figure 8A is configured to preferentially direct plasma-generated ions based on the formed bend 11B toward the edge pocket surface 114A-B. By directing plasma-generated ions toward the edge pocket surface 114A-B and simultaneously reducing the voltage between the plasma and the substrate support surface 105A, method 700 can be used to preferentially clean the surface of the edge ring 114 while substantially reducing undesirable plasma-based erosion of the substrate support 105.

[0114]

[0123] In some embodiments, Method 700 optionally includes processing the substrate 103 using a second plasma formed before or after the priority cleaning steps described in steps 702-706. For example, Method 700 may optionally include positioning the substrate 103 on the substrate support surface 105A in step 708, generating a second plasma within the processing area 129A in step 710, exposing the substrate 103 to the second plasma for a second time in step 712, and establishing a first pulsed voltage (PV) waveform on the bias electrode 104 in step 714. In some embodiments, the substrate 103 used to perform the optional steps 708-714 of Method 700 is a non-production substrate. That is, the substrate is of a type commonly referred to as a “blanket” or “dummy” wafer, used to perform cleaning, testing, and / or maintenance operations.

[0115]

[0124] In some embodiments, step 708 of method 700 further includes electrostatically clamping the substrate 103 to the substrate support 105 by supplying a chucking voltage to the bias electrode 104 from a DC power supply 155 electrically connected to the bias electrode 104 using a power supply line 157. The chucking voltage is used to create a voltage potential difference between the substrate 103 and the bias electrode 104, thereby generating an electrostatic attractive force (chucking force) through the capacitance C1 (Figure 1C) of a first portion of dielectric material placed between them. In some embodiments, method 700 further includes electrostatically clamping the edge ring 114 to the substrate support assembly 136 by supplying a chucking voltage to the edge control electrode 115 from a DC power supply 155 electrically connected to the edge control electrode 115 using a power supply line 158. In some embodiments, the method 700 includes introducing an inert gas (e.g., helium) into the back space 105D (Figure 1D) located between the substrate 103 and the substrate support surface 105A and / or between the edge ring 114 and the surface of the substrate support assembly 136 to facilitate heat transfer between them.

[0116]

[0125] In some embodiments, step 714 of method 700 further includes adjusting one or more characteristics of a second pulse voltage (PV) waveform to one or more characteristics of a first pulse voltage (PV) waveform in order to control the shape of the plasma sheath boundary 11 formed on the substrate 103 and edge ring 114 during the second period. Thus, in some embodiments, step 714 includes adjusting one or more characteristics of the first PV waveform established at bias electrode 104 to one or more characteristics of the second PV waveform established at edge control electrode 115. In some embodiments, adjusting one or more characteristics involves adjusting the PV waveform frequencies (1 / T) of the first and / or second PV waveforms established at bias electrode 104 and edge control electrode 115, respectively. P This includes adjusting one or a combination of the pulse voltage level Vpp and the pulse voltage on time. In some embodiments, one or more characteristics may be controlled to increase or decrease the sheath height on the edge control electrode 115 relative to the sheath height on the bias electrode 104, thereby bending the plasma sheath at the substrate edge or the edge of the substrate support 105 to allow fine-tuning of ion orbitals and ion energy in the edge region of the substrate 103 or substrate support 105.

[0117]

[0126] Figure 7B is a process flow diagram showing a method 720 for preferentially cleaning a surface defining an edge pocket region 117 of a substrate support assembly 136, according to one embodiment. An embodiment of method 720 is schematically shown in Figure 8B. However, method 720 is intended to be performed using any of the processing system configurations described in Figures 1A to 1D. In some embodiments, the substrate 103 is a non-production substrate; that is, the substrate is of a type used to perform cleaning, testing, and / or maintenance operations, commonly referred to as a “blanket” or “dummy” wafer. In other embodiments, method 720 may be performed during plasma processing of a manufacturing substrate having at least partially formed semiconductor devices thereon, for example, to remove processing by-product residues from the beveled edges or back edges of the manufacturing substrate.

[0118]

[0127] Here, Method 720 generally involves preferentially cleaning the surface defining the edge pocket region 117 by adjusting the characteristics of the respective pulse voltage (PV) waveforms established by the bias electrode 104 and the edge control electrode 115. During the cleaning process, the substrate 103 remains on the substrate support surface 105A so that the substrate 103 is positioned between the substrate support surface 105A and the plasma. The substrate 103 acts as a cover to prevent ion collisions and erosion of the substrate support surface 105A. In some embodiments, the substrate 103 is at least partially lifted from the substrate support surface 105A so that radical species formed in and / or within the plasma can more easily diffuse into the edge pocket region 117 and react with processing byproducts (e.g., carbon-containing polymers) formed on the surface therein. At least some of the steps of Method 720 are intended to be identical or substantially similar to the corresponding steps of Method 700 described above.

[0119]

[0128] Method 720 generally includes positioning the substrate 103 on the substrate support assembly 136 in step 722, generating plasma in step 724 so that the substrate 103 and edge ring 114 are (optionally) exposed to the plasma for a first period in step 726, and optionally adjusting the plasma sheath boundary by biasing one or both of the substrate 103 and edge ring 114 in step 728.

[0120]

[0129] Positioning the substrate 103 in step 722 generally involves transferring the substrate 103 to the substrate support surface 105A. In some embodiments, the substrate is electrically clamped to a substrate support assembly, as described in step 708 of method 700. Plasma may be generated in step 724 using RF signals as described above in steps 702 and / or 710 of method 700.

[0121]

[0130] In some embodiments, the substrate 103 is optionally exposed to plasma for a first period in step 728. The substrate 103 and edge ring 114 are optionally biased by using first and second pulsed voltage waveform generators to establish PV waveforms at the bias electrode and edge control electrode, for example, as described in steps 712 and 714 of method 700.

[0122]

[0131] In step 730, method 720 includes lifting the substrate 103 at least partially from the substrate support surface 105A, as shown in Figure 8B. Typically, the substrate 103 is lifted at least partially from the substrate support surface 105A using a plurality of lift pins 20 extending through the substrate support assembly 136. If the substrate is electrostatically clamped to the substrate support 105 as described in step 708, lifting the substrate 103 at least partially may include stopping or adjusting the supply of a chucking voltage to the bias electrode 104 and / or discharging static charge between the substrate 103 and the bias electrode 104, for example, by setting the DC voltage potential of the bias electrode 104 to be similar to the DC voltage potential of the substrate 103.

[0123]

[0132] In steps 732 and 734, method 720 includes exposing the edge pocket surfaces 114A and 114B to plasma and simultaneously adjusting the plasma sheath boundary 11. Steps 732 and 734 may be performed using substantially the same processes as those used to perform steps 704 and 706 of method 700, with the addition of a partially lifted substrate 103 positioned on the substrate support surface 105A. It is intended that one or more steps of method 720 may be used in combination with method 740, or vice versa, to enhance the efficiency of in-situ plasma cleaning in the edge pocket region 117 while protecting the substrate support surface 105A from undesirable plasma-based erosion.

[0124]

[0133] Figure 7C is a process flow diagram showing a method 740 for preferentially cleaning the edge pocket surfaces 114A-B of a substrate support assembly 136 according to another embodiment. Method 740 is intended to be performed using any of the processing systems described herein, such as any one of the substrate support assemblies 136 in Figures 1A-1D and Figures 8A-8C. As shown in Figure 8C, Method 740 generally involves using a tuning circuit 170 to concentrate plasma between the outer peripheral edge of the substrate 103, which is at least partially lifted from the substrate support surface 105A, and the edge pocket surfaces 114A-B, e.g., the edge pocket region 117. The concentrated plasma increases the radical and ion concentration in the edge pocket region 117, which can be used to preferentially clean the surfaces 114A-B within it. Typically, the substrate 103 is partially lifted only to a distance small enough to prevent plasma from forming between the substrate 103 and the substrate support surface 105A, thus preventing plasma-based erosion. In some embodiments, the substrate 103 is a non-production substrate, commonly referred to as a “blanket” or “dummy” wafer. In other embodiments, method 740 may be performed during plasma processing of a manufacturing substrate having a semiconductor device at least partially formed thereon, for example, to remove processing by-product residues from the beveled edges or back edges of the manufacturing substrate.

[0125]

[0134] Step 742 of Method 740 includes positioning the substrate 103 on the substrate support surface 105A of the substrate support assembly 136 as shown in Figure 8C. Step 742 may be identical to or substantially similar to step 722 of Method 720.

[0126]

[0135] Step 744 of Method 740 includes igniting and maintaining a plasma by using a radio frequency (RF) signal. In some embodiments, the RF signal is supplied to the support base 107 of the substrate support assembly 136 using an electrically connected plasma generator assembly 163. Here, the RF signal is configured to ignite and / or maintain a processing plasma 101 in a processing area 129A of the processing chamber 100. The processing area 129A is located between the substrate support assembly 136 and the chamber lid 123. In some embodiments, the RF signal has a frequency of about 1 MHz or more, for example, about 20 MHz or more, for example, between about 30 MHz and about 60 MHz, or about 40 MHz.

[0127]

[0136] Typically, the RF signal supplied to the support base 107 establishes a first RF waveform 501 (Figures 6A-6B) at the bias electrode 104. This bias electrode 104 is capacitively coupled to the support base 107 through a third portion of dielectric material (e.g., dielectric material layer 105C) positioned between them. The bias electrode 104 is spaced apart from the processing plasma by the first portion of dielectric material (e.g., dielectric material layer 105B), and the substrate 103 is positioned on the substrate support surface 105A. In some embodiments, method 740 further includes electrostatically clamping the substrate 103 to the substrate support 105, as described in step 708 of method 700.

[0128]

[0137] In step 746, method 740 includes exposing the surface of the substrate 103 to the plasma for a first period of time. Step 748 of method 740 optionally includes adjusting one or both of the plasma density and / or the shape of the plasma sheath boundary 11. In some embodiments, adjusting the plasma density includes adjusting one or more characteristics of the second RF waveform 502 established at the edge control electrode 115 with respect to one or more characteristics of the first RF waveform 501 established at the bias electrode 104. In some embodiments, adjusting one or more characteristics of the second RF waveform 502 with respect to one or more characteristics of the first RF waveform 501 is the voltage amplitude ratio (e.g., V) between the second RF waveform 502 and the first RF waveform 501, as shown in Figure 5A or Figure 5B. RF2 / V RF1 This includes changing the current amplitude ratio between the second RF waveform 502 and the first RF waveform, adjusting the phase difference (e.g., delta Φ) between the second RF waveform 502 and the first RF waveform 501, or a combination thereof. In some embodiments, adjusting one or more characteristics of the second RF waveform 502 relative to the first RF waveform 501 is performed by adjusting the electrical characteristics of one or more elements in the edge tuning circuit 170.

[0129]

[0138] In some embodiments, adjusting the second RF waveform 502 relative to the first RF waveform 501 alters the plasma uniformity over at least a portion of the processing region 129A (Figures 1A-1B). For example, in one embodiment, the processing region 129A is defined by a chamber lid 123 and a substrate support assembly 136, and the plasma 101 is the bulk plasma formed between them. In some embodiments, the first portion of the plasma 101 is formed in the region located between the chamber lid 123 and the bias electrode 104. The second portion of the plasma 101 is formed in the region located between the chamber lid 123 and the edge control electrode 115. In those embodiments, adjusting the second RF waveform 502 relative to the first RF waveform 501 alters the plasma density in the second portion of the plasma 101 relative to the plasma density in the first portion of the plasma 101.

[0130]

[0139] In some embodiments, adjusting one or more characteristics of a second RF waveform 502 established at the edge control electrode 115 to one or more characteristics of a first RF waveform 501 established at the bias electrode 104 involves using an edge tuning circuit 170. In some embodiments, the edge tuning circuit 170 includes one or more variable capacitors C7, C8, and adjusting one or more characteristics of the second RF waveform 502 to one or more characteristics of the first RF waveform 501 involves changing one or more capacitors C7, C8. The adjustment of the edge tuning circuit 170 may be performed automatically by a system controller 126 to adjust the electrical characteristics of one or more components of the edge tuning circuit 170, such as capacitors C7, C8, based on desired characteristics of the RF waveforms 501, 502 and / or a desired difference between them.

[0131]

[0140] For example, in some embodiments, the system controller 126 may be configured to determine the characteristics of each waveform by measuring one or more characteristics of electrical signals taken at one or more nodes N using a signal detection module 187, compare the determined characteristics with a desired characteristic, and change the output of the components of the edge tuning circuit 170 based on the comparison. In some embodiments, the edge tuning circuit 170 may be manually tuned when a user changes the setpoint of a component of the edge tuning circuit 170, such as the capacitance of variable capacitors C7, C8 or the inductance L of the circuit. The user may change the setpoint by using the system controller 126 and / or the signal detection module 187 to change, for example, a recipe parameter corresponding to a component or another setting in an instruction used by the system controller 126 to operate processing systems 10A, 10B.

[0132]

[0141] Generally, assuming that a relatively constant RF power is supplied from the plasma generator assembly 163 to the support base 107, the V due to the use of the edge tuning circuit 170 RF2 / V RF1 An increase in the ratio results in an increase in the ratio of plasma density near the substrate edge to plasma density near the center of the substrate. The relative increase in plasma density leads to a corresponding increase in plasma-generated species in the bulk plasma, resulting in a relative increase in ion flux and reactive neutral molecule concentration at the substrate surface edge below. Similarly, V RF2 / V RF1 As the ratio decreases, the ratio of plasma density near the substrate edge to plasma density near the substrate center decreases, and the ion flux and reactive neutral molecule concentration at the substrate edge decrease accordingly.

[0133]

[0142] By controlling the relative plasma density between the first and second portions of the plasma, the corresponding distribution of active species within the processing region 129A is also controlled and can be used to improve overall processing non-uniformity, such as in-wafer processing non-uniformity. Advantageously, step 748 may be carried out as processing parameter adjustment, such as by controlling the edge tuning circuit 170 using the system controller 126 and adjusting capacities C7 and / or C8. Thus, method 740 can be carried out without relying on mechanical adjustments or hardware configuration changes, which are typically required to adjust the bulk plasma distribution in a capacitively coupled plasma (CCP) system and therefore hinder its fine control.

[0134]

[0143] Step 750 of Method 700 optionally includes biasing the substrate 103 and / or edge ring 114 by establishing a pulse voltage (PV) waveform in one or both of the bias electrode 104 and the edge control electrode 115. The process used to bias the substrate 103 and / or edge ring 114 during the first period may be the same as or substantially similar to the process described in step 714 of Method 700.

[0135]

[0144] Step 752 of Method 740 includes lifting the substrate at least partially from the substrate support surface 105A, which may be performed using the same or substantially similar process as described in Step 830 of Method 720. In Step 754, Method 740 includes exposing the edge pocket surfaces 114A-B to plasma for a period of time.

[0136]

[0145] Prior to or during steps 752 and 754, step 756 of method 740 includes adjusting one or more characteristics of the high-frequency (RF) waveforms established at the bias electrode 104 and the edge control electrode 115, respectively, to form plasma in the edge pocket region 117 for at least a portion of the period. In some embodiments, adjusting one or more characteristics of the RF waveforms includes adjusting the phase difference (e.g., delta Φ) between a second RF waveform 502 and a first RF waveform 501 so that plasma is formed between the outer edge of the substrate 103 and the edge pocket surfaces 114A-B. Here, the substrate is lifted at least partially to provide a gap or space between the substrate and the edge pocket surfaces 114A-B that is sufficient for plasma to form, while maintaining a gap between the substrate and the substrate support surface 105A that is small enough to prevent plasma from forming. In some embodiments, the bias voltages established on the bias electrode 104 and the edge control electrode 115, respectively, using an electrically connected waveform generator 150, are maintained at a constant or zero value for at least a portion of the period. For example, in some embodiments, the bias voltage established on one or both of the bias electrode 104 and the edge control electrode 115 is maintained at zero volts VPP (e.g., about 0 volts ± 1 volt (null volt)) for at least a portion of the period, such as about 1 second or more, about 5 seconds or more, or about 10 seconds or more. Maintaining the bias voltage at zero volts VPP may include connecting each electrode to ground, or using the PV waveform generator 150 or another driver (not shown) to drive the bias voltage to zero volts, as described in relation to Figure 7A for method 700.

[0137]

[0146] In some embodiments, method 740 further includes preferentially adjusting the plasma density toward the portion of plasma 101 formed on the edge control electrode 115 relative to the plasma density of the portion of plasma formed on the bias electrode 104. Here, preferentially adjusting the plasma density means adjusting the voltage amplitude ratio (e.g., V) between the second RF waveform 502 and the first RF waveform 501, as shown in Figure 6A or Figure 6B.RF2 / V RF1 This includes changing the current amplitude ratio between the second RF waveform 502 and the first RF waveform, adjusting the phase difference (e.g., delta Φ) between the second RF waveform 502 and the first RF waveform 501, or a combination thereof.

[0138]

[0147] The embodiments described above can be used alone or in combination to provide fine control over the generation and distribution of active species within the processing area of ​​an inductively coupled plasma (ICP) chamber or a capacitively coupled plasma (CCP) chamber. Beneficially, these embodiments can be implemented using a system controller without adjusting or modifying individual chamber components. Thus, easily adjustable processing recipe parameters are provided for processing a single substrate and / or between continuously processed substrates. RF plasma density control methods can be implemented independently and / or in combination with pulsed voltage (PV) waveform biasing methods to independently and finely control ion energy, IEDF, ion directionality, ion flux, and the concentration of reactive neutral molecules on the substrate surface, compared to conventional RF biased CCP systems.

[0139]

[0148] While the above description applies to embodiments of the present disclosure, other embodiments and additional embodiments of the present disclosure may be devised without departing from the basic scope of the present disclosure. The scope of the present disclosure is determined by the following claims.

Claims

1. A processing and cleaning method, Ignition and maintenance of plasma from cleaning gas or vapor supplied to a processing area defined by the chamber lid and the substrate support assembly facing the chamber lid, To partially lift the substrate above the substrate support assembly and Includes, The substrate support assembly is A first portion of the dielectric material forming the substrate support surface, A first electrode separated from the substrate support surface by the first portion of the dielectric material, An edge ring surrounding the substrate support surface, having one or more edge pocket surfaces that define an edge pocket region together with the outer peripheral edge of the substrate which is partially lifted and placed on the substrate support surface, A second electrode separated from the edge ring by the second portion of the dielectric material and Equipped with, The substrate support assembly is electrically connected to an RF generator that supplies a radio frequency (RF) signal used to ignite and maintain the plasma. The RF signal establishes a first RF waveform at the first electrode and a second RF waveform at the second electrode. The second electrode is electrically connected to an edge tuning circuit configured to control the uniformity of the plasma density within the processing region by adjusting one or more characteristics of the second RF waveform relative to the first RF waveform. At least one characteristic of the second RF waveform is different from the characteristics of the first RF waveform, The above method further, Exposing one or more edge pocket surfaces to the plasma Methods that include...

2. The method according to claim 1, wherein the different at least one characteristic includes a phase difference between the second RF waveform and the first RF waveform.

3. The method according to claim 2, wherein the phase difference between the second RF waveform and the first RF waveform results in an increase in plasma density in the edge pocket region.

4. The method according to claim 1, wherein the edge tuning circuit includes one or more variable capacitors.

5. The method according to claim 4, wherein the edge tuning circuit is electrically connected between the second electrode and ground.

6. The method according to claim 4, wherein the edge tuning circuit is electrically connected between the second electrode and the RF generator.

7. The method according to claim 4, wherein the edge tuning circuit is electrically connected to the second electrode, ground, and RF generator.

8. The method according to claim 1, wherein the substrate support assembly comprises a support base, the RF signal is supplied to the support base, and the first electrode is capacitively coupled to the support base via the second portion of the dielectric material disposed between the support base and the first electrode.

9. The method according to claim 8, wherein the first electrode is electrically connected to a first bias generator configured to establish a first pulse voltage (PV) waveform at the first electrode during substrate processing.

10. The method according to claim 9, wherein the second electrode is electrically connected to a second bias generator configured to establish a second pulse voltage (PV) waveform at the second electrode during substrate processing.

11. The method according to claim 10, further comprising exposing one or more edge pocket surfaces to the plasma while simultaneously maintaining a voltage established in one or both of the first electrode or edge control electrodes at approximately 0 volts ± 1 volt (V).

12. The method according to claim 1, wherein the RF signal has a frequency of approximately 27 MHz or higher.

13. A plasma processing chamber, A chamber body and chamber lid that define the processing space, A substrate support assembly disposed within the processing space, Support base, and A substrate support disposed on the support base, comprising: a dielectric material forming a substrate support surface; a bias electrode disposed within the dielectric material and separated from the substrate support surface and the support base by a portion of the dielectric material; and an edge control electrode positioned at a distance from the center of the bias electrode. A substrate support assembly, An edge tuning circuit electrically connected to the edge control electrode, A non-temporary computer-readable medium containing instructions for performing a cleaning method and Includes, The cleaning method described above The method involves generating plasma from cleaning gas or vapor supplied to the processing space by using an RF signal supplied to the support base, wherein the RF signal is supplied to the support base by an RF generator, and the RF signal generates plasma that establishes a first RF waveform at the bias electrode and a second RF waveform at the edge control electrode. Partially lifting the substrate above the substrate support assembly, wherein an edge pocket region is defined along the outer edge of the partially lifted substrate; By using the edge tuning circuit, the characteristics of one or more of the second RF waveforms with respect to the first RF waveform are adjusted. A plasma processing chamber, including a plasma processing chamber.

14. The plasma processing chamber according to claim 13, wherein adjusting one or more characteristics of the second RF waveform with respect to the first RF waveform includes adjusting one or more of the voltage amplitude ratio, current amplitude ratio, or phase difference between the second RF waveform and the first RF waveform by using the edge tuning circuit.

15. The plasma processing chamber according to claim 14, wherein adjusting one or more characteristics of the second RF waveform with respect to the first RF waveform includes adjusting the phase difference between the second RF waveform and the first RF waveform.

16. The plasma processing chamber according to claim 15, wherein adjusting the phase difference between the second RF waveform and the first RF waveform increases the concentration of plasma formed in the gap region between the partially lifted edge of the substrate and the edge ring disposed on the substrate support.

17. The plasma processing chamber according to claim 13, wherein the edge tuning circuit includes one or more variable capacitors.

18. The plasma processing chamber according to claim 13, wherein the edge tuning circuit is electrically connected between the edge control electrode and ground.

19. The plasma processing chamber according to claim 13, wherein the edge tuning circuit is electrically connected between the edge control electrode and the RF generator.

20. The plasma processing chamber according to claim 13, wherein the edge tuning circuit is electrically connected to the edge control electrode, ground, and the RF generator.

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