Indication device

Abstract

To provide a semiconductor device having a thin film transistor using an oxide semiconductor layer, in which a low power consumption semiconductor device is provided, and to provide a highly reliable semiconductor device in the semiconductor device having a thin film transistor using the oxide semiconductor layer.SOLUTION: In the semiconductor device, a gate electrode layer (gate wiring layer) and a wiring layer that electrically connects to a source electrode layer or a drain electrode layer intersect with each other via an insulating layer covering the oxide semiconductor layer of the thin film transistor and a gate insulating layer present in between. It is possible to reduce the parasitic capacitance formed by the laminated structure of the gate electrode layer, the gate insulating layer, and the source electrode layer or the drain electrode layer, and it is possible to realize low power consumption of the semiconductor device.SELECTED DRAWING: Figure 1

Description

[Technical Field]

[0001] This invention relates to a semiconductor device using an oxide semiconductor and a method for manufacturing the same.

[0002] In this specification, a semiconductor device refers to a device that can function by utilizing semiconductor properties. This term encompasses a wide range of electronic devices, including electro-optical devices, semiconductor circuits, and electronic equipment. [Background technology]

[0003] In recent years, semiconductor thin films (thickness of several to several hundred nm) formed on substrates having an insulating surface have been used The technology for constructing thin-film transistors (TFTs) is attracting attention. Thin-film transistors are I It is widely applied in electronic devices such as carbon and electro-optical devices, and especially in switches for image display devices. Development as a luminaire element is being expedited. Metal oxides exist in a wide variety of forms and are used in various applications. Indium oxide is a well-known material and is required in liquid crystal displays, etc. It is used as a transparent electrode material.

[0004] Some metal oxides exhibit semiconductor properties. For example, there are tungsten oxide, tin oxide, indium oxide, zinc oxide, and so on. Thin-film transistors using metal oxides exhibiting semiconductor properties as channel formation regions are already known. (See Patent Documents 1 and 2.)

[0005] Electrical devices using thin-film transistors include mobile phones and notebook personal computers. Examples include mobile devices such as TTDS, but for such portable electronic devices Power consumption, which affects continuous operating time, is a major issue. Furthermore, television equipment is becoming larger. For all of them, it is important to suppress the increase in power consumption that comes with larger sizes. [Prior art documents] [Patent Documents]

[0006] [Patent Document 1] Japanese Patent Publication No. 2007-123861 [Patent Document 2] Japanese Patent Publication No. 2007-96055 [Overview of the project] [Problems that the invention aims to solve]

[0007] In a semiconductor device having a thin-film transistor using an oxide semiconductor layer, low power consumption half One of the objectives is to provide a conductive device.

[0008] In a semiconductor device having a thin-film transistor using an oxide semiconductor layer, a highly reliable semiconductor One of the objectives is to provide a conductive device. [Means for solving the problem]

[0009] In a semiconductor device, the gate electrode layer (gate wiring layer) and the source electrode layer or drain electrode The wiring layer that electrically connects to the layer is the insulating layer that covers the oxide semiconductor layer of the thin-film transistor and The structure is such that the gate electrode layer and the saw are intersected with a gate insulating layer in between. The electrode layer and drain electrode layer overlap partially on the oxide semiconductor layer, except for the gate electrode layer and the gate electrode layer. It does not have a laminated structure consisting of a base insulating layer and a source electrode layer or drain electrode layer.

[0010] Therefore, the stacked structure consists of a gate electrode layer, a gate insulating layer, and a source electrode layer or drain electrode layer. This reduces the parasitic capacitance formed by this process, enabling lower power consumption in semiconductor devices. to cut

[0011] One form of the configuration of the invention disclosed in this specification includes a gate electrode layer, a gate insulating layer on the gate electrode layer, an oxide semiconductor layer on the gate insulating layer, a source electrode layer and a drain electrode layer on the oxide semiconductor layer, an oxide insulating layer in contact with the oxide semiconductor layer on the source electrode layer and the drain electrode layer, and a wiring layer electrically connected to the source electrode layer or the drain electrode layer on the oxide insulating layer. An opening reaching the source electrode layer or the drain electrode layer is provided in the oxide insulating layer. The wiring layer contacts the source electrode layer or the drain electrode layer at the opening, and the gate electrode layer and the wiring layer partially overlap through the gate insulating layer and the oxide semiconductor layer, which is a semiconductor device.

[0012] The source electrode layer and the drain electrode layer preferably use a thin film with a film thickness of 0.1 nm or more and 50 nm or less, and a film thinner than the wiring layer is used. Since the source electrode layer and the drain electrode layer are thin conductive films, the parasitic capacitance with the gate electrode layer can be reduced.

[0013] It is preferable to use a material containing a metal with high oxygen affinity for the source electrode layer and the drain electrode layer. Further, the metal with high oxygen affinity is preferably a material selected from any one or more of titanium, aluminum, manganese, magnesium, zirconium, beryllium, and thorium. In this embodiment, a titanium film is used as the source electrode layer and the drain electrode layer.

[0014] When the oxide semiconductor layer and the metal layer with high oxygen affinity are brought into contact and heat-treated, oxygen atoms move from the oxide semiconductor layer to the metal layer, and the carrier density increases near the interface. Therefore ​​​​​​​​​​​​​​​​​​​​​​​​​​A low-resistance region is formed near the interface, and the oxide semiconductor layer, source electrode layer and drain This can reduce the contact resistance with the in electrode layer.

[0015] Furthermore, heat-resistant conductive materials may be used for the source electrode layer and the drain electrode layer. When using this material, even if heat treatment is performed after the source electrode layer and drain electrode layer are formed, the source electrode This prevents alteration and deterioration of the layer and the drain electrode layer.

[0016] Examples of heat-resistant conductive materials include titanium (Ti), tantalum (Ta), and tungsten (W). Choose from molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc). The elements that have been identified, or alloys containing the aforementioned elements, or alloys combining the aforementioned elements. A film, or a nitride containing the aforementioned elements, can be used. By combining low-resistance conductive materials such as aluminum (Al) and copper (Cu) with the above-mentioned heat-resistant conductive materials... A conductive film with improved heat resistance may also be used.

[0017] Furthermore, the source electrode layer and the drain electrode layer may also contain a metal oxide layer, for example, a metal oxide layer. A structure having a titanium oxide film between the conductive layer and the titanium film, or a titanium film (for example, a film thickness of 0.1 A titanium oxide film (for example, film thickness of 1 nm or more and 20 nm or less) is placed between the oxide insulating layer and the oxide insulating layer. The structure may also have elements less than or equal to nm.

[0018] Furthermore, if the source electrode layer and drain electrode layer are thin films that transmit light, The electrode layer and the drain electrode layer are translucent.

[0019] The wiring layer uses a conductive film with lower resistance than the source electrode layer and the drain electrode layer. Specifically, Aluminum, copper, chromium, tantalum, molybdenum, tungsten, titanium, neodymium, Using metallic materials such as scandium or alloy materials mainly composed of these materials, in a single layer or in a laminated form. It can be formed in this way. In this embodiment, as the wiring layer, an aluminum is used in the first wiring layer. A laminated structure of a titanium film is used for the first and second wiring layers.

[0020] Another embodiment of the configuration of the invention disclosed herein is a gate electrode layer, and a gate electrode A gate insulating layer is formed on the pole layer, and an oxide semiconductor layer is formed on the gate insulating layer, and an oxide semiconductor After dehydrating or dehydrogenating the body layer, water or water is introduced into the oxide semiconductor layer without exposure to the atmosphere. To prevent the re-incorporation of elements, a source electrode layer and a drain electrode layer are formed on the oxide semiconductor layer, oxidation On the material semiconductor layer, source electrode layer and drain electrode layer, an oxide semiconductor layer in contact with a portion of the oxide semiconductor layer A material insulating layer is formed, and an opening is formed in the oxide insulating layer that reaches the source electrode layer or the drain electrode layer. The opening is in contact with the source electrode layer or the drain electrode layer, and the gate electrode layer and the gate insulating layer A wiring layer is formed that partially overlaps via an oxide insulating layer, and the wiring layer consists of a source electrode layer and a drain. This is a method for fabricating a semiconductor device that has a thinner film thickness than the electrode layer and low resistance.

[0021] Each of the above configurations solves at least one of the above problems.

[0022] The oxide semiconductor layer is InMO3(ZnO) m For thin films denoted as (m>0) Yes, and a thin-film transistor is fabricated using that thin film as an oxide semiconductor layer. Note that M is This indicates one or more metallic elements selected from Ga, Fe, Ni, Mn, and Co. For example, as M, there are cases where it is Ga, as well as Ga and Ni or Ga and Fe, etc. Other metal elements besides a may be included. In addition to the metallic elements contained, impurity elements include Fe, Ni and other transition metal elements, or Some products contain oxides of the transition metal. In this specification, InMO3(Zn O) m Among oxide semiconductor layers with a structure represented by (m>0), the structure containing Ga as M Oxide semiconductors are called In-Ga-Zn-O oxide semiconductors, and their thin films are called In-Ga-Z It is also called an nO-based non-single crystal film.

[0023] In addition to the above, other metal oxides that can be applied to oxide semiconductor layers include In-Sn-O systems and I n-Sn-Zn-O system, In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga -Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al- Zn-O-based, In-O-based, Sn-O-based, and Zn-O-based metal oxides can be applied. Furthermore, silicon oxide may be included in the oxide semiconductor layer made of the above-mentioned metal oxide.

[0024] Furthermore, dehydration or dehydrogenation involves the deactivation of nitrogen or noble gases (argon, helium, etc.). Under a gaseous atmosphere, the substrate strain point is maintained at 400°C to 750°C, preferably 425°C or higher. This is a complete heat treatment that reduces impurities such as moisture contained in the oxide semiconductor layer. This prevents re-impregnation with water (H2O).

[0025] Dehydration or dehydrogenation heat treatment is preferably carried out in a nitrogen atmosphere with H2O at a concentration of 20 ppm or less. It is also possible to perform the procedure in ultra-dry air with an H2O concentration of 20 ppm or less.

[0026] Heat treatment for dehydration or dehydrogenation is performed using an electric furnace or a heated gas. The GRTA (Gas Rapid Thermal Anneal) method or lamp light Instantaneous methods such as LRTA (Lamp Rapid Thermal Anneal) that use Intermittent heating methods can be used.

[0027] The oxide semiconductor layer that has undergone dehydration or dehydrogenation is the oxide semiconductor layer after dehydration or dehydrogenation. Even when measuring TDS up to 450°C for the body layer, two peaks for water are still visible, at least 300°C. The heat treatment conditions should be such that the single peak appearing around °C is not detectable. Therefore, dehydration Alternatively, for thin-film transistors using an oxide semiconductor layer that has undergone dehydrogenation, the TDS is 45 Even when measurements are taken down to 0°C, the water peak that typically appears around 300°C is not detected.

[0028] Then, from the heating temperature T at which dehydration or dehydrogenation is performed on the oxide semiconductor layer, to the dehydration period Alternatively, the oxide semiconductor layer is slowly cooled in the same furnace where dehydrogenation was performed, without exposure to the atmosphere, and water or hydrogen is added. It is important to prevent further contamination. Dehydration or dehydrogenation is performed to remove the oxide semiconductor layer. Lowering the resistance, i.e., making it N-type (N - , N + After performing (etc.), the oxide semiconductor is made into a type I by increasing its resistance. When a thin-film transistor is fabricated using a conductive layer, the threshold voltage value of the thin-film transistor can be increased. This allows for the realization of a so-called normally-off switching element. Thin film transistor The channel is formed with a positive threshold voltage as close as possible to 0V as the gate voltage of the transistor. This is desirable for display devices. Furthermore, the threshold voltage value of the thin-film transistor is negative. This means that even with a gate voltage of 0V, current flows between the source and drain electrodes, a so-called normal current flow. It is prone to becoming a leon. In active matrix type display devices, the circuit is configured The electrical characteristics of thin-film transistors are crucial, as these characteristics determine the performance of the display device. In particular, the threshold voltage (Vth) is an important electrical characteristic of thin-film transistors. Even if the effective mobility is high, if the threshold voltage value is high, or if the threshold voltage value is negative, , it is difficult to control as a circuit. The threshold voltage value is high, and the absolute value of the threshold voltage In the case of a thin-film transistor with a large saturation, it acts as a switch for TFTs when the drive voltage is low. It may fail to perform its function and become a burden. n-channel thin film transistor In the case of a transistor, a channel is formed only when a positive voltage is applied to the gate voltage, and the drain voltage A transistor that allows current to flow is desirable. A channel will not form unless the drive voltage is high enough. Transistors, and transistors that form a channel and allow drain current to flow even in a negative voltage state. Sta is unsuitable as a thin-film transistor for use in circuits.

[0029] Furthermore, the gas atmosphere used to lower the temperature from heating temperature T is different from the gas atmosphere used to raise the temperature to heating temperature T. The atmosphere may be switched to a gaseous atmosphere. For example, in the same furnace where dehydration or dehydrogenation has been performed, the atmosphere may be switched to air. Without contact, high-purity oxygen gas or N2O gas, or ultra-dry air (with a dew point) is passed through the furnace. Cooling is performed by filling the container with water at -40°C or below, preferably -60°C or below.

[0030] After reducing the moisture content in the membrane by heat treatment that involves dehydration or dehydrogenation, the moisture content is reduced. Slow cooling (or cooling) in an atmosphere where there is no dew (dew point of -40°C or lower, preferably -60°C or lower). Using the oxide semiconductor film, the electrical characteristics of thin-film transistors are improved, and mass production is also possible. Realize a thin film transistor having both properties and high performance.

[0031] In this specification, the heat treatment in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium) is called a heat treatment for dehydration or dehydrogenation. In this specification, this heat treatment is not only called dehydrogenation when desorbing as H2, but also includes desorbing H , OH, etc., and is conveniently called dehydration or dehydrogenation.

[0032] When performing heat treatment in an inert gas atmosphere of nitrogen or a noble gas (such as argon or helium), the oxide semiconductor layer becomes oxygen-deficient type by the heat treatment and has reduced resistance, that is, is N-type ([ N - type conversion, etc.).

[0033] Also, a high-resistance drain region (also called a HRD (High Resistance Drain) region) that is oxygen-deficient and overlaps with the drain electrode layer is formed. Also, the source electrode A high-resistance source region (also called a HRS (High Resistanc e Source) region) that is oxygen-deficient and overlaps with the layer is formed.

[0034] Specifically, the carrier concentration of the high-resistance drain region is within the range of 1×10 18 / cm 3 or more, and is higher than at least the carrier concentration of the channel formation region (less than 1×10 18 / cm [[ID=

[42] ] 3 ). Note that the carrier concentration in this specification refers to the value of the carrier concentration obtained from Hall effect measurement at room temperature. less than) region. is obtained.

[0035] And at least a part of the dehydrated or dehydrogenated oxide semiconductor layer is in an oxygen-excess state. This further increases the resistance, i.e., makes it type I, and forms a channel-forming region. As a treatment to bring a hydrated or dehydrogenated oxide semiconductor layer into an oxygen-rich state, dehydration is performed. or a sputtering method for oxide insulating film in contact with a dehydrogenated oxide semiconductor layer (sputtering method) (also known as) film formation, or heat treatment after oxide insulating film formation, or in an oxygen-containing atmosphere Heat treatment, or a process of heating in an inert gas atmosphere followed by cooling in an oxygen atmosphere, ultra-drying This is done by cooling with air (with a dew point of -40°C or lower, preferably -60°C or lower). .

[0036] Furthermore, at least a portion of the dehydrated or dehydrogenated oxide semiconductor layer (overlapping with the gate electrode layer) By selectively creating an oxygen-rich state in the (part) to form a channel-forming region, high resistance is achieved. It can also be converted to type I. It is in contact with a dehydrated or dehydrogenated oxide semiconductor layer. Then, a source electrode layer and a drain electrode layer made of metal electrodes such as Ti are formed, and the source electrode layer The exposed region that does not overlap with the drain electrode layer is selectively treated as an oxygen-rich state to form a channel. This can be formed. When selectively creating an oxygen-rich state, the high layer overlaps the source electrode layer. A resistance source region and a high-resistance drain region overlapping the drain electrode layer are formed, and the high-resistance source region The region between the drain region and the high-resistance drain region becomes the channel-forming region. The channel length of the formed region becomes self-aligned with the source electrode layer and the drain electrode layer.

[0037] This allows for the fabrication of semiconductor devices with thin-film transistors that exhibit good electrical characteristics and high reliability. And it becomes possible to provide it.

[0038] Furthermore, a high-resistance drain region is formed in the oxide semiconductor layer superimposed on the drain electrode layer. This improves the reliability of the drive circuit when it is formed. Specifically, By forming a resistive drain region, a high-resistance drain region and a channel are created from the drain electrode layer. It is possible to create a structure in which the conductivity can be changed in stages across the formation region. Therefore, when operating by connecting to wiring that supplies a high power potential VDD to the drain electrode layer, Even when a high electric field is applied between the drain electrode layer and the drain electrode layer, the high-resistance drain region buffs This configuration prevents the application of a localized high electric field, thereby improving the breakdown voltage of the thin-film transistor. It is possible.

[0039] Furthermore, in the oxide semiconductor layer superimposed on the drain electrode layer and the source electrode layer, a high-resistance drain By forming an in region and a high-resistance source region, the channel is formed when a drive circuit is created. This can reduce leakage current in the formed region. Specifically, the high-resistance drain region By forming this, the leakage current of the transistor that flows between the drain electrode layer and the source electrode layer The flow path consists of a drain electrode layer, a high-resistance drain region on the drain electrode layer side, and a channel shape. The order is the formed region, the high-resistance source region on the source electrode layer side, and the source electrode layer. At this time, the channel In the channel formation region, the channel flows from the high-resistance drain region on the drain electrode layer side to the channel region. The current is drawn at the interface between the gate insulating layer and the channel formation region, which have high resistance when the transistor is off. It can be concentrated in the vicinity, and the back channel (channels that are far from the gate electrode layer) This can reduce leakage current in a portion of the surface of the formed region.

[0040] Furthermore, there is a high-resistance source region that overlaps the source electrode layer and a high-resistance drain region that overlaps the drain electrode layer. The region depends on the width of the gate electrode layer, but it overlaps with a part of the gate electrode layer and the gate insulating layer. This allows for a more effective reduction of the electric field strength near the edges of the drain electrode layer.

[0041] Furthermore, an oxide conductive layer is formed between the oxide semiconductor layer and the source electrode layer and drain electrode layer. The oxide conductive layer preferably contains zinc oxide as a component, and indium oxide may also be used. It is preferable that it does not contain zinc oxide, aluminum zinc oxide, or acid nitrate. Aluminum zinc oxide, gallium zinc oxide, etc. can be used. The oxide conductive layer is low Resistive drain region (LRN (Low Resistance N-type conduction) Both the ctivity region and the LRD (Low Resistance Drain) region It also functions as a call. Specifically, the carrier concentration in the low-resistance drain region is higher in the high-resistance drain region. Larger than the Rain region (HRD region), for example, 1 × 10⁻⁶ 20 / cm 3 The above 1 x 10 21 / cm 3 Preferably, the oxide conductive layer is within the range of the oxide semiconductor layer and the source electrode layer. By placing it between the drain electrode layer and the other electrode layer, contact resistance can be reduced, enabling high-speed operation of the transistor. This makes it possible to improve the frequency characteristics of the peripheral circuits (drive circuits). Cut.

[0042] The metal layers for forming the oxide conductive layer, source electrode layer, and drain electrode layer are formed by continuous film deposition. It is possible.

[0043] Furthermore, the aforementioned first and second wirings are oxidized to function as LRN or LRD. A laminated wiring harness may be constructed using the same material as the material conductive layer and a metallic material. By laminating conductive layers, coverage against uneven surfaces such as overlapping wiring and openings is improved. This can reduce wiring resistance. Also, localized wiring due to migration etc. Because it can also be expected to have the effect of increasing resistance and preventing wire breakage, it is possible to provide highly reliable semiconductor devices. can.

[0044] Furthermore, when connecting the first and second wirings as described above, an oxide conductive layer is placed in between. By continuing, an insulating oxide is formed on the metal surface of the connection (contact) part. This is expected to prevent an increase in contact resistance and make semiconductor equipment more reliable. We can provide a place for you.

[0045] Furthermore, thin-film transistors are susceptible to damage from static electricity, so the gate wire or source wire may be damaged. For each line, a protection circuit for protecting the thin-film transistors in the pixel area is provided on the same substrate. Preferably, the protection circuit is constructed using a nonlinear element with an oxide semiconductor layer. It's nice.

[0046] The ordinal numbers "1st" and "2nd" are used for convenience only and do not represent the order of processes or stacking. This does not indicate that the invention is uniquely named. This does not indicate anything.

[0047] Furthermore, thin-film transistors using oxide semiconductor layers are used in electronic and optical devices. This is possible. For example, switching elements in liquid crystal display devices and switching elements in light-emitting devices. Thin-film transistors using oxide semiconductor layers are used for children and electronic paper switching elements. It can be used.

[0048] Furthermore, not limited to display devices, insulated gate semiconductor devices for high-power control, especially power MOS devices, are also applicable. It is also possible to fabricate semiconductor devices called vices. As for power MOS devices, Examples include MOSFETs and IGBTs. [Effects of the Invention]

[0049] In a semiconductor device having a thin-film transistor using an oxide semiconductor layer, parasitic capacitance is reduced. This enables the provision of low-power semiconductor devices.

[0050] In a semiconductor device having a thin-film transistor using an oxide semiconductor layer, a highly reliable semiconductor A conductive device can be provided. [Brief explanation of the drawing]

[0051] [Figure 1] A diagram illustrating a semiconductor device. [Figure 2] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 3] A diagram illustrating a semiconductor device. [Figure 4] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 5] A diagram illustrating the method for manufacturing semiconductor devices. [Figure 6] A diagram illustrating a semiconductor device. [Figure 7] A diagram illustrating a semiconductor device. [Figure 8] A diagram illustrating a semiconductor device. [Figure 9] A diagram illustrating a semiconductor device. [Figure 10] A diagram illustrating a semiconductor device. [Figure 11] A diagram illustrating the pixel equivalent circuit of a semiconductor device. [Figure 12] A diagram illustrating a semiconductor device. [Figure 13]A diagram illustrating a semiconductor device. [Figure 14] A diagram illustrating a semiconductor device. [Figure 15] A diagram illustrating a semiconductor device. [Figure 16] A diagram illustrating a semiconductor device. [Figure 17] A diagram illustrating a semiconductor device. [Figure 18] A diagram illustrating the pixel equivalent circuit of a semiconductor device. [Figure 19] A diagram illustrating a semiconductor device. [Figure 20] A diagram showing electronic equipment. [Figure 21] A diagram showing electronic equipment. [Figure 22] A diagram showing electronic equipment. [Figure 23] A diagram showing electronic equipment. [Figure 24] A diagram showing electronic equipment. [Figure 25] A diagram illustrating a multi-level mask. [Figure 26] A diagram illustrating the calculation results. [Figure 27] A diagram illustrating the calculation results. [Modes for carrying out the invention]

[0052] The embodiments of the present invention will be described in detail below with reference to the drawings. However, the present invention is... Not limited to the following description, the form and details can be modified in various ways, as any person skilled in the art would know. This is easily understood. Furthermore, the present invention shall be interpreted as being limited to the contents of the embodiments described below. It's not something that can be done.

[0053] (Embodiment 1) One embodiment of a semiconductor device and a method for manufacturing a semiconductor device will be explained using Figures 1, 2, and 6. .

[0054] Figure 1 shows an example of the planar and cross-sectional structure of a semiconductor device. The thin film trace shown in Figure 1(A2)(B) The 410 is a bottom gate structure called a channel etch type, and is an inverse staggered type. Also known as a thin-film transistor.

[0055] Figure 1(A1) shows the gate wiring layer (formed in the same process as the gate electrode layer) and the source wiring layer ( Figure 1(A2) is a plan view of the intersection with the wiring layer (formed in the same process as the wiring layer), and shows a channel etch type This is a plan view of the thin-film transistor 410, and Figure 1(B) is a plan view of the line C1- in Figures 1(A1) and (A2). This is a cross-sectional view along C2 and line D1-D2.

[0056] Thin-film transistor 410 is a channel-etch type thin-film transistor and has an insulating surface. On the substrate 400, a gate electrode layer 411, a gate insulating layer 402, and at least a channel are formed. Oxidation having region 413, high-resistance source region 414a, and high-resistance drain region 414b It includes a monocrystalline semiconductor layer 412, a source electrode layer 415a, and a drain electrode layer 415b. The oxide insulating layer 407 that covers the thin-film transistor 410 and is in contact with the channel formation region 413 is A protective insulating layer 408 is provided on top of it.

[0057] The oxide insulating layer 407 and the protective insulating layer 408 have a source electrode layer 415a and a drain electrode. An opening (contact hole) is formed that reaches layer 415b, and wiring layers 417a and 4 Layers 17b, 418a, and 418b are formed. Meanwhile, at the intersection, the gate wiring layer is formed. 421 and source wiring layers 422, 423 are gate insulating layer 402, oxide insulating layer 407 and The layers are laminated with a protective insulating layer 408 in between.

[0058] In this way, the gate electrode layer (gate wiring layer) and the source electrode layer or drain electrode layer are electrically connected. The wiring layers that are directly connected are the insulating layer and gate insulating layer that cover the oxide semiconductor layer of the thin-film transistor. The structure is such that the layers intersect with a marginal layer in between. This is the gate electrode layer and source electrode layer of a thin-film transistor. The drain electrode layer and the gate electrode layer overlap only partially on the oxide semiconductor layer, and the gate insulating layer. It does not have a layered structure consisting of a layer and a source electrode layer or a drain electrode layer.

[0059] Therefore, the stacked structure consists of a gate electrode layer, a gate insulating layer, and a source electrode layer or drain electrode layer. This reduces the parasitic capacitance formed by this process, enabling lower power consumption in semiconductor devices. Cut.

[0060] Furthermore, the thin-film transistor 410 will be explained using a single-gate thin-film transistor. However, if necessary, a thin film transistor with a multi-gate structure having multiple channel formation regions It can also form a "ta".

[0061] The following describes the process of fabricating a thin-film transistor 410 on a substrate, using Figures 2(A) to (F). explain.

[0062] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography is performed. The gate electrode layer 411 and gate wiring layer 421 are formed by the process. Note that a resist mask The resist mask may be formed by an inkjet method. Because it does not use a photomask, manufacturing costs can be reduced.

[0063] There are no major restrictions on the substrates that can be used for the substrate 400 having an insulating surface, however In both cases, it is necessary that it has sufficient heat resistance to withstand subsequent heat treatment. Glass substrates such as borosilicate glass and aluminoborsilicate glass can be used.

[0064] Furthermore, for glass substrates, if the subsequent heat treatment temperature is high, the strain point will be 730°C or higher. It is best to use the following. Also, for the glass substrate, for example, aluminosilicate glass, Glass materials such as luminoborosilicate glass and bariumborosilicate glass are used. By including more barium oxide (BaO) compared to boric acid, a more practical heat-resistant gas canister can be created. Lath can be obtained. For this reason, it is preferable to use a glass substrate that contains more BaO than B2O3. Mashii

[0065] In addition, ceramic substrates, quartz substrates, sapphire substrates, etc. can be used instead of the glass substrates mentioned above. A substrate made of edge material may also be used. Other materials, such as crystallized glass, can also be used.

[0066] An insulating film, which will serve as the base layer, is placed between the substrate 400 and the gate electrode layer 411 and the gate wiring layer 421. It may also be provided. The undercoat has the function of preventing the diffusion of impurity elements from the substrate 400. One or more selected from silicon nitride film, silicon oxide film, silicon nitride oxide film, or silicon oxide nitride film. It can be formed by a single-layer or multi-layer structure of a film.

[0067] Furthermore, the materials for the gate electrode layer 411 and the gate wiring layer 421 are molybdenum, titanium, and Metal materials such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium It can be formed in a single layer or in layers using materials or alloy materials that mainly consist of these materials. ru.

[0068] Next, a gate insulating layer 402 is formed on the gate electrode layer 411 and the gate wiring layer 421. ru.

[0069] The gate insulating layer 402 is formed by a silicon oxide layer using plasma CVD or sputtering. , a silicon nitride layer, a silicon oxide nitride layer, a silicon oxide nitride layer, or an aluminum oxide layer as a single layer or It can be formed by stacking. For example, SiH4, oxygen, and nitrogen can be used as the film-forming gas. Then, a silicon oxide nitride layer can be formed by plasma CVD. The thickness shall be between 100 nm and 500 nm, and in the case of lamination, for example, the film thickness shall be 50 nm or more. A first gate insulating layer with a thickness of 00 nm or less, and a layer with a film thickness of 5 nm or more and 300 nm on the first gate insulating layer. The second gate insulating layer is laminated with a length of m or less.

[0070] In this embodiment, the gate insulating layer 402 is made to a thickness of 200 nm or less by plasma CVD. It forms the silicon nitride layer below.

[0071] Next, an oxide semiconductor film 44 with a thickness of 2 nm to 200 nm is placed on the gate insulating layer 402. Formation of 0. Heat treatment for dehydration or dehydrogenation after the formation of the oxide semiconductor film 440. Even if this is done, the oxide semiconductor film will be in an amorphous state, so the film thickness will be thinned to 50 nm or less. This is preferable. By making the thickness of the oxide semiconductor film thin, the heat treatment after the formation of the oxide semiconductor layer is performed. This process can suppress crystallization.

[0072] Furthermore, before depositing the oxide semiconductor film 440 by sputtering, an argon gas is introduced. Reverse sputtering is performed to generate plasma by introducing material, and the material adheres to the surface of the gate insulating layer 402. It is preferable to remove any debris. Reverse sputtering is a method where no voltage is applied to the target side. Under an argon atmosphere, a voltage is applied to the substrate side using an RF power supply to form plasma near the substrate. This is a method of modifying the surface. Note that nitrogen, helium, oxygen, etc., can be used instead of an argon atmosphere. You may use any of these.

[0073] Oxide semiconductor film 440 is an In-Ga-Zn-O non-single crystal film, In-Sn-Zn-O system In-Al-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn- Al-Zn-O series, In-Zn-O series, Sn-Zn-O series, Al-Zn-O series, In-O Oxide semiconductor films of the following types are used: Sn-O system, Zn-O system, and Zn-O system.

[0074] In this embodiment, the oxide semiconductor film 440 is an In-Ga-Zn-O based oxide semiconductor The film is deposited using sputtering with a GET. A cross-sectional view at this stage is shown in Figure 2(A). It corresponds to this. Also, the oxide semiconductor film 440 is acidic under a noble gas (typically argon) atmosphere. Sputtering under an ambient atmosphere, or under a noble gas (typically argon) and oxygen atmosphere. It can be formed by the sputtering method. Also, when using the sputtering method, SiO2 is 2 A target containing between 10% by weight and 10% by weight is used to form an oxide semiconductor film 440. By including SiOx (X>0) which inhibits crystallization, the dehydration or dehydrogenation process carried out in a later step will be... It is preferable to suppress crystallization during the heat treatment process.

[0075] Here, an oxide semiconductor target containing In, Ga, and Zn (In2O3:Ga2O 3:ZnO=1:1:1[mol ratio], In:Ga:Zn=1:1:0.5[atom ratio Using ]), the distance between the substrate and the target is 100 mm, the pressure is 0.2 Pa, and DC (D C) Power supply 0.5kW, argon and oxygen (argon:oxygen = 30 sccm:20 sccm) The film is deposited in an atmosphere with an oxygen flow rate ratio of 40%. Note that when using a pulsed DC power supply... This is preferable because it reduces dust and ensures a uniform film thickness distribution. In-Ga-Zn-O non-monochromatic The thickness of the crystalline film shall be between 5 nm and 200 nm. In this embodiment, an oxide semiconductor film As an example, using an In-Ga-Zn-O oxide semiconductor target, the sputtering method is used. A non-single-crystal In-Ga-Zn-O film with a thickness of 20 nm is deposited. In addition, In, Ga, and As an oxide semiconductor target containing Zn, In:Ga:Zn=1:1:1[atom A target having a composition ratio of In:Ga:Zn=1:1:2 [atom ratio] It can also be used.

[0076] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering, and D There is the C sputtering method, and furthermore, pulsed DC sputtering, which applies a pulsed bias. There is also the RF sputtering method. RF sputtering is mainly used when depositing insulating films, and DC sputtering. Taring is primarily used for depositing metal films.

[0077] There are also multi-point sputtering systems that can set up multiple targets made of different materials. The apparatus can deposit multiple layers of different material films in the same chamber, or multiple types of materials in the same chamber. It is also possible to deposit films by simultaneously discharging electrical currents from similar materials.

[0078] Furthermore, sputtering using a magnetron sputtering method that incorporates a magnetic mechanism inside the chamber... ECRs use devices that generate plasma using microwaves instead of glow discharges. There are sputtering machines that use the puttering method.

[0079] Furthermore, as a film deposition method using the sputtering method, the target material and sputtering gas are used during film deposition. Reactive sputtering is a method that uses chemical reactions to form thin films of compounds. Alternatively, there is a bias sputtering method that applies voltage to the substrate during film deposition.

[0080] Next, the oxide semiconductor film 440 is transformed into island-shaped oxide semiconductors by a second photolithography process. The material is processed into layers. Additionally, a resist mask is used to form island-shaped oxide semiconductor layers. It may also be formed by the jet method. If the resist mask is formed by the inkjet method, photomask Because no screws are used, manufacturing costs can be reduced.

[0081] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400°C to 750°C, preferably 400°C or higher, to reduce substrate strain. The value is set to less than 1. Here, a substrate is introduced into an electric furnace, which is one of the heat treatment devices, and an oxide semiconductor The body layer is subjected to a heat treatment at 450°C for 1 hour under a nitrogen atmosphere, and then exposed to air. Without doing so, water and hydrogen are prevented from being re-mixed into the oxide semiconductor layer, and the oxide semiconductor layer 441 is obtained. See Figure 2(B).

[0082] As an example of the mechanism of water desorption in oxide semiconductor films, the following reaction pathway was analyzed. (In oxide semiconductor films, the reaction occurs not only with water, but also with OH or H). An In-Ga-Zn-O amorphous film was used as the conductive film.

[0083] Furthermore, the optimal molecular structure in the ground state of the computational model is determined using density functional theory (DFT). I calculated it. The total energy of the DFT is the potential energy, the electrostatic energy between electrons, and the electrons. It is expressed as the sum of the kinetic energy of the electrons and the exchange-correlation energy, which includes all the complex interactions between electrons. In DFT, the exchange-correlation interaction is expressed in terms of electron density as a generalized one-electron potential. Because it approximates using numbers (meaning functions of functions), the calculation is fast and highly accurate. Here, Using the syngenetic function B3LYP, the weights of each parameter related to exchange and correlation energies are obtained. It was defined. Also, as a basis function, Lan was used for indium, gallium, and zinc atoms. L2DZ (Ne shell effective shell potential with split valence base system added) (Base function), for other atoms 6-311 (using three shortening functions for each valence orbital) The basis functions of the triple split valence basis system were applied. Depending on the basis set, for example, in the case of a hydrogen atom, the 1s to 3s orbitals are considered, and also oxygen For atoms, the 1s-4s and 2p-4p orbitals are considered. Furthermore, the calculation accuracy To improve the polarization, a p-function was added to the hydrogen atom and a d-function to the oxygen atom as the polarization base system. .

[0084] The Gaussian03 quantum chemistry calculation program was used. The test was conducted using a high-performance computer (SGI Altix4700).

[0085] Heat treatment that involves dehydration or dehydrogenation causes the -OH groups contained in the oxide semiconductor film to separate. It is thought that H2O is produced in the reaction. Therefore, the water production and desorption mechanism shown in Figure 26 The canism was analyzed. Note that in Figure 26, since Zn is divalent, in the case of M=Zn, One MO bond has been removed from Figure 26.

[0086] In Figure 26, M represents a metal atom, and there are three types: In, Ga, and Zn. Initial state 1 Then, -OH forms a coordinate bond that bridges M1 and M2. In transition state 2, -O The H in H rearranges to another -OH group. In intermediate 3, the resulting H2O molecule interacts with the metal atom. A coordinate bond is formed. In the final state 4, the H2O molecule is eliminated and moves away to infinity.

[0087] The total combinations of (M1-M2) are: 1. In-In, 2. Ga-Ga, 3. Zn-Zn, There are 6 possibilities: 4. In-Ga, 5. In-Zn, 6. Ga-Zn, so all combinations are... Calculations were performed for se. Note that in this calculation, M' was replaced with H for simplification. This was performed using cluster computation with a computational model.

[0088] The calculations obtained the energy diagrams corresponding to the reaction pathways in Figure 26. There are a total of 6 possibilities. As a representative example of the M1-M2 combinations, Figure 27 shows the calculation results for the In-In case. vinegar.

[0089] From Figure 27, it was found that the activation energy for water production is 1.16 eV. When a water molecule is removed, the system becomes unstable by about 1.58 eV.

[0090] Conversely, if we consider Figure 27 as a reaction from right to left, the reaction in which water enters the oxide semiconductor film is This can be observed. When this happens, the water coordinated to the metal undergoes hydrolysis, forming two OH groups. The activation energy for this reaction is 0.47 eV.

[0091] Similarly, the reaction pathways for other (M1-M2) combinations were also analyzed. 1-6 Table 1 shows the activation energy (Ea [eV]) of the water formation reaction in the case of .

[0092] [Table 1]

[0093] Table 1 shows that the water formation reaction is more likely to occur with 1.In-In and 4.In-Ga. In contrast, the water formation reaction is unlikely to occur in Zn-Zn. Therefore, the Zn atom It is presumed that the water formation reaction mediated by this medium is less likely to occur.

[0094] Furthermore, the heat treatment device is not limited to electric furnaces, but also includes heat conduction or heat from heat-generating elements such as resistance heating elements. The device may include an apparatus that heats the object to be processed by radiation. For example, GRTA(Gas Rapid Thermal Anneal) equipment, LRTA (Lamp Rapid RTA (Rapid Thermal Angle) for Thermal Annealing devices, etc. A neal device can be used. The LRTA device uses halogen lamps and metal halide lamps. Lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high pressure A device that heats an object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as mercury lamps. The GRTA device is a device that performs heat treatment using high-temperature gas. The gas contains A Inert gases such as argon or nitrogen, which do not react with the material being treated by heat treatment, are used. A gaseous substance is used.

[0095] For example, as a first heat treatment, the base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The board is moved and placed inside, heated for several minutes, then the substrate is moved and placed in a hot inert gas chamber. GRTA can be performed using this method. Using GRTA allows for high-temperature heat treatment in a short time. Yes.

[0096] In the first heat treatment, nitrogen or a noble gas such as helium, neon, or argon is used. It is preferable that it does not contain water, hydrogen, etc. Alternatively, nitrogen introduced into the heat treatment device, Alternatively, the purity of noble gases such as helium, neon, and argon must be 6N (99.9999%) or higher. Preferably 7N (99.99999%) or higher (i.e., impurity concentration of 1 ppm or less, preferably It is preferable to keep the concentration at 0.1 ppm or less.

[0097] Furthermore, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, crystallization may occur, and microcrystalline formation may occur. It may also be a crystalline film or a polycrystalline film. For example, a crystallinity of 90% or more, or 80% or less. In some cases, the above microcrystalline oxide semiconductor film may form. Also, the conditions of the first heat treatment, or acid Depending on the material of the oxide semiconductor layer, it may result in an amorphous oxide semiconductor film that does not contain crystalline components. There are also microcrystalline regions (particle size 1 nm to 20 nm) within amorphous oxide semiconductors. On the surface, the oxide semiconductor film may contain a mixture of wavelengths between 2 nm and 4 nm. When high-temperature heat treatment is performed using RTA (GRTA, LRTA), the surface of the oxide semiconductor film Needle-shaped crystals may also form on the side in the longitudinal direction (thickness direction).

[0098] Furthermore, the first heat treatment of the oxide semiconductor layer is performed on the oxide before it is processed into an island-shaped oxide semiconductor layer. This can also be done on the semiconductor film 440. In that case, after the first heat treatment, the heating device is used The substrate is removed, and the photolithography process is performed.

[0099] Heat treatment for dehydration and dehydrogenation of oxide semiconductor layers is performed after the oxide semiconductor layer is formed. After stacking source electrodes and drain electrodes on a semiconductor layer, the source electrodes and drain electrodes This can be done either after forming a protective insulating film on top, or afterwards.

[0100] Furthermore, when forming contact holes in the gate insulating layer 402, the process is carried out in an oxide semiconductor. This can be done before or after the dehydration or dehydrogenation treatment of the membrane 440.

[0101] The oxide semiconductor layer is preferably an oxide semiconductor containing In, more preferably In, It is an oxide semiconductor containing Ga. In order to make the oxide semiconductor layer type I (intrinsic), Hydrogenation or dehydrogenation is effective.

[0102] Note that the etching of oxide semiconductor films here is not limited to wet etching, but also includes dry etching. Etching may be used.

[0103] Etching gases used in dry etching include chlorine-containing gases (chlorine-based gases, for example) Chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC) l4) etc.) are preferable.

[0104] Also, fluorine-containing gases (fluorinated gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF4)) 6) Nitrogen fluoride (NF3), trifluoromethane (CHF3), etc., hydrogen bromide (HBr ), oxygen (O2), and noble gases such as helium (He) and argon (Ar) are added to these gases. Added gases, etc., can be used.

[0105] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. The desired processing shape can be etched. To that end, etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) Adjust the amount of power used, the electrode temperature on the substrate, etc., as appropriate.

[0106] The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid, Ammonia Hydrogenated Water (31% hydrogen peroxide by weight: 28% ammonia by weight: water = 5:2:2) These can be used. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0107] Furthermore, the etching solution after wet etching is washed away along with the etched material. The material is removed. The waste etching solution containing the removed material is purified, and the material contained in it is removed. It may be reused. Indium and other elements contained in the oxide semiconductor layer can be extracted from the waste liquid after etching. By recovering and reusing materials, resources can be used effectively and costs can be reduced. .

[0108] Etching conditions (etching) can be adjusted according to the material so that the desired processing shape can be etched. Adjust the solution, etching time, temperature, etc. as appropriate.

[0109] Next, a metallic conductive film is formed on the gate insulating layer 402 and the oxide semiconductor layer 441. A third photolithography step forms a resist mask, and selective etching is performed. After forming the source electrode layer 415a and the drain electrode layer 415b, a resist mask is applied. Remove it (see Figure 2(C)).

[0110] Furthermore, the oxide semiconductor layer 441 is not removed during the etching of the metal conductive film. The materials and etching conditions are adjusted as appropriate.

[0111] In this embodiment, a Ti film is used as the metal conductive film, and the oxide semiconductor layer 441 contains In- Using a Ga-Zn-O-based oxide, the etchant is ammonia peroxide (ammonia, Use a mixture of water and hydrogen peroxide.

[0112] The source electrode layer and drain electrode layer are preferably thin films with a thickness of 0.1 nm to 50 nm. A film thinner than the wiring layer is used. The source electrode layer and drain electrode layer are thin conductive films. Therefore, the parasitic capacitance with the gate electrode layer can be reduced.

[0113] The source electrode layer and drain electrode layer use materials containing metals with high oxygen affinity. This is preferable. Furthermore, the metals with high oxygen affinity mentioned above include titanium, aluminum, and manganese. Select one or more of the following: magnesium, zirconium, beryllium, or thorium. It is preferable that the material is made of a material that has been treated. In this embodiment, the source electrode layer and the drain electrode layer are A titanium film is used.

[0114] When an oxide semiconductor layer is brought into contact with a metal layer with high oxygen affinity and subjected to heat treatment, the oxide semiconductor... Oxygen atoms move from the body layer to the metal layer, and the carrier density increases near the interface. A low-resistance region is formed near the interface, and the oxide semiconductor layer, source electrode layer and drain This can reduce the contact resistance with the in electrode layer.

[0115] Furthermore, heat-resistant conductive materials may be used for the source electrode layer and the drain electrode layer. When using this material, even if heat treatment is performed after the source electrode layer and drain electrode layer are formed, the source electrode This prevents alteration and deterioration of the layer and the drain electrode layer.

[0116] Examples of heat-resistant conductive materials include titanium (Ti), tantalum (Ta), and tungsten (W). Choose from molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc). The elements that have been identified, or alloys containing the aforementioned elements, or alloys combining the aforementioned elements. A film, or a nitride containing the aforementioned elements, can be used. By combining low-resistance conductive materials such as aluminum (Al) and copper (Cu) with the above-mentioned heat-resistant conductive materials... A conductive film with improved heat resistance may also be used.

[0117] Furthermore, the source electrode layer and the drain electrode layer may also contain a metal oxide layer, for example, a metal oxide layer. A structure having a titanium oxide film between the conductive layer and the titanium film, or a titanium film (for example, a film thickness of 0.1 A titanium oxide film (for example, film thickness of 1 nm or more and 20 nm or less) is placed between the oxide insulating layer and the oxide insulating layer. The structure may also have elements less than or equal to nm.

[0118] Furthermore, if the source electrode layer and drain electrode layer are thin films that transmit light, The electrode layer and the drain electrode layer are translucent.

[0119] In the third photolithography process, only a portion of the oxide semiconductor layer 441 is etched. This can result in an oxide semiconductor layer having grooves (recesses). Also, the source electrode layer 4 A resist mask for forming 15a and the drain electrode layer 415b is inkjet It may be formed by a method. If the resist mask is formed by the inkjet method, a photomask can be used. Since it does not require any additional components, manufacturing costs can be reduced.

[0120] Furthermore, in order to reduce the number of photomasks and processes used in the photolithography process, The resist mask formed by a multi-tone mask, which is an exposure mask where the light has multiple intensities, is formed by the light. The etching process may be performed using a mask. A resist mask formed using a multi-gradation mask. The ske will have a shape with multiple film thicknesses, and its shape can be further deformed by etching. Because it can do this, it can be used in multiple etching processes that process different patterns. Therefore, a single multi-tone mask can accommodate at least two different patterns. This allows for the formation of a resist mask. Therefore, the number of exposure masks can be reduced. Furthermore, the corresponding photolithography process can also be reduced, thus simplifying the overall process.

[0121] Next, plasma treatment is performed using a gas such as N2O, N2, or Ar. The process removes adsorbed water and other substances adhering to the surface of the exposed oxide semiconductor layer. Alternatively, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0122] After plasma treatment, a protective insulation is applied to a portion of the oxide semiconductor layer without contact with the atmosphere. An oxide insulating layer 407, which forms the edge film, is created.

[0123] The oxide insulating layer 407 has a thickness of at least 1 nm, and is formed by sputtering or other methods. The marginal layer 407 can be formed using appropriate methods to prevent the introduction of impurities such as water and hydrogen. If hydrogen is present in the oxide insulating layer 407, the hydrogen may penetrate into the oxide semiconductor layer, or water may enter the layer. The oxygen is extracted from the oxide semiconductor layer by the element, and the back channel of the oxide semiconductor layer is formed. The resistance is reduced (N-type), and parasitic channels are formed. Therefore, the oxide insulating layer 40 For item 7, it is important to avoid using hydrogen in the film deposition method in order to create a film that contains as little hydrogen as possible. Yes.

[0124] In this embodiment, a silicon oxide film with a thickness of 200 nm is used as the oxide insulating layer 407, and it is formed by sputtering using the ring method. The substrate temperature during film formation may be room temperature or higher and 300 °C or lower, and in this embodiment, it is set to 100 °C. The film formation of the silicon oxide film by sputtering is carried out in a rare gas (typically argon) atmosphere, an oxygen atmosphere, or a rare gas (typically argon) and an oxygen atmosphere. Also, a silicon oxide target or a silicon target can be used. For example, using a silicon target, a silicon oxide film can be formed by sputtering in an oxygen , and nitrogen atmosphere. The oxide insulating layer 407 formed in contact with the low-resistance oxide semiconductor layer is an inorganic insulating film that does not contain impurities such as moisture, hydrogen ions, , and OH - and blocks the intrusion of these from the outside. Typically, a silicon oxide film, a silicon oxynitride film, an aluminum oxide film, or aluminum oxynitride is used.

[0125] Next, a second heat treatment (preferably 2 00 °C or higher and 400 °C or lower, for example, 250 °C or higher and 350 °C or lower) is performed in an inert gas atmosphere or an oxygen gas atmosphere. For example, a second heat treatment at 250 °C for 1 hour is performed in a nitrogen atmosphere. When the second heat treatment is performed, a part of the oxide semiconductor layer (channel formation region) is heated in contact with the oxide insulating layer 407.

[0126] By going through the above steps, after performing a heat treatment for dehydration or dehydrogenation on the formed oxide semiconductor film to reduce the resistance, a part of the oxide semiconductor film is selectively made oxygen-excessive Set it to this state. As a result, the channel formation region 413 overlapping the gate electrode layer 411 becomes of type I and a high-resistance source region 414a overlapping the source electrode layer 415a and a high-resistance drain region 414b overlapping the drain electrode layer 41 5b are self-alignedly formed. The thin film transistor 410 is formed in the above process.

[0127] Furthermore, heat treatment may be performed in the atmosphere at 100 °C or higher and 200 °C or lower for 1 hour or longer and 30 hours or shorter. In this embodiment, heat treatment is performed at 150 °C for 10 hours. This heat treatment may be performed while maintaining a constant heating temperature, or may be performed by repeating the temperature increase from room temperature to a heating temperature of 100 °C or higher and 200 °C and the temperature decrease from the heating temperature to room temperature a plurality of times. Also, this heat treatment may be performed under reduced pressure before forming the oxide insulating film. When heat treatment is performed under reduced pressure , the heating time can be shortened. By this heat treatment, hydrogen is taken into the oxide insulating layer from the oxide semiconductor layer, and a normally-off thin film transistor can be obtained. Thus, the reliability of the semiconductor device can be improved.

[0128] Note that by forming the high-resistance drain region 414b (and the high-resistance source region 414a) in the oxide semiconductor layer overlapping the drain electrode layer 415b (and the source electrode layer 415a), the reliability of the thin film transistor can be improved. Specifically, by forming the high-resistance drain region 414b, a structure can be formed such that the conductivity can be changed stepwise from the drain electrode layer 415b to the high-resistance drain region 4 14b and the channel formation region. Therefore, it is connected to a wiring for supplying a high power supply potential VDD to the drain electrode layer 415b. ​​​​​When operating continuously, a high electric field is generated between the gate electrode layer 411 and the drain electrode layer 415b. Even when applied, the high-resistance drain region acts as a buffer, preventing a localized high electric field from being applied. This allows for a configuration that improves the pressure resistance of the ZISTA.

[0129] Furthermore, the high-resistance source region or high-resistance drain region in the oxide semiconductor layer is When the body layer is thin, with a thickness of 15 nm or less, it is formed throughout the entire thickness direction, but oxide semi-semi If the thickness of the conductive layer is thicker than 30 nm to 50 nm, a portion of the oxide semiconductor layer, - The region in contact with the electrode layer or drain electrode layer and its vicinity becomes low resistance, resulting in a high resistance source region. Alternatively, a high-resistance drain region is formed, and in the oxide semiconductor layer, the region close to the gate insulating film is It can also be classified as type I.

[0130] A protective insulating layer may be formed on the oxide insulating layer 407. For example, RF sputtering A silicon nitride film is formed using the sputtering method. RF sputtering is excellent for mass production, so This is a preferred method for forming a protective insulating layer. The protective insulating layer is resistant to moisture, hydrogen ions, and OH - etc. Using an inorganic insulating film that does not contain impurities and blocks them from entering from the outside, Silicon dioxide films, aluminum nitride films, silicon nitride oxide films, aluminum oxide nitride films, etc., are used. In this embodiment, a protective insulating layer 408 is formed using a silicon nitride film as the protective insulating layer. (See Figure 2(D).)

[0131] Next, a resist mask is formed by a fourth photolithography step, and then selectively etched. By performing a process to remove a portion of the oxide insulating layer 407 and the protective insulating layer 408, the source electrode layer 4 15a. Form openings 442a and 442b that reach the drain electrode layer 415b (see Fig. 2(E ).).

[0132] Form conductive layers in the openings 442a and 442b by sputtering or vacuum evaporation so as to contact the source electrode layer 415a and the drain electrode layer 415b, and form a resist mask in the fifth photolithography process. Selectively etch the stacked conductive layer to form wiring layers 4 17a, 417b, 418a, 418b, and at the intersections, source wiring layers 422 and 423 are formed (see Fig. 2(F).). <00009�2> The wiring layers 417a, 417b, 418a, and 418b use a conductive film with lower resistance than the source electrode layer and the drain electrode layer. Specifically, metal materials such as aluminum, copper, chromium, tantalum, molybdenum denum, tungsten, titanium, neodymium, scandium, etc., or alloy materials with these as the main components can be used to form them either singly or in a stacked manner. In this embodiment [[ID=2⁵]]

[0134] ​​​​​​​​​​By providing this, the distance between the gate wiring layer 421 and the source wiring layers 422 and 423 becomes even longer. Therefore, the parasitic capacity can be reduced.

[0135] The planar insulating layer 409 can be polyimide, acrylic, benzocyclobutene, or polyamide. In addition, heat-resistant organic materials such as epoxy can be used. In addition, low-dielectric constant materials (low-k materials), siloxane resins, PSG (phosphorus glass), BP SG (Limboron glass), etc., can be used. A planar insulating layer 409 may be formed by laminating multiple edge films.

[0136] Siloxane-based resins are formed using siloxane-based materials as the starting material for Si-OS. This corresponds to a resin containing i-bonds. Siloxane resins use organic groups (e.g., alkyl groups) as substituents. You may also use aryl groups or fluoro groups. Furthermore, organic groups may have fluoro groups. You can.

[0137] The method for forming the planar insulating layer 409 is not particularly limited and may vary depending on the material, such as sputtering. , spin coating method, dipping method, spray coating method, droplet ejection method (inkjet method, Screen printing, offset printing, etc.), roll coating method, curtain coating method, knife coating Methods such as the T method can be used.

[0138] Furthermore, as shown in Figure 6(B), without providing a protective insulating layer, a wiring layer and saw are placed on the oxide insulating layer 407. A source wiring layer may be formed. In Figure 6(B), a source wiring layer is formed on the oxide insulating layer 407. A 422 is provided, and wiring layers 417a and 417b are provided in the openings formed in the oxide insulating layer 407. It is provided. Thus, the wiring layer may also be a single-layer structure.

[0139] As described above, in a semiconductor device having a thin-film transistor using an oxide semiconductor layer, This makes it possible to reduce parasitic capacitance and provide a semiconductor device with low power consumption.

[0140] Furthermore, in a semiconductor device having a thin-film transistor using an oxide semiconductor layer, reliability We can provide high-performance semiconductor devices.

[0141] (Embodiment 2) In this embodiment, a semiconductor device having a thin-film transistor with a different structure from that of Embodiment 1 is provided. An example is explained below.

[0142] Figure 3 shows an example of the planar and cross-sectional structure of a semiconductor device. The thin film trace shown in Figure 3(A2)(B) The 450 is a bottom gate known as a channel protection type (also called a channel stop type). It is a type of staggered thin-film transistor, also known as an inverse staggered thin-film transistor.

[0143] Figure 3(A1) shows the gate wiring layer (formed in the same process as the gate electrode layer) and the source wiring layer ( Figure 3(A2) is a plan view of the intersection with the wiring layer (formed in the same process as the wiring layer), and shows a channel-protection type thin This is a plan view of the film transistor 450, and Figure 3(B) is a view of the line C3-C in Figures 3(A1) and (A2). This is a cross-sectional view along line 4 and line D3-D4.

[0144] Thin-film transistor 450 is a channel-protected thin-film transistor having an insulating surface. On the substrate 400, a gate electrode layer 451, a gate insulating layer 402, and at least a channel formation region An oxide having region 453, a high-resistance source region 454a, and a high-resistance drain region 454b. It includes a semiconductor layer 452, a source electrode layer 455a, and a drain electrode layer 455b. It covers the film transistor 450, is in contact with the channel formation region 413, and acts as a channel protection layer. An oxide insulating layer 456 is provided, and a protective insulating layer 408 is provided on top of it. ru.

[0145] The protective insulating layer 408 has openings that reach the source electrode layer 455a and the drain electrode layer 455b. (Contact holes) are formed, and wiring layers 457a, 457b, 458a, 45 8b is formed. Meanwhile, at the intersection, the gate wiring layer 421 and the source wiring layer 4 22 and 423 are in between the gate insulating layer 402, the oxide insulating layer 459, and the protective insulating layer 408. They are layered together via intermediaries.

[0146] Although it is not necessarily required to provide the oxide insulating layer 459 at the intersection, By providing this, the gate wiring layer 421 and the source wiring layers 422 and 423 can be moved further apart. Therefore, the parasitic capacity can be further reduced.

[0147] The oxide insulating layer 456 and oxide insulating layer 459 are formed by etching the oxide insulating layer. This can be achieved, and the materials and manufacturing method are the same as those for the oxide insulating layer 407 shown in Embodiment 1. This is sufficient. In this embodiment, an oxide insulating layer is formed using the sputtering method, and photolithography is used. The oxide insulating layer 456 and oxide insulating layer 459 are processed using a sography process.

[0148] Thus, the gate electrode layer (gate wiring layer) and the source electrode layer or drain electrode layer are electrically connected. The wiring layers that are directly connected are the protective insulating layer and gate insulating layer that cover the thin-film transistor, with these layers in between. The structure is such that the gate electrode layer, source electrode layer, and drain of the thin-film transistor intersect. The electrode layer consists of the gate electrode layer, gate insulating layer, and saw, except for a portion overlapping on the oxide semiconductor layer. It does not have a laminated structure consisting of a drain electrode layer or a s electrode layer.

[0149] Therefore, the stacked structure consists of a gate electrode layer, a gate insulating layer, and a source electrode layer or drain electrode layer. This reduces the parasitic capacitance formed by this process, enabling lower power consumption in semiconductor devices. Cut.

[0150] Furthermore, the thin-film transistor 450 will be explained using a single-gate thin-film transistor. However, if necessary, a thin film transistor with a multi-gate structure having multiple channel formation regions It can also form a "ta".

[0151] The following describes the process of fabricating a thin-film transistor 450 on a substrate, using Figures 4(A) to (F). explain.

[0152] First, a conductive film is formed on a substrate 400 having an insulating surface, and then a first photolithography is performed. The gate electrode layer 451 and gate wiring layer 421 are formed by the process. Note that a resist mask The resist mask may be formed by an inkjet method. Because it does not use a photomask, manufacturing costs can be reduced.

[0153] Furthermore, the materials for the gate electrode layer 451 and the gate wiring layer 421 are molybdenum, titanium, and Metal materials such as chromium, tantalum, tungsten, aluminum, copper, neodymium, and scandium It can be formed in a single layer or in layers using materials or alloy materials that mainly consist of these materials. ru.

[0154] Next, a gate insulating layer 402 is formed on the gate electrode layer 451 and the gate wiring layer 421. ru.

[0155] In this embodiment, the gate insulating layer 402 is made to a thickness of 200 nm or less by plasma CVD. It forms the silicon nitride layer below.

[0156] Next, an oxide semiconductor film with a thickness of 2 nm to 200 nm is formed on the gate insulating layer 402. This is achieved, and then processed into island-shaped oxide semiconductor layers by a second photolithography process. In terms of form, an In-Ga-Zn-O-based oxide semiconductor target is used as the oxide semiconductor film. The film is then deposited using the sputtering method.

[0157] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400°C to 750°C, preferably 400°C or higher, to reduce substrate strain. The value is set to less than 1. Here, a substrate is introduced into an electric furnace, which is one of the heat treatment devices, and an oxide semiconductor The body layer is subjected to a heat treatment at 450°C for 1 hour under a nitrogen atmosphere, and then exposed to air. Without doing so, water and hydrogen are prevented from being re-mixed into the oxide semiconductor layer, and the oxide semiconductor layer 441 is obtained. See Figure 4(A).

[0158] Next, plasma treatment is performed using a gas such as N2O, N2, or Ar. The process removes adsorbed water and other substances adhering to the surface of the exposed oxide semiconductor layer. Alternatively, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0159] Next, an oxide insulating layer was formed on the gate insulating layer 402 and the oxide semiconductor layer 441. Next, a resist mask is formed by a third photolithography process, followed by selective etching. After performing the following steps to form oxide insulating layer 456 and oxide insulating layer 459, the resist mask is removed. do.

[0160] In this embodiment, oxide insulating layer 456 and oxide insulating layer 459 are made of an oxide with a film thickness of 200 nm. A silicon dioxide film is deposited using the sputtering method. The substrate temperature during deposition is above room temperature, up to 300°C. The temperature should be below ℃, and in this embodiment, it is set to 100℃. Sputtering method for silicon oxide film The film deposition is carried out under a noble gas (typically argon) atmosphere, an oxygen atmosphere, or a noble gas ( This can typically be performed under an argon (or oxygen) atmosphere. Furthermore, the target and A silicon oxide target or silicon target can be used. For example, a silicon target Using a GET, silicon oxide films are formed by sputtering under oxygen and nitrogen atmospheres. This is possible. The oxide insulating layer 456 formed in contact with the low-resistance oxide semiconductor layer is Water, hydrogen ions, OH - It does not contain impurities such as these, and prevents them from entering from the outside. Using an inorganic insulating film to block, typically silicon oxide film, silicon nitride film, and aluminum oxide film are used. A um film or aluminum oxide nitride is used.

[0161] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. The temperature may be between 0°C and 400°C, for example between 250°C and 350°C. For example, A second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. During the second heat treatment, the acid A portion of the oxide semiconductor layer (channel formation region) is heated while in contact with the oxide insulating layer 456. ru.

[0162] In this embodiment, an oxide semiconductor is further provided with an oxide insulating layer 456, and a portion of it is exposed. Layer 441 is heat-treated under nitrogen, an inert gas atmosphere, or under reduced pressure. Oxide insulating layer 4 The region of the exposed oxide semiconductor layer 441 that is not covered by 56 is nitrogen, inert gas Heat treatment under a nitrogen atmosphere or reduced pressure can reduce resistance. For example, nitrogen Heat treatment is performed at 250°C for 1 hour under controlled conditions.

[0163] Heat treatment of an oxide semiconductor layer 441 provided with an oxide insulating layer 456 under a nitrogen atmosphere As a result, the exposed region of the oxide semiconductor layer 441 has low resistance, and the region with different resistance (Figure 4(B) In this case, the oxide semiconductor layer 452 has a shaded area and a white area.

[0164] Next, gold is placed on the gate insulating layer 402, the oxide semiconductor layer 452, and the oxide insulating layer 456. After forming the conductive film, a resist mask is formed by a fourth photolithography step. Selective etching was performed to form the source electrode layer 455a and the drain electrode layer 455b. Next, remove the resist mask (see Figure 4(C)).

[0165] The source electrode layer 455a and the drain electrode layer 455b have a film thickness of 0.1 nm to 50 nm. A thin film is preferred, and a film thinner than the wiring layer is used. Film thickness of the source electrode layer and drain electrode layer Because it is a thin conductive film, the parasitic capacitance with the gate electrode layer can be reduced.

[0166] The source electrode layer 455a and the drain electrode layer 455b contain a metal with high oxygen affinity. It is preferable to use materials. Furthermore, metals with high oxygen affinity mentioned above include titanium and aluminum. One of the following: nium, manganese, magnesium, zirconium, beryllium, or thorium It is preferable that the material is selected from multiple materials. In this embodiment, the source electrode layer 45 A titanium film is used for 5a and the drain electrode layer 455b.

[0167] When an oxide semiconductor layer is brought into contact with a metal layer with high oxygen affinity and subjected to heat treatment, the oxide semiconductor... Oxygen atoms move from the body layer to the metal layer, and the carrier density increases near the interface. A low-resistance region is formed near the interface, and the oxide semiconductor layer, source electrode layer and drain This can reduce the contact resistance with the in electrode layer.

[0168] Furthermore, heat-resistant conductive materials may be used for the source electrode layer 455a and the drain electrode layer 455b. i. When a heat-resistant conductive material is used, the source electrode layer 455a and the drain electrode layer 455b are formed Even if heat treatment is performed after formation, the source electrode layer 455a and drain electrode layer 455b will not change in quality or deteriorate. This can prevent that.

[0169] Examples of heat-resistant conductive materials include titanium (Ti), tantalum (Ta), and tungsten (W). Choose from molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc). The elements that have been identified, or alloys containing the aforementioned elements, or alloys combining the aforementioned elements. A film, or a nitride containing the aforementioned elements, can be used. By combining low-resistance conductive materials such as aluminum (Al) and copper (Cu) with the above-mentioned heat-resistant conductive materials... A conductive film with improved heat resistance may also be used.

[0170] Furthermore, the source electrode layer 455a and the drain electrode layer 455b may also contain a metal oxide layer. For example, a structure having a titanium oxide film between an oxide semiconductor layer and a titanium film, or a titanium film ( For example, a titanium oxide film (for example, a film with a thickness of 0.1 nm to 5 nm) is placed between the oxide insulating layer and the oxide insulating layer. The structure may have a thickness of 1 nm to 20 nm.

[0171] Furthermore, the source electrode layer 455a and the drain electrode layer 455b are made of a thin film that transmits light. In this case, the source electrode layer 455a and the drain electrode layer 455b are light-transmitting.

[0172] Through the above process, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After performing a heat treatment to reduce resistance, a portion of the oxide semiconductor film is selectively treated to remove excess oxygen. This is the state. As a result, the channel formation region 453 that overlaps with the gate electrode layer 451 is type I and This results in a high-resistance source region 454a overlapping the source electrode layer 455a, and a drain electrode layer 45 The high-resistance drain region 454b that overlaps with 5b is formed in a self-aligned manner. A film transistor 450 is formed.

[0173] Furthermore, a heat treatment is performed in air at a temperature between 100°C and 200°C for between 1 hour and 30 hours. This may also be done. In this embodiment, the heat treatment is performed at 150°C for 10 hours. This heat treatment is constant You may heat while maintaining the heating temperature, or you may heat from room temperature to a heating temperature of 100°C or higher and 200°C or higher. The heating and cooling process from the heating temperature back to room temperature may be repeated multiple times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This allows for a reduction in heating time. This heat treatment removes oxide from the oxide semiconductor layer. By incorporating hydrogen into the marginal layer, a thin-film transistor that is normally off can be obtained. Therefore, the reliability of semiconductor devices can be improved.

[0174] Furthermore, the oxide semiconductor layer superimposed on the drain electrode layer 455b (and source electrode layer 455a) To form a high-resistance drain region 454b (and a high-resistance source region 454a) in this region. This can improve the reliability of thin-film transistors. Specifically, high resistance drain By forming the in region 454b, the drain electrode layer 455b is separated into a high-resistance drain region 4 54b. The structure is designed so that the conductivity can be changed in steps in the channel formation region. This is possible. Therefore, the wiring that supplies the high power supply potential VDD to the drain electrode layer 415b is connected to it. When operating continuously, a high electric field is generated between the gate electrode layer 451 and the drain electrode layer 455b. Even when applied, the high-resistance drain region acts as a buffer, preventing a localized high electric field from being applied. This allows for a configuration that improves the pressure resistance of the ZISTA.

[0175] Source electrode layer 455a, drain electrode layer 455b, oxide insulating layer 456, oxide insulating layer 4 A protective insulating layer 408 is formed on 59. For example, silicon nitride using the RF sputtering method. A film is formed. RF sputtering is a method for forming the protective insulating layer 408 because it offers good mass production capabilities. It is preferable as a law. The protective insulating layer 408 is protected against moisture, hydrogen ions, and OH - Impurities such as It does not contain these substances, and uses an inorganic insulating film that blocks their intrusion from the outside, a silicon nitride film, Aluminum nitride film, silicon nitride film, aluminum oxide nitride, etc. are used. In this configuration, the protective insulating layer 408 is formed using a silicon nitride film (see Figure 4(D)).

[0176] Note that the source electrode layer 455a, drain electrode layer 455b, oxide insulating layer 456, oxide insulating An oxide insulating layer is further formed on the edge layer 459, and a protective insulating layer 408 is stacked on the oxide insulating layer. Layers may be added, or a planar insulating layer 409 as shown in Figure 6(A) may be formed. When the insulating layer 409 is provided, the distance between the gate wiring layer 421 and the source wiring layers 422 and 423 Because it becomes even longer, the parasitic capacity can be reduced further.

[0177] Next, a resist mask is formed by a fifth photolithography step, and then selectively etched. By performing a process to remove a portion of the protective insulating layer 408, the source electrode layer 455a and drain electrode are removed. Openings 467a and 467b are formed, reaching layer 455b (see Figure 4(E)).

[0178] Openings 467a and 467b are in contact with the source electrode layer 455a and the drain electrode layer 455b. A layered conductive layer is formed by sputtering or vacuum deposition, and the sixth photolithograph A resist mask is formed by the following process. The laminated conductive layer is selectively etched to form the wiring layer 4 57a, 457b, 458a, 458b, at the intersection, source wiring layers 422, 423 It forms (see Figure 4(F)).

[0179] Wiring layers 457a, 457b, 458a, and 458b are located further apart from the source electrode layer and the drain electrode layer. Use a conductive film with low resistance. Specifically, aluminum, copper, chromium, tantalum, molybdenum. Metal materials such as den, tungsten, titanium, neodymium, scandium, or these as the main components Using an alloy material, it can be formed in a single layer or in layers. In this embodiment, A laminated structure is used as the wiring layer, and the first wiring layers, wiring layers 457a and 457b, are made of aluminum. The nium film and the second wiring layers, wiring layers 458a and 458b, are made of titanium.

[0180] As described above, in a semiconductor device having a thin-film transistor using an oxide semiconductor layer, This makes it possible to reduce parasitic capacitance and provide a semiconductor device with low power consumption.

[0181] Furthermore, in a semiconductor device having a thin-film transistor using an oxide semiconductor layer, reliability We can provide high-performance semiconductor devices.

[0182] (Embodiment 3) In this embodiment, part of the manufacturing process for a semiconductor device having a thin-film transistor is described as an embodiment. Another example different from 1 is shown in Figure 5. Figure 5 is the same as Figures 1 and 2 except that the process is slightly different. Therefore, the same symbols will be used for the same sections, and detailed explanations of the same sections will be omitted. In terms of form, in the photolithography process, a mask layer formed by a multi-tone mask is Use.

[0183] A mask layer formed using a multi-gradation mask has a shape with multiple film thicknesses, and the mask layer By etching, the shape can be further deformed, allowing for different patterns. It can be used in multiple etching processes. Therefore, a single multi-gradation mask can be used. This allows for the formation of mask layers that correspond to at least two different patterns. Therefore, the number of exposure masks can be reduced, and the corresponding photolithography process can also be reduced. Therefore, the process can be simplified.

[0184] According to Embodiment 1, gates are arranged on the substrate 400 by a first photolithography process. A wire layer 421 and a gate electrode layer 481 are formed, and a gate insulating layer 402 is laminated. An oxide semiconductor film is formed on layer 402. In this embodiment, In is used as the oxide semiconductor film. - A film is deposited by sputtering using a Ga-Zn-O oxide semiconductor target.

[0185] As a dehydration or dehydrogenation process, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and oxides are produced. The semiconductor layer was subjected to a heat treatment at 450°C for 1 hour under a nitrogen atmosphere, and then exposed to air. Without any contamination, the re-importation of water and hydrogen into the oxide semiconductor layer is prevented, and an oxide semiconductor film 465 is obtained. ru.

[0186] Next, a metal conductive film 466 is applied to the oxide semiconductor film 465 by sputtering or vacuum deposition. Formed by (see Figure 5(A)).

[0187] The metal conductive film 466 is a conductive film that serves as the source electrode layer and the drain electrode layer. The drain electrode layer is preferably a thin film with a thickness of 0.1 nm to 50 nm, and is thinner than the wiring layer. A thin film is used. Because the thickness of the source electrode layer and drain electrode layer is a thin conductive film, This can reduce the parasitic capacitance with the electrode layer.

[0188] The source electrode layer and drain electrode layer use materials containing metals with high oxygen affinity. This is preferable. Furthermore, the metals with high oxygen affinity mentioned above include titanium, aluminum, and manganese. Select one or more of the following: magnesium, zirconium, beryllium, or thorium. It is preferable that the material is made of a material that has been treated. In this embodiment, the source electrode layer and the drain electrode layer are A titanium film is used.

[0189] When an oxide semiconductor layer is brought into contact with a metal layer with high oxygen affinity and subjected to heat treatment, the oxide semiconductor... Oxygen atoms move from the body layer to the metal layer, and the carrier density increases near the interface. A low-resistance region is formed near the interface, and the oxide semiconductor layer, source electrode layer and drain This can reduce the contact resistance with the in electrode layer.

[0190] Furthermore, heat-resistant conductive materials may be used for the source electrode layer and the drain electrode layer. When using this material, even if heat treatment is performed after the source electrode layer and drain electrode layer are formed, the source electrode This prevents alteration and deterioration of the layer and the drain electrode layer.

[0191] Examples of heat-resistant conductive materials include titanium (Ti), tantalum (Ta), and tungsten (W). Choose from molybdenum (Mo), chromium (Cr), neodymium (Nd), and scandium (Sc). The elements that have been identified, or alloys containing the aforementioned elements, or alloys combining the aforementioned elements. A film, or a nitride containing the aforementioned elements, can be used. By combining low-resistance conductive materials such as aluminum (Al) and copper (Cu) with the above-mentioned heat-resistant conductive materials... A conductive film with improved heat resistance may also be used.

[0192] Furthermore, the source electrode layer and the drain electrode layer may also contain a metal oxide layer, for example, a metal oxide layer. A structure having a titanium oxide film between the conductive layer and the titanium film, or a titanium film (for example, a film thickness of 0.1 A titanium oxide film (for example, film thickness of 1 nm or more and 20 nm or less) is placed between the oxide insulating layer and the oxide insulating layer. The structure may also have elements less than or equal to nm.

[0193] Furthermore, if the source electrode layer and drain electrode layer are thin films that transmit light, The electrode layer and the drain electrode layer are translucent.

[0194] A second photolithography process is performed on the oxide semiconductor film 465 and the metal conductive film 466. A resist mask 460 is formed on it.

[0195] In this embodiment, exposure using a high-gradation mask is performed to form the resist mask 460. An example of what to do is shown. A resist is formed to create a resist mask 460. The resist is Positive or negative resists can be used. Here, a positive resist is used. This is shown using [a specific method]. The resist may be formed by spin coating or by inkjet. It may be formed selectively. If the resist is formed selectively by the inkjet method, unwanted areas can be formed. Since the formation of resist can be reduced, material waste can be minimized.

[0196] Next, using a multi-gradation mask 81 as an exposure mask, the resist is irradiated with light, Expose it to light.

[0197] Here, we will explain exposure using a multi-gradation mask 81 with reference to Figure 25.

[0198] A multi-gradation mask applies three exposure levels to the exposed area, the mid-exposed area, and the unexposed area. This is a mask that allows for exposure, where transmitted light has multiple intensities. A resist mask having multiple (typically two) thickness regions due to light and development processes. It is possible to form this. Therefore, by using a multi-gradation mask, the number of exposure masks It is possible to reduce the number.

[0199] A typical example of a multi-tone mask is the gray tone mask 81a shown in Figure 25(A). There is a halftone mask 81b as shown in Figure 25(C).

[0200] As shown in Figure 25(A), the gray tone mask 81a is placed on the translucent substrate 83 and on the surface thereof It consists of a light-shielding portion 84 and a diffraction grating 85. The transient is 0%. On the other hand, the diffraction grating 85 has light-transmitting parts such as slits, dots, and meshes. By setting the interval to be less than or equal to the resolution limit of the light used for exposure, the transmittance of light can be controlled. This is possible. The diffraction grating 85 can be a periodic slit, dot, mesh, or non Periodic slits, dots, or meshes can all be used.

[0201] As the translucent substrate 83, a translucent substrate such as quartz can be used. The folded lattice 85 can be formed using light-absorbing light-shielding materials such as chromium or chromium oxide. Cut.

[0202] When exposure light is shone on the gray tone mask 81a, the light-shielding portion is as shown in Figure 25(B). In 84, the light transmittance 86 is 0%, and the light-shielding portion 84 and the diffraction grating 85 are provided. In areas where there is no light, the light transmittance of 86 is 100%. Also, in diffraction grating 85, 10~ It is adjustable within a 70% range. The adjustment of the light transmittance in the diffraction grating 85 is done by the diffraction grating. This can be achieved by adjusting the spacing and pitch of slits, dots, or meshes.

[0203] As shown in Figure 25(C), the halftone mask 81b is placed on the translucent substrate 83 and on the translucent substrate 83. It is composed of a semi-transparent portion 87 and a light-shielding portion 88. The semi-transparent portion 87 is made of MoSiN, MoSi, MoSiO, MoSiON, CrSi, etc. can be used. Light-shielding part 88 These can be formed using light-absorbing light-shielding materials such as chromium or chromium oxide.

[0204] When exposure light is shone on the halftone mask 81b, the light-shielding portion appears as shown in Figure 25(D). In 88, the light transmittance 89 is 0%, and a light-shielding portion 88 and a semi-transparent portion 87 are provided. In areas where there is no light, the light transmittance 89 is 100%. Also, in the semi-transparent area 87, 10~ It is adjustable within a range of 70%. The light transmittance in the semi-transparent part 87 is adjusted by the semi-transparent part 8 It can be adjusted using 7 different materials.

[0205] After exposure using a multi-tone mask and then development, different film thicknesses are achieved as shown in Figure 5(B). A resist mask 460 having a region can be formed.

[0206] Next, the first etching process is performed using the resist mask 460 to create an oxide semiconductor film 46 5. The metal conductive film 466 is etched and processed into island shapes. As a result, the oxide semiconductor layer 461 A metallic conductive layer 462 can be formed (see Figure 5(B)).

[0207] Next, the resist mask 460 is ashing. As a result, the area of ​​the resist mask (3rd) Originally, the volume (of the film) decreases and the thickness becomes thinner. At this time, the resist in the thin film area The resist of the screen (the region overlapping with part of the gate electrode layer 481) is removed, and the separated resin Dist masks 463a and 463b can be formed.

[0208] Using resist masks 463a and 463b, unwanted parts are removed by etching. A drain electrode layer 485a and a drain electrode layer 485b are formed (see Figure 5(C)).

[0209] Furthermore, when etching the metal conductive layer 462, the oxide semiconductor layer 461 is not removed. The respective materials and etching conditions are adjusted as appropriate.

[0210] In this embodiment, a Ti film is used as the metal conductive layer 462, and the oxide semiconductor layer 461 is Using an In-Ga-Zn-O system oxide, ammonia peroxide (ammo) is used as the etchant. Use a mixture of hydrogen peroxide, water, and hydrogen peroxide solution.

[0211] Note that the etching of metal conductive films and oxide semiconductor films discussed here is limited to wet etching. Dry etching may be used instead.

[0212] Etching gases used in dry etching include chlorine-containing gases (chlorine-based gases, for example) Chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (CC) l4) etc.) are preferable.

[0213] Also, fluorine-containing gases (fluorinated gases, such as carbon tetrafluoride (CF4) and sulfur fluoride (SF4)) 6) Nitrogen fluoride (NF3), trifluoromethane (CHF3), etc., hydrogen bromide (HBr ), oxygen (O2), and noble gases such as helium (He) and argon (Ar) are added to these gases. Added gases, etc., can be used.

[0214] As for dry etching methods, parallel plate type RIE (Reactive Ion Etching) Methods such as the ing method and ICP (Inductively Coupled Plasma: induction) A coupled plasma etching method can be used. The desired processing shape can be etched. To that end, etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) Adjust the amount of power used, the electrode temperature on the substrate, etc., as appropriate.

[0215] The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid, Ammonia Hydrogenated Water (31% hydrogen peroxide by weight: 28% ammonia by weight: water = 5:2:2) These can be used. Alternatively, ITO07N (manufactured by Kanto Chemical Co., Ltd.) may be used.

[0216] Furthermore, the etching solution after wet etching is washed away along with the etched material. The material is removed. The waste etching solution containing the removed material is purified, and the material contained in it is removed. It may be reused. Indium and other elements contained in the oxide semiconductor layer can be extracted from the waste liquid after etching. By recovering and reusing materials, resources can be used effectively and costs can be reduced. .

[0217] Etching conditions (etching) can be adjusted according to the material so that the desired processing shape can be etched. Adjust the solution, etching time, temperature, etc. as appropriate.

[0218] Next, remove the resist masks 463a and 463b, and the protective layer in contact with the oxide semiconductor layer 461. An oxide insulating layer 407, which will be an insulating film, is formed. In this embodiment, the oxide insulating layer 407 and Then, a silicon oxide film with a thickness of 200 nm is deposited using the sputtering method.

[0219] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. Perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). For example, under a nitrogen atmosphere. A second heat treatment is performed at 250°C for 1 hour under gas pressure. After the second heat treatment, the oxide semiconductor A portion of the body layer (channel-forming region) is heated while in contact with the oxide insulating layer 407.

[0220] Through the above process, the oxide semiconductor film after deposition is dehydrated or dehydrogenated. After performing a heat treatment to reduce resistance, a portion of the oxide semiconductor film is selectively treated to remove excess oxygen. This is the state. As a result, the channel formation region 483 that overlaps with the gate electrode layer 481 is type I and This results in a high-resistance source region 484a overlapping the source electrode layer 485a, and a drain electrode layer 48 The high-resistance drain region 484b that overlaps with 5b is formed in a self-aligned manner. A film transistor 480 is formed.

[0221] Furthermore, a heat treatment is performed in air at a temperature between 100°C and 200°C for between 1 hour and 30 hours. This may also be done. In this embodiment, the heat treatment is performed at 150°C for 10 hours. This heat treatment is constant You may heat while maintaining the heating temperature, or you may heat from room temperature to a heating temperature of 100°C or higher and 200°C or higher. The heating and cooling process from the heating temperature back to room temperature may be repeated multiple times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This allows for a reduction in heating time. This heat treatment removes oxide from the oxide semiconductor layer. By incorporating hydrogen into the marginal layer, a thin-film transistor that is normally off can be obtained. Therefore, the reliability of semiconductor devices can be improved.

[0222] A protective insulating layer 408 is formed on the oxide insulating layer 407. In this embodiment, the protective insulating layer and Then, a protective insulating layer 408 is formed using a silicon nitride film (see Figure 5(D)).

[0223] Next, a resist mask is formed by a third photolithography process, and then selectively etched. By performing a process to remove a portion of the oxide insulating layer 407 and the protective insulating layer 408, the source electrode layer 4 85a forms openings 464a and 464b that reach the drain electrode layer 485b (Figure 5(E) )reference.).

[0224] Openings 464a and 464b are in contact with the source electrode layer 485a and the drain electrode layer 485b. A layered conductive layer is formed by sputtering or vacuum deposition, and a fourth photolithograph is used. A resist mask is formed by the following process. The laminated conductive layer is selectively etched to form the wiring layer 4 87a, 487b, 488a, 488b, at the intersection, source wiring layers 422, 423 It forms (see Figure 5(F)).

[0225] Wiring layers 487a, 487b, 488a, and 488b are located further apart from the source electrode layer and the drain electrode layer. Use a conductive film with low resistance. Specifically, aluminum, copper, chromium, tantalum, molybdenum. Metal materials such as den, tungsten, titanium, neodymium, scandium, or these as the main components Using an alloy material, it can be formed in a single layer or in layers. In this embodiment, A laminated structure is used as the wiring layer, and the first wiring layers, wiring layers 487a and 487b, are made of aluminum. The nium film and the second wiring layers, wiring layers 488a and 488b, are made of titanium.

[0226] As described above, in a semiconductor device having a thin-film transistor using an oxide semiconductor layer, This makes it possible to reduce parasitic capacitance and provide a semiconductor device with low power consumption.

[0227] Furthermore, in a semiconductor device having a thin-film transistor using an oxide semiconductor layer, reliability We can provide high-performance semiconductor devices.

[0228] This embodiment can be implemented in appropriate combination with other embodiments.

[0229] (Embodiment 4) In this embodiment, in Embodiment 1, a transparent conductive material is used for the gate electrode layer. An example is shown in Figure 7. Therefore, the rest can be done in the same way as in Embodiment 1. The explanation of parts that are identical or have similar functions, and the repetition of processes, will be omitted. Figure 7 is the same as Figures 1 and 2 except for some differences in the process, therefore the same symbols are used in the same locations. We will use a number and omit detailed explanations of the same section.

[0230] The thin-film transistor 430 shown in Figure 7 is a channel-etch type thin-film transistor, and is an insulating A gate electrode layer 431, a gate insulating layer 402, and at least one ch The channel formation region 433, the high-resistance source region 434a, and the high-resistance drain region 434b It includes an oxide semiconductor layer 432, a source electrode layer 435a, and a drain electrode layer 435b. Furthermore, an oxide insulating layer 4 covers the thin-film transistor 430 and is in contact with the channel formation region 433. A layer 07 is provided, and a protective insulating layer 408 is provided on top of it.

[0231] The oxide insulating layer 407 and the protective insulating layer 408 have openings (con) that reach the source electrode layer 435a. A tact hole is formed, and wiring layers 437 and 438 are formed in the opening. In the gap, the gate wiring layer 421 and the source wiring layers 422 and 423 are connected by the gate insulating layer 4 02. The oxide insulating layer 407 and the protective insulating layer 408 are laminated with an oxide insulating layer 407 in between. See Figure 7. An opening reaching the source electrode layer 435a shown and wiring layers 437, 438 provided in the opening As shown above, the openings and wiring layers may be provided in regions that do not overlap with the oxide semiconductor layer 432.

[0232] Thus, the gate electrode layer (gate wiring layer) and the source electrode layer or drain electrode layer are electrically connected. The wiring layers that are directly connected are the insulating layer and gate insulating layer that cover the oxide semiconductor layer of the thin-film transistor. The structure is such that the layers intersect with a marginal layer in between. This is the gate electrode layer and source electrode layer of a thin-film transistor. The drain electrode layer and the gate electrode layer overlap only partially on the oxide semiconductor layer, and the gate insulating layer. It does not have a layered structure consisting of a layer and a source electrode layer or a drain electrode layer.

[0233] Therefore, the stacked structure consists of a gate electrode layer, a gate insulating layer, and a source electrode layer or drain electrode layer. This reduces the parasitic capacitance formed by this process, enabling lower power consumption in semiconductor devices. Cut.

[0234] A planar insulating layer 409 is formed on the wiring layer 438, the source wiring layer 423, and the protective insulating layer 408. Furthermore, a pixel electrode layer 427 is provided on the planar insulating layer 409. Pixel electrode layer 427 The thin film transistor is in contact with the wiring layer 438 through an opening formed in the planarized insulating layer 409. The zista 430 and the pixel electrode layer 427 are electrically connected via wiring layers 437 and 438. ru.

[0235] The source electrode layer 435a and the drain electrode layer 435b are thin metal conductive films and therefore have light transmission properties. It can be a conductive film having the properties of [the specified material].

[0236] Furthermore, in Figure 7, the gate electrode layer 431 of the thin-film transistor 430 also has light-transmitting properties. Use an electroluminescent film.

[0237] The material of the gate electrode layer 431 is a conductive material that is transparent to visible light, such as In-S nO series, In-Sn-Zn-O series, In-Al-Zn-O series, Sn-Ga-Zn-O series , Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, Sn-Zn- Apply metal oxides of the following types: O-based, Al-Zn-O-based, In-O-based, Sn-O-based, and Zn-O-based. The film thickness can be appropriately selected within the range of 50 nm to 300 nm. (Gate plate layer) The metal oxide film deposition methods used for 431 include sputtering and vacuum deposition (electron beam vapor deposition). Methods such as coating, arc discharge ion plating, and spraying are used. When using the tarring method, a target containing 2% to 10% by weight of SiO2 is used. The film is then formed, and the transparent conductive film contains SiOx (X>0) which inhibits crystallization. This prevents crystallization during subsequent heat treatments for dehydration or dehydrogenation. It is preferable to control it.

[0238] Therefore, the thin-film transistor 430 can be a thin-film transistor that is transparent to light. .

[0239] Furthermore, pixels on which thin-film transistors 430 are placed have a pixel electrode layer 427, or other The electrode layer (such as a capacitive electrode layer) and other wiring layers (such as a capacitive wiring layer) are transparent to visible light. A display device with a high aperture ratio is realized using a photosensitive conductive film. Of course, the gate insulating layer 402, the oxide insulating layer 407, and the protective insulating layer 408 are also films that are transparent to visible light. It is preferable that they be present.

[0240] In this specification, a film that is transparent to visible light is defined as a film with a visible light transmittance of 75 to 100. This refers to a film with a thickness of %; if the film is conductive, it is also called a transparent conductive film. Also, gate electrode layer, source electrode layer, drain electrode layer, pixel electrode layer, or other electrodes As a metal oxide applied to the layer and other wiring layers, a conductive film that is semi-transparent to visible light is used. It is acceptable. Semi-transparent to visible light means that the transmittance of visible light is between 50% and 75%. .

[0241] Because the thin-film transistor 430 is light-transmitting, the aperture ratio can be improved. In small LCD display panels of 10 inches or less, the number of gate wires can be increased to improve the display. To achieve higher resolution in displayed images, even when pixel dimensions are reduced, a high aperture ratio can be achieved. It is possible. Furthermore, by using a light-transmitting film as a component of the thin-film transistor 430, To achieve a wide viewing angle, a high aperture ratio is achieved even when one pixel is divided into multiple subpixels. This is possible. In other words, even when arranging a high-density group of thin-film transistors, a large aperture ratio can be achieved. This allows for sufficient display area. For example, 2 to 4 pixels within a single pixel. When there are multiple subpixels, the thin-film transistor is light-transmitting, thus improving the aperture ratio. It can be made possible to retain the components of thin-film transistors using the same process and materials. By forming a volume, the retained volume can also be made light-transmitting, further improving the aperture ratio. It is possible.

[0242] This embodiment can be implemented in appropriate combination with other embodiments.

[0243] (Embodiment 5) In this embodiment, Figure 8 shows an example where part of the thin-film transistor fabrication process differs from that of Embodiment 1. As shown, Figure 8 is the same as Figures 1 and 2 except that the process is slightly different, so in the same place The same symbols are used, and detailed explanations of the same sections are omitted.

[0244] According to Embodiment 1, a gate wiring layer 421 and a gate electrode layer 471 are formed on the substrate 400. Then, a gate insulating layer 402 is laminated.

[0245] Next, an oxide semiconductor film is formed, and the oxide semiconductor film is processed using a photolithography process to create island-like structures. It is processed into an oxide semiconductor layer.

[0246] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature for the heat treatment in step 1 shall be 400°C or higher and 750°C or lower for the substrate, preferably 425°C or higher. Furthermore, if the temperature is 425°C or higher, the heat treatment time can be 1 hour or less, but if it is below 425°C... If so, the heat treatment time shall be longer than 1 hour. Here, one of the heat treatment apparatuses The substrate is introduced into an electric furnace, and the oxide semiconductor layer is heat-treated under a nitrogen atmosphere. After this process, without exposure to the atmosphere, the re-incorporation of water and hydrogen into the oxide semiconductor layer is prevented, and oxidation occurs. A material semiconductor layer is obtained. Then, high-purity oxygen gas, high-purity N2O gas, or ultra-dry gas is introduced into the same furnace. Cooling is performed by introducing dry air (dew point of -40°C or lower, preferably -60°C or lower). It is preferable that the gas or N2O gas does not contain water, hydrogen, etc. Alternatively, heat treatment equipment The purity of the oxygen gas or N2O gas introduced into the device should preferably be 6N (99.9999%) or higher. Or 7N (99.99999%) or higher (i.e., the concentration of impurities in oxygen gas or N2O gas) It is preferable to set the concentration to 1 ppm or less, preferably 0.1 ppm or less.

[0247] Furthermore, the heating apparatus is not limited to electric furnaces; for example, GRTA (Gas Rapid Th) thermal annealing) equipment, LRTA (Lamp Rapid Thermal) Using RTA (Rapid Thermal Anneal) devices such as Anneal devices It is possible to use a LRTA device with halogen lamps, metal halide lamps, and xenon lamps. Arc lamps, carbon arc lamps, high-pressure sodium lamps, high-pressure mercury lamps, etc. This device heats the object being processed by radiating light (electromagnetic waves) from a lamp. The TA device utilizes not only lamps but also heat conduction or thermal radiation from heat-generating elements such as resistive heating elements. It may also be equipped with a device to heat the material to be processed. GRTA is a device that uses high-temperature gas to process This is a method of heat treatment. The gas used is a noble gas such as argon, or a gas such as nitrogen, which is heated. An inert gas that does not react with the material being treated is used during the process. Using the RTA method, 600 Heat treatment at 750°C for several minutes may also be performed.

[0248] Furthermore, after the first heat treatment in which dehydration or dehydrogenation is performed, the temperature is preferably between 200°C and 400°C. Alternatively, heating treatment at a temperature between 200°C and 300°C under an oxygen or N2O gas atmosphere. It is permissible to act rationally.

[0249] Furthermore, the first heat treatment of the oxide semiconductor layer is performed on the oxide before it is processed into an island-shaped oxide semiconductor layer. This can also be done on semiconductor films. In that case, after the first heat treatment, the substrate is removed from the heating device. The material is removed and the photolithography process is performed.

[0250] By going through the above process, the entire oxide semiconductor film is made into an oxygen-rich state, The material is converted to type I, i.e., type I. Thus, an oxide semiconductor layer 472 that is entirely type I is obtained.

[0251] Next, a resist mask is formed on the oxide semiconductor layer 472 by a photolithography process. The source electrode layer 475a and drain electrode layer 475b are formed by selective etching. Then, an oxide insulating layer 407 is formed by sputtering.

[0252] Next, in order to reduce variations in the electrical characteristics of thin-film transistors, under an inert gas atmosphere or perform heat treatment under a nitrogen gas atmosphere (preferably 150°C or higher and less than 350°C). Alternatively, a heat treatment may be performed at 250°C for 1 hour under a nitrogen atmosphere.

[0253] Furthermore, heat treatment is performed in air at temperatures between 100°C and 200°C for between 1 hour and 30 hours. This may also be done. In this embodiment, the heat treatment is performed at 150°C for 10 hours. This heat treatment is constant You may heat while maintaining the heating temperature, or you may heat from room temperature to a heating temperature of 100°C or higher and 200°C or higher. The heating and cooling process from the heating temperature back to room temperature may be repeated multiple times. The heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This allows for a reduction in heating time. This heat treatment removes oxide from the oxide semiconductor layer. By incorporating hydrogen into the marginal layer, a thin-film transistor that is normally off can be obtained. Therefore, the reliability of semiconductor devices can be improved.

[0254] Next, a protective insulating layer 408 is formed on the oxide insulating layer 407.

[0255] Next, a resist mask is formed by a photolithography process, and selective etching is performed. The oxide insulating layer 407 and a portion of the protective insulating layer 408 are removed, and the source electrode layer 475a is removed. This forms an opening that reaches the drain electrode layer 475b.

[0256] Sputtering method applied to the opening so as to be in contact with the source electrode layer 475a and the drain electrode layer 475b A layered conductive layer is formed by vacuum deposition, and a resist mass is formed by photolithography. Forms a cross. Selectively etch the laminated conductive layer to form wiring layers 477a, 477b, 478 At the intersections of a and 478b, source wiring layers 422 and 423 are formed (see Figure 8). .

[0257] As described above, in a semiconductor device having a thin-film transistor using an oxide semiconductor layer, This makes it possible to reduce parasitic capacitance and provide a semiconductor device with low power consumption.

[0258] Furthermore, in a semiconductor device having a thin-film transistor using an oxide semiconductor layer, reliability We can provide high-performance semiconductor devices.

[0259] This embodiment can be implemented in appropriate combination with other embodiments.

[0260] (Embodiment 6) In this embodiment, in Embodiment 1, the oxide semiconductor layer and the source electrode layer or drain Figure 9 shows an example in which an oxide conductive layer is provided between the electrode layer as a source region and a drain region. Therefore, the rest can be carried out in the same manner as in Embodiment 1, and the same parts or the same parts as in Embodiment 1. The explanation of parts with various functions and the repetition of processes will be omitted. Also, Figure 9 is a comparison with Figure 1 and Since it is the same as Figure 2 except for some differences in the process, the same symbols are used for the same parts. I will omit a detailed explanation of the place.

[0261] The thin-film transistor 469 shown in Figure 9 is a channel-etch type thin-film transistor, and is an insulating... A gate electrode layer 411, a gate insulating layer 402, and at least one ch The channel formation region 413, the high-resistance source region 414a, and the high-resistance drain region 414b The oxide semiconductor layer 412, oxide conductive layers 416a, 416b, and source electrode layer 415a are included. , and includes a drain electrode layer 415b. It also covers the thin-film transistor 469 and channel An oxide insulating layer 407 is provided in contact with the formation region 413, and a protective insulating layer 40 is further placed on top of it. An 8 is provided.

[0262] According to Embodiment 1, a gate wiring layer 421 and a gate electrode layer 411 are formed on the substrate 400. Then, a gate insulating layer 402 is laminated. An oxide semiconductor film is formed on the gate insulating layer 402. A dehydrated or dehydrogenated oxide semiconductor layer is formed.

[0263] Oxide conductive layers 416a and 416b are formed on a dehydrated or dehydrogenated oxide semiconductor layer. In this embodiment, the oxide conductive layers 416a and 416b are made of the same photopolymer as the oxide semiconductor layer. An example of shaping by lithography is shown, but oxide conductive layers 416a and 416b The shape is processed by the same photolithography process as the source electrode layer and drain electrode layer. That's fine.

[0264] The methods for depositing the oxide conductive layers 416a and 416b include sputtering and vacuum deposition (electron vapor deposition). Methods such as vapor deposition, arc discharge ion plating, and spraying are used. The materials for the conductive layers 416a and 416b preferably contain zinc oxide as a component. It is preferable that it does not contain indium oxide. Such oxide conductive layer 416 a, 416b are zinc oxide, zinc aluminum oxide, zinc aluminum oxynitride, oxide Zinc gallium and other materials can be used. The film thickness is within the range of 50 nm to 300 nm. Select as appropriate. Also, when using the sputtering method, SiO2 should be 2% by weight or more per 10 layers. Film deposition is performed using a target containing less than % of SiOx, which inhibits crystallization in oxide conductive films. (X>0) is included, and crystals are formed during the heat treatment for dehydration or dehydrogenation in a later step. It is preferable to suppress the transformation process.

[0265] In this embodiment, the oxide conductive layers 416a and 416b are photolithographically treated, similar to the oxide semiconductor layer. After the shape is processed by the roughing process, the source electrode layer 415a and the drain electrode layer 415b Using this as a mask, the oxide conductive layer is further etched, and oxide conductive layers 416a and 416b The oxide conductive layers 416a and 416b, which have zinc oxide as a component, are, for example, resists. It can be easily etched using an alkaline solution such as a stripping agent.

[0266] By utilizing the difference in etching rates between the oxide semiconductor layer and the oxide conductive layer, a channel region is formed. To separate the oxide conductive layer, an etching process is performed. By taking advantage of the fact that the pulsation rate is faster compared to the oxide semiconductor layer, the oxide conductive layer on the oxide semiconductor layer The layers are selectively etched.

[0267] Therefore, the resist mask used for forming the source electrode layer 415a and the drain electrode layer 415b Removal of the material is preferably done by an ashing process. Etching using a stripping solution In this case, to prevent the oxide conductive layer and oxide semiconductor layer from being excessively etched, Adjust the etching conditions (etchant type, concentration, etching time) as appropriate.

[0268] An oxide semiconductor layer 412 and a drain electrode layer 415b made of a metal material are provided between the oxide semiconductor layer 412 and the drain electrode layer 415b The material conductive layer 416b is a low-resistance drain region (LRN (Low Resistance N-) type conductivity) region, LRD (Low Resistance) region It also functions as a Drain region. Similarly, the oxide semiconductor layer 412 and the metal material The oxide conductive layer 416a provided between the source electrode layers 415a, which are made of material, is a low-resistance drain LRN (Low Resistance N-type conduction region) (Also called the ty) region, or LRS (Low Resistance Source) region) It still functions. The drain electrode consists of an oxide semiconductor layer, a low-resistance drain region, and a metallic material. By using a layered configuration, the transistor's voltage rating can be further improved. In general, the carrier concentration in the low-resistance drain region is higher than in the high-resistance drain region (HRD region). It can also be large, for example, 1 x 10 20 / cm 3 The above 1 x 10 21 / cm 3 Within the following range preferable.

[0269] The source region and drain region consist of an oxide conductive layer, an oxide semiconductor layer and a source electrode layer and By placing it between the drain electrode layer, the resistance of the source region and the drain region can be reduced. This enables high-speed operation of the transistor. The use of an oxide conductive layer is intended to improve the frequency characteristics of the peripheral circuit (drive circuit). It is effective for this purpose. Compared to contact between a metal electrode (Ti, etc.) and an oxide semiconductor layer, This is because contact between the ) and the oxide conductive layer can reduce contact resistance.

[0270] Furthermore, molybdenum (Mo), which is used as part of the wiring material in semiconductor devices, is (for example) The problem was that the contact resistance with the oxide semiconductor layer (Mo / Al / Mo) was high. Compared to Ti, Mo is less prone to oxidation, so it has a weaker effect of extracting oxygen from the oxide semiconductor layer, M This is because the contact interface between oxygen and the oxide semiconductor layer does not become n-type. However, even in such cases, acid An oxide conductive layer is interposed between the oxide semiconductor layer and the source electrode layer and drain electrode layer. This reduces contact resistance and improves the frequency characteristics of the surrounding circuitry (drive circuitry).

[0271] The channel length of a thin-film transistor is determined during the etching of the oxide conductive layer, therefore It is possible to shorten the channel length. For example, the channel length can be shortened to 0.1 μm or more and 2 μm or less. It can increase the operating speed.

[0272] Although Embodiment 1 has been described as an example, this embodiment can be appropriately combined with other embodiments. It is possible to implement this.

[0273] As described above, in a semiconductor device having a thin-film transistor using an oxide semiconductor layer, This makes it possible to reduce parasitic capacitance and provide a semiconductor device with low power consumption.

[0274] Furthermore, in a semiconductor device having a thin-film transistor using an oxide semiconductor layer, reliability We can provide high-performance semiconductor devices.

[0275] (Embodiment 7) In this embodiment, Figure 10 shows an example where the oxide semiconductor layer is surrounded by a nitride insulating film when viewed in cross-section. Figure 10 shows the differences between the top surface shape and edge position of the oxide insulating layer and the gate insulating layer in Figure 1. Since they are the same except for the differences in structure, the same symbols are used for the same parts, and the details of the same parts I will omit the explanation.

[0276] Thin-film transistor 410 is a channel-etch type thin-film transistor and has an insulating surface. A gate electrode layer 411 and a first gate insulating layer 49 made of a nitride insulating film are placed on the substrate 400. 2a, a second gate insulating layer 492b made of an oxide insulating film, at least a channel forming region 413, an oxide semiconductor having a high-resistance source region 414a and a high-resistance drain region 414b It includes a conductive layer 412, a source electrode layer 415a, and a drain electrode layer 415b. The oxide semiconductor layer covering the transistor 410 is in contact with the channel formation region of the oxide semiconductor layer 412. An edge layer 497b is provided. A protective insulating layer 498 is further provided on the oxide insulating layer 497b. It is formed.

[0277] The oxide insulating layer 497b and the protective insulating layer 498 have a source electrode layer 415a and a drain electrode layer. An opening (contact hole) is formed that reaches the pole layer 415b, and the wiring layer 417a is located in the opening. 417b, 418a, and 418b are formed. Meanwhile, at the intersection, gate wiring Layer 421 and source wiring layers 422 and 423 are connected to the gate insulating layer 402 and oxide insulating layer 497a. The layers are laminated with a protective insulating layer 498 in between.

[0278] In this embodiment, in the thin-film transistor 410, the gate insulating layer is from the gate electrode layer side. A laminated structure consisting of a nitride insulating film and an oxide insulating film is formed. In addition, openings are formed in the oxide insulating layer. In the process, the oxide insulating film of the second gate insulating layer is also selectively removed, exposing the nitride insulating film. Process the sea urchin.

[0279] At least the upper surface shape of the oxide insulating layer 497b and the second gate insulating layer 492b is oxide semiconductor The top surface shape is wider than that of the conductive layer 412 and covers the thin-film transistor 410. It is preferable.

[0280] Furthermore, the top and side surfaces of the oxide insulating layer 497b are covered, and the first gate insulating layer 492a A protective insulating layer 498 made of a nitride insulating film is formed in contact with the nitride insulating film.

[0281] The protective insulating layer 498 and the first gate insulating layer 492a, which are made of a nitride insulating film, are sputtered Silicon nitride films, silicon oxide nitride films, and aluminum nitride films obtained by the CVD method and plasma CVD method. , water, hydrogen ions, and OH in aluminum oxide and nitride films, etc. - It does not contain impurities such as, An inorganic insulating film is used to block these from entering from the outside.

[0282] In this embodiment, the protective insulating layer 498 made of a nitride insulating film is an oxide semiconductor layer 41 RF sputtering was used to surround the top and sides of part 2, creating a silicon nitride film thickness of 100 nm. A base film is provided. In addition, the protective insulating layer 498 is a first gate insulating layer 49 made of a nitride insulating film. The configuration will be such that it is in contact with 2a.

[0283] By adopting the structure shown in Figure 10, the manufacturing process after the formation of the protective insulating layer 498 made of nitride insulating film is performed. In the process, it is possible to prevent the intrusion of moisture from the outside. Also, semiconductor devices, for example Even after the device is completed as a liquid crystal display, it will not be able to prevent moisture from entering from the outside over the long term. This can improve the long-term reliability of the device.

[0284] Furthermore, this embodiment shows a configuration in which one thin-film transistor is surrounded by a nitride insulating film, but The configuration is not limited to this, and multiple thin-film transistors may be surrounded by a nitride insulating film, or pixels A configuration in which multiple thin-film transistors are grouped together and surrounded by a nitride insulating film is also possible. A protective insulating layer 498 and a first gate surround the periphery of the pixel area of ​​the active matrix substrate. The configuration should include a region in contact with the insulating layer 492a.

[0285] This embodiment can be implemented in appropriate combination with other embodiments.

[0286] (Embodiment 8) In this embodiment, in the semiconductor device shown in Embodiments 1 to 7, thin-film transistor And, using an electroluminescent light-emitting element, an active matrix type This shows an example of how to fabricate a light-emitting display device.

[0287] Light-emitting devices that utilize electroluminescence use either organic or inorganic light-emitting materials. They are distinguished by whether they are compounds; generally, the former are organic EL elements, and the latter are inorganic EL elements. It is called

[0288] Organic EL elements emit electrons and holes from a pair of electrodes when a voltage is applied to the light-emitting element. Each of these is injected into a layer containing a luminescent organic compound, and an electric current flows through it. Then, these... The recombination of electrons and holes causes the luminescent organic compound to form an excited state. And when that excited state returns to the ground state, it emits light. From this mechanism, Such light-emitting devices are called current-excited light-emitting devices.

[0289] Inorganic electroluminescent (EL) elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements based on their element configuration. They are classified as such. Dispersive inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. The luminescence mechanism utilizes donor and acceptor levels, and the donor-acceptor level is the key to this process. This is a receptor recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism utilizes the inner-shell electron transition of metal ions. This is a localized light emission. Here, we will explain using an organic EL element as the light-emitting element. ru.

[0290] Figure 11 shows an example of a pixel configuration to which digital time-gradation driving can be applied as an example of a semiconductor device. This is a diagram.

[0291] This section describes the pixel configuration and operation to which digital time-based gradation driving can be applied. This uses an n-channel transistor with an oxide semiconductor layer as the channel formation region as one pixel. Here are two examples of its use.

[0292] Pixel 6400 consists of a switching transistor 6401, a driving transistor 6402, It has a light-emitting element 6404 and a capacitive element 6403. Switching transistor 64 01 has a gate connected to scan line 6406, and the first electrode (source electrode and drain electrode) The (side) is connected to signal line 6405, and the second electrode (the other of the source electrode and drain electrode) is driven It is connected to the gate of the drive transistor 6402. The drive transistor 6402 is The gate is connected to the power line 6407 via the capacitive element 6403, and the first electrode is connected to the power line 640 It is connected to 7, and the second electrode is connected to the first electrode (pixel electrode) of the light-emitting element 6404. The second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. The common electrode 6408 is identical It is electrically connected to a common potential line formed on the substrate.

[0293] Furthermore, a low power supply potential is set for the second electrode (common electrode 6408) of the light-emitting element 6404. The low power supply potential is defined as the low power supply potential set on power line 6407 relative to the high power supply potential. The potential is the potential that satisfies the high power supply potential, and low power supply potentials include, for example, GND and 0V. It may be fixed. The potential difference between this high power supply potential and the low power supply potential is applied to the light-emitting element 6404. Then, in order to pass current through the light-emitting element 6404 and make the light-emitting element 6404 emit light, a high power supply potential is used. The potential difference between the low power supply potential and the light-emitting element 6404 is set to be greater than or equal to the forward threshold voltage of the light-emitting element 6404. Set the potential for each.

[0294] Note that the capacitive element 6403 is omitted by substituting the gate capacitance of the drive transistor 6402. This is also possible. Regarding the gate capacitance of the drive transistor 6402, the channel region A capacitance may be formed between the gate electrode and the gate electrode.

[0295] In the case of a voltage input / voltage drive method, the gate of the drive transistor 6402 is: The drive transistor 6402 is either fully on or completely off. The video signal is input. In other words, the driver transistor 6402 is operated in the linear region. The driver transistor 6402 operates in the linear region, therefore the voltage of the power line 6407 is higher than A high voltage is applied to the gate of the drive transistor 6402. The signal line 6405 is connected to... Apply a voltage equal to or greater than (power line voltage + Vth of the drive transistor 6402).

[0296] Furthermore, when using analog gradation drive instead of digital time gradation drive, the signal input is different. By doing so, the same pixel configuration as in Figure 11 can be used.

[0297] When performing analog grayscale driving, the gate of the driving transistor 6402 is connected to the light-emitting element 6404 Apply a voltage equal to or greater than the forward voltage of the drive transistor 6402 + Vth. (Light-emitting element 64) The forward voltage of 04 refers to the voltage required to achieve the desired brightness, and at least the forward voltage is Includes key voltage. Note that the drive transistor 6402 operates in the saturation region. By inputting an O signal, current can be supplied to the light-emitting element 6404. The drive transistor... To operate the 6402 in the saturation region, the potential of the power line 6407 is set to the drive transistor The gate potential of the TA6402 is set higher. By making the video signal analog, the light-emitting element... By supplying current to the 6404 according to the video signal, analog grayscale driving can be performed.

[0298] Note that the pixel configuration shown in Figure 11 is not limited to this. For example, if new pixels are added to the pixels shown in Figure 11... Switches, resistors, capacitives, transistors, or logic circuits may be added to it.

[0299] Next, the configuration of the light-emitting element will be explained using Figure 12. Here, the driving TFT is n Let's take the case of a type as an example to explain the cross-sectional structure of a pixel. Figure 12(A)(B)(C) The driver TFTs 7001, 7011, and 7021 used in the semiconductor device are as follows in Embodiment 4. It can be fabricated in the same way as the thin-film transistor shown, and is a transparent thin-film transistor containing an oxide semiconductor layer. Here is an example of using "ta".

[0300] A light-emitting element only needs to have at least one of its electrodes, either the anode or the cathode, transparent in order to extract light. Then, thin-film transistors and light-emitting elements are formed on the substrate, and light is emitted from the side opposite to the substrate. An upper surface injection structure that emits light, a lower surface injection structure that extracts light from the substrate side, and the substrate side and the substrate It has a double-sided emission light-emitting element that extracts light from the opposite side, and the pixel configuration is regardless of the emission structure It can also be applied to the light-emitting elements of the structure.

[0301] The light-emitting element with a bottom-extrusion structure will be explained using Figure 12(A).

[0302] The driving TFT 7011 is n-type, and the light emitted from the light-emitting element 7012 is directed to the first electrode 701 Figure 12(A) shows a cross-sectional view of the pixel when it is ejected to side 3. Wiring layers 7018a and 7018b are formed, which are electrically connected to the drain electrode layer. A planar insulating layer 7036 is formed on top of it. The wiring layer 7018b is the planar insulating layer 7 In the opening formed in 036, it is in contact with the light-transmitting conductive film 7017, for driving The TFT7011 and the light-transmitting conductive film 7017 are electrically connected. A first electrode 7013 of the light-emitting element 7012 is formed on the conductive film 7017, An EL layer 7014 and a second electrode 7015 are stacked sequentially on the first electrode 7013.

[0303] The light-transmitting conductive film 7017 includes indium oxide containing tungsten oxide, acid Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, oxide Titanium-containing indium tin oxide, indium tin oxide, indium zinc oxide, oxide A transparent conductive film such as indium tin oxide with added inium can be used. Cut.

[0304] Furthermore, the first electrode 7013 of the light-emitting element can be made of various materials. For example, the first When using electrode 7013 as the cathode, a material with a small work function is used, specifically, for example For example, alkali metals such as Li and Cs, and alkaline earth metals such as Mg, Ca, Sr, and In addition to alloys containing these (such as Mg:Ag and Al:Li), rare earth metals such as Yb and Er are also included. This is preferable. In Figure 12(A), the film thickness of the first electrode 7013 is such that it transmits light (preferably Or, it should be about 5 nm to 30 nm. For example, an aluminum film with a thickness of 20 nm. This is used as the first electrode 7013.

[0305] Furthermore, after laminating a transparent conductive film and an aluminum film, selective etching is performed. A transparent conductive film 7017 and a first electrode 7013 may be formed, in which case the same This is preferable because etching can be performed using a mask.

[0306] Furthermore, the periphery of the first electrode 7013 is covered with a partition wall 7019. The partition wall 7019 is made of polyimi Organic resin films such as acrylic, polyamide, epoxy, inorganic insulating films, or organic polysilicone It is formed using Sun. The partition wall 7019 is made of a photosensitive resin material in particular, and the first electrode 70 An opening is formed on 13, and the side walls of the opening are inclined surfaces formed with a continuous curvature. It is preferable to form it in such a way. When a photosensitive resin material is used as the partition wall 7019. This eliminates the need to form a resist mask.

[0307] Furthermore, the EL layer 7014 formed on the first electrode 7013 and the partition wall 7019 is at least It is sufficient to include a light-emitting layer, and even if it consists of a single layer, it can be configured so that multiple layers are stacked on top of each other. Either way is fine. If the EL layer 7014 is composed of multiple layers, the cathode is... An electron injection layer, electron transport layer, light emission layer, hole transport layer, and hole are placed on the first electrode 7013 which functions. The layers are stacked in the order of the injection-treated layers. Note that it is not necessary to provide all of these layers.

[0308] Furthermore, the stacking order is not limited to the above, and the first electrode 7013 can function as an anode, and the first electrode A hole injection layer, hole transport layer, light emission layer, electron transport layer, and electron injection layer are stacked on top of 7013 in that order. This is also acceptable. However, when comparing power consumption, the first electrode 7013 is used as the cathode. On the first electrode 7013, there is an electron injection layer, an electron transport layer, an emissive layer, a hole transport layer, and a hole injection layer. Stacking the layers in the order they are placed inside out can suppress the voltage rise in the drive circuit and reduce power consumption. Therefore, it is preferable.

[0309] Furthermore, various materials can be used for the second electrode 7015 formed on the EL layer 7014. This is possible. For example, when the second electrode 7015 is used as the anode, a material with a large work function can be used. Materials such as ZrN, Ti, W, Ni, Pt, Cr, etc., and ITO, IZO, ZnO, etc. A transparent conductive material is preferred. Also, a shielding film 7016, for example, a light shielding film, is placed on the second electrode 7015. A light-shielding metal, a light-reflecting metal, etc., is used. In this embodiment, the second electrode 7015 and An ITO film is used, and a Ti film is used as the shielding film 7016.

[0310] The first electrode 7013 and the second electrode 7015 sandwich the EL layer 7014 which includes the light-emitting layer. The region corresponds to the light-emitting element 7012. In the device structure shown in Figure 12(A), The light emitted from 7012 is directed toward the first electrode 7013, as indicated by the arrow.

[0311] Note that in Figure 12(A), a transparent conductive film is used as the gate electrode layer, and the source electric An example is shown in which a thin film with light-transmitting properties is used for the polar layer and drain electrode layer, and a light-emitting element is shown. The light emitted from 7012 passes through the color filter layer 7033, then through the substrate and is emitted. It can be made to happen.

[0312] The color filter layer 7033 is used in droplet ejection methods such as inkjet printing, as well as in photolithography. These are formed using etching methods employing graphic technology.

[0313] Furthermore, the color filter layer 7033 is covered with an overcoat layer 7034, providing additional protective insulation. It is covered by layer 7035. Note that in Figure 12(A), the overcoat layer 7034 is a thin film. As illustrated, the overcoat layer 7034 has irregularities caused by the color filter layer 7033. It has the function of flattening.

[0314] Furthermore, the protective insulating layer 7035, the insulating layer 7032, and the insulating layer 7031 are formed, and The contact holes that reach the rain electrode layer are positioned to overlap with the partition wall 7019.

[0315] Next, a light-emitting element with a double-sided injection structure will be explained using Figure 12(B).

[0316] Figure 12(B) shows the drain electrode layer of the drive TFT7021 and the wiring layer that is electrically connected to it. 7028a and 7028b are formed, and a planar insulating layer 7046 is formed on top of them. The wiring layer 7028b has light-transmitting properties in the opening formed in the planar insulating layer 7046. The conductive film 7027 is in contact with the driving TFT 7021 and the light-transmitting conductive film 702 7 is electrically connected. The light-emitting element 7022 is on a light-transmitting conductive film 7027. A first electrode 7023 is formed, and an EL layer 7024 and a second electrode 7023 are formed on the first electrode 7023. The electrodes 7025 are stacked in sequence.

[0317] The transparent conductive film 7027 includes indium oxide containing tungsten oxide, acid Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, oxide Titanium-containing indium tin oxide, indium tin oxide, indium zinc oxide, oxide A transparent conductive film such as indium tin oxide with added inium can be used. Cut.

[0318] Furthermore, the first electrode 7023 can be made of various materials. For example, the first electrode 70 When using 23 as the cathode, a material with a small work function is preferred, specifically, for example, Li or Cs. Alkali metals such as Mg, Ca, Sr and other alkaline earth metals, and those containing these. In addition to alloys (such as Mg:Ag and Al:Li), rare earth metals such as Yb and Er are preferred. In this embodiment, the first electrode 7023 is used as the cathode, and its film thickness is such that it transmits light. (Preferably, about 5 nm to 30 nm). For example, aluminum with a film thickness of 20 nm A um film is used as the cathode.

[0319] Furthermore, after laminating a transparent conductive film and an aluminum film, selective etching is performed. A transparent conductive film 7027 and a first electrode 7023 may be formed, in which case the same Etching can be performed using a mask, which is preferable.

[0320] Furthermore, the periphery of the first electrode 7023 is covered with a partition wall 7029. The partition wall 7029 is made of polyimi Organic resin films such as acrylic, polyamide, epoxy, inorganic insulating films, or organic polysilicone It is formed using Sun. The partition wall 7029 is made of a photosensitive resin material in particular, and the first electrode 70 An opening is formed on 23, and the side walls of the opening are inclined surfaces formed with a continuous curvature. It is preferable to form it in such a way. When a photosensitive resin material is used as the partition wall 7029. This eliminates the need to form a resist mask.

[0321] Furthermore, the EL layer 7024 formed on the first electrode 7023 and the partition wall 7029 includes a light-emitting layer. It is fine as long as it is composed of a single layer, or multiple layers stacked on top of each other. Either is fine. If the EL layer 7024 consists of multiple layers, it functions as a cathode. On the first electrode 7023, there is an electron injection layer, an electron transport layer, an emissive layer, a hole transport layer, and a hole injection layer. The layers are stacked in this order. Note that it is not necessary to include all of these layers.

[0322] Furthermore, the stacking order is not limited to the above, and the first electrode 7023 may be used as the anode, with holes placed on the anode. The layers may be stacked in the order of injection layer, hole transport layer, light emission layer, electron transport layer, and electron injection layer. When comparing power consumption, the first electrode 7023 is used as the cathode, and an electron injection layer is placed on the cathode. , stacking the electron transport layer, light-emitting layer, hole transport layer, and hole injection layer in that order consumes less power. It is preferable because there is less of it.

[0323] Furthermore, various materials can be used for the second electrode 7025 formed on the EL layer 7024. This is possible. For example, when the second electrode 7025 is used as the anode, a material with a large work function can be used. Materials such as transparent conductive materials like ITO, IZO, and ZnO can preferably be used. In this embodiment, the second electrode 7025 is used as the anode, and an ITO film containing silicon oxide is used. It forms.

[0324] The first electrode 7023 and the second electrode 7025 sandwich the EL layer 7024 which includes the light-emitting layer. The region corresponds to the light-emitting element 7022. In the element structure shown in Figure 12(B), The light emitted from 7022 is directed towards the second electrode 7025 and the first electrode 70, as indicated by the arrows. It is injected on both sides of the 23 side.

[0325] Note that in Figure 12(B), a transparent conductive film is used as the gate electrode layer, and the source electric An example is shown in which a thin film with light-transmitting properties is used for the polar layer and drain electrode layer, and a light-emitting element is shown. Light emitted from 7022 toward the first electrode 7023 passes through the color filter layer 7043. And it can be ejected by passing through the substrate.

[0326] The color filter layer 7043 is used in droplet ejection methods such as inkjet printing, as well as in photolithography. These are formed using etching methods employing graphic technology.

[0327] Furthermore, the color filter layer 7043 is covered with an overcoat layer 7044, providing additional protection and insulation. It is covered by layer 7045.

[0328] Furthermore, protective insulating layer 7045, insulating layer 7042, and insulating layer 7041 are formed, and The contact holes that reach the rain electrode layer are positioned to overlap with the partition wall 7029.

[0329] However, when using a double-sided injection-type light-emitting element and both display surfaces are to display in full color, Since the light from the second electrode 7025 does not pass through the color filter layer 7043, a separate color filter is required. - It is preferable to provide a sealing substrate with a filter layer above the second electrode 7025.

[0330] Next, the light-emitting element with an upper surface injection structure will be explained using Figure 12(C).

[0331] Figure 12(C) shows that the driving TFT 7001 is n-type, and the light emitted from the light-emitting element 7002 is Figure 12(C) shows a cross-sectional view of the pixel when it exits towards the second electrode 7005. The drain electrode layer of the TFT7001 and the wiring layers 7008a and 7008b are electrically connected. It is formed thereon, and a planar insulating layer 7056 is formed thereon. The wiring layer 7008b is In the opening formed in the planar insulating layer 7056, the first electrode 700 of the light-emitting element 7002 It is in contact with 3, and the first electrode 7003 of the driving TFT 7001 and the light-emitting element 7002 are electrically connected. They are electrically connected. The EL layer 7004 and the second electrode 7005 are sequentially connected on the first electrode 7003. It is stacked on top of each other.

[0332] Furthermore, the first electrode 7003 can be made of various materials. For example, the first electrode 70 When using O3 as the cathode, materials with a low work function are preferred, specifically, for example, Li or Cs. Alkali metals such as Mg, Ca, Sr and other alkaline earth metals, and those containing these. In addition to alloys (such as Mg:Ag and Al:Li), rare earth metals such as Yb and Er are also preferred.

[0333] Furthermore, the periphery of the first electrode 7003 is covered with a partition wall 7009. The partition wall 7009 is made of polyimi Organic resin films such as acrylic, polyamide, epoxy, inorganic insulating films, or organic polysilicone It is formed using Sun. The partition wall 7009 is made of a photosensitive resin material in particular, and the first electrode 70 An opening is formed on 03, and the side walls of the opening are inclined surfaces formed with a continuous curvature. It is preferable to form it in such a way. When a photosensitive resin material is used as the partition wall 7009. This eliminates the need to form a resist mask.

[0334] Furthermore, the EL layer 7004 formed on the first electrode 7003 and the partition wall 7009 is at least It is sufficient to include a light-emitting layer, and even if it consists of a single layer, it can be configured so that multiple layers are stacked on top of each other. Either way is fine. If the EL layer 7004 is composed of multiple layers, the cathode is On the first electrode 7003 used, an electron injection layer, an electron transport layer, an emissive layer, a hole transport layer, and a hole layer are placed. The layers are stacked in the order of injection. Note that it is not necessary to provide all of these layers.

[0335] Furthermore, the stacking order is not limited to the above, and a hole injection layer is placed on the first electrode 7003 used as the anode. Alternatively, the layers may be stacked in the order of a hole transport layer, an emissive layer, an electron transport layer, and an electron injection layer.

[0336] Figure 12(C) shows a layered film consisting of a Ti film, an aluminum film, and another Ti film, onto which a hole injection is applied. The layers are stacked in the following order: indentation layer, hole transport layer, light emission layer, electron transport layer, and electron injection layer, with Mg:A on top of them. A layer is formed between a g alloy thin film and ITO.

[0337] However, if the driving TFT 7001 is n-type, an electron injection layer is placed on the first electrode 7003, electron Stacking the transport layer, light-emitting layer, hole transport layer, and hole injection layer in that order is preferable in the drive circuit. This is preferable because it can suppress voltage rise and reduce power consumption.

[0338] The second electrode 7005 is formed using a light-transmitting conductive material, for example, acid Indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium Indium tin oxide, indium zinc oxide, indium tin oxide with added silicon dioxide, etc. A photosensitive conductive film may also be used.

[0339] The EL layer 7004, which includes the light-emitting layer, is sandwiched between the first electrode 7003 and the second electrode 7005. The region corresponds to the light-emitting element 7002. In the element structure shown in Figure 12(C), the light-emitting element 7 The light emitted from 002 is directed toward the second electrode 7005, as indicated by the arrow.

[0340] Furthermore, in Figure 12(C), the drain electrode layer of the driving TFT7001 is an oxide insulating layer. 7051, protective insulating layer 7052, planar insulating layer 7056, planar insulating layer 7053, and insulation The first electrode 7003 is electrically connected to the edge layer 7055 via a contact hole provided in the edge layer 7055. The planar insulating layers 7036, 7046, 7053, and 7056 are made of polyimide and acrylic. Resin materials such as benzocyclobutene, polyamide, and epoxy can be used. In addition to the above resin materials, low dielectric constant materials (low-k materials), siloxane resins, PSG ( Materials such as glass (e.g., BPSG (limboron glass)) can be used. By stacking multiple insulating films formed from the material, planar insulating layers 7036, 7046, 70 53, 7056 may be formed. Planar insulating layers 7036, 7046, 7053, 705 The formation method for 6 is not particularly limited and may vary depending on the material, such as sputtering or spin coating. , dipping method, spray coating method, droplet ejection method (inkjet method, screen printing, Offset printing, etc., using methods such as roll coating, curtain coating, and knife coating. It is possible.

[0341] Furthermore, a partition wall 700 is used to insulate the first electrode 7003 from the first electrode of the adjacent pixel. A partition 7009 is provided. The partition wall 7009 is made of organic resin such as polyimide, acrylic, polyamide, and epoxy. It is formed using a lipid film, an inorganic insulating film, or an organic polysiloxane. The partition wall 7009 is particularly sensitive Using a photosensitive resin material, an opening is formed on the first electrode 7003, and the side walls of the opening are connected It is preferable to form it so that it becomes an inclined surface with a continuous curvature. Partition wall 700 9. When using a photosensitive resin material, the step of forming a resist mask is omitted. It is possible.

[0342] Furthermore, in the structure shown in Figure 12(C), when full-color display is performed, for example, the light-emitting element 70 02 is a green light-emitting element, one of the adjacent light-emitting elements is a red light-emitting element, and the other is The light-emitting element will be a blue light-emitting element. In addition to the three types of light-emitting elements, a white element will be added, making it a four-element system. A light-emitting display device capable of full-color display may be manufactured using various types of light-emitting elements.

[0343] Furthermore, in the structure shown in Figure 12(C), all of the multiple light-emitting elements to be arranged are white light-emitting elements. The configuration involves placing a sealing substrate having a color filter or the like above the light-emitting element 7002. A light-emitting device capable of full-color display may be manufactured. By forming a material and combining it with color filters and color conversion layers, full-color display is achieved. It is possible.

[0344] The source electrode layer or drain electrode layer is the source electrode layer 415a and drain electrode layer shown in Embodiment 1. It can be formed using the same process and materials as the in electrode layer 415b. Also, the wiring layer 700 8a, 7008b, 7018a, 7018b, 7028a, and 7028b are also in Embodiment 1. The wiring layers 417a, 417b, 418a, and 418b shown are formed using the same process and materials. It is possible.

[0345] The source electrode layer and drain electrode layer are preferably thin films with a thickness of 0.1 nm to 50 nm. A film thinner than the wiring layer is used. The source electrode layer and drain electrode layer are thin conductive films. Therefore, the parasitic capacitance with the gate electrode layer can be reduced. Thus, the oxide semiconductor layer This can be used to create a low-power semiconductor device having a thin-film transistor.

[0346] Of course, single-color illumination may also be used. For example, a lighting device can be formed using white light. Alternatively, a monochromatic light emission may be used to form an area-color type light-emitting device.

[0347] Furthermore, if necessary, optical films such as polarizing films, including circular polarizers, may be provided.

[0348] Here, we have discussed organic EL elements as light-emitting elements, but inorganic EL elements can also be used as light-emitting elements. It is also possible to incorporate an L element.

[0349] Furthermore, the thin-film transistor (driving TFT) that controls the driving of the light-emitting element and the light-emitting element are electrically connected. An example of connection was shown, but a current control TFT is connected between the driving TFT and the light-emitting element. It may be a continuation of the same configuration.

[0350] This embodiment can be implemented in appropriate combination with other embodiments.

[0351] (Embodiment 9) In this embodiment, the external appearance and cross-section of the light-emitting display panel (also called a light-emitting panel) are shown in Figure This will be explained using Figure 13. Figure 13 shows a thin-film transistor and light-emitting element formed on a first substrate. Figure 13 is a plan view of the panel in which the element is sealed between the second substrate and the panel with a sealing material. (B) corresponds to the cross-sectional view at HI in Figure 13(A).

[0352] Pixel section 4502, signal line driving circuit 4503a, 450 provided on the first substrate 4501 3b, and the scan line drive circuits 4504a and 4504b are surrounded by a sealing material 4505 A pixel unit 4502, signal line driving circuits 4503a, 4503b, and A second substrate 4506 is provided on top of the scan line driving circuits 4504a and 4504b. The pixel section 4502, signal line driving circuits 4503a, 4503b, and scan line driving circuit 45 04a and 4504b consist of a first substrate 4501, a sealing material 4505, and a second substrate 4506. It is sealed together with the filler 4507. Highly dense protective film with minimal degassing (laminated film, UV-curing resin film) It is preferable to package (seal) the product with a cover material such as a linoleum.

[0353] Also provided on the first substrate 4501 are the pixel section 4502, the signal line driving circuit 4503a, 4 503b, and the scan line driving circuits 4504a and 4504b have multiple thin-film transistors. In Figure 13(B), the thin-film transistor 4510 included in the pixel section 4502 and the signal The thin-film transistor 4509 included in the wire drive circuit 4503a is shown as an example.

[0354] A highly reliable thin-film transistor including an oxide semiconductor layer as shown in Embodiments 1 to 7 is used as a pixel It can be used as a thin-film transistor 4510 for use in drive circuits. As for TA4509, the channel of the oxide semiconductor layer of the thin-film transistor shown in Embodiment 1 The structure is such that a conductive layer is provided at a position overlapping with the layer formation region. In this embodiment, the thin film trace The 4509 and 4510 transistors are n-channel thin-film transistors.

[0355] On the oxide insulating layer 4542, the oxide semiconductor of the thin-film transistor 4509 for the drive circuit A conductive layer 4540 is provided in a position that overlaps with the channel formation region of the layer. By positioning it in a location that overlaps with the channel formation region of the oxide semiconductor layer, before and after the BT test This can reduce the change in the threshold voltage of the thin-film transistor 4509. Furthermore, the conductive layer 4540 may have the same potential as the gate electrode layer of the thin-film transistor 4509. Furthermore, they may be different, and can also function as a second gate electrode layer. The potential of the 4540 electrode may be GND, 0V, or floating.

[0356] Furthermore, an oxide insulating layer 4542 is formed to cover the oxide semiconductor layer of the thin-film transistor 4510. The source electrode layer or drain electrode layer of the thin-film transistor 4510 is thin-film transistor In the openings formed in the oxide insulating layer 4542 and insulating layer 4551 provided on the sta It is electrically connected to the wiring layer 4550. The wiring layer 4550 is in contact with the first electrode 4517. The thin-film transistor 4510 and the first electrode 4517 are connected via the wiring layer 4550. They are electrically connected.

[0357] The source electrode layer or drain electrode layer is the source electrode layer 415a and drain electrode layer shown in Embodiment 1. It can be formed using the same process and materials as the in electrode layer 415b. Also, the wiring layer 455 The process for step 0 is the same as that for the wiring layers 417a, 417b, 418a, and 418b shown in Embodiment 1. It can be formed from the materials.

[0358] The source electrode layer and drain electrode layer are preferably thin films with a thickness of 0.1 nm to 50 nm. A film thinner than the wiring layer is used. The source electrode layer and drain electrode layer are thin conductive films. Therefore, the parasitic capacitance with the gate electrode layer can be reduced. Thus, the oxide semiconductor layer This can be used to create a low-power semiconductor device having a thin-film transistor.

[0359] The oxide insulating layer 4542 is made of the same materials and is made using the same methods as the oxide insulating layer 407 shown in Embodiment 1. That's how you should form it.

[0360] The color filter layer 4545 overlaps with the light-emitting region of the light-emitting element 4511, and the insulating layer 455 Formed on 1.

[0361] Furthermore, it functions as a planarizing insulating film to reduce surface irregularities of the color filter layer 4545. It is constructed by covering it with an overcoat layer 4543.

[0362] Furthermore, an insulating layer 4544 is formed on the overcoat layer 4543. Insulating layer 4544 This can be formed in the same way as the protective insulating layer 408 shown in Embodiment 1, for example, a silicon nitride film. This can be formed using the sputtering method.

[0363] Furthermore, 4511 corresponds to a light-emitting element, and the first electrode 4 is a pixel electrode of the light-emitting element 4511. 517 is the source electrode layer or drain electrode layer and wiring layer 45 of the thin-film transistor 4510. It is electrically connected via 50. The configuration of the light-emitting element 4511 is as follows: 7. The structure is a laminated structure of an electroluminescent layer 4512 and a second electrode 4513, but is not limited to the configuration shown. No. The configuration of the light-emitting element 4511 is adjusted according to the direction of the light extracted from the light-emitting element 4511. This can be changed as needed.

[0364] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, using a photosensitive material, an opening is formed on the first electrode 4517, and the side walls of the opening are connected It is preferable to form the inclined surface with a continuous curvature.

[0365] Even if the electroluminescent layer 4512 consists of a single layer, it is configured to be stacked with multiple layers. It's fine either way.

[0366] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4511, the second electrode 45 A protective film may be formed on 13 and the partition wall 4520. The protective film may be a silicon nitride film, a nitride film. It can form silicon oxide films, DLC films, and the like.

[0367] Also, signal line drive circuits 4503a, 4503b and scan line drive circuits 4504a, 4504b The various signals and potentials applied to the pixel section 4502 are FPC4518a, 4518 It is supplied by b.

[0368] The connecting terminal electrode 4515 is made from the same conductive film as the first electrode 4517 of the light-emitting element 4511. The terminal electrode 4516 is formed and connects to the source electrode layer and drain of the thin-film transistor 4509. It is formed from the same conductive film as the electrode layer.

[0369] The connecting terminal electrode 4515 is connected to the terminal of FPC4518a via the anisotropic conductive film 4519. They are electrically connected.

[0370] The second substrate located in the direction of light extraction from the light-emitting element 4511 must be translucent. No. In that case, glass plate, plastic plate, polyester film or acrylic A light-transmitting material, such as a film, is used.

[0371] Furthermore, in addition to inert gases such as nitrogen and argon, UV-curable resin can also be used as the filler 4507. Oils or thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's all you need to do.

[0372] Furthermore, if necessary, a polarizing plate or circular polarizing plate (including elliptical polarizing plate) may be placed on the emission surface of the light-emitting element. You may also appropriately incorporate optical films such as phase difference plates (λ / 4 plate, λ / 2 plate) and color filters. Furthermore, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, by the surface irregularities An anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0373] The signal line drive circuits 4503a and 4503b, and the scan line drive circuits 4504a and 4504b are Drive turns formed by a single-crystal semiconductor film or polycrystalline semiconductor film on a separately prepared substrate It may be implemented in the circuit. Also, only the signal line drive circuit, or part of it, or the scan line drive circuit The road may be formed separately or partially, and the implementation is not limited to the configuration shown in Figure 13.

[0374] Through the above process, a highly reliable light-emitting display device (display panel) is manufactured as a semiconductor device. It is possible.

[0375] This embodiment can be implemented in appropriate combination with other embodiments.

[0376] (Embodiment 10) Figure 14 shows the external appearance and cross-section of a liquid crystal display panel, which is a form of semiconductor device. Let me explain. Figure 14 shows thin-film transistors 4010 and 4011, and liquid crystal element 4013. A sealing material 4005 is used to seal the first substrate 4001 and the second substrate 4006. This is a plan view of the panel, and Figure 14(B) is the same as MN in Figure 14(A) or Figure 14(C). This corresponds to a cross-sectional view.

[0377] The pixel section 4002 and the scanning line driving circuit 4004 are surrounded on the first substrate 4001. A sealing material 4005 is provided in this manner. Also, the pixel section 4002 and the scan line drive rotation A second substrate 4006 is provided on the path 4004. Therefore, the pixel section 4002 and the scanning The line drive circuit 4004 consists of the first substrate 4001, the sealing material 4005, and the second substrate 4006. It is sealed together with the liquid crystal layer 4008. Also, the seal on the first substrate 4001 A single crystal is placed on a separately prepared substrate in a region different from the area enclosed by material 4005. A signal line driving circuit 4003, formed from a semiconductor film or a polycrystalline semiconductor film, is mounted.

[0378] Furthermore, the method of connecting the separately formed drive circuit is not particularly limited, and COG method, Wire bonding methods or TAB methods can be used. Figure 14(A) This is an example of implementing the signal line drive circuit 4003 using the COG method, and Figure 14(C) shows TA This is an example of implementing the signal line drive circuit 4003 using method B.

[0379] Furthermore, the pixel section 4002 and the scanning line driving circuit 4004 provided on the first substrate 4001 are, It has multiple thin-film transistors, and in Figure 14(B), the thin film included in the pixel section 4002 Transistor 4010 and thin-film transistor 4011 included in scan line drive circuit 4004 This illustrates the following: Insulating layers 4041 and 404 are placed on thin-film transistors 4010 and 4011. 2, 4020, and 4021 are provided.

[0380] Thin-film transistors 4010 and 4011 have an oxide semiconductor layer as shown in Embodiments 1 to 7. Highly reliable thin-film transistors can be applied. Thin-film transistors for drive circuits The star 4011 and the thin-film transistor 4010 for the pixels are shown in Embodiments 1 to 7. Thin-film transistors can be used. In this embodiment, thin-film transistors The 4010 and 4011 are n-channel thin-film transistors.

[0381] On the insulating layer 4021, the oxide semiconductor layer of the thin-film transistor 4011 for the drive circuit A conductive layer 4040 is provided in a position that overlaps with the channel formation region. The conductive layer 4040 is acid By placing it in a position that overlaps with the channel formation region of the synthetic semiconductor layer, before and after BT testing... This can reduce the change in the threshold voltage of the thin-film transistor 4011. The conductive layer 4040 may have the same potential as the gate electrode layer of the thin-film transistor 4011. They can be different, and can also function as a second gate electrode layer. Also, the conductive layer The potential of 4040 may be GND, 0V, or floating.

[0382] Furthermore, the pixel electrode layer 4030 of the liquid crystal element 4013 is a thin-film transistor 4010 The - electrode layer or drain electrode layer is electrically connected to the wiring layer 4050. The counter electrode layer 4031 of the liquid crystal element 4013 is formed on the second substrate 4006. The portion where the pixel electrode layer 4030, the counter electrode layer 4031, and the liquid crystal layer 4008 overlap is This corresponds to the liquid crystal element 4013. Note that the pixel electrode layer 4030 and the counter electrode layer 4031 are respectively Insulating layers 4032 and 4033 are provided, which function as alignment films. The liquid crystal layer 4008 is sandwiched between the three layers.

[0383] Furthermore, translucent substrates can be used as the first substrate 4001 and the second substrate 4006. Glass, ceramics, and plastics can be used. As for plastics... , FRP (Fiberglass-Reinforced Plastics) board, PV F (polyvinyl fluoride) film, polyester film, or acrylic resin film A film can be used.

[0384] Furthermore, 4035 is a columnar spacer obtained by selectively etching an insulating film. To control the distance (cell gap) between the pixel electrode layer 4030 and the counter electrode layer 4031 It is provided in [location]. A spherical spacer may also be used. Also, the counter electrode layer 4031 It is electrically connected to a common potential line provided on the same substrate as the thin-film transistor 4010. Using a common connection part, the opposing electrode layer 40 is connected via conductive particles placed between the pair of substrates. 31 and the common potential line can be electrically connected. Note that the conductive particles are the sealing material 40 It will be included in 05.

[0385] Alternatively, a liquid crystal exhibiting a blue phase without an alignment layer may be used. The blue phase is one of the liquid crystal phases. Yes, as the temperature of a cholesteric liquid crystal is increased, it transitions from the cholesteric phase to the isotropic phase. This is the phase that appears earlier. The blue phase only appears within a narrow temperature range, so improving the temperature range is necessary. To achieve this, a liquid crystal composition containing 5% or more by weight of a chiral agent is used in the liquid crystal layer 4008. The liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent has a response speed of 1 msec. It is short, optically isotropic, and therefore requires no orientation processing, and has low dependence on viewing angle.

[0386] In addition to transmissive liquid crystal displays, this method can also be applied to semi-transmissive liquid crystal displays.

[0387] Furthermore, in liquid crystal display devices, a polarizing plate is provided on the outside (viewing side) of the substrate, and a colored layer and display element are provided on the inside. The example shows the electrode layers being arranged in the order of the child, but the polarizing plate may be placed on the inside of the substrate. Furthermore, the laminated structure of the polarizing plate and the colored layer is not limited to this embodiment, and the materials of the polarizing plate and the colored layer may also vary. The settings should be adjusted as appropriate depending on the manufacturing process conditions. In addition, a black matrix can be used in addition to the display area. A light-shielding film that functions in this way may be provided.

[0388] On thin-film transistors 4011 and 4010, an insulating layer 4041 is in contact with the oxide semiconductor layer. The insulating layer 4041 is made of the same material as the oxide insulating layer 407 shown in Embodiment 1. It can be formed by the material and method. Here, the insulating layer 4041 is formed using Embodiment 1. A silicon oxide film is formed by sputtering. Furthermore, a protective insulating layer is formed in contact with the insulating layer 4041. An edge layer 4042 is formed. Furthermore, the protective insulating layer 4042 is the protective insulating layer shown in Embodiment 1. It can be formed in the same way as 408, for example, a silicon nitride film can be used. The edge layer 4042 functions as a planarizing insulating film to reduce surface irregularities of the thin-film transistor. It is constructed by covering it with an insulating layer 4021.

[0389] Furthermore, an insulating layer 4021 is formed as a planar insulating film. The insulating layer 4021 is made of poly Heat-resistant organic materials such as mids, acrylics, benzocyclobutenes, polyamides, and epoxys. Materials can be used. In addition to the above organic materials, low dielectric constant materials (low-k materials) can also be used. Using siloxane-based resins, PSG (phosphorus glass), BPSG (phosphorus boron glass), etc. This can be achieved by stacking multiple insulating films made of these materials. 4021 may be formed.

[0390] The method for forming the insulating layer 4021 is not particularly limited and may be done by sputtering, depending on the material. Pin coating method, dipping method, spray coating method, droplet ejection method (inkjet method, spray Lean printing, offset printing, etc.), roll coating method, curtain coating method, knife coating method The following can be used. The firing process of the insulating layer 4021 and the annealing of the semiconductor layer are combined. This makes it possible to efficiently manufacture semiconductor devices.

[0391] The pixel electrode layer 4030 and the counter electrode layer 4031 are made of indium oxide containing tungsten oxide. , indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, Titanium oxide-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), Translucent materials such as indium zinc oxide and indium tin oxide with added silicon dioxide. A translucent conductive material can be used.

[0392] Furthermore, conductive polymers are used as the pixel electrode layer 4030 and the counter electrode layer 4031. It can be formed using a conductive composition containing (also known as). The resulting pixel electrodes have a sheet resistance of 10,000 Ω / □ or less and a light transmittance at a wavelength of 550 nm. It is preferable that the ratio is 70% or more. Also, the resistance of the conductive polymer contained in the conductive composition The ratio is preferably 0.1 Ω·cm or less.

[0393] As the conductive polymer, so-called π-electron conjugated conductive polymers can be used. For example For example, polyaniline or its derivatives, polypyrrole or its derivatives, polythiophene Examples include derivatives thereof, or copolymers of two or more of these.

[0394] In addition, a separately formed signal line drive circuit 4003 and a scan line drive circuit 4004 or pixel unit 4 The various signals and potentials supplied to 002 are provided by the FPC4018.

[0395] Is the connection terminal electrode 4015 made of the same conductive film as the pixel electrode layer 4030 of the liquid crystal element 4013? The terminal electrode 4016 is formed from the source electrode layer of the thin-film transistors 4010 and 4011. It is formed of the same conductive film as the drain electrode layer.

[0396] The connecting terminal electrode 4015 is connected to the terminal of the FPC 4018 via the anisotropic conductive film 4019. They are electrically connected.

[0397] Furthermore, in Figure 14, a signal line driving circuit 4003 is formed separately and implemented on the first substrate 4001. The example shown illustrates this configuration, but it is not limited to this setup. A separate scan line drive circuit can be formed to implement it. Alternatively, you may install it, or separately form only a part of the signal line drive circuit or a part of the scan line drive circuit. It's okay to implement it.

[0398] Furthermore, the LCD display module supports TN (Twisted Nematic) mode and IP S (In-Plane-Switching) mode, FFS (Fringe Fiel) d Switching) mode, MVA (Multi-domain Vertica) l Alignment) mode, PVA(Patterned Vertical A) Ignition mode, ASM (Axially Symmetric align) ed Micro-cell) mode, OCB (Optical Compensate) d Birefringence) mode, FLC (Ferroelectric Li) quid Crystal) mode, AFLC(AntiFerroelectric) mode Modes such as Liquid Crystal can be used.

[0399] An example of a VA-type liquid crystal display is shown below.

[0400] A VA-type liquid crystal display device is a type of method that controls the arrangement of liquid crystal molecules in a liquid crystal display panel. In a VA-type liquid crystal display device, liquid crystal molecules are formed on the panel surface when no voltage is applied. This is a method in which the pixels are oriented vertically. In this embodiment, the pixels are particularly divided into several regions It is divided into regions (subpixels), and the molecules are tilted in a different direction in each region. This is called multi-domain architecture or multi-domain design. In the following explanation, multi-domain This section describes a liquid crystal display device with design considerations.

[0401] Figures 15 and 16 show the pixel structure of a VA-type liquid crystal display panel. Figure 16 shows the substrate 600 This is a plan view, and Figure 15 shows the cross-sectional structure corresponding to the cutting line YZ shown in the figure. The explanation below will refer to these two figures.

[0402] This pixel structure has multiple pixel electrodes for each pixel, and a TFT is in contact with each pixel electrode. It continues. Each TFT is configured to be driven by a different gate signal. In a multi-domain designed pixel, the signals applied to each pixel electrode are independently It has a configuration that controls it.

[0403] The pixel electrode layer 624 has wiring 6 in contact hole 623 and contact hole 660. It is connected to the source electrode layer or drain electrode layer 618 of the TFT628 via 62. Furthermore, the pixel electrode layer 626 is provided on the insulating layer 620 and the insulating layer 622 that covers the insulating layer 620. In contact hole 627 and contact hole 661, TFT6 is connected via wiring 663. The gate of the TFT628 is connected to the source electrode layer or drain electrode layer 619. Line 602 and the gate wiring 603 of TFT629 can be supplied with different gate signals. They are separated in such a way that they can be separated. On the other hand, the source electrode layer or drain electrode layer that functions as a data line The polar layer 616 is used in common with TFT628 and TFT629. The FT629 can appropriately use any one of the thin-film transistors from Embodiments 1 to 7. Cut.

[0404] Source electrode layer or drain electrode layer 616, 618, 619 is the source shown in Embodiment 1. It can be formed using the same process and materials as the electrode layer 415a and the drain electrode layer 415b. Also, wiring 662 and 663 are also wiring layers 417a, 417b, 41 shown in Embodiment 1. It can be formed using the same process and materials as 8a and 418b.

[0405] The source electrode layer and drain electrode layer are preferably thin films with a thickness of 0.1 nm to 50 nm. A film thinner than the wiring is used. The source electrode layer and drain electrode layer are thin conductive films. Therefore, the parasitic capacitance with the gate electrode layer can be reduced. Thus, the oxide semiconductor layer This can be used to create a low-power semiconductor device that has thin-film transistors.

[0406] Furthermore, capacitive wiring 690 is provided, and the stacked gate insulating layer 606 serves as a dielectric, and the pixel electrode Alternatively, a capacitive electrode electrically connected to the pixel electrode forms a retaining capacitance.

[0407] The shapes of the pixel electrode layer 624 and the pixel electrode layer 626 are different, and they are separated by the slit 625. They are separated. The pixel electrode layer 626 surrounds the outside of the V-shaped pixel electrode layer 624. It is formed. The timing of the voltage applied to the pixel electrode layer 624 and the pixel electrode layer 626 is The orientation of the liquid crystal is controlled by using different TFT628 and TFT629 chips. The equivalent circuit of the pixel structure is shown in Figure 18. The TFT628 is connected to the gate wiring 602, and TF T629 is connected to gate wiring 603. Gate wiring 602 and gate wiring 603 are different. By applying a gate signal, the operating timing of the TFT628 and TFT629 can be made different. It can be done.

[0408] A light-shielding film 632, a second colored film 636, and a counter electrode layer 640 are formed on the opposing substrate 601. Furthermore, between the second colored film 636 and the counter electrode layer 640, there is also what is called an overcoat film. A planarization film 637 is formed, preventing misalignment of the liquid crystal. Figure 17 shows the opposite substrate side. The structure is shown. The counter electrode layer 640 is an electrode that is common to different pixels, but slit Slit 641 is formed. This slit 641, pixel electrode layer 624 and pixel electrode layer 6 By arranging the slits 625 on side 26 to interlock alternately, the oblique electric field is effectively This allows for the control of liquid crystal orientation. This enables the direction in which the liquid crystals orient themselves to be controlled. This allows for variations and broadens the field of view.

[0409] The pixel electrode layer 624, the liquid crystal layer 650, and the counter electrode layer 640 overlap, forming the first liquid crystal element A child is formed. Also, the pixel electrode layer 626, the liquid crystal layer 650, and the counter electrode layer 640 overlap. By coming together, a second liquid crystal element is formed. Also, each pixel contains a first liquid crystal element and a second liquid crystal element. It is a multi-domain structure equipped with liquid crystal elements.

[0410] This embodiment can be implemented in appropriate combination with other embodiments.

[0411] (Embodiment 11) In this embodiment, an example of an electronic paper is shown as a semiconductor device that is one embodiment of the present invention. vinegar.

[0412] Figure 19 shows an active matrix as an example of a semiconductor device to which one embodiment of the present invention is applied. This shows a type of electronic paper. The thin-film transistor 581 used in semiconductor devices is actually... A thin-film transistor of any one of the embodiments 1 to 7 can be used as appropriate.

[0413] The electronic paper in Figure 19 is an example of a display device using a twist ball display method. The Toball display method uses spherical particles painted in white and black as display elements, and the electrode layer It is placed between the first electrode layer and the second electrode layer, and a potential difference is applied between the first electrode layer and the second electrode layer. This method of display is achieved by controlling the orientation of spherical particles by generating a phenomenon.

[0414] The thin-film transistor 581 provided on the substrate 580 is a thin-film transistor with a bottom gate structure. The source electrode layer or drain electrode layer consists of an oxide insulating layer 583 and a protective insulating layer 584. The opening formed therein is electrically connected to the wiring layers 589a and 589b. 89b is the first electrode layer 587 in an opening formed in the insulating layer 585 provided above. It is provided in contact with the wiring layer 58, and the thin-film transistor 581 and the first electrode layer 587 are connected to the wiring layer 58 They are electrically connected via 9a and 589b.

[0415] The source electrode layer or drain electrode layer is the source electrode layer 415a and drain electrode layer shown in Embodiment 1. It can be formed using the same process and materials as the in electrode layer 415b. Also, the wiring layer 589 a, 589b are also the wiring layers 417a, 417b, 418a, 418b shown in Embodiment 1. It can be formed using similar processes and materials.

[0416] The source electrode layer and drain electrode layer are preferably thin films with a thickness of 0.1 nm to 50 nm. A film thinner than the wiring layer is used. The source electrode layer and drain electrode layer are thin conductive films. Therefore, the parasitic capacitance with the gate electrode layer can be reduced. Thus, the oxide semiconductor layer This can be used to create a low-power semiconductor device having a thin-film transistor.

[0417] Between the first electrode layer 587 and the second electrode layer 588 are a black region 590a and a white region 59 A spherical particle is provided having 0b and containing a cavity 594 that is filled with liquid around it. The spherical particles are surrounded by a filler material 595 such as resin (see Figure 19). In this embodiment, the first electrode layer 587 corresponds to the pixel electrode and is provided on the opposing substrate 596. The second electrode layer 588 corresponds to the common electrode.

[0418] Alternatively, an electrophoretic element can be used instead of a twist ball. (Transparent liquid) And, positively charged white particles and negatively charged black particles are enclosed in a diameter of 10 μm to 20 Microcapsules of approximately 0 μm are used. They are placed between the first electrode layer and the second electrode layer. The microcapsules, when an electric field is applied, are formed by the first electrode layer and the second electrode layer, and white The white and black particles move in opposite directions, allowing for the display of either white or black. An electrophoretic display element, commonly known as electronic paper, is a display element that applies this principle. Electrophoretic display elements have a higher reflectivity than liquid crystal display elements, so auxiliary lights are not required. Furthermore, it consumes little power and the display can be seen even in dimly lit places. Even if power is not supplied to the display unit, it is possible to retain the image that has been displayed. Therefore, a semiconductor device with a display function (simply a display device, or equipped with a display device) is transmitted from a radio wave source. Even when the semiconductor device (also called a semiconductor device) is moved away, the displayed image is saved. This becomes possible.

[0419] Through the above process, highly reliable electronic paper can be manufactured as a semiconductor device. .

[0420] This embodiment can be implemented in appropriate combination with other embodiments.

[0421] (Embodiment 12) The semiconductor devices disclosed herein are applicable to a variety of electronic devices (including amusement machines). This is possible. As an electronic device, for example, a television set (television, or television Receivers (also called receivers), computer monitors, digital cameras, digital video cameras Digital photo frame, mobile phone (also called mobile phone or mobile phone device), portable Examples include game consoles, personal digital assistants, audio playback devices, and large game machines such as pachinko machines. ru.

[0422] Figure 20(A) shows an example of the mobile phone 1100. The mobile phone 1100 has a housing In addition to the display unit 1102 incorporated into 1101, there are also operation buttons 1103 and an external connection port 11 It is equipped with 04, speaker 1105, microphone 1106, etc.

[0423] The mobile phone 1100 shown in Figure 20(A) allows you to touch the display unit 1102 with your finger or the like to receive information. You can enter information. Also, operations such as making phone calls or sending emails are performed on the display. This can be done by touching 1102 with a finger or other object.

[0424] The display unit 1102 has three main modes. The first is a display that primarily displays images. The first mode is display mode, the second is input mode which is mainly for inputting information such as characters. The third is display mode. This is a display + input mode, which is a combination of two modes: display mode and input mode.

[0425] For example, when making a phone call or composing an email, the display unit 1102 is used for text input. In this case, the primary text input mode should be used, and you should perform the input operation for the characters displayed on the screen. It is preferable to display a keyboard or number buttons on most of the screen of the display unit 1102. It seems so.

[0426] Furthermore, the mobile phone 1100 contains sensors that detect tilt, such as a gyroscope and an accelerometer. By providing a detection device, the orientation (vertical or horizontal) of the mobile phone 1100 can be determined, and the display The display on the display unit 1102 can be automatically switched.

[0427] Furthermore, the screen mode can be switched by touching the display unit 1102 or by operating the housing 1101. This is done by operating button 1103. Also, the type of image displayed on display unit 1102 Therefore, it is also possible to switch between them. For example, the image signal displayed on the display unit is a video signal. Switch to display mode if it's data, or to input mode if it's text data.

[0428] Furthermore, in input mode, the signal detected by the optical sensor of the display unit 1102 is detected and displayed If there is no input via touch operation on unit 1102 for a certain period of time, the screen mode will be changed to input mode. You may also control the system to switch from that display mode to a different mode.

[0429] The display unit 1102 can also function as an image sensor. For example, the display unit 11 By touching the palm or fingers to device 02, the device can capture palm prints, fingerprints, etc., to perform identity verification. It can also be used. In addition, the display unit has a backlight that emits near-infrared light or a sensor that emits near-infrared light. Using a light source designed for imaging, it is also possible to image finger veins, palmar veins, and other veins.

[0430] The display unit 1102 uses a thin-film transistor as the pixel switching element, as shown in Embodiment 1. Place multiple staves.

[0431] Figure 20(B) is also an example of a mobile phone. A portable information terminal, as exemplified by Figure 20(B), is: It can have multiple functions. For example, in addition to telephone functionality, it can have a built-in computer, etc. It can also be equipped with various data processing functions.

[0432] The portable information terminal shown in Figure 20(B) consists of two housings, housing 1800 and housing 1801. It has been done. The enclosure 1800 contains a display panel 1802, a speaker 1803, and a micro Phone 1804, pointing device 1806, camera lens 1807, external connection It is equipped with terminal 1808, and the chassis 1801 contains a keyboard 1810 and an external memory slot. It is equipped with components such as the 1811. The antenna is also built into the 1801 housing.

[0433] Furthermore, the display panel 1802 is equipped with a touch panel, and the image displayed in Figure 20(B) is Multiple operation keys 1805 are indicated by dotted lines.

[0434] In addition to the above configuration, a contactless IC chip, a small recording device, etc., may also be incorporated.

[0435] The light-emitting device can be used with the display panel 1802, and the display direction can be adjusted according to the usage. It changes as appropriate. Furthermore, a camera lens 1807 is provided on the same plane as the display panel 1802. Therefore, video calls are possible. Speaker 1803 and microphone 1804 produce sound. In addition to voice calls, it is also capable of video calls, recording, and playback. Furthermore, the enclosure 1800 and the enclosure Body 1801 slides and changes from an unfolded state as shown in Figure 20(B) to an overlapping state. It can be made compact enough to be portable.

[0436] External connection terminal 1808 can be connected to various cables such as AC adapters and USB cables. It is capable of charging and data communication with personal computers, etc. By inserting a recording medium into memory slot 1811, it becomes possible to store and move larger amounts of data. ru.

[0437] Furthermore, even if it has infrared communication capabilities, television reception capabilities, etc. in addition to the above functions good.

[0438] Figure 21(A) shows an example of the television equipment 9600. In the case of 00, the display unit 9603 is incorporated into the housing 9601. The display unit 9603 displays It is possible to display an image. Also, here, the stand 9605 is used to display the housing 9601 This shows a configuration that supports this.

[0439] The television unit 9600 is operated using the control switches on the housing 9601 and a separate remote control. This can be done using the control unit 9610. The remote control unit 9610 has control keys The 9609 allows you to control the channel and volume, and the information is displayed on the display unit 9603. The video can be controlled. Furthermore, the remote control unit 9610 can be controlled by the remote control unit. A display unit 9607 may be provided to display the information output from 9610.

[0440] The television system 9600 will consist of a receiver, modem, and other components. It can receive more general television broadcasts, and furthermore, it can connect via a modem, either wired or wirelessly. By connecting to the communication network, one-way (sender to receiver) or two-way communication is possible. It is also possible to communicate information (between a sender and a receiver, or between receivers, etc.).

[0441] The display unit 9603 uses a thin-film transistor as the pixel switching element, as shown in Embodiment 1. Place multiple staves.

[0442] Figure 21(B) shows the Digital Photo Frame 9700 as an example of a digital photo frame. This shows that, for example, the digital photo frame 9700 has a display unit 97 on the housing 9701. 03 is incorporated. The display unit 9703 is capable of displaying various images, for example. For example, by displaying image data taken with a digital camera, it is the same as a regular photo frame. It can be made to function in a certain way.

[0443] The display unit 9703 uses a thin-film transistor as the pixel switching element, as shown in Embodiment 1. Place multiple staves.

[0444] The Digital Photo Frame 9700 includes an operating unit and external connection terminals (USB terminal, USB port). A structure that includes terminals that can connect to various cables such as B cables, a recording medium insertion section, etc. These components may be incorporated on the same surface as the display unit, but may also be on the sides or back. It's desirable to include it because it improves the design. For example, the 9700 digital photo frame. Insert a memory device containing image data taken with a digital camera into the recording medium insertion slot. Image data can be captured and displayed on the display unit 9703. ru.

[0445] Furthermore, the digital photo frame 9700 may be configured to send and receive information wirelessly. It is also possible to configure the system to acquire and display desired image data wirelessly.

[0446] Figure 22 shows a portable gaming machine, which consists of two cabinets, cabinet 9881 and cabinet 9891. The two parts are connected by a connecting part 9893 so that they can be opened and closed. The housing 9881 has a display unit 988 Unit 2 is incorporated, and the display unit 9883 is incorporated into the housing 9891.

[0447] The display unit 9883 has a thin-film transistor as the pixel switching element as shown in Embodiment 1. Place multiple staves.

[0448] Furthermore, the portable gaming machine shown in Figure 22 also includes a speaker section 9884 and a recording medium insertion section 98 86, LED lamp 9890, input means (operation key 9885, connection terminal 9887, sensor) 9888 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance, light, liquid, magnetism, temperature) , chemical substances, sound, time, hardness, electric field, electric current, voltage, power, radiation, flow rate, humidity, gradient, Equipped with functions to measure vibration, odor, or infrared radiation, microphones (9889), etc. Of course, the configuration of portable gaming machines is not limited to those described above, and at least this specification includes... Any configuration comprising the thin-film transistor disclosed in this document is acceptable, and other auxiliary equipment may be provided as appropriate. A configuration can be achieved. The portable gaming machine shown in Figure 22 is recorded on a recording medium. Functions include reading programs or data and displaying them on the display unit, and wireless communication with other portable gaming machines. It has the function of communicating and sharing information. Note that this is the function of the portable gaming machine shown in Figure 22. This is not limited to this, and it can have a variety of functions.

[0449] Figure 24 shows a light-emitting device formed by applying the above embodiment, connected to an indoor lighting device 3001. This is an example of its use. The light-emitting device shown in Embodiment 4 or Embodiment 5 can also be made to cover a large area. Because it is capable, it can be used as a large-area lighting device. Also, as shown in the above embodiment The resulting light-emitting device can also be used as a desk lamp 3000. In addition to ceiling-mounted and desk lamps, this includes wall-mounted and in-car lighting fixtures. This also includes emergency exit signs.

[0450] As described above, the thin-film transistor shown in any one of Embodiments 1 to 7 is as described above. It can be placed on the display panels of various electronic devices. Thin-film transistors for display panels By using it as a switching element, it is possible to provide highly reliable electronic equipment. can.

[0451] (Embodiment 13) The semiconductor device disclosed herein can be used as electronic paper. PA can be used in electronic devices in any field that displays information. For example, using e-paper, e-books, posters, and trains This can be applied to in-vehicle advertisements for goods, displays on various cards such as credit cards, etc. An example of an electronic device is shown in Figure 23.

[0452] Figure 23 shows eBook 2700 as an example of an eBook. 00 consists of two enclosures: enclosure 2701 and enclosure 2703. Enclosure 2701 The housing 2703 is integrated with the shaft portion 2711, and the shaft portion 2711 is the axis This allows for opening and closing operations. This configuration enables operation similar to that of a paper book. This becomes possible.

[0453] The display unit 2705 is incorporated into the housing 2701, and the display unit 2707 is incorporated into the housing 2703. It is included. Display units 2705 and 2707 are configured to display a continuation screen. Alternatively, a configuration that displays different screens is also acceptable. For example, text is displayed on the right-hand display unit (display unit 2705 in Figure 23), and the left-hand display unit An image can be displayed on the display unit 2707 in Figure 23.

[0454] Furthermore, Figure 23 shows an example in which the housing 2701 is equipped with an operating unit, etc. For example, housing 2 Unit 701 is equipped with a power supply 2721, operation keys 2723, speaker 2725, and the like. The page can be turned using operation key 2723. Note that the key is located on the same side as the display unit of the casing. The configuration may include a board or pointing device. Also, the back or sides of the enclosure may be used. On the side, there are external connection terminals (earphone terminal, USB terminal, or AC adapter and USB cable). The configuration includes terminals that can connect to various cables such as cables, a recording medium insertion section, and more. It is also permissible to do so. Furthermore, the eBook 2700 is configured to have the functionality of an electronic dictionary. That's good too.

[0455] Furthermore, the e-book 2700 may be configured to transmit and receive information wirelessly. By wireless means, The system will be configured to allow users to purchase and download desired book data from an e-book server. It is also possible.

[0456] This embodiment can be implemented in appropriate combination with other embodiments.

Claims

1. A first conductive layer having the function of a gate electrode of a transistor, A first insulating layer having a region located on the first conductive layer, An oxide semiconductor layer having a region located on the first insulating layer and having a channel formation region for the transistor, A second conductive layer having a region in contact with the upper surface of the oxide semiconductor layer, a region in contact with the side surface of the oxide semiconductor layer, and a region in contact with the upper surface of the first insulating layer, and having the function of one of the source electrode and drain electrode of the transistor, A second insulating layer having a region in contact with the upper surface of the second conductive layer, a region in contact with the side surface of the second conductive layer, and a region in contact with the upper surface of the oxide semiconductor layer, A third conductive layer having a region in contact with the upper surface of the second insulating layer and a region in contact with the upper surface of the second conductive layer through a first opening in the second insulating layer, A fourth conductive layer having a region in contact with the upper surface of the second insulating layer and functioning as a source wiring, A third insulating layer having a region in contact with the upper surface of the third conductive layer and a region in contact with the upper surface of the fourth conductive layer, A fifth conductive layer having a region located on the third insulating layer and a region in contact with the third conductive layer through a second opening in the third insulating layer, The second insulating layer has a laminated structure of a silicon oxide film having a region in contact with the oxide semiconductor layer and a silicon nitride film having a region located above the silicon oxide film. The aforementioned second conductive layer has a single-layer structure, The third conductive layer described above has a laminated structure, The fourth conductive layer has a laminated structure and is made of the same material as the third conductive layer. The fifth conductive layer has the function of a pixel electrode, The thickness of the second conductive layer is less than or equal to the thickness of the oxide semiconductor layer. The thickness of the second conductive layer is smaller than the thickness of the fourth conductive layer. In a cross-sectional view of the transistor in the channel length direction, the first opening of the second insulating layer does not overlap with the oxide semiconductor layer. A display device wherein, in a cross-sectional view of the transistor in the channel length direction, the second opening of the third insulating layer does not overlap with the oxide semiconductor layer.

2. A first conductive layer having the function of a gate electrode of a transistor, A first insulating layer having a region located on the first conductive layer, An oxide semiconductor layer having a region located on the first insulating layer and having a channel formation region for the transistor, A second conductive layer having a region in contact with the upper surface of the oxide semiconductor layer, a region in contact with the side surface of the oxide semiconductor layer, and a region in contact with the upper surface of the first insulating layer, and having the function of one of the source electrode and drain electrode of the transistor, A second insulating layer having a region in contact with the upper surface of the second conductive layer, a region in contact with the side surface of the second conductive layer, and a region in contact with the upper surface of the oxide semiconductor layer, A third conductive layer having a region in contact with the upper surface of the second insulating layer and a region in contact with the upper surface of the second conductive layer through a first opening in the second insulating layer, A fourth conductive layer having a region in contact with the upper surface of the second insulating layer and functioning as a source wiring, A third insulating layer having a region in contact with the upper surface of the third conductive layer and a region in contact with the upper surface of the fourth conductive layer, A fifth conductive layer having a region located on the third insulating layer and a region in contact with the third conductive layer through a second opening in the third insulating layer, The second insulating layer has a laminated structure of a silicon oxide film having a region in contact with the oxide semiconductor layer and a silicon nitride film having a region located above the silicon oxide film. The aforementioned second conductive layer has a single-layer structure, The third conductive layer described above has a laminated structure, The fourth conductive layer has a laminated structure and is made of the same material as the third conductive layer. The fifth conductive layer has the function of a pixel electrode, The thickness of the second conductive layer is less than or equal to the thickness of the oxide semiconductor layer. The thickness of the second conductive layer is smaller than the thickness of the fourth conductive layer. In a cross-sectional view of the transistor in the channel length direction, the first opening of the second insulating layer does not overlap with the oxide semiconductor layer. In a cross-sectional view of the transistor in the channel length direction, the second opening of the third insulating layer does not overlap with the oxide semiconductor layer. A display device wherein, in a cross-sectional view of the transistor in the channel length direction, the third conductive layer does not overlap with the oxide semiconductor layer.

3. In claim 1 or 2, The oxide semiconductor layer comprises oxygen and indium, in a display device.

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