Semiconductor device and manufacturing method

Abstract

To reduce the variation of doping concentration in the area under the insulating film.SOLUTION: The provided semiconductor device comprises: a semiconductor substrate having a drift region of the first conductivity type in which both first dopants of the first conductivity type and second dopants of the second conductivity type are distributed throughout; an insulating film provided on a top surface of the semiconductor substrate; an insulating film provided below the insulating film and in contact with the insulating film, and having high concentration region of the first conductivity type with a higher doping concentration than the drift region, and a decreasing region provided below the insulating film and in contact with the insulating film, where the concentration of dopants of the second conductivity type decreases toward the insulating film.SELECTED DRAWING: Figure 11

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a manufacturing method thereof.

Background Art

[0002] Conventionally, a semiconductor device including an edge termination structure portion including a guard ring has been known (see, for example, Patent Document 1). Patent Document 1 JP-A-2017-143136

[0003] In an edge termination structure portion or the like, an insulating film is provided on the upper surface of a semiconductor substrate.

Summary of the Invention

Problems to be Solved by the Invention

[0004] It is preferable to reduce variations in the doping concentration in the region under the insulating film.

Means for Solving the Problems

[0005] In order to solve the above problems, in a first aspect of the present invention, a semiconductor device is provided. The semiconductor device may include a semiconductor substrate in which both a first dopant of a first conductivity type and a second dopant of a second conductivity type are distributed throughout and which has a drift region of the first conductivity type. The semiconductor device may include an insulating film provided on the upper surface of the semiconductor substrate. Any of the above semiconductor devices may include a high-concentration region of the first conductivity type that is provided in contact with the insulating film below the insulating film and has a higher doping concentration than the drift region. Any of the above semiconductor devices may include a decreasing region that is provided in contact with the insulating film below the insulating film and in which the concentration of the second dopant of the second conductivity type decreases toward the insulating film.

[0006] In any of the above semiconductor devices, the difference between the maximum value and the minimum value of the concentration of the first dopant of the first conductivity type in the high-concentration region may be larger than the difference between the maximum value and the minimum value of the concentration of the second dopant in the decreasing region.

[0007] In any of the above semiconductor devices, the high-concentration region may extend below the decreasing region.

[0008] In any of the above semiconductor devices, the maximum net doping concentration in the high-concentration region may be 10 times or more the net doping concentration in the drift region.

[0009] In any of the above semiconductor devices, the maximum value of the net doping concentration in the high-concentration region is 1 × 10⁻⁶ 14 / cm 3 That's all.

[0010] Any of the above semiconductor devices may further include an active portion on a semiconductor substrate, where at least one of a transistor portion and a diode portion is provided. Any of the above semiconductor devices may also include an edge termination structure portion on the semiconductor substrate located outside the active portion. In any of the above semiconductor devices, a high-concentration region and a low-concentration region may be formed in the edge termination structure portion.

[0011] In any of the above semiconductor devices, the edge termination structure may have a plurality of guard rings of a second conductivity type provided in contact with the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the high-density region may be located between two guard rings. In any of the above semiconductor devices, the insulating film may be located between two guard rings. In any of the above semiconductor devices, the lower end of the high-density region may be located on the upper surface side of the semiconductor substrate than the lower end of the guard ring.

[0012] In any of the above semiconductor devices, the edge termination structure may have a plurality of guard rings of a second conductivity type provided in contact with the upper surface of the semiconductor substrate. In any of the above semiconductor devices, the high-density region may be located between two guard rings. In any of the above semiconductor devices, the insulating film may be located between two guard rings. In any of the above semiconductor devices, the lower end of the high-density region may be located on the lower surface side of the semiconductor substrate than the lower end of the guard ring.

[0013] In any of the above semiconductor devices, the insulating film may be embedded in the semiconductor substrate in at least a portion of its form.

[0014] In any of the above semiconductor devices, the depth from the top surface of the semiconductor substrate to the bottom edge of the insulating film may be 0.3 μm or more. In any of the above semiconductor devices, the depth from the top surface of the semiconductor substrate to the bottom edge of the insulating film may be 2 μm or more.

[0015] In any of the above semiconductor devices, the insulating film may have a first insulating film and a second insulating film laminated on the first insulating film.

[0016] Any of the above semiconductor devices may include a field plate made of polysilicon, which extends from above the guard ring to above the insulating film. In any of the above semiconductor devices, the field plate may have a groove that is recessed toward the upper surface of the semiconductor substrate at a position overlapping with the insulating film. In any of the above semiconductor devices, the field plate may have an extended portion that extends toward the center of the insulating film from the groove.

[0017] In any of the above semiconductor devices, the net doping concentration NF_s( / cm²) at the boundary between the high-concentration region and the insulating film is 3 The following equation may be satisfied. NF_s≧γ(1.35-0.6α)(1 / (1-α))Nnet However, γ is a real number greater than or equal to 2, and α is the bulk acceptor concentration Na ( / cm³). 3 ) and bulk donor concentration Nd( / cm³) 3 ) is the ratio Na / Nd, and Nnet is the bulk net doping concentration ( / cm³). 3 )

[0018] In any of the above semiconductor devices, α may be 0.7 or less.

[0019] Any of the above semiconductor devices may include a plurality of guard rings of a second conductivity type provided in contact with the upper surface of a semiconductor substrate. Any of the above semiconductor devices may include an embedded insulating film disposed between two guard rings, with at least a portion embedded inside the semiconductor substrate. In any of the above semiconductor devices, the high-density region may be disposed between two guard rings. In any of the above semiconductor devices, the insulating film may be disposed between two guard rings. In any of the above semiconductor devices, the lower end of the high-density region may be located on the upper surface side of the semiconductor substrate below the lower end of the guard rings. In any of the above semiconductor devices, the guard rings may be provided below the embedded insulating film. In any of the above semiconductor devices, the lower end of the high-density region may be located on the lower surface side of the semiconductor substrate below the lower end of the guard rings.

[0020] In any of the above semiconductor devices, the active portion may have a well region of a second conductivity type located at the boundary with the edge termination structure. In any of the above semiconductor devices, an extended region of a second conductivity type, connected to the well region and having a lower doping concentration than the well region, may be provided in the edge termination structure. In any of the above semiconductor devices, a high-concentration region may be located outside the extended region.

[0021] In any of the above semiconductor devices, the lower end of the high-density region may be located deeper than the lower end of the extended region when viewed from the upper surface of the semiconductor substrate.

[0022] In any of the above semiconductor devices, the high-concentration region may also be provided between the extended region and the drift region.

[0023] In any of the above semiconductor devices, a high-concentration region may also be provided between the well region and the drift region.

[0024] In any of the above semiconductor devices, the lower end of the high-density region may be positioned shallower than the lower end of the extended region when viewed from the upper surface of the semiconductor substrate.

[0025] In any of the above semiconductor devices, the doping concentration in the extended region may be lower the further it is from the well region.

[0026] In any of the above semiconductor devices, the first dopant and the first conductivity type dopant in the high-concentration region may be the same element.

[0027] In any of the above semiconductor devices, the first dopant and the first conductivity type dopant in the high-concentration region may be different elements.

[0028] A second embodiment of the present invention provides a method for manufacturing a semiconductor device. The manufacturing method may include a substrate preparation step of preparing a semiconductor substrate having a drift region of the first conductivity type, in which both a first dopant of the first conductivity type and a second dopant of the second conductivity type are distributed throughout. The manufacturing method may include a high-concentration region formation step of forming a high-concentration region having a doping concentration of the first conductivity type higher than that of the drift region in at least a portion of the upper surface of the semiconductor substrate. Any of the above manufacturing methods may include an insulating film formation step of forming an insulating film disposed in contact with the high-concentration region on the upper surface of the semiconductor substrate, and a decreasing region below the insulating film that is in contact with the insulating film and in which the concentration of the second conductivity type dopant decreases toward the insulating film.

[0029] In any of the above manufacturing methods, the insulating film may be formed by thermal oxidation in the insulating film formation step. In any of the above manufacturing methods, the depth of the high-concentration region formed in the high-concentration region formation step may be adjusted according to the thermal oxidation conditions in the insulating film formation step.

[0030] In any of the above manufacturing methods, the first dopant and the first conductivity type dopant in the high-concentration region may be the same element.

[0031] In any of the above manufacturing methods, the first dopant and the first conductivity type dopant in the high-concentration region may be different elements.

[0032] It should be noted that the above summary of the invention does not enumerate all the necessary features of the present invention. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]

[0033] [Figure 1] This is an example of a top view of a semiconductor device 100. [Figure 2] Figure 1 shows an example of a cross-section AA. [Figure 3] Figure 1 shows an example of a BB cross-section. [Figure 4] This is a magnified view of the vicinity of the guard ring 92 and the embedded insulating film 95. [Figure 5] This figure shows another example of the configuration of the embedded insulating film 95. [Figure 6] This figure shows examples of the shapes of the embedded insulating film 95 and the field plate 93. [Figure 7] This figure shows some of the steps in the manufacturing method of a semiconductor device 100. [Figure 8] This figure shows the manufacturing process after the manufacturing process shown in Figure 7. [Figure 9] Figure 1 shows an example of a cross-section of CC. [Figure 10] This figure shows another example of a BB cross section. [Figure 11] This is a magnified view of the vicinity of the high-concentration region 302. [Figure 12] Figure 11 shows an example of the distribution of N-type dopant concentration, P-type dopant concentration, and net doping concentration along the DD line. [Figure 13] This figure shows another example of the high-concentration region 302. [Figure 14] This figure shows another example of a BB cross section. [Figure 15] This figure shows another example of a BB cross section. [Figure 16] This figure shows an example of the arrangement of the field plate 93. [Figure 17] This figure shows another example of a BB cross section. [Figure 18] This figure shows another example of a BB cross section. [Figure 19A] This figure shows another example of a BB cross section. [Figure 19B] This figure shows another example of a BB cross section. [Figure 20] This figure shows another example of a BB cross section. [Figure 21] This figure shows another example of a BB cross section. [Figure 22] This figure shows another example of a BB cross section. [Figure 23] This figure shows some steps in the manufacturing method of a semiconductor device 100 having a high-concentration region 302. [Figure 24] This figure shows an example of the boron concentration distribution below the oxide film. [Figure 25] This figure shows an example of the concentration distribution of bulk donors and bulk acceptors, as well as the net doping concentration distribution. [Figure 26] This figure shows the relationship between concentration Nnet_s and α. [Figure 27] This figure shows an example of the net doping concentration distribution in the high-concentration region 302. [Modes for carrying out the invention]

[0034] The present invention will be described below through embodiments, but these embodiments are not intended to limit the scope of the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.

[0035] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top" and "bottom" are not limited to the direction of gravity or the direction in which the semiconductor device is mounted.

[0036] In this specification, technical matters may be described using the Cartesian coordinate axes, the X, Y, and Z axes. The Cartesian coordinate axes merely specify the relative positions of components and do not limit any particular direction. For example, the Z axis does not limit the direction to height relative to the ground. Note that the +Z axis direction and the -Z axis direction are opposite directions. When the sign is not specified and only the Z axis direction is written, it means the direction parallel to the +Z and -Z axes.

[0037] In this specification, the orthogonal axes parallel to the top and bottom surfaces of the semiconductor substrate are defined as the X and Y axes. The axis perpendicular to the top and bottom surfaces of the semiconductor substrate is defined as the Z axis. In this specification, the direction of the Z axis may be referred to as the depth direction. In this specification, the direction parallel to the top and bottom surfaces of the semiconductor substrate, including the X and Y axes, may be referred to as the horizontal direction. In this specification, when the term "top surface side" refers to the region from the center to the top surface in the depth direction of the semiconductor substrate, it means the region from the center to the bottom surface in the depth direction of the semiconductor substrate.

[0038] In this specification, the terms "identical" or "equal" may include cases where there are errors due to manufacturing variations, etc. Such errors are, for example, within 10%.

[0039] In this specification, the conductivity type of a doped region containing impurities is described as P-type or N-type. N-type and P-type are examples of first and second conductivity types. N-type may be the first conductivity type and P-type the second conductivity type, or P-type may be the first conductivity type and N-type the second conductivity type. In this specification, impurities may particularly mean either an N-type donor or a P-type acceptor, and may be referred to as dopants. In this specification, doping means introducing a donor or acceptor into a semiconductor substrate to make it a semiconductor exhibiting an N-type conductivity type or a P-type conductivity type.

[0040] In this specification, the doping concentration means the concentration of donors or acceptors in the thermal equilibrium state. In this specification, the net doping concentration means the net concentration obtained by adding the donor concentration as the positive ion concentration and the acceptor concentration as the negative ion concentration, including the polarity of the charge. As an example, if the donor concentration is N D , and the acceptor concentration is N A , then the net net doping concentration at any position is |N D - N A |.

[0041] A donor has the function of supplying electrons to a semiconductor. An acceptor has the function of receiving electrons from a semiconductor. Donors and acceptors are not limited to the impurities themselves. For example, a VOH defect in which a vacancy (V), oxygen (O), and hydrogen (H) present in a semiconductor are combined functions as a donor that supplies electrons.

[0042] When described as P+ type or N+ type in this specification, it means that the doping concentration is higher than that of P type or N type. When described as P- type or N- type, it means that the doping concentration is lower than that of P type or N type. Also, when described as P++ type or N++ type in this specification, it means that the doping concentration is higher than that of P+ type or N+ type.

[0043] In this specification, the chemical concentration refers to the atomic density of impurities measured regardless of the electrical activation state. The chemical concentration (atomic density) can be measured, for example, by secondary ion mass spectrometry (SIMS). The net doping concentration described above can be measured by the voltage-capacitance measurement method (CV method). Also, the carrier density measured by the spreading resistance measurement method (SR method) may be used as the net doping concentration. The carrier density measured by the CV method or the SR method may be taken as the value in the thermal equilibrium state. Also, in the N-type region, since the donor concentration is sufficiently larger than the acceptor concentration, the carrier density in the region may be used as the donor concentration. Similarly, in the P-type region, the carrier density in the region may be used as the acceptor concentration.

[0044] Furthermore, if the concentration distribution of donor, acceptor, or net doping has a peak, the peak value may be used as the concentration of donor, acceptor, or net doping in that region. In cases where the concentrations of donor, acceptor, or net doping are nearly uniform, the average value of the concentrations of donor, acceptor, or net doping in that region may be used as the concentration of donor, acceptor, or net doping.

[0045] The carrier density measured by the SR method may be lower than the donor or acceptor concentration. When measuring spreading resistance, the carrier mobility of the semiconductor substrate may be lower than the value for the crystalline state in the range where current flows. The decrease in carrier mobility occurs because carriers are scattered due to disorder in the crystal structure caused by lattice defects, etc.

[0046] The donor or acceptor concentrations calculated from carrier densities measured by the CV or SR method may be lower than the chemical concentrations of the elements exhibiting donor or acceptor properties. For example, in silicon semiconductors, the donor concentrations of phosphorus or arsenic, or the acceptor concentration of boron, are approximately 99% of their respective chemical concentrations. On the other hand, the donor concentration of hydrogen in silicon semiconductors is approximately 0.1% to 10% of the hydrogen chemical concentration.

[0047] Figure 1 is an example of a top view of a semiconductor device 100. In Figure 1, the positions of each component projected onto the top surface of the semiconductor substrate 10 are shown. In Figure 1, only some of the components of the semiconductor device 100 are shown, and some components are omitted.

[0048] The semiconductor device 100 comprises a semiconductor substrate 10. The semiconductor substrate 10 is a substrate formed of a semiconductor material. As an example, the semiconductor substrate 10 is a silicon substrate. In this example, the semiconductor substrate 10 has N-type bulk donors distributed throughout. Bulk donors are donors from dopants that are substantially uniformly contained in the ingot during the manufacturing of the ingot that forms the basis of the semiconductor substrate 10. In this example, the bulk donors are elements other than hydrogen. The bulk donor dopants are, for example, group V and group VI elements, such as phosphorus, antimony, arsenic, selenium, or sulfur, but are not limited to these. In this example, the bulk donor is phosphorus. Bulk donors are also included in the P-type region. The semiconductor substrate 10 may be a wafer cut from a semiconductor ingot, or it may be a chip made by cutting a wafer into individual pieces. Semiconductor ingots may be manufactured using one of the following methods: the Czochralski method (CZ method), the magnetic field-applied Czochralski method (MCZ method), or the float zone method (FZ method).

[0049] The oxygen chemical concentration in substrates manufactured by the MCZ method is, for example, 1 × 10⁻⁶. 17 ~7×10 17 atoms / cm 3 For example, the oxygen chemical concentration in a substrate manufactured by the FZ method is 1 × 10⁻⁶. 15 ~5×10 16 atoms / cm 3 The bulk donor concentration may be the chemical concentration of the bulk donor distributed throughout the semiconductor substrate 10, and may be a value between 90% and 100% of that chemical concentration. In a semiconductor substrate doped with group V and group VI dopants such as phosphorus, the bulk donor concentration is 1 × 10⁻⁶. 11 / cm 3 The above is 3 x 10 13 / cm 3 The following may apply: The bulk donor concentration of the semiconductor substrate doped with group V and group VI dopants is preferably 1 × 10⁻⁶. 12 / cm 3 The above is 1 x 10 13 / cm 3The following applies. Furthermore, the semiconductor substrate 10 may be a non-doped substrate that substantially does not contain bulk dopants such as phosphorus. In that case, the bulk donor concentration of the non-doped substrate is, for example, 1 × 10⁻⁶. 10 / cm 3 The above 5 x 10 12 / cm 3 The following applies: The bulk donor concentration of the non-doped substrate is preferably 1 × 10⁻⁶. 11 / cm 3 That concludes the explanation. The bulk donor concentration of the non-doped substrate is preferably 5 × 10⁻⁶. 12 / cm 3 The following applies:

[0050] Furthermore, P-type bulk acceptors may be distributed throughout the semiconductor substrate 10. The bulk acceptors may be acceptors formed by dopants that are substantially uniformly contained within the ingot during the manufacturing of the ingot that forms the basis of the semiconductor substrate 10, or they may be acceptors injected throughout the wafer or chip-shaped semiconductor substrate 10. The bulk acceptors may be boron. The bulk acceptor concentration may be lower than the bulk donor concentration. In other words, the bulk of the ingot or semiconductor substrate 10 is N-type. As an example, the bulk acceptor concentration may be 5 × 10⁻⁶. 11 ( / cm 3 )~8×10 14 ( / cm 3 ) and the bulk donor concentration is 5 × 10 12 ( / cm 3 )~1×10 15 ( / cm 3 The bulk acceptor concentration may be 1% or more, 10% or more, or 50% or more of the bulk donor concentration. The bulk acceptor concentration may be 99% or less, 95% or less, or 90% or less of the bulk donor concentration. The bulk acceptor concentration and bulk donor concentration may be the chemical concentration of impurities such as boron or phosphorus distributed throughout the semiconductor substrate 10. The bulk acceptor concentration and bulk donor concentration may be the value at the center in the depth direction of the semiconductor substrate 10 of the chemical concentration of impurities such as boron or phosphorus distributed throughout the semiconductor substrate 10.

[0051] The semiconductor substrate 10 has a top surface and a bottom surface. The top surface and the bottom surface are the two main surfaces of the semiconductor substrate 10. The semiconductor substrate 10 has edges 102 when viewed from above. When referred to simply as "top view" in this specification, it means viewing from the top side of the semiconductor substrate 10. In this example, the semiconductor substrate 10 has two pairs of edges 102 that face each other when viewed from above. In Figure 1, the X and Y axes are parallel to either edge 102. The Z axis is perpendicular to the top surface of the semiconductor substrate 10.

[0052] The semiconductor substrate 10 is provided with an active section 160. The active section 160 is a region in which the main current flows in the depth direction between the upper and lower surfaces of the semiconductor substrate 100 when the semiconductor device 100 is operating. An emitter electrode is provided above the active section 160, but it is omitted in Figure 1.

[0053] The active section 160 is provided with at least one of a transistor section 70 including a transistor element such as an IGBT, and a diode section 80 including a diode element such as a freewheeling diode (FWD). In the example shown in Figure 1, the transistor section 70 and the diode section 80 are arranged alternately along a predetermined arrangement direction (in this example, the X-axis direction) on the upper surface of the semiconductor substrate 10. In other examples, the active section 160 may be provided with only one of the transistor section 70 and the diode section 80.

[0054] In Figure 1, the region where the transistor section 70 is located is denoted by the symbol "I," and the region where the diode section 80 is located is denoted by the symbol "F." In this specification, the direction perpendicular to the arrangement direction in a top view may be referred to as the extension direction (Y-axis direction in Figure 1). The transistor section 70 and the diode section 80 may each have their longitudinal length in the extension direction. That is, the length of the transistor section 70 in the Y-axis direction is greater than its width in the X-axis direction. Similarly, the length of the diode section 80 in the Y-axis direction is greater than its width in the X-axis direction. The extension direction of the transistor section 70 and the diode section 80 may be the same as the longitudinal direction of each trench section described later.

[0055] The diode section 80 has an N+ type cathode region in the area in contact with the lower surface of the semiconductor substrate 10. In this specification, the region in which the cathode region is provided is referred to as the diode section 80. In other words, the diode section 80 is the region that overlaps with the cathode region when viewed from above. A P+ type collector region may be provided on the lower surface of the semiconductor substrate 10 in areas other than the cathode region. In this specification, an extension region 81, which is an extension of the diode section 80 in the Y-axis direction to the gate wiring described later, may also be included in the diode section 80. A collector region is provided on the lower surface of the extension region 81.

[0056] The transistor section 70 has a P+ type collector region in the area in contact with the lower surface of the semiconductor substrate 10. Furthermore, the transistor section 70 has a gate structure periodically arranged on the upper surface side of the semiconductor substrate 10, which includes an N+ type emitter region, a P- type base region, a gate conductive portion, and a gate insulating film.

[0057] The semiconductor device 100 may have one or more pads on the semiconductor substrate 10. In this example, the semiconductor device 100 has a gate pad 112. The semiconductor device 100 may have an anode pad and a cathode pad connected to a diode for temperature detection, and may also have a pad for current detection. Each pad is located near the edge 102. The vicinity of the edge 102 refers to the region between the edge 102 and the emitter electrode in a top view. When the semiconductor device 100 is mounted, each pad may be connected to an external circuit via wiring such as wires.

[0058] A gate potential is applied to the gate pad 112. The gate pad 112 is electrically connected to the conductive portion of the gate trench of the active portion 160. The semiconductor device 100 is provided with gate wiring that connects the gate pad 112 to the gate trench. In Figure 1, the gate wiring is hatched with diagonal lines.

[0059] The gate wiring in this example has an outer perimeter gate wiring 130 and an active-side gate wiring 131. The outer perimeter gate wiring 130 is positioned between the active portion 160 and the edge 102 of the semiconductor substrate 10 in a top view. In this example, the outer perimeter gate wiring 130 surrounds the active portion 160 in a top view. The area surrounded by the outer perimeter gate wiring 130 in a top view may be considered the active portion 160. The outer perimeter gate wiring 130 is also connected to the gate pad 112. The outer perimeter gate wiring 130 is positioned above the semiconductor substrate 10. The gate wiring may be a metal wiring containing aluminum or the like, a wiring formed from polysilicon, or a laminated wiring in which these wirings are stacked.

[0060] The active gate wiring 131 is provided in the active section 160. By providing the active gate wiring 131 in the active section 160, variations in the wiring length from the gate pad 112 can be reduced for each region of the semiconductor substrate 10.

[0061] The active gate wiring 131 is connected to the gate trench portion of the active section 160. The active gate wiring 131 is positioned above the semiconductor substrate 10. The active gate wiring 131 may be wiring formed of a semiconductor such as polysilicon doped with impurities.

[0062] The active gate wiring 131 may be connected to the outer gate wiring 130. In this example, the active gate wiring 131 extends in the X-axis direction, crossing the active section 160 from one outer gate wiring 130 to the other outer gate wiring 130 approximately in the center in the Y-axis direction. When the active section 160 is divided by the active gate wiring 131, the transistor section 70 and the diode section 80 may be arranged alternately in the X-axis direction in each divided region.

[0063] Furthermore, the semiconductor device 100 may also include a temperature sensing unit (not shown) which is a PN junction diode made of polysilicon or the like, and a current detection unit (not shown) which simulates the operation of a transistor unit provided in the active unit 160.

[0064] The semiconductor device 100 in this example includes an edge termination structure 90 between the active portion 160 and the edge 102. The edge termination structure 90 is located on the semiconductor substrate 10, outside of the active portion 160. On the semiconductor substrate 10, "outside" refers to the side closer to the edge 102. In this example, the edge termination structure 90 is located between the outer peripheral gate wiring 130 and the edge 102. The edge termination structure 90 mitigates electric field concentration on the upper surface side of the semiconductor substrate 10. The edge termination structure 90 has a plurality of guard rings 92. The guard rings 92 are P-shaped regions in contact with the upper surface of the semiconductor substrate 10. The guard rings 92 may surround the active portion 160 when viewed from above. The plurality of guard rings 92 are arranged at predetermined intervals between the outer peripheral gate wiring 130 and the edge 102. The outer guard rings 92 may surround the guard ring 92 located one position inward. The outer side refers to the side closer to the edge 102, and the inner side refers to the side closer to the center when viewed from above the semiconductor substrate 10. By providing multiple guard rings 92, the depletion layer on the upper side of the active portion 160 can be extended outwards, thereby improving the breakdown voltage of the semiconductor device 100. The edge termination structure 90 may further include at least one of a field plate and a resurf, which are provided in an annular shape surrounding the active portion 160.

[0065] Figure 2 shows an example of the AA cross-section in Figure 1. The AA cross-section is the XZ plane passing through the transistor section 70 and the diode section 80. In this example, the semiconductor device 100 has a semiconductor substrate 10, an interlayer insulating film 38, an emitter electrode 52, and a collector electrode 24 in this cross-section. The interlayer insulating film 38 is provided on the upper surface 21 of the semiconductor substrate 10. The interlayer insulating film 38 is a film that includes at least one layer of insulating film such as silicate glass with impurities such as boron or phosphorus added, a thermal oxide film, a nitride film, and other insulating films. The interlayer insulating film 38 is provided with a contact hole 54 that connects the emitter electrode 52 and the semiconductor substrate 10.

[0066] The emitter electrode 52 is provided above the interlayer insulating film 38. The emitter electrode 52 is in contact with the upper surface 21 of the semiconductor substrate 10 through the contact hole 54 of the interlayer insulating film 38. The emitter electrode 52 may be in contact with the emitter region 12, contact region and base region 14, which will be described later. The collector electrode 24 is provided on the lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are made of a metallic material such as aluminum. In this specification, the direction connecting the emitter electrode 52 and the collector electrode 24 (Z-axis direction) is referred to as the depth direction.

[0067] The semiconductor substrate 10 has an N-- type drift region 18. The doping concentration of the drift region 18 may be equal to the bulk donor concentration, or it may be equal to the bulk net doping concentration, which is the difference between the bulk donor concentration and the bulk acceptor concentration. In other examples, the doping concentration of the drift region 18 may be higher than the bulk donor concentration or the bulk net doping concentration. The drift region 18 is provided in both the transistor section 70 and the diode section 80.

[0068] One or more gate trenches 40 and dummy trenches 30 are provided on the upper surface of the semiconductor substrate 10. The gate trenches 40 function as gate electrodes when a gate voltage is applied, while the dummy trenches 30 do not function as gate electrodes when no gate voltage is applied. In this specification, the gate trenches 40 and dummy trenches 30 may be referred to as trenches. The trenches are provided in the depth direction from the upper surface 21 of the semiconductor substrate 10 to the drift region 18. The trenches also extend in the stretching direction (Y-axis direction) on the upper surface 21 of the semiconductor substrate 10.

[0069] Each of the transistor section 70 and the diode section 80 has multiple trench sections arranged in the direction of arrangement. In this example, the transistor section 70 has one or more gate trench sections 40 and one or more dummy trench sections 30 alternately provided along the direction of arrangement. In this example, the diode section 80 has multiple dummy trench sections 30 provided along the direction of arrangement. In this example, the diode section 80 does not have gate trench sections 40.

[0070] In the arrangement direction, mesa portions are provided between each trench portion. A mesa portion refers to a region within the semiconductor substrate 10 that is sandwiched between trench portions. For example, the upper end of a mesa portion is the upper surface of the semiconductor substrate 10. The depth position of the lower end of a mesa portion is the same as the depth position of the lower end of a trench portion. In this example, the mesa portion is provided on the upper surface of the semiconductor substrate 10, extending along the trench in the extension direction (Y-axis direction). In this example, a mesa portion 60 is provided in the transistor portion 70, and a mesa portion 61 is provided in the diode portion 80. In this specification, when simply referred to as a mesa portion, it refers to mesa portion 60 and mesa portion 61, respectively.

[0071] The mesa portion 60 of the transistor portion 70 is provided with an N+ type emitter region 12 and a P- type base region 14, arranged sequentially from the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. An N- type storage region 16 may also be provided in the mesa portion 60. The storage region 16 is located between the base region 14 and the drift region 18.

[0072] The emitter region 12 is exposed on the upper surface 21 of the semiconductor substrate 10 and is provided in contact with the gate trench portion 40. The emitter region 12 may be in contact with the trench portions on both sides of the mesa portion 60. The doping concentration of the emitter region 12 is higher than that of the drift region 18.

[0073] The base region 14 is located below the emitter region 12. In this example, the base region 14 is located in contact with the emitter region 12. The base region 14 may be in contact with the trenches on both sides of the mesa region 60.

[0074] The storage region 16 is located below the base region 14. The storage region 16 is an N-type region with a higher doping concentration than the drift region 18. By providing a high-concentration storage region 16 between the drift region 18 and the base region 14, the carrier injection promotion effect (IE effect) can be enhanced, and the on-voltage can be reduced. The storage region 16 may be provided so as to cover the entire lower surface of the base region 14 in each mesa portion 60.

[0075] A P-type base region 14 is provided in the mesa portion 61 of the diode portion 80, in contact with the upper surface 21 of the semiconductor substrate 10. A drift region 18 is provided below the base region 14. A storage region 16 may also be provided below the base region 14 in the mesa portion 61.

[0076] At least one of the mesa portion 60 and the mesa portion 61 may be provided with a P+ type contact region exposed on the upper surface 21 of the semiconductor substrate 10. For example, in the mesa portion 60, the contact region and the emitter region 12 may be arranged alternately along the Y-axis.

[0077] In both the transistor section 70 and the diode section 80, an N-type buffer section 20 may be provided on the lower surface 23 side of the drift section 18. The doping concentration of the buffer section 20 is higher than that of the drift section 18. The buffer section 20 has one or more donor concentration peaks with higher donor concentrations than the drift section 18. The buffer section 20 may function as a field stop layer that prevents the depletion layer extending from the lower end of the base section 14 from reaching the P+ type collector section 22 and the N+ type cathode section 82.

[0078] In the transistor section 70, a P+ type collector region 22 is provided below the buffer region 20. The acceptor concentration of the collector region 22 is higher than that of the base region 14. The collector region 22 may contain the same acceptors as the base region 14, or it may contain different acceptors. The acceptors of the collector region 22 are, for example, boron.

[0079] In the diode section 80, an N+ type cathode region 82 is provided below the buffer region 20. The donor concentration of the cathode region 82 is higher than that of the drift region 18. The donor of the cathode region 82 is, for example, hydrogen or phosphorus. Note that the elements that serve as donors and acceptors for each region are not limited to the examples described above. The collector region 22 and the cathode region 82 are exposed to the lower surface 23 of the semiconductor substrate 10 and are connected to the collector electrode 24. The collector electrode 24 may be in contact with the entire lower surface 23 of the semiconductor substrate 10. The emitter electrode 52 and the collector electrode 24 are formed of a metallic material such as aluminum.

[0080] Each trench extends from the upper surface 21 of the semiconductor substrate 10, through the base region 14, and reaches the drift region 18. In regions where at least one of the emitter region 12, contact region, and storage region 16 is provided, each trench also extends through these doping regions and reaches the drift region 18. The statement that a trench penetrates a doping region is not limited to manufacturing processes where the doping region is formed before the trench. Manufacturing processes where doping regions are formed between trenches after the trenches have been formed are also included in the statement that a trench penetrates a doping region.

[0081] As described above, the transistor section 70 is provided with a gate trench section 40 and a dummy trench section 30. The diode section 80 is provided with a dummy trench section 30, but not with a gate trench section 40. In this example, the boundary between the diode section 80 and the transistor section 70 in the X-axis direction is the boundary between the cathode region 82 and the collector region 22.

[0082] The gate trench portion 40 has a groove-shaped gate trench provided on the upper surface 21 of the semiconductor substrate 10, a gate insulating film 42, and a gate conductive portion 44. The gate trench portion 40 is an example of a gate structure. The gate insulating film 42 is provided covering the inner wall of the gate trench. The gate insulating film 42 may be formed by oxidizing or nitriding the semiconductor on the inner wall of the gate trench. The gate conductive portion 44 is provided inside the gate trench, on the inside of the gate insulating film 42. In other words, the gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon.

[0083] The gate conductive portion 44 may be longer than the base region 14 in the depth direction. The gate trench portion 40 in this cross-section is covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. The gate conductive portion 44 is electrically connected to the gate wiring. When a predetermined gate voltage is applied to the gate conductive portion 44, a channel formed by an electron inversion layer is formed on the surface layer of the interface of the base region 14 that is in contact with the gate trench portion 40.

[0084] The dummy trench portion 30 may have the same structure as the gate trench portion 40 in its cross-section. The dummy trench portion 30 includes a dummy trench, a dummy insulating film 32, and a dummy conductive portion 34 provided on the upper surface 21 of the semiconductor substrate 10. The dummy conductive portion 34 may be connected to an electrode different from the gate pad. For example, the dummy conductive portion 34 may be connected to a dummy pad (not shown) that is connected to an external circuit different from the gate pad, and different control may be performed from that of the gate conductive portion 44. Alternatively, the dummy conductive portion 34 may be electrically connected to the emitter electrode 52. The dummy insulating film 32 is provided covering the inner wall of the dummy trench. The dummy conductive portion 34 is provided inside the dummy trench and is located inside the dummy insulating film 32. The dummy insulating film 32 insulates the dummy conductive portion 34 from the semiconductor substrate 10. The dummy conductive portion 34 may be formed from the same material as the gate conductive portion 44. For example, the dummy conductive part 34 is formed of a conductive material such as polysilicon. The dummy conductive part 34 may have the same length as the gate conductive part 44 in the depth direction.

[0085] The gate trench portion 40 and the dummy trench portion 30 in the cross-section are covered by an interlayer insulating film 38 on the upper surface 21 of the semiconductor substrate 10. As described above, the gate trench portion 40 may be connected to the gate wiring at any point, and the dummy trench portion 30 may be connected to the emitter electrode 52 at any point.

[0086] Figure 3 shows an example of a BB cross-section in Figure 1. The BB cross-section is the XZ plane passing through the outer gate wiring 130 and the edge termination structure 90. In Figure 3, a portion of the transistor section 70 near the outer gate wiring 130 is also shown.

[0087] The outer gate wiring 130 is positioned above the upper surface 21 of the semiconductor substrate 10. In this example, outer gate wiring 130-1 and outer gate wiring 130-2 are stacked in the Z-axis direction. Outer gate wiring 130-1 is made of a metallic material such as aluminum, and outer gate wiring 130-2 is made of polysilicon with impurities added.

[0088] The outer periphery gate wiring 130-2 and the semiconductor substrate 10 are insulated by an insulating film such as a thermal oxide film, but this is omitted in Figure 3. The outer periphery gate wiring 130-2 is connected to the gate conductive part 44 at one of the positions.

[0089] The outer gate wiring 130-1 is positioned above the outer gate wiring 130-2. An interlayer insulating film 38 is positioned between the outer gate wiring 130-1 and the outer gate wiring 130-2. The interlayer insulating film 38 is provided with a contact hole 132 for connecting the outer gate wiring 130-1 and the outer gate wiring 130-2. The contact hole 132 may be provided along the outer gate wiring 130 so as to surround the active part 160. The outer gate wiring 130-1 is connected to the outer gate wiring 130-2 through the contact hole 132.

[0090] A well region 11 is provided in the semiconductor substrate 10 below the outer peripheral gate wiring 130. The well region 11 extends from the upper surface 21 of the semiconductor substrate 10 to a depth greater than the base region 14. Preferably, the well region 11 extends deeper than the trench portion. The well region 11 is a P+ type region with a higher concentration than the base region 14. An interlayer insulating film 38 may be formed between the emitter electrode 52 and the well region 11. The well region 11 may be connected to the emitter electrode 52 via one or more contact holes 54 formed in the interlayer insulating film 38. That is, the well region 11 may be electrically connected to the emitter electrode 52.

[0091] The well region 11 is provided overlapping with the outer gate wiring 130. The well region 11 may also be provided extending to a predetermined width in areas that do not overlap with the outer gate wiring 130. The well region 11 may also be provided along the outer gate wiring 130 so as to surround the active portion 160. The well region 11 may also be located below the active-side gate wiring 131. By providing the well region 11, the depletion layer spreading from the active portion 160 can be easily extended to the edge termination structure 90, thereby suppressing failure in the active portion 160.

[0092] The edge termination structure 90 has a plurality of guard rings 92 and a plurality of embedded insulating films 95. The edge termination structure 90 in this example further has a plurality of field plates 93, a plurality of field electrodes 94, an outer electrode 97, an outer plate 96 and a channel stopper 98. The edge termination structure 90 may be in a region further outward than the outer peripheral end of the well region 11.

[0093] The guard ring 92 is a P+ type region provided in contact with the upper surface 21 of the semiconductor substrate 10. As shown in Figure 1, each guard ring 92 surrounds the active portion 160. The active portion 160 may be a region on the inner side of the outer peripheral edge of the well region 11. The lower end of the guard ring 92 may be positioned on the lower surface 23 side of the lower end of the base region 14. The lower end of the guard ring 92 may be positioned on the lower surface 23 side of the lower end of the trench portion. The lower end of the guard ring 92 may be positioned on the lower surface 23 side of the lower end of the well region 11, on the upper surface 21 side of the lower end of the well region 11, or at the same depth as the lower end of the well region 11. In this example, the lower end of the guard ring 92 is positioned at the same depth as the lower end of the well region 11.

[0094] Each embedded insulating film 95 is positioned between the two guard rings 92. The embedded insulating film 95 may be provided along the guard rings 92 so as to surround the active portion 160. The embedded insulating film 95 may also be provided between the outermost guard ring 92 and the channel stopper 98. The embedded insulating film 95 may also be provided between the innermost guard ring 92 and the well region 11.

[0095] The embedded insulating film 95 is embedded in the semiconductor substrate 10 in at least a portion of its structure. That is, at least a portion of the embedded insulating film 95 is located below the upper surface 21 of the semiconductor substrate 10. The upper surface 21 of the semiconductor substrate 10 may refer to the uppermost surface among the surfaces made of semiconductor material such as silicon. The thickness of the portion of the embedded insulating film 95 below the upper surface 21 of the semiconductor substrate 10 may be greater than the thickness of the portion above the upper surface 21. The entire embedded insulating film 95 may be located at the same position as or below the upper surface 21 of the semiconductor substrate 10. In this example, the upper surface of the embedded insulating film 95 is at the same position as the upper surface 21 of the semiconductor substrate 10, and the entire embedded insulating film 95 is located from the same position as the upper surface 21 of the semiconductor substrate 10, but below the upper surface 21.

[0096] The embedded insulating film 95 may have an insulating film obtained by oxidizing or nitriding the semiconductor substrate 10, an insulating film deposited by CVD or the like, or other insulating films. The embedded insulating film 95 may be a single-layer insulating film, or an insulating film obtained by laminating multiple films formed by different methods. In this example, the embedded insulating film 95 is a LOCOS film formed by creating a recess on the upper surface 21 of the semiconductor substrate 10 and thermally oxidizing the semiconductor material exposed in the recess.

[0097] By providing the embedded insulating film 95, it is possible to prevent the semiconductor substrate 10 from being exposed between the guard rings 92. In other words, it is possible to prevent the semiconductor substrate 10 between the guard rings 92 from coming into contact with the conductive member. Furthermore, by placing at least a portion of the embedded insulating film 95 inside the semiconductor substrate 10, the unevenness on the upper surface 21 of the semiconductor substrate 10 can be reduced. This makes it easier to form members that are placed above the upper surface 21 of the semiconductor substrate 10. For example, the step height of the field plate 93 can be reduced, making it easier to form the field plate 93.

[0098] In this example, the field plate 93 is made of polysilicon with impurities added. The field plate 93 is positioned above the guard ring 92. The field plate 93 is positioned to cover at least a portion of the guard ring 92. The field plate 93 may be positioned to cover the entire guard ring 92. The field plate 93 may be extended to a position where it does not overlap with the guard ring 92. An insulating film, such as a thermal oxide film, may be provided between the field plate 93 and the semiconductor substrate 10. In other examples, the field plate 93 and the guard ring 92 may be in contact, as shown in Figure 3.

[0099] In this example, the field electrode 94 is made of a metallic material such as aluminum. The field electrode 94 is positioned above the field plate 93. An interlayer insulating film 38 is positioned between the field electrode 94 and the field plate 93. The field electrode 94 and the field plate 93 are connected via contact holes provided in the interlayer insulating film 38. Although the cross-section shown in Figure 3 does not show these contact holes, other cross-sections show that the interlayer insulating film 38 has these contact holes. For example, as shown in Figure 9 later, which illustrates the CC cross-section of Figure 1, the interlayer insulating film 38 has these contact holes near the corners of the semiconductor substrate 10. In addition, the interlayer insulating film 38 has contact holes that connect the field electrode 94 and the guard ring 92. These contact holes may also be provided near the corners of the semiconductor substrate 10. Each field electrode 94 is electrically floating. For example, when the gate of the semiconductor device 100 is off, a voltage V is applied to the collector electrode 24. CE When a voltage V is applied, each field electrode 94 receives a voltage V CE A predetermined voltage lower than the specified value is applied.

[0100] The channel stopper 98 is provided in contact with the edge 102 and the top surface 21 of the semiconductor substrate 10. The channel stopper 98 is P-type with the same or higher concentration as the base region 14, or N-type with a higher concentration than the drift region 18. The outer plate 96 is positioned above the channel stopper 98 and is electrically connected to the channel stopper 98. The outer plate 96 is formed of polysilicon with impurities added. The outer plate 96 and the channel stopper 98 may be provided on an insulating film (not shown), connected via contact holes provided in the insulating film, or in direct contact. The channel stopper 98 may be connected to the outer electrode 97 via contact holes.

[0101] The outer electrode 97 is positioned above the outer plate 96. The outer electrode 97 is made of a metallic material such as aluminum. An interlayer insulating film 38 is provided between the outer electrode 97 and the outer plate 96. The outer electrode 97 and the outer plate 96 are connected via a contact hole provided in the interlayer insulating film 38. This contact hole may be provided near a corner of the semiconductor substrate 10. A predetermined voltage is applied to the outer electrode 97. The potential of the channel stopper 98 is the potential of the collector electrode 24. By setting the potential of the channel stopper 98 to the potential of the collector electrode 24, the depletion layer extending from the active portion 160 is suppressed by the outer electrode 97, preventing it from reaching the side surface of the semiconductor substrate 10. This improves the breakdown voltage of the semiconductor device 100. Note that the outer plate 96 is optional. In this case, the channel stopper 98 is connected to the outer electrode 97 via a contact hole provided in the interlayer insulating film 38.

[0102] Figure 4 is an enlarged view of the vicinity of the guard ring 92 and the embedded insulating film 95. The guard ring 92 extends below the embedded insulating film 95. That is, the end 203 of the guard ring 92 (the end in the X-axis direction in Figure 4) overlaps with the embedded insulating film 95 below it. Let Z1 be the distance in the Z-axis direction between the upper surface 21 of the semiconductor substrate 10 and the lower end of the embedded insulating film 95, and let Z2 be the distance in the Z-axis direction between the upper surface 21 of the semiconductor substrate 10 and the lower end of the guard ring 92. Distance Z2 is greater than distance Z1. Distance Z2 may be 1.5 times or more, 2 times or more, or 3 times or more than distance Z1. On the other hand, the difference between distance Z2 and distance Z1 (Z2-Z1) may be less than distance Z1. This allows for mitigation of the electric field strength and improves the breakdown voltage.

[0103] By providing an embedded insulating film 95 between the guard rings 92, the diffusion of ions such as phosphorus that form the guard rings 92 in the XY plane is suppressed by the embedded insulating film 95, and the width of each guard ring 92 (the width in the X-axis direction in the example of Figure 3) is reduced. For example, if impurity ions are implanted between two embedded insulating films 95 at a depth shallower than the embedded insulating film 95 and then heat-treated, at least a portion of the impurities will diffuse to a depth deeper than the embedded insulating film 95 before diffusing in the X-axis direction. Therefore, the diffusion of impurities in the X-axis direction is suppressed.

[0104] Furthermore, by providing the embedded insulating film 95, the end 203 of the guard ring 92 is not exposed to the upper surface 21 and is in contact with the embedded insulating film 95. As a comparative example, the guard ring 92 without the embedded insulating film 95 is shown by a dashed line. In the absence of the embedded insulating film 95, the end 204 of the guard ring 92 is exposed to the upper surface 21. As shown in Figure 4, by providing the embedded insulating film 95, the X-axis end 203 of the guard ring 92 can be positioned below the upper surface 21 of the semiconductor substrate 10. The closer the guard ring 92 is to the upper surface 21 of the semiconductor substrate 10, the wider the guard ring 92 becomes. Therefore, by positioning the end 203 below the upper surface 21, the width of the guard ring 92 in the X-axis direction can be reduced. The amount of reduction in the width of the guard ring 92 can be adjusted by the thickness Z1 of the embedded insulating film 95.

[0105] By reducing the width of the guard ring 92, the spacing between the guard rings 92 can be reduced while maintaining the pressure resistance, and the width of the edge termination structure 90 can be reduced. This makes it possible to miniaturize the semiconductor device 100. In other words, with respect to the semiconductor device 100, by providing the embedded insulating film 95, the flatness of the upper surface 21 of the semiconductor substrate 10 can be improved, and the size of the semiconductor device 100 can be reduced in the XY plane.

[0106] The embedded insulating film 95 in this example has a flat portion 201 and an end portion 202. The flat portion 201 includes the lower end of the embedded insulating film 95 and is a region with a substantially constant depth. The flat portion 201 may be a region of the embedded insulating film 95 with a depth of 0.5 × Z1 or more, a region of 0.7 × Z1 or more, or a region of 0.9 × Z1 or more. The end portion 202 is located outside the flat portion 201 and is a region with a smaller depth than the flat portion 201. The end portion 202 may include a portion in which the depth gradually decreases toward the outside. The end portion 203 of the guard ring 92 may be in contact with the flat portion 201. This can suppress variations in the width of the guard ring 92.

[0107] The depth Z1 from the upper surface 21 of the semiconductor substrate 10 to the lower end of the embedded insulating film 95 may be 0.3 μm or more. Increasing the depth Z1 allows the width of the guard ring 92 to be reduced. The depth Z1 may be 1 μm or more, or 2 μm or more. If the depth Z1 is made too large, it becomes difficult to form the embedded insulating film 95 flat. The depth Z1 may be 3 μm or less, 2 μm or less, or 1 μm or less.

[0108] Figure 5 shows another example of the configuration of the embedded insulating film 95. In this example, the embedded insulating film 95 has a first insulating film 206 and a second insulating film 208. The first insulating film 206 is in contact with the semiconductor substrate 10. The first insulating film 206 is, for example, a film obtained by oxidizing or nitriding the semiconductor substrate 10. The second insulating film 208 is laminated on the first insulating film 206. The second insulating film 208 is, for example, a deposited film formed by the CVD method. Because the embedded insulating film 95 has a laminated structure, an embedded insulating film 95 with a large thickness Z1 can be easily formed. Therefore, the width of the guard ring 92 can be easily reduced.

[0109] Figure 6 shows examples of the shapes of the embedded insulating film 95 and the field plate 93. When a recess is formed on the upper surface 21 of the semiconductor substrate 10 and the recess is thermally oxidized to form the embedded insulating film 95, a valley 210 may be formed on the upper surface of the embedded insulating film 95. The valley 210 is a portion that is recessed on the lower side. For example, the valley 210 may be formed at the intersection of an insulating film growing from the bottom surface of the recess and an insulating film growing from the side surface. At least a portion of the valley 210 may be formed on the upper surface of the end 202 of the embedded insulating film 95.

[0110] In this example, the field plate 93 has a valley 214 at a position overlapping with the embedded insulating film 95. The valley 214 is provided on the upper surface of the field plate 93 and is a recessed portion toward the upper surface 21 of the semiconductor substrate 10. In this example, the field plate 93 has an extended portion 218 that extends toward the center of the embedded insulating film 95 (position Xc in this example) from the valley 214. Position Xc is the center of the embedded insulating film 95 in the radial direction (X-axis direction in Figure 6) of the embedded insulating film 95 surrounding the active portion 160. The extended portion 218 may extend toward position Xc from the valley 210.

[0111] The extended portion 218 of any of the field plates 93 may extend beyond position Xc. For example, the extended portion 218 of the field plate 93 including the end on the active portion 160 side may extend beyond position Xc.

[0112] Figure 7 shows some steps in the manufacturing method of a semiconductor device 100. In recess formation step S702, a recess 232 is formed on the upper surface 21 of the semiconductor substrate 10. The recess 232 is formed between the regions where two guard rings 92 are to be formed in the edge termination structure 90. In the example in Figure 7, a mask 230 is selectively formed on the upper surface 21 of the semiconductor substrate 10, and a recess 232 is formed on the upper surface 21 of the semiconductor substrate 10 that is not covered by the mask 230. The mask 230 may include at least one of an oxide film, a nitride film, and a resist film. In this example, an initial oxide film is formed on the upper surface 21 of the semiconductor substrate 10, and then a nitride film is formed by CVD. A photoresist is applied on the nitride film and exposed in a predetermined pattern. After exposure, the photoresist, nitride film, and initial oxide film are selectively removed to form the mask 230.

[0113] Next, in the insulating film formation step S704, the upper surface 21 of the semiconductor substrate 10 is oxidized. In S704, the upper surface 21 of the semiconductor substrate 10 is oxidized while the mask 230 remains in place. Since oxidation of the upper surface 21 of the semiconductor substrate 10 does not proceed in the area covered by the mask 230, the embedded insulating film 95 can be selectively formed within the recess 232. After the embedded insulating film 95 is formed, the mask 230 is removed. The upper end of the embedded insulating film 95 is preferably at the same height as the upper surface 21 of the semiconductor substrate 10, but is not limited to this.

[0114] Next, in the implantation step S706, P-type dopant ions are implanted into the upper surface 21 of the semiconductor substrate 10. The P-type dopant is, for example, boron. In S706, ions are implanted with a mask 234 formed on the upper surface 21 of the semiconductor substrate 10. The mask 234 has an opening in the region where the guard ring 92 is to be formed. In this example, ions are implanted between two embedded insulating films 95. This allows for selective ion implantation into the region where the guard ring 92 is to be formed. After ion implantation, the semiconductor substrate 10 is annealed to form the guard ring 92. The annealing temperature may be 1000°C or higher and 1200°C or lower. The annealing time may be 1 hour or higher and 12 hours or lower. By performing annealing at a high temperature for a long time, a guard ring 92 that protrudes below the embedded insulating film 95 can be formed.

[0115] In S706, the depth to which the P-type dopant is injected may be on the upper surface 21 side of the lower end of the embedded insulating film 95. By injecting the P-type dopant shallower than the embedded insulating film 95, the diffusion of the P-type dopant in the X-axis direction is suppressed by the embedded insulating film 95. This makes it possible to reduce the width of the guard ring 92 in the X-axis direction. Also, as explained in Figure 4, the presence of the embedded insulating film 95 causes the end portion 203 of the guard ring 92 to be positioned below the upper surface 21. This also makes it possible to reduce the width of the guard ring 92 in the X-axis direction. In the manufacturing method of this example, the width of the edge termination structure 90 can be designed to be smaller, taking into consideration that the width of the guard ring 92 will be reduced.

[0116] In the example shown in Figure 7, the injection step S706 was performed after the recess formation step S702 and the insulating film formation step S704. However, the recess formation step S702 and the insulating film formation step S704 may be performed after the guard ring 92 has been formed by the injection step S706. In this case as well, the end portion 204 of the guard ring 92, as explained in Figure 4, is removed by the recess formation step S702, so the width of the guard ring 92 can be reduced.

[0117] Figure 8 shows the manufacturing process after the manufacturing process shown in Figure 7. After forming the embedded insulating film 95 and the guard ring 92, in the field plate formation step S802, the field plate 93 is formed above the guard ring 92. Before forming the field plate 93, an oxide film may be formed to cover the upper surface 21 of the semiconductor substrate 10. This oxide film may be formed in the same process as the gate insulating film 42. In S802, at least a portion of other parts formed of polysilicon (for example, the gate conductive part 44, the dummy conductive part 34, gate wiring such as the outer peripheral gate wiring 130-2, the outer plate 96, etc.) may also be formed. Note that between the injection step S706 and the field plate formation step S802, there may be a step to form a portion of the active part 160. The step to form a portion of the active part 160 may be, for example, a step to form a trench.

[0118] Next, in the field electrode formation step S804, a field electrode 94 is formed above the field plate 93. It is preferable to form the interlayer insulating film 38 before forming the field electrode 94. In S804, at least a portion of other parts formed of metallic material (for example, the emitter electrode 52, gate wiring such as the outer peripheral gate wiring 130-1, the outer electrode 97, etc.) may also be formed. Note that there may be other formation steps for the active part 160 between the field plate formation step S802 and the field electrode formation step S804. Other formation steps for the active part 160 may be, for example, formation steps for the base region, emitter region, or contact region. By such steps, the semiconductor device 100 can be manufactured.

[0119] Figure 9 shows an example of a CC cross-section in Figure 1. The CC cross-section is a cross-section perpendicular to the XY plane near the corner of the semiconductor substrate 10. As described above, the field plate 93 and the field electrode 94 are connected via a contact hole 240 provided in the interlayer insulating film 38. The field electrode 94 and the guard ring 92 are also connected via a contact hole 240 provided in the interlayer insulating film 38. The guard ring 92 may have a P++ type contact region 242 with a higher density than other parts in the region in contact with the contact hole 240.

[0120] The field plate 93 may have an opening for passing through a contact hole 240 that connects the field electrode 94 and the guard ring 92. The outer electrode 97 and the outer plate 96 are also connected via contact holes 240 provided in the interlayer insulating film 38. The inside of these contact holes 240 may be filled with a metallic material such as aluminum or tungsten. These contact holes 240 may be provided near the four corners of the semiconductor substrate 10.

[0121] The channel stopper 98 may be connected to the outer electrode 97 via a contact hole 240. The outer electrode 97 may be connected to the outer plate 96 via a contact hole. A contact region 242 may be provided on the upper surface of the channel stopper 98 below the contact hole 240. An insulating film (not shown) may be provided between the outer plate 96 and the channel stopper 98. The potential of the channel stopper 98 is the same as the potential of the collector electrode 24. Near the four corners of the semiconductor substrate 10, the potential of the outer electrode 97 or the outer plate 96 is made to match the potential of the channel stopper 98. This prevents the ring-shaped outer electrode 97 from causing the depletion layer to reach the edge of the semiconductor substrate.

[0122] Figure 10 shows another example of a BB cross-section. In this example, the semiconductor substrate 10 has both a first-type dopant (e.g., phosphorus) and a second-type dopant (e.g., boron) distributed throughout. The concentration of the first-type dopant is higher than the concentration of the second-type dopant. In other words, the semiconductor substrate 10 is a first-type (N-type in this example) substrate.

[0123] The semiconductor device 100 in this example further comprises a high-concentration region 302 in addition to any of the embodiments described in Figures 1 to 10. The high-concentration region 302 is provided below and in contact with an insulating film provided on the upper surface 21 of the semiconductor substrate 10. In this example, the insulating film is an embedded insulating film 95. The high-concentration region 302 is an N-type region with a higher doping concentration than the drift region 18.

[0124] The high-concentration region 302 may cover the lower surface of the insulating film provided on the upper surface 21 of the semiconductor substrate 10 so that the insulating film does not come into direct contact with the drift region 18. The high-concentration region 302 does not need to be provided on the lower surface of the insulating film that is covered by a region with a higher doping concentration than the drift region 18 (e.g., guard ring 92, well region 11, etc.). In this example, the high-concentration region 302 is provided between two guard rings 92. The high-concentration region 302 may also be provided between the outermost guard ring 92 and the channel stopper 98. The high-concentration region 302 may also be provided between the innermost guard ring 92 and the well region 11.

[0125] Figure 11 is an enlarged view of the vicinity of the high-density region 302. Let Z3 be the distance in the depth direction from the upper surface 21 of the semiconductor substrate 10 to the lower edge of the high-density region 302. Distance Z3 is greater than distance Z1. Distance Z3 may be less than distance Z2, the same as distance Z2, or greater than distance Z2. In the example in Figure 11, distance Z3 is slightly smaller than distance Z2. Distance Z3 may be less than 1 times distance Z2, and may be 0.9 times or less. Distance Z3 may be 0.5 times or more distance Z2, and may be 0.7 times or more.

[0126] Figure 12 shows an example of the distribution of N-type dopant concentration, P-type dopant concentration, and net doping concentration along the DD line in Figure 11. The DD line is parallel to the Z-axis and passes through the high-concentration region 302 and part of the drift region 18. In this example, the N-type dopant is phosphorus and the P-type dopant is boron. The horizontal axis in Figure 12 shows the depth position relative to the top surface 21 of the semiconductor substrate 10. However, the origin of the horizontal axis is the depth position Z1 at the lower end of the embedded insulating film 95.

[0127] As described above, both phosphorus and boron are distributed throughout the semiconductor substrate 10. The overall doping concentration of the semiconductor substrate 10 is adjusted by the difference in phosphorus and boron concentrations. In areas where phosphorus and boron are not locally implanted, the concentrations of phosphorus and boron are almost constant throughout the semiconductor substrate 10.

[0128] However, near the insulating film, impurities contained in the semiconductor substrate 10 may be drawn out into the insulating film or segregate, causing the impurity concentration to change. In the example in Figure 12, during processes such as thermal oxidation to form the embedded insulating film 95, the embedded insulating film 95 grows while incorporating boron from the surrounding region. As a result, the boron concentration in the surrounding region of the embedded insulating film 95 decreases toward the embedded insulating film 95. Also, the embedded insulating film 95 grows while sweeping phosphorus into the surrounding region. As a result, the phosphorus concentration in the surrounding region of the embedded insulating film 95 increases toward the boundary with the embedded insulating film 95. In Figure 12, the phosphorus concentration distribution and net doping concentration distribution before the formation of the high-concentration region 302 are shown by dashed lines, and the phosphorus concentration distribution and net doping concentration distribution after the formation of the high-concentration region 302 are shown by solid lines.

[0129] Near the embedded insulating film 95, the phosphorus concentration increases and the boron concentration decreases, so the net doping concentration in the N-type region increases. Therefore, in an N-type semiconductor substrate 10 in which P-type dopants such as boron are distributed throughout the substrate, the net doping concentration in the N-type region near the embedded insulating film 95 increases significantly. The magnitude of the increase in net doping concentration varies depending on the manufacturing process, resulting in large variations in the net doping concentration near the embedded insulating film 95.

[0130] In this example, an N-type high-concentration region 302 is formed in contact with the embedded insulating film 95. The dopant concentration in the high-concentration region 302 can be controlled with relatively high precision by the amount of ion implantation, etc. Therefore, the dopant concentration in the region below the embedded insulating film 95 includes not only components that vary due to impurity extraction, etc., but also components that can be controlled with high precision. Consequently, the controllability of the net doping concentration in the region below the embedded insulating film 95 can be improved.

[0131] In this example, the reduction region 304 is defined as a region below the embedded insulating film 95 that is in contact with the embedded insulating film 95 and in which the concentration of the second conductivity type dopant (boron in this example) decreases monotonically toward the embedded insulating film 95. In other words, in the reduction region 304, the closer the distance to the embedded insulating film 95, the lower the concentration of the second conductivity type dopant. The high-concentration region 302 and the reduction region 304 may be provided in the edge termination structure 90.

[0132] Let Bmax be the maximum boron concentration and Bmin be the minimum boron concentration in the reduction region 304. The concentration Bmax may be the same as the boron concentration in the drift region 18. Alternatively, the concentrations in the center of the semiconductor substrate 10 in the depth direction may be used as the concentrations in the drift region 18. Alternatively, the average value of the concentrations in a region including the center of the semiconductor substrate 10 in the depth direction and having a predetermined width in the depth direction may be used as the concentrations in the drift region 18. This predetermined width may be, for example, 10 μm or 20 μm. The concentration Bmin may be the boron concentration at the boundary with the embedded insulating film 95. Let D2 be the difference between the concentration Bmax and the concentration Bmin.

[0133] Furthermore, the lower end position of the reduction region 304 is defined as Z4. Position Z4 is the position where the boron concentration begins to decrease from the concentration Bmax in the drift region 18. If the position where the concentration begins to decrease is unclear, position Z4 may be defined as the position where the boron concentration is 0.9 × Bmax in the direction from the drift region 18 toward the embedded insulating film 95.

[0134] Let Pmax be the maximum phosphorus concentration and Pmin be the minimum phosphorus concentration in the high-concentration region 302. The concentration Pmin may be the same as the phosphorus concentration in the drift region 18. The concentration Pmax may also be the phosphorus concentration at the boundary with the embedded insulating film 95. Let D1 be the difference between the concentration Pmax and the concentration Pmin.

[0135] Furthermore, the lower end position of the high-concentration region 302 is Z3. Position Z3 is the position where the net doping concentration begins to rise from the concentration Dd in the drift region 18. If the position where the concentration begins to rise is unclear, position Z3 may be defined as the position where the net doping concentration is 1.1 × Dd in the direction from the drift region 18 toward the embedded insulating film 95.

[0136] As described above, the difference D1 in phosphorus concentration in the high-concentration region 302 can be controlled with relatively good accuracy by the amount of ion implantation, etc. On the other hand, the difference D2 in boron concentration in the depletion region 304 varies greatly during the manufacturing process. The controllability of the net doping concentration in the region near the embedded insulating film 95 can be improved by increasing the ratio of dopant concentrations that can be controlled with good accuracy (difference D1 in this example). It is preferable that the difference D1 in phosphorus concentration in the high-concentration region 302 is greater than the difference D2 in boron concentration in the depletion region 304. The difference D1 may be twice or more the difference D2, five times or more, or ten times or more.

[0137] On the other hand, if the phosphorus concentration in the high-concentration region 302 is made too high, it will affect the doping concentration of the adjacent guard ring 92. The maximum net doping concentration Dmax in the high-concentration region 302 may be smaller than the maximum net doping concentration of the guard ring 92. The maximum net doping concentration Dmax in the high-concentration region 302 may be 1 / 10 or less of the maximum net doping concentration of the guard ring 92, or it may be 1 / 100 or less.

[0138] Furthermore, the maximum net doping concentration Dmax in the high-concentration region 302 may be 10 times or more, 20 times or more, 50 times or more, or 100 times or more, the net doping concentration Dd in the drift region 18. The maximum net doping concentration Dmax in the high-concentration region 302 is 1 × 10⁻⁶ 14 / cm 3 The above is sufficient, 5 × 10 14 / cm 3 The above is sufficient, 1 × 10 15 / cm 3 That's fine too.

[0139] Furthermore, it is preferable that the high-concentration region 302 extends below the reduction region 304. In other words, it is preferable that position Z3 is located on the lower surface 23 side of position Z4. This reduces the variation in net doping concentration caused by the reduction region 304. The width of the high-concentration region 302 in the depth direction (Z3-Z1) may be 1.5 times or more, 2 times or more, or 5 times or more, the width of the reduction region 304 in the depth direction (Z4-Z1). As shown in Figure 11, the lower end of the high-concentration region 302 may be located on the upper surface 21 side of the semiconductor substrate 10 than the lower end of the guard ring 92.

[0140] Figure 13 shows another example of the high-concentration region 302. In this example, the lower end of the high-concentration region 302 is located on the lower surface 23 side of the semiconductor substrate 10, rather than on the lower end of the guard ring 92. That is, the distance Z3 from the upper surface 21 to the lower end of the high-concentration region 302 is greater than the distance Z2 from the upper surface 21 to the lower end of the guard ring 92. The high-concentration region 302 may or may not be provided in the active portion 160.

[0141] Figure 14 shows another example of a BB cross-section. The semiconductor device 100 in this example has an insulating film 195 instead of the embedded insulating film 95 in any of the configurations described in Figures 10 to 13. The insulating film 195 is, for example, a thermal oxide film. The other structures are the same as any of the configurations described in Figures 10 to 13.

[0142] The insulating film 195 is provided on the upper surface 21 of the semiconductor substrate 10. The position where the insulating film 195 is provided in the XY plane is the same as that of the embedded insulating film 95. That is, the insulating film 195 is located between the two guard rings 92 in the XY plane. At least a portion of the insulating film 195 is provided above the upper surface 21 of the semiconductor substrate 10. The entire insulating film 195 may be provided above the upper surface 21 of the semiconductor substrate 10. The guard rings 92 are formed below the insulating film 195. The insulating film 195 may also be a film in which the first insulating film and the second insulating film are laminated, as in the example in Figure 5.

[0143] The high-concentration region 302 is in contact with the insulating film 195 below the insulating film 195. In this example, the high-concentration region 302 is exposed on the upper surface 21 of the semiconductor substrate 10. The insulating film 195 covers the high-concentration region 302 exposed on the upper surface 21. Below the insulating film 195, the reduced-concentration region 304, as described in Figure 12, is formed. In this example as well, by providing the high-concentration region 302, the influence of variations in net doping concentration due to the reduced-concentration region 304 can be reduced.

[0144] Figure 15 shows another example of a BB cross-section. The structure of the high-concentration region 302 is different from the configuration shown in Figure 14. The other structures are the same as those shown in Figure 14. The high-concentration region 302 in this example has the same structure as the high-concentration region 302 described in Figure 13. In other words, the high-concentration region 302 in this example is formed to a greater depth than the guard ring 92. In this example as well, by providing the high-concentration region 302, the influence of variations in net doping concentration due to the reduction region 304 can be reduced.

[0145] Figure 16 shows an example of the arrangement of the field plate 93. In this example, the field plate 93 is positioned biased toward the active part 160 side relative to the guard ring 92 below. For example, in the X-axis direction, the center position of the field plate 93 is positioned toward the active part 160 side than the center position of the guard ring 92.

[0146] In this example, the end of the field plate 93 on the active part 160 side is designated as end 311, and the end on the edge 102 side is designated as end 312. End 311 may be positioned on the active part 160 side of the guard ring 92. End 312 may be positioned to overlap with the guard ring 92. At least one field plate 93 may be arranged as shown in Figure 16, and all field plates 93 may be arranged as shown in Figure 16. The arrangement of the field plates 93 in this example may be applied to any of the configurations shown in Figures 1 to 15.

[0147] Figure 17 shows another example of a BB cross section. The edge termination structure 90 in this example has a structure in which at least one field plate 93 of the edge termination structure 90 in Figures 1 to 16 is replaced with a guard ring electrode 91. The other structures are the same as those of the edge termination structure 90 in any of the embodiments described in Figures 1 to 16. The material of the guard ring electrode 91 is the same as that of the field plate 93. As an example, the guard ring electrode 91 is made of polysilicon. Each guard ring electrode 91 is connected to the field electrode 94 via a contact hole provided in the interlayer insulating film 38, similar to the field plate 93 in Figure 3.

[0148] The width of the field plate 93 in the X-axis direction, as shown in Figures 1 to 16, may be greater than the width of the guard ring 92 in the X-axis direction. In other words, in a top view, the field plate 93 covers a wider area than the guard ring 92 on either the active part 160 side or the edge 102 side of the semiconductor substrate 10, or both. In contrast, the width Xa of the guard ring electrode 91 in the X-axis direction is smaller than the width Xb of the guard ring 92 to which the guard ring electrode 91 is connected in the X-axis direction. In a top view, the entire guard ring electrode 91 overlaps with the guard ring 92.

[0149] Guard ring electrodes 91 may be provided for all guard rings 92, or guard ring electrodes 91 may be provided for some guard rings 92 and field plates 93 may be provided for the remaining guard rings 92. For example, guard ring electrodes 91 may be provided for one or more guard rings 92 located on the active part 160 side, and field plates 93 may be provided for one or more guard rings 92 located on the edge 102 side of the semiconductor substrate 10. In the example in Figure 17, a field plate 93 is provided for the outermost guard ring 92, and guard ring electrodes 91 are provided for the other guard rings 92.

[0150] Figure 18 shows another example of a BB cross section. The edge termination structure 90 in this example differs from the examples in Figures 1 to 17 in that the spacing of the guard rings 92 in the X-axis direction (X1, X2, X3) increases as it approaches the edge 102 of the semiconductor substrate 10. The other structures are the same as any of the embodiments described in Figures 1 to 17. Figure 18 shows an example in the structure shown in Figure 17 where the spacing of the guard rings 92 widens towards the outside. In this example, guard ring electrodes 91 are also provided for the outermost guard ring 92.

[0151] The doping concentrations in the high-concentration regions 302 located between each guard ring 92 may be the same. In another example, the doping concentrations in the high-concentration regions 302 located between each guard ring 92 may increase in proportion to the increase in the spacing between the guard rings 92. When the spacing between the guard rings 92 increases, the area in contact between the insulating film, such as the embedded insulating film 95, and the semiconductor substrate 10 increases. In this case, variations in the phosphorus and boron concentrations near the insulating film, such as the embedded insulating film 95, tend to increase. By increasing the doping concentration in the high-concentration regions 302 in proportion to the spacing between the guard rings 92, the influence of variations in the phosphorus and boron concentrations on the breakdown voltage of the semiconductor device 100 can be suppressed.

[0152] Figure 19A shows another example of a BB cross section. The edge termination structure 90 in this example differs from the examples in Figures 10 to 18 in that it has an extended region 306. Also, the edge termination structure 90 in this example does not have a guard ring 92, a guard ring electrode 91, a field plate 93, and a field electrode 94. The other structures are the same as in any of the embodiments described in Figures 10 to 18.

[0153] The extended region 306 is connected to the well region 11. In this example, the extended region 306 extends from the well region 11 toward the edge 102 of the semiconductor substrate 10. The doping concentration of the extended region 306 is lower than that of the well region 11. The doping concentration of the extended region 306 may be higher or lower than that of the base region 14. The extended region 306 may be formed to the same depth as the well region 11, to a shallower depth than the well region 11, or to a deeper depth than the well region 11.

[0154] A high-concentration region 302 is located outside the extended region 306. The high-concentration region 302 is in contact with the extended region 306. In this example, the high-concentration region 302 extends from the extended region 306 to the channel stopper 98. When viewed from the upper surface 21 of the semiconductor substrate 10, the lower end of the high-concentration region 302 may be located at a shallower position than the lower end of the extended region 306. In the edge termination structure 90 of each example described herein, the drift region 18 does not need to be exposed on the upper surface 21 of the semiconductor substrate 10. In the edge termination structure 90, a region with a higher doping concentration than the drift region 18 may be exposed on the upper surface 21 of the semiconductor substrate 10. An insulating film, such as an insulating film 195 or an embedded insulating film 95, is provided above the extended region 306 and the high-concentration region 302. In the edge termination structure 90, the insulating film, such as the insulating film 195 or the embedded insulating film 95, does not need to be in contact with the drift region 18.

[0155] The doping concentration in the extended region 306 is relatively low, and the extended region 306 is easily depleted. Therefore, the potential of the extended region 306 gradually changes in the direction from the well region 11 toward the edge 102 of the semiconductor substrate 10. This mitigates the concentration of the electric field at the edge termination structure 90, thereby improving the breakdown voltage of the semiconductor device 100. The length X4 in the X-axis direction of the extended region 306 may be greater than the length X5 in the X-axis direction of the high-concentration region 302. The length X5 may be less than or equal to half the length X4, or less than or equal to one-quarter of the length X4. In other examples, the length X4 may be the same as the length X5, or it may be smaller than the length X5. The doping concentration in the extended region 306 may be higher than or equal to that of the high-concentration region 302.

[0156] For example, the doping concentration in extended region 306 is 1 × 10⁻⁶ 15 / cm 3 The above is 1 x 10 17 / cm 3 The following is an example of the doping concentration in the high-concentration region 302, which is 1 × 10⁻⁶. 15 / cm 3The following applies: The doping concentrations in the extended region 306 and the high-concentration region 302 may be the concentrations on the upper surface 21 of the semiconductor substrate 10, or they may be the maximum concentrations in each region.

[0157] Figure 19B shows another example of a BB cross section. The edge termination structure 90 in this example differs from the example in Figure 19A in that, when viewed from the top surface 21, the lower end of the high-concentration region 302 is located deeper than the lower end of the extended region 306. In other words, the high-concentration region 302 in this example extends deeper than the extended region 306. The other structures are the same as in the example in Figure 19A. The high-concentration region 302 may also be provided between the well region 11 and the drift region 18. The high-concentration region 302 may also be provided between the channel stopper 98 and the drift region 18.

[0158] In the depth direction (Z-axis direction), the length Zn of the high-concentration region 302 may be 1.1 times or more, 1.5 times or more, or 2 times or more, the length Zp of the extended region 306. Length Zn is the maximum length in the Z-axis direction in the high-concentration region 302, and length Zp is the maximum length in the Z-axis direction in the extended region 306.

[0159] Figure 20 shows another example of a BB cross section. The edge termination structure 90 in this example differs from the example in Figure 19A or Figure 19B in that multiple extended regions 306 are arranged from the well region 11 toward the edge 102 of the semiconductor substrate 10. The other structures are the same as those in the example in Figure 19A or Figure 19B.

[0160] Of the multiple extended regions 306, the extended region 306 closest to the active region 160 is connected to the well region 11. Two adjacent extended regions 306 in the X-axis direction may be connected to each other or they may be separated. Let Xp be the distance between the centers of two adjacent extended regions 306 in the X-axis direction. The distance Xp may increase as it approaches the edge 102 of the semiconductor substrate 10. Two or more extended regions 306 on the well region 11 side may be connected to each other. Two or more extended regions 306 on the edge 102 side may be separated from each other.

[0161] The doping concentrations in each extended region 306 may be the same. In other examples, the doping concentration in the extended region 306 may decrease as it moves away from the well region 11. This allows for a gentler potential distribution in the X-axis direction of the extended region 306. In the examples of Figures 19A and 19B, the doping concentration in the extended region 306 may also decrease as it moves away from the well region 11.

[0162] The high-concentration region 302 is provided from the extended region 306 closest to the edge 102 to the edge 102 (or channel stopper 98). The high-concentration region 302 may also be provided between two extended regions 306 that are far apart from each other. Furthermore, the high-concentration region 302 may also be provided between the extended region 306 and the drift region 18. The high-concentration region 302 may be formed to a greater depth than the extended region 306, or it may be formed to a shallower depth.

[0163] Even if the high-concentration region 302 is shallower than the extended region 306, the high-concentration region 302 may also be provided between the extended region 306 and the drift region 18. As shown in Figure 20, the high-concentration region 302 may be provided between the connection portion 307 of two connected extended regions 306 and the drift region 18. The thickness of the connection portion 307 from the top surface 21 may be small. For this reason, the connection portion 307 alone may not be able to cover the range in which the phosphorus concentration or boron concentration tends to vary. By providing the high-concentration region 302 between the connection portion 307 and the drift region 18, a region with a higher concentration than the drift region 18 can be provided in the range in which the doping concentration tends to vary.

[0164] Figure 21 shows another example of a BB cross section. In this example, the thickness Zp of the edge termination structure 90 in the depth direction of the extended region 306 decreases as it moves away from the well region 11. Other structures are the same as any of the embodiments described in Figures 19A to 20. Even when multiple extended regions 306 are discretely arranged, as in the example of Figure 20, the thickness Zp of the extended region 306 in the depth direction may decrease as it moves away from the well region 11. In such a configuration, the potential distribution in the X-axis direction of the extended region 306 can be made gentler. In the example of Figure 21, the doping concentration of the extended region 306 may be constant regardless of the distance from the well region 11, and may even decrease as it moves away from the well region 11. The length of the extended region 306 in the X-axis direction is the same as in the example of Figure 19A.

[0165] When viewed from the upper surface 21 of the semiconductor substrate 10, the lower end of the high-density region 302 may be positioned shallower than the lower end of the extended region 306. The lower end of the high-density region 302 is the point in the high-density region 302 that is at its maximum distance from the upper surface 21. The lower end of the extended region 306 is the point in the extended region 306 that is at its maximum distance from the upper surface 21.

[0166] Figure 22 shows an example of the arrangement of the high-density region 302 in a top view. Figure 22 shows the high-density region 302 in the example of Figure 19A, but the same may be true for other examples. In a top view, the high-density region 302 surrounds the extended region 306. The extended region 306 surrounds the outside of the active portion 160, and further outside, the high-density region 302 surrounds the extended region 306. "Outside" refers to the side closer to the edge 102 of the semiconductor substrate 10. A channel stopper 98 is located outside the high-density region 302, but it is omitted in Figure 22. If a channel stopper 98 is not provided, the high-density region 302 may extend to the edge 102 of the semiconductor substrate 10.

[0167] In each example described in Figures 10 to 22, the high-concentration region 302 may be formed deeper than the well region 11, as shown in Figure 15, or shallower than the well region 11, as shown in Figure 14. In each example described in Figures 1 to 22, the insulating film 195 may be replaced with the embedded insulating film 95, or the embedded insulating film 95 may be replaced with the insulating film 195.

[0168] Figure 23 shows some steps in a method for manufacturing a semiconductor device 100 having a high-concentration region 302. In this example, in the substrate preparation step S1702, a semiconductor substrate 10 is prepared. For example, the semiconductor substrate 10 is a substrate in which both a first-type dopant and a second-type dopant are distributed throughout. In this specification, the first-type dopant distributed throughout the semiconductor substrate 10 may be referred to as the first dopant, and the second-type dopant distributed throughout the semiconductor substrate 10 may be referred to as the second dopant. The first conductivity type may be N-type, and the second conductivity type may be P-type. The first dopant may be any or more of phosphorus, arsenic, antimony, hydrogen, and nitrogen. The second dopant may be any or more of boron, aluminum, and indium. Also, as shown in Figure 10, when forming an embedded insulating film 95, a recess 232 (see Figure 7) is formed in the semiconductor substrate 10 in the substrate preparation step S1702. The method for forming the recess 232 is the same as the recess formation step S702 described in Figure 7.

[0169] Next, in the high-concentration region formation step S1704, a high-concentration region 302 is formed in at least a portion of the upper surface 21 of the semiconductor substrate 10. In S1704, the high-concentration region 302 is formed by selectively implanting N-type dopant ions such as phosphorus from the upper surface 21 of the semiconductor substrate 10. If a recess 232 is formed in the semiconductor substrate 10, N-type dopant ions such as phosphorus are implanted from the bottom of the recess 232. In this case, the mask 230 shown in Figure 7 may be used as the ion implantation mask. After implanting the N-type dopant ions, the semiconductor substrate 10 may be heat-treated in S1704. In other examples, the heat treatment of the semiconductor substrate 10 may be performed in a later step than S1704. The dopant of the N-type dopant ion may be the same as or different from the first dopant.

[0170] Next, in the insulating film formation step S1706, an insulating film 195 or an embedded insulating film 95 is formed on the upper surface 21 of the semiconductor substrate 10, in contact with the high-concentration region 302. The embedded insulating film 95 can be formed in the same manner as in S704 in Figure 7. When forming the insulating film 195, the entire upper surface 21 of the semiconductor substrate 10 may be thermally oxidized to form an oxide film, and the insulating film 195 may be formed by selectively removing the oxide film. In another example, the insulating film 195 may be formed by selectively thermally oxidizing the upper surface 21 of the semiconductor substrate 10. In S1706, when forming the insulating film 195 or the embedded insulating film 95, a reduction region 304 (see Figure 12) is also formed. Since a high-concentration region 302 is formed, the influence of the reduction region 304 on the doping concentration can be reduced.

[0171] Next, in the P-type region formation step S1708, P-type regions such as guard rings 92 are formed. The method for forming the guard rings 92 is the same as in S706 in Figure 7. In S1708, well regions 11 and channel stoppers 98 may also be formed. By these steps, the semiconductor device 100 can be manufactured.

[0172] In the high-concentration region formation step S1704, the depth of the high-concentration region 302 to be formed may be adjusted according to the thermal oxidation conditions in the insulating film formation step S1706. The depth of the high-concentration region 302 can be adjusted by the implantation depth of N-type dopant ions, etc. The thermal oxidation conditions are at least one of the thermal oxidation temperature and the length of the thermal oxidation time.

[0173] The degree to which boron is incorporated into the oxide film changes depending on the thermal oxidation conditions. Therefore, the depth range in which the boron concentration fluctuates may also fluctuate depending on the thermal oxidation conditions. In the high-concentration region formation step S1704, the depth of the high-concentration region 302 may be adjusted to cover the depth range in which the boron concentration fluctuates.

[0174] Figure 24 shows an example of the phosphorus and boron concentration distributions below a thermal oxide film. This example shows the phosphorus and boron concentration distributions when a thermal oxide film is formed on the upper surface of a semiconductor substrate 10 in which boron and phosphorus are uniformly distributed throughout. This example shows the concentration distributions under two different thermal oxidation conditions (conditions A and B). Condition B has a higher thermal oxidation temperature and a longer thermal oxidation time than condition A. The thermal oxidation temperature for condition A is 1000°C and the thermal oxidation time is 115 minutes. The thermal oxidation temperature for condition B is 1050°C and the thermal oxidation time is 475 minutes. The horizontal axis of Figure 24 shows the depth position in the Z-axis direction, with the boundary between the thermal oxide film and the semiconductor substrate 10 as the reference position. As shown in Figure 24, the range in which the boron and phosphorus concentrations change varies depending on the thermal oxidation conditions. Under condition A, at least one of the boron concentration or phosphorus concentration changes within the range from depth position 0 to Z1, and under condition B, at least one of the boron concentration or phosphorus concentration changes within the range from depth position 0 to Z2. Depth position Z2 is deeper than depth position Z1.

[0175] In the high-concentration region formation step S1704, the high-concentration region 302 may be formed to cover the entire range in which at least one of the boron concentration or phosphorus concentration changes. Under condition A, the high-concentration region 302 may be formed to a depth greater than Z1, and under condition B, the high-concentration region 302 may be formed to a depth greater than Z2. This makes it possible to suppress the effects of changes in boron concentration or phosphorus concentration.

[0176] In Figure 24, both the thermal oxidation temperature and thermal oxidation time are varied between conditions A and B. When either the thermal oxidation temperature or thermal oxidation time is changed, the boron concentration distribution and phosphorus concentration distribution change, similar to the example in Figure 24. In the high-concentration region formation step S1704, the higher the thermal oxidation temperature in the insulating film formation step S1706, the deeper the high-concentration region 302 may be formed. In the high-concentration region formation step S1704, the longer the thermal oxidation time in the insulating film formation step S1706, the deeper the high-concentration region 302 may be formed.

[0177] Figure 25 shows an example of the concentration distribution of bulk donor and bulk acceptor, and the net doping concentration distribution. Figure 25 shows the distribution before the formation of the high-concentration region 302. The horizontal axis of Figure 25 represents the distance in the Z-axis direction from the lower end of the insulating film 195. The dopant of the first conductivity type in the high-concentration region 302 may be of the same element as the first dopant. The dopant of the bulk donor may be the first dopant. The dopant of the bulk acceptor may be the second dopant. In this example, the bulk donor is phosphorus and the bulk acceptor is boron. The dopant of the first conductivity type in the high-concentration region 302 may be of a different element than the first dopant.

[0178] Figure 25 shows four examples with different ratios of bulk donor concentration Nd to bulk acceptor concentration Na. As mentioned above, the concentrations of bulk donor and bulk acceptor may be the concentration values ​​at the center in the depth direction of the semiconductor substrate 10. In the four examples, the net doping concentration distribution in the drift region 18 is the same. Phosphorus concentration distribution 401, boron concentration distribution 411, and doping concentration distribution 421 are examples with a Na / Nd ratio of 0.5; phosphorus concentration distribution 402, boron concentration distribution 412, and doping concentration distribution 422 are examples with a Na / Nd ratio of 0.4; phosphorus concentration distribution 403, boron concentration distribution 413, and doping concentration distribution 423 are examples with a Na / Nd ratio of 0.3; and phosphorus concentration distribution 404, boron concentration distribution 414, and doping concentration distribution 424 are examples with a Na / Nd ratio of 0.2.

[0179] Similar to the example in Figure 12, in all the examples in Figure 25, the phosphorus concentration increases and the boron concentration decreases in the direction toward the insulating film 195. In all the examples in Figure 25, the phosphorus and boron concentrations at the boundary with the insulating film 195 fluctuate by approximately 30% relative to their respective concentrations in the drift region 18. Near the insulating film 195, the boron concentration decreases, so the net doping concentration approaches the phosphorus concentration as the distance from the insulating film 195 decreases.

[0180] The difference between the bulk donor concentration Nd and the bulk donor concentration Na is defined as the bulk net doping concentration Nnet. In other words, the bulk net doping concentration Nnet is expressed by the following formula. Nnet = Nd - Na Equation (1a) Furthermore, if we let Na / Nd be α, equation (1a) can be transformed as shown below. Nnet=(1-α)Nd=(1 / α-1)Na Equation (1b) In this example, Nd > Na and α < 1.

[0181] Let Nd_s be the donor concentration and Na_s be the acceptor concentration at the boundary with insulating film 195. The net doping concentration Nnet_s at the boundary with insulating film 195 is given by the following formula. Nnet_s = Nd_s - Na_s Equation (2) In each example shown in Figure 25, the acceptor concentration Na_s is 58% to 62% of the bulk acceptor concentration Na. Here, we assume Na_s = 0.6Na. ​​Also, from equation (1a), Na_s = 0.6αNd, ​​so equation (2) becomes the following equation. Nnet_s = Nd_s - 0.6αNd Equation (3)

[0182] Furthermore, the donor concentration Nd_s is expressed as shown in the following formula. Nd_s = βNd Equation (4) In each example shown in Figure 25, the donor concentration Nd_s at the boundary is 130% to 140% of the bulk donor concentration Nd, so β ​​is 1.3 to 1.4. Here, we assume β = 1.35.

[0183] Equation (3) can be transformed from equation (4) as follows. Nnet_s=Nd_s-0.6αNd = 1.35Nd - 0.6αNd =(1.35-0.6α)Nd Equation (5) Furthermore, equations (1b) through (5) can be transformed as follows. Nnet_s=(1.35-0.6α)Nd =(1.35-0.6α)(1 / (1-α))Nnet Equation (6) As shown in equation (6), when a semiconductor substrate 10 containing bulk donors and bulk acceptors is oxidized, the net doping concentration near the oxide film can be expressed using the bulk net doping concentration Nnet and the ratio α of the bulk acceptor concentration to the donor concentration.

[0184] Furthermore, when a high-concentration region 302 is formed, the net doping concentration at the surface of the high-concentration region 302 (i.e., the boundary with the insulating film 195) is denoted as NF_s. If the concentration NF_s is sufficiently large compared to the concentration Nnet_s, the region can be made less susceptible to fluctuations in acceptor and donor concentrations in the depletion region 304 (see Figure 12). In other words, it is preferable that the concentration NF_s satisfies the following equation. NF_s≧γNnet_s Equation (7) Here, γ is a value greater than 1. For example, γ may be 2 or greater, 5 or greater, or 7 or greater. Also, γ may be 50 or less, 30 or less, or 20 or less. In this example, γ is 10. Substituting equation (6) into equation (7) yields the following equation. NF_s≧γ(1.35-0.6α)(1 / (1-α))Nnet Equation (8) The net doping concentration NF_s on the surface of the high-concentration region 302 preferably satisfies formula (8).

[0185] Figure 26 shows the relationship between concentration Nnet_s and α. In Figure 26, the bulk net doping concentration Nnet is set to 1 × 10⁻⁶. 13 / cm 3 , 2×10 13 / cm 3 , 3 x 10 13 / cm 3 , 5×10 13 / cm 3 , 5.41×10 13 / cm 3 , 7×10 13 / cm 3 , 1 x 10 14 / cm 3 The following examples are shown. As the bulk acceptor concentration Na increases and α approaches 1, the decrease in acceptor concentration in the decrease region 304 also increases, so the concentration Nnet_s increases. In the region where the concentration Nnet_s changes little with respect to α and shows a stable value, the effect of stabilizing pressure resistance can be achieved. For this reason, α may be 0.7 or less, 0.6 or less, 0.5 or less, or 0.4 or less. On the other hand, if the concentration Nnet_s is relatively high, pressure resistance can be stabilized. For this reason, α may be 0.01 or more, 0.05 or more, 0.1 or more, 0.2 or more, or 0.3 or more.

[0186] Figure 27 shows an example of the net doping concentration distribution in the high-concentration region 302. The horizontal axis in Figure 27 represents the distance from the lower edge of the insulating film 195. Figure 27 shows four examples with γ = 7.8, 14.5, 27.9, and 67.6. In each example, α = 0.5 and Nnet = 5.41 × 10⁻¹⁰. 13 / cm 3 The concentration Nnet_s can be determined from Figure 26.

[0187] In the example shown in Figure 27, when γ = 67.6, the net doping concentration NF_s at the upper end of the high-concentration region 302 (depth position 0 μm) becomes too large, resulting in a decrease in pressure resistance. As mentioned above, γ can be 50 or less.

[0188] In the example described above, the bulk net doping concentration Nnet may be the net doping concentration Dd in the drift region 18 measured by the SR method. Alternatively, the bulk net doping concentration Nnet may be calculated from the difference between the bulk donor concentration Nd and the bulk acceptor concentration Na measured by the SIMS method. As described above, the net doping concentration Dd, bulk donor concentration Nd, and bulk acceptor concentration Na may be the values ​​at the center of the semiconductor substrate 10.

[0189] As described above, by forming a high-concentration region 302, the variation in the net doping concentration of the semiconductor substrate beneath the embedded insulating film 95 or insulating film 195 can be reduced. This makes it possible to suppress variations in the elongation width of the depletion layer when the depletion layer extends across the high-concentration region 302 (in the x-axis direction). As a result, it is possible to suppress variations in characteristics in semiconductor devices using a semiconductor substrate in which both first-type and second-type dopants are distributed throughout the semiconductor substrate, and the concentration of the second-type dopant decreases toward the insulating film.

[0190] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.

[0191] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of Symbols]

[0192] 10...Semiconductor substrate, 11...Well region, 12...Emitter region, 14...Base region, 16...Storage region, 18...Drift region, 20...Buffer region, 21...Top surface, 22...Collector region, 23...Bottom surface, 24...Collector electrode, 30...Dummy trench region, 32...Dummy insulating film, 34...Dummy conductive region, 38...Interlayer insulating film, 40...Gate trench region, 42...Gate insulating film 44...Gate conductive part, 52...Emitter electrode, 54...Contact hole, 60, 61...Mesa part, 70...Transistor part, 80...Diode part, 81...Extended region, 82...Cathode region, 90...Edge termination structure part, 91...Guard ring electrode, 92...Guard ring, 93...Field plate, 94...Field electrode, 95...Embedded insulating film, 96...Outer plate, 97... Outer electrode, 98... Channel stopper, 100... Semiconductor device, 102... Edge, 112... Gate pad, 130... Outer periphery gate wiring, 131... Active side gate wiring, 132... Contact hole, 160... Active part, 195... Insulating film, 201... Flat part, 202, 203, 204... Edge, 206... First insulating film, 208... Second insulating film, 210, 214... Valley part, 218... Extending part, 2 30...Mask, 232...Recess, 234...Mask, 240...Contact hole, 242...Contact area, 302...High concentration area, 304...Decrease area, 306...Expansion area, 307...Connection area, 311, 312...Ends, 401, 402, 403, 404...Phosphorus concentration distribution, 411, 412, 413, 414...Boron concentration distribution, 421, 422, 423, 424...Doping concentration distribution

Claims

1. A semiconductor substrate having a drift region of the first conductivity type, wherein both a first dopant of a first conductivity type and a second dopant of a second conductivity type having a lower concentration than the first dopant are distributed throughout the substrate, An insulating film provided on the upper surface of the semiconductor substrate, A high-concentration region of a first conductivity type with a doping concentration higher than that of the drift region is provided below the insulating film in contact with the insulating film, A reduction region is provided below the insulating film in contact with the insulating film, and the concentration of the second dopant decreases toward the insulating film. Equipped with, The difference between the maximum and minimum concentrations of the first conductivity type dopant in the high-concentration region is greater than the difference between the maximum and minimum concentrations of the second dopant in the decreasing region. Semiconductor equipment.

2. A semiconductor substrate having a drift region of the first conductivity type, wherein both a first dopant of the first conductivity type and a second dopant of the second conductivity type at a lower concentration than the first dopant are distributed throughout the substrate, An insulating film provided on the upper surface of the semiconductor substrate, A high-concentration region of a first conductivity type with a doping concentration higher than that of the drift region is provided below the insulating film in contact with the insulating film, A reduction region is provided below the insulating film in contact with the insulating film, and the concentration of the second dopant decreases toward the insulating film. Equipped with, The high-concentration region extends below the decreasing-concentration region. Semiconductor equipment.

3. A semiconductor substrate having a drift region of the first conductivity type, wherein both a first dopant of the first conductivity type and a second dopant of the second conductivity type at a lower concentration than the first dopant are distributed throughout the substrate, An insulating film provided on the upper surface of the semiconductor substrate, A high-concentration region of a first conductivity type with a doping concentration higher than that of the drift region is provided below the insulating film in contact with the insulating film, A reduction region is provided below the insulating film in contact with the insulating film, wherein the concentration of the second dopant decreases toward the insulating film, The semiconductor substrate has an active portion provided with at least one of a transistor portion and a diode portion, An edge termination structure provided outside the active portion in the semiconductor substrate Equipped with, The high-concentration region and the decreasing region are formed in the edge terminal structure. The insulating film is embedded in the semiconductor substrate in at least a portion of it. The depth from the upper surface of the semiconductor substrate to the lower end of the insulating film is 2 μm or more. Semiconductor equipment.

4. A semiconductor substrate having a drift region of the first conductivity type, wherein both a first dopant of the first conductivity type and a second dopant of the second conductivity type at a lower concentration than the first dopant are distributed throughout the substrate, An insulating film provided on the upper surface of the semiconductor substrate, A high-concentration region of a first conductivity type with a doping concentration higher than that of the drift region is provided below the insulating film in contact with the insulating film, A reduction region is provided below the insulating film in contact with the insulating film, wherein the concentration of the second dopant decreases toward the insulating film, The semiconductor substrate has an active portion provided with at least one of a transistor portion and a diode portion, An edge termination structure provided outside the active portion in the semiconductor substrate Equipped with, The high-concentration region and the decreasing region are formed in the edge terminal structure. The insulating film is embedded in the semiconductor substrate in at least a portion of it. The aforementioned insulating film, A first insulating film and A second insulating film laminated on the first insulating film and Semiconductor device.

5. A semiconductor substrate having a drift region of the first conductivity type, wherein both a first dopant of the first conductivity type and a second dopant of the second conductivity type at a lower concentration than the first dopant are distributed throughout the substrate, An insulating film provided on the upper surface of the semiconductor substrate, A high-concentration region of a first conductivity type with a doping concentration higher than that of the drift region is provided below the insulating film in contact with the insulating film, A reduction region is provided below the insulating film in contact with the insulating film, wherein the concentration of the second dopant decreases toward the insulating film, The semiconductor substrate has an active portion provided with at least one of a transistor portion and a diode portion, An edge termination structure provided outside the active portion in the semiconductor substrate Equipped with, The high-concentration region and the decreasing region are formed in the edge terminal structure. The edge termination structure has a plurality of guard rings of the second conductivity type provided in contact with the upper surface of the semiconductor substrate. The aforementioned high-concentration region is located between two guard rings. The insulating film is positioned between the two guard rings. The lower end of the high-concentration region is positioned on the upper surface side of the semiconductor substrate, compared to the lower end of the guard ring. The device further comprises a field plate made of polysilicon, which extends from above the guard ring to above the insulating film, The aforementioned field plate is At a position overlapping with the insulating film, a valley portion recessed toward the upper surface of the semiconductor substrate, An extended portion extending toward the center of the insulating film from the aforementioned valley portion and Semiconductor device.

6. A semiconductor substrate having a drift region of the first conductivity type, wherein both a first dopant of the first conductivity type and a second dopant of the second conductivity type at a lower concentration than the first dopant are distributed throughout the substrate, An insulating film provided on the upper surface of the semiconductor substrate, A high-concentration region of a first conductivity type with a doping concentration higher than that of the drift region is provided below the insulating film in contact with the insulating film, A reduction region is provided below the insulating film in contact with the insulating film, and the concentration of the second dopant decreases toward the insulating film. Equipped with, Net doping concentration NF_s( / cm²) at the boundary between the high-concentration region and the insulating film. ３ ) satisfies the following equation NF_s≧γ(1.35-0.6α)(1 / (1-α))Nnet However, γ is a real number greater than or equal to 2, and α is the bulk acceptor concentration Na ( / cm³). ３ ) and bulk donor concentration Nd( / cm³) ３ ) is the ratio Na / Nd, and Nnet is the bulk net doping concentration ( / cm³). ３ ) Semiconductor equipment.

7. The above α is 0.7 or less. The semiconductor device according to claim 6.

8. A semiconductor substrate having a drift region of the first conductivity type, wherein both a first dopant of the first conductivity type and a second dopant of the second conductivity type at a lower concentration than the first dopant are distributed throughout the substrate, An insulating film provided on the upper surface of the semiconductor substrate, A high-concentration region of a first conductivity type with a doping concentration higher than that of the drift region is provided below the insulating film in contact with the insulating film, A reduction region is provided below the insulating film in contact with the insulating film, wherein the concentration of the second dopant decreases toward the insulating film, The semiconductor substrate has an active portion provided with at least one of a transistor portion and a diode portion, An edge termination structure provided outside the active portion in the semiconductor substrate Equipped with, The high-concentration region and the decreasing region are formed in the edge terminal structure. The active portion has a second conductivity type well region located at the boundary with the edge termination structure, An extended region of a second conductivity type, connected to the well region and having a lower doping concentration than the well region, is provided in the edge termination structure. The high-concentration region is located outside the aforementioned extended region. When viewed from the upper surface of the semiconductor substrate, the lower end of the high-density region is located deeper than the lower end of the expanded region. Semiconductor equipment.

9. The aforementioned high-concentration region is also provided between the expanded region and the drift region. The semiconductor device according to claim 8.

10. The aforementioned high-concentration region is also provided between the well region and the drift region. The semiconductor device according to claim 8.

11. A semiconductor substrate having a drift region of the first conductivity type, wherein both a first dopant of the first conductivity type and a second dopant of the second conductivity type at a lower concentration than the first dopant are distributed throughout the substrate, An insulating film provided on the upper surface of the semiconductor substrate, A high-concentration region of a first conductivity type with a doping concentration higher than that of the drift region is provided below the insulating film in contact with the insulating film, A reduction region is provided below the insulating film in contact with the insulating film, and the concentration of the second dopant decreases toward the insulating film. Equipped with, The first dopant and the first conductivity type dopant in the high-concentration region are made of different elements. Semiconductor equipment.

12. A semiconductor substrate having a drift region of the first conductivity type, wherein both a first dopant of the first conductivity type and a bulk acceptor of the second conductivity type at a lower concentration than the first dopant are distributed throughout the substrate, An insulating film provided on the upper surface of the semiconductor substrate, A high-concentration region of a first conductivity type with a doping concentration higher than that of the drift region is provided below the insulating film in contact with the insulating film, A reduction region is provided below the insulating film in contact with the insulating film, wherein the concentration of the bulk acceptor decreases toward the insulating film. A semiconductor device equipped with a semiconductor device.

13. The maximum net doping concentration in the high-concentration region is 10 times or more the net doping concentration in the drift region. The semiconductor device according to any one of claims 1 to 12.

14. The maximum value of the net doping concentration in the aforementioned high-concentration region is 1 × 10⁻⁶ １４ / cm ３ That's all. The semiconductor device according to any one of claims 1 to 12.

15. The semiconductor substrate has an active portion provided with at least one of a transistor portion and a diode portion, An edge termination structure provided outside the active portion in the semiconductor substrate Equipped with, The high-concentration region and the reduced-concentration region are formed in the edge terminal structure. A semiconductor device according to any one of claims 1, 2, 6, 7, 11, or 12.

16. The edge termination structure has a plurality of guard rings of the second conductivity type provided in contact with the upper surface of the semiconductor substrate. The aforementioned high-concentration region is located between two guard rings. The insulating film is positioned between the two guard rings. The lower end of the high-concentration region is located on the lower surface side of the semiconductor substrate, lower than the lower end of the guard ring. The semiconductor device according to claim 15.

17. The insulating film is embedded in the semiconductor substrate in at least a portion thereof. The semiconductor device according to claim 15.

18. The depth from the upper surface of the semiconductor substrate to the lower end of the insulating film is 0.3 μm or more. The semiconductor device according to claim 17.

19. The semiconductor substrate is provided with a plurality of second-conductivity type guard rings in contact with the upper surface, The insulating film is an embedded insulating film positioned between two adjacent guard rings among the plurality of guard rings, and at least a portion of it is embedded inside the semiconductor substrate. The high-concentration region is located between the two adjacent guard rings. The lower end of the high-concentration region is positioned on the upper surface side of the semiconductor substrate than the lower ends of the two adjacent guard rings. The two adjacent guard rings are provided below the embedded insulating film. A semiconductor device according to any one of claims 1, 2, 6, 11, or 12.

20. The semiconductor substrate is provided with a plurality of second-conductivity type guard rings in contact with the upper surface, The insulating film is an embedded insulating film positioned between the two guard rings and at least a portion of it is embedded inside the semiconductor substrate. The aforementioned high-concentration region is located between two guard rings. The lower end of the high-concentration region is positioned on the lower surface side of the semiconductor substrate than the lower end of the guard ring. The guard ring is provided below the embedded insulating film. A semiconductor device according to any one of claims 1, 2, 6, 11, or 12.

21. The active portion has a second conductivity type well region located at the boundary with the edge termination structure, An extended region of a second conductivity type, connected to the well region and having a lower doping concentration than the well region, is provided in the edge termination structure. The high-concentration region is located outside the aforementioned expanded region. The semiconductor device according to claim 15.

22. When viewed from the upper surface of the semiconductor substrate, the lower end of the high-density region is positioned shallower than the lower end of the expanded region. The semiconductor device according to claim 21.

23. The doping concentration in the expanded region decreases as it moves away from the well region. The semiconductor device according to claim 21.

24. The first dopant and the first conductivity type dopant in the high-concentration region are of the same element. The semiconductor device according to any one of claims 1 to 10 or 12.

25. A method for manufacturing a semiconductor device, A substrate preparation step is performed to prepare a semiconductor substrate having a drift region of the first conductivity type, in which both a first dopant of the first conductivity type and a second dopant of the second conductivity type are distributed throughout, A high-concentration region formation step, in which a high-concentration region having a first conductivity type dopant with a higher doping concentration than the drift region is formed in at least a portion of the upper surface of the semiconductor substrate, An insulating film formation step, which forms an insulating film disposed on the upper surface of the semiconductor substrate in contact with the high-concentration region, and a decreasing region below the insulating film that is in contact with the insulating film and in which the concentration of the second conductivity type dopant decreases toward the insulating film. Equipped with, In the insulating film formation step, the insulating film is formed by thermal oxidation, The depth of the high-concentration region formed in the high-concentration region formation stage is adjusted according to the thermal oxidation conditions in the insulating film formation stage. Manufacturing method.

26. A method for manufacturing a semiconductor device, A substrate preparation step is performed to prepare a semiconductor substrate having a drift region of the first conductivity type, in which both a first dopant of the first conductivity type and a second dopant of the second conductivity type are distributed throughout, A high-concentration region formation step, in which a high-concentration region having a first conductivity type dopant with a higher doping concentration than the drift region is formed in at least a portion of the upper surface of the semiconductor substrate, An insulating film formation step, which forms an insulating film disposed on the upper surface of the semiconductor substrate in contact with the high-concentration region, and a decreasing region below the insulating film that is in contact with the insulating film and in which the concentration of the second conductivity type dopant decreases toward the insulating film. Equipped with, The first dopant and the first conductivity type dopant in the high-concentration region are made of different elements. Manufacturing method.

27. ​​A method for manufacturing a semiconductor device, A substrate preparation step is performed to prepare a semiconductor substrate having a drift region of the first conductivity type, in which both a first dopant of the first conductivity type and a bulk acceptor of the second conductivity type are distributed throughout, A high-concentration region formation step, in which a high-concentration region having a first conductivity type dopant with a higher doping concentration than the drift region is formed in at least a portion of the upper surface of the semiconductor substrate, An insulating film formation step, which forms an insulating film disposed on the upper surface of the semiconductor substrate in contact with the high-concentration region, and a decreasing region below the insulating film that is in contact with the insulating film and in which the concentration of the second conductivity type bulk acceptor decreases toward the insulating film. A manufacturing method that includes the following features.

28. The first dopant and the first conductivity type dopant in the high-concentration region are of the same element. The manufacturing method according to claim 25 or 27.

29. A semiconductor substrate having an upper surface and a lower surface, comprising a first dopant of a first conductivity type and a second dopant of a second conductivity type having a lower concentration than the first dopant, wherein both the first dopant and the second dopant are distributed throughout the depth direction from the upper surface to the lower surface, and the substrate has a drift region of the first conductivity type, An insulating film provided on the upper surface of the semiconductor substrate, A high-concentration region of a first conductivity type with a doping concentration higher than that of the drift region is provided below the insulating film in contact with the insulating film, A reduction region is provided below the insulating film in contact with the insulating film, and the concentration of the second dopant decreases toward the insulating film. Equipped with, The aforementioned high-concentration region is The first contact surface that contacts the drift region, A second contact surface that contacts the insulating film on the upper side of the first contact surface, It has, The reduction region is provided on the second contact surface side of the high-concentration region. Semiconductor equipment.

30. A method for manufacturing a semiconductor device, A substrate preparation step of preparing a semiconductor substrate having an upper surface and a lower surface, having a first dopant of a first conductivity type and a second dopant of a second conductivity type at a lower concentration than the first dopant, wherein both the first dopant and the second dopant are distributed throughout the depth direction from the upper surface to the lower surface, and the substrate has a drift region of the first conductivity type, A high-concentration region formation step, in which a high-concentration region having a first conductivity type dopant with a higher doping concentration than the drift region is formed in at least a portion of the upper surface of the semiconductor substrate, An insulating film formation step, which forms an insulating film disposed on the upper surface of the semiconductor substrate in contact with the high-concentration region, and a decreasing region below the insulating film that is in contact with the insulating film and in which the concentration of the second conductivity type dopant decreases toward the insulating film. Equipped with, The aforementioned high-concentration region is The first contact surface that contacts the drift region, A second contact surface that contacts the insulating film on the upper side of the first contact surface, It has, The reduction region is provided on the second contact surface side of the high-concentration region. Manufacturing method.

31. The high-concentration region extends below the lower surface of the decreasing region. The semiconductor device according to claim 29.

32. The high-concentration region extends below the lower surface of the decreasing region. The manufacturing method according to claim 30.

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