Silicon carbide semiconductor device and method for manufacturing a silicon carbide semiconductor device
A polymorphic poly-SiC structure in silicon carbide semiconductor devices blocks interface dislocation elongation, addressing manufacturing issues and improving chip reliability and yield.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- FUJI ELECTRIC CO LTD
- Filing Date
- 2022-11-04
- Publication Date
- 2026-06-30
AI Technical Summary
Existing silicon carbide semiconductor devices face issues with strain and reliability due to the occurrence of interface dislocations during manufacturing, which can lead to unusable chips.
The introduction of a polymorphic structure made of poly-SiC with a different crystal structure than the semiconductor substrate, specifically in the element isolation portion, which prevents the elongation of interface dislocations by blocking them in the [1-100] direction, and is formed using laser irradiation along the [11-20] direction.
This approach reduces the number of unusable silicon carbide semiconductor chips by preventing interface dislocation elongation, thereby enhancing the reliability and yield of the manufacturing process.
Smart Images
Figure 0007882085000001 
Figure 0007882085000002 
Figure 0007882085000003
Abstract
Description
Technical Field
[0001] The present invention relates to a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device.
Background Art
[0002] Patent Document 1 describes "a silicon carbide semiconductor device and a method for manufacturing a silicon carbide semiconductor device that suppress the occurrence of strain in the internal direction of a cut surface, so that reliability does not decrease even after long-term use." [Prior Art Document] [Patent Document] [Patent Document 1] Japanese Patent No. 6953876 [Non-Patent Document] [Non-Patent Document 1] Akihiro Hon, Naoya Takahashi, Yohei Yamada, Junichi Ikeno, "Damage-Free Laser Processing of SiC", Proceedings of the Academic Lecture Meeting of the Precision Engineering Society Autumn Conference 2015, Precision Engineering Society, August 20, 2015, p. 191-192 [Non-Patent Document 2] Yoh Kakuida, "Nanoscale Processing of Single-Crystalline SiC Surfaces by 355 nm Polarized UV Lasers", Research Summary Report and International Exchange Report of the Amada Foundation, Amada Foundation, March 2012, No. 24, p. 236-239
Summary of the Invention
[0003] In a first aspect of the present invention, there is provided a silicon carbide semiconductor device including a semiconductor substrate made of silicon carbide and having an epitaxial region on a front surface, the semiconductor substrate including an active portion provided on the semiconductor substrate, a breakdown voltage structure portion provided on the semiconductor substrate and outside the active portion, and an element isolation portion provided on the semiconductor substrate and outside the breakdown voltage structure portion, the element isolation portion having a polymorphic structure portion made of poly-SiC on an upper surface of the epitaxial region.
[0004] In the silicon carbide semiconductor device, the polymorphic structure portion may have a crystal structure different from that of the semiconductor substrate.
[0005] In any of the silicon carbide semiconductor devices described above, the crystal structure of the polymorphic structure may include 4H-SiC, 6H-SiC, or 3C-SiC.
[0006] In any of the silicon carbide semiconductor devices described above, the polymorphic structure may have a thickness greater than 0 in the depth direction of the semiconductor substrate and a thickness of 50% or less of the thickness of the epitaxial region.
[0007] In any of the silicon carbide semiconductor devices described above, the polymorphic structure may have a thickness of 5 μm or less from the upper surface of the epitaxial region in the depth direction of the semiconductor substrate.
[0008] Any of the above silicon carbide semiconductor devices may be silicon carbide semiconductor chips separated from a wafer. The polymorphic structure may be provided on the first edge of the silicon carbide semiconductor chip and on the second edge opposite the first edge.
[0009] In any of the silicon carbide semiconductor devices described above, the extension direction of the first edge and the second edge may be the [11-20] direction of the semiconductor substrate.
[0010] In any of the silicon carbide semiconductor devices described above, the silicon carbide semiconductor device may be a silicon carbide semiconductor chip separated from a wafer. The polymorphic structure may be provided on all four sides of the silicon carbide semiconductor chip.
[0011] In any of the silicon carbide semiconductor devices described above, the polymorphic structure may be located on the edge of the silicon carbide semiconductor chip.
[0012] A second aspect of the present invention provides a method for manufacturing a silicon carbide semiconductor device, comprising the steps of: providing a semiconductor substrate made of silicon carbide; providing an active portion on the semiconductor substrate; providing a pressure-resistant structure on the outer periphery of the active portion; providing an element isolation portion on the outer periphery of the pressure-resistant structure; and providing a polymorphic structure made of poly-SiC on the upper surface of the epitaxial region of the semiconductor substrate in the element isolation portion.
[0013] In the method for manufacturing the silicon carbide semiconductor device, the step of activating and annealing the semiconductor substrate may be included after the step of providing the polymorphic structure.
[0014] In any of the above-described methods for manufacturing a silicon carbide semiconductor device, the activation annealing step may include, after the step of providing the semiconductor substrate, the first step of activating and annealing the semiconductor substrate at 1500°C or higher.
[0015] In any of the above-described methods for manufacturing a silicon carbide semiconductor device, the method may include a step of forming alignment marks on the semiconductor substrate before the step of providing the polymorphic structure.
[0016] In any of the above-described methods for manufacturing a silicon carbide semiconductor device, the step of providing the polymorphic structure may include the step of forming the polymorphic structure by irradiating the upper surface of the epitaxial region with a laser.
[0017] In any of the above-described methods for manufacturing a silicon carbide semiconductor device, the step of forming the polymorphic structure by laser irradiation may include the step of irradiating the semiconductor substrate with a laser along the [11-20] direction.
[0018] In any of the above-described methods for manufacturing a silicon carbide semiconductor device, the step of forming the polymorphic structure by laser irradiation may include the step of irradiating the semiconductor substrate with a laser along the [1-100] direction.
[0019] It should be noted that the above summary of the invention does not enumerate all of its features. Furthermore, subcombinations of these features may also constitute an invention. [Brief explanation of the drawing]
[0020] [Figure 1A] An example of a top view of a silicon carbide semiconductor device 100 is shown. [Figure 1B]An example of an enlarged view of the PQRS region of the silicon carbide semiconductor device 100 shown in FIG. 1A is shown. [Figure 1C] An example of a top view of the silicon carbide semiconductor chip 100a is shown. [Figure 2] An example of a cross-sectional view of the active portion 110 is shown. [Figure 3] An example of an A-A' cross-sectional view of the silicon carbide semiconductor device 100 shown in FIG. 1B is shown. [Figure 4A] An example of a B-B' cross-sectional view of the silicon carbide semiconductor device 100 shown in FIG. 1B is shown. [Figure 4B] A modified example of the B-B' cross-sectional view of the silicon carbide semiconductor device 100 shown in FIG. 1B is shown. [Figure 5A] A modified example of a top view of the silicon carbide semiconductor device 100 is shown. [Figure 5B] An example of an enlarged view of the PQRS region of the silicon carbide semiconductor device 100 shown in FIG. 5A is shown. [Figure 5C] A modified example of a top view of the silicon carbide semiconductor chip 100a is shown. [Figure 6A] An example of a flowchart of the manufacturing process of the silicon carbide semiconductor device 100 is shown. [Figure 6B] A modified example of a flowchart of the manufacturing process of the silicon carbide semiconductor device 100 is shown. [Figure 6C] A modified example of a flowchart of the manufacturing process of the silicon carbide semiconductor device 100 is shown. [Figure 6D] A modified example of a flowchart of the manufacturing process of the silicon carbide semiconductor device 100 is shown. [Figure 7] An example of the formation process of the interfacial dislocation 76 is shown. [Figure 8A] An example of the process of preventing the elongation of the interfacial dislocation 76 in the silicon carbide semiconductor device 100 is shown. [Figure 8B] An example of the formation process of the interfacial dislocation 76 in the silicon carbide semiconductor device according to the comparative example is shown.
Embodiments for Carrying Out the Invention
[0021] The present invention will be described below through embodiments of the invention, but these embodiments are not intended to limit the invention as defined in the claims. Furthermore, not all combinations of features described in the embodiments are necessarily essential to the solution of the invention.
[0022] In this specification, one side of a semiconductor substrate parallel to its depth direction is referred to as "top," and the other side as "bottom." Of the two main surfaces of a substrate, layer, or other component, one surface is referred to as the top surface, and the other surface as the bottom surface. The directions of "top," "bottom," "front," and "back" are not limited to the direction of gravity or the direction of attachment to the substrate, etc., when mounting a semiconductor device.
[0023] In this specification, technical matters may be described using the Cartesian coordinate axes X, Y, and Z. In this specification, the plane parallel to the top surface of the semiconductor substrate is defined as the XY plane, and the depth direction of the semiconductor substrate is defined as the Z axis.
[0024] In each embodiment, an example is shown where the first conductivity type is N-type and the second conductivity type is P-type, but the first conductivity type may be P-type and the second conductivity type may be N-type. In this case, the conductivity types of the substrate, layer, region, etc. in each embodiment will have opposite polarities.
[0025] In this specification, layers or regions prefixed with N or P indicate that electrons or holes are the majority carriers, respectively. Furthermore, the + and - signs attached to N and P indicate higher and lower doping concentrations, respectively, compared to layers or regions without these prefixes.
[0026] Figure 1A shows an example of a top view of a silicon carbide semiconductor device 100. The silicon carbide semiconductor device 100 has a semiconductor substrate 10, and the semiconductor substrate 10 includes an active portion 110, a voltage-resistant structure portion 120, an element isolation portion 130, and a polymorphic structure portion 132. The silicon carbide semiconductor device 100 may also include alignment marks 150 and an orientation flat 152 on the semiconductor substrate 10.
[0027] The semiconductor substrate 10 is made of silicon carbide. The semiconductor substrate 10 may have an epitaxial region 20 on its front surface 11. The front surface 11 and the epitaxial region 20 of the semiconductor substrate 10 will be described later. The front surface 11 and the epitaxial region 20 of the semiconductor substrate 10 are not shown in Figure 1A. As an example, the crystal structure of the semiconductor substrate 10 is 4H-SiC. In Figure 1A, the X-axis may be the [11-20] direction of the silicon carbide semiconductor substrate 10, the Y-axis may be the [1-100] direction of the semiconductor substrate 10, and the Z-axis may be the [000-1] direction of the semiconductor substrate 10.
[0028] The active portion 110 is provided on the semiconductor substrate 10. The active portion 110 may be the region through which the main current flows when the silicon carbide semiconductor device 100 is in operation. For example, the active portion 110 has an insulated gate field-effect transistor (MOSFET) structure, but is not limited to this. The silicon carbide semiconductor device 100 in this example has 22 active portions 110, but the number of active portions 110 provided on the silicon carbide semiconductor device 100 in wafer state may be 21 or less, or 23 or more. The number of active portions 110 provided on the silicon carbide semiconductor device 100 in wafer state may be appropriately designed based on the chip size for individualizing the silicon carbide semiconductor device 100 in wafer state.
[0029] The pressure-resistant structure 120 is provided on the outer periphery of the active portion 110 in the semiconductor substrate 10. The pressure-resistant structure 120 may mitigate electric field concentration on the upper surface side of the semiconductor substrate 10. As an example, the pressure-resistant structure 120 has a junction termination extension (JTE) structure. As another example, the pressure-resistant structure 120 may have a guard ring, a field plate, a resurf, or a structure combining these.
[0030] The element isolation section 130 is provided on the outer periphery of the breakdown structure section 120 in the semiconductor substrate 10. The element isolation section 130 may be a region that separates the active section 110 and the breakdown structure section 120, respectively, provided on each chip when the silicon carbide semiconductor device 100 in wafer state is separated into individual chips. That is, as shown in Figure 1A, the element isolation section 130 may be a region that separates adjacent breakdown structure sections 120 in the X-axis direction, or a region that separates adjacent breakdown structure sections 120 in the Y-axis direction. Alternatively, the element isolation section 130 may be a region in the semiconductor substrate 10 other than the region where the active section 110 and the breakdown structure section 120 are provided.
[0031] The boundary between the pressure-resistant structure 120 and the element isolation section 130 may be defined by the ends of the structure of the pressure-resistant structure 120. That is, the boundary between the pressure-resistant structure 120 and the element isolation section 130 may be defined by the ends of the structures that are provided on the outermost side of the structure of the pressure-resistant structure 120, centered on the active section 110. Details of the structure of the pressure-resistant structure 120 and the boundary between the pressure-resistant structure 120 and the element isolation section 130 will be described later.
[0032] The element isolation portion 130 has a polymorphic structure portion 132 made of poly-SiC. The polymorphic structure portion 132 may have a crystal structure different from that of the semiconductor substrate 10. If the crystal structure of the semiconductor substrate 10 is 4H-SiC, the crystal structure of the polymorphic structure portion 132 may include structures other than 4H-SiC. That is, the crystal structure of the polymorphic structure portion 132 may include 4H-SiC, 6H-SiC, or 3C-SiC.
[0033] In this example, the polymorphic structure 132 is provided parallel to the X-axis direction. The polymorphic structure 132 may be provided parallel to the [11-20] direction of the semiconductor substrate 10. The polymorphic structure 132 may be provided in all regions where adjacent breakdown structure 120 are spaced apart in the Y-axis direction. In the silicon carbide semiconductor device 100 of this example, since there are up to five active parts 110 and breakdown structure 120 in the Y-axis direction, at least four polymorphic structure 132 are provided. The polymorphic structure 132 may be provided further outside the outermost active parts 110 and breakdown structure 120. In the silicon carbide semiconductor device 100 of this example, since the polymorphic structure 132 is provided further outside the outermost active parts 110 and breakdown structure 120, six polymorphic structure 132 are provided.
[0034] By providing the polymorphic structure 132 in the [11-20] direction of the semiconductor substrate 10, the elongation of interface dislocations that occur during the manufacturing process of the silicon carbide semiconductor device 100 can be prevented. Interface dislocations that occur during the manufacturing process of the silicon carbide semiconductor device 100 elongate in the [1-100] direction of the semiconductor substrate 10. Since the polymorphic structure 132 has a different crystal structure from the crystal structure of the semiconductor substrate 10, there is no crystal orientation corresponding to the [1-100] direction of the semiconductor substrate 10 in the polymorphic structure 132, and therefore the elongation of interface dislocations can be prevented. As a result, even if interface dislocations occur during the manufacturing process of the silicon carbide semiconductor device 100, the elongation of the interface dislocations is blocked by the polymorphic structure 132, thus reducing the number of silicon carbide semiconductor chips that become unusable due to the elongation of interface dislocations. Details of the interface dislocation formation process during the manufacturing process of the silicon carbide semiconductor device 100 will be described later.
[0035] The alignment marks 150 are marks used for alignment during the manufacturing process of the silicon carbide semiconductor device 100. The alignment marks 150 can be formed by a conventional method used by those skilled in the art. In this example, four alignment marks 150 are provided on the semiconductor substrate 10, but this is not limited to this.
[0036] An orientation flat 152 is a flat surface provided on the outer periphery of a wafer to facilitate the determination and / or alignment of the crystal orientation of the semiconductor substrate 10. As an example, the orientation flat 152 is provided parallel to the [11-20] direction of the semiconductor substrate 10. Further orientation flats parallel to the [1-100] direction of the semiconductor substrate 10 may be provided.
[0037] The silicon carbide semiconductor device 100 may be a power semiconductor device that controls high voltage and / or high current. For example, the silicon carbide semiconductor device 100 is a MOSFET. The silicon carbide semiconductor device 100 may be a PIN diode or an IGBT. The silicon carbide semiconductor device 100 may be in wafer form or in individual chip form.
[0038] Figure 1B shows an example of an enlarged view of the PQRS region of the silicon carbide semiconductor device 100 shown in Figure 1A. The double-headed arrows indicated by the dashed lines represent the dicing regions 134 for dicing the silicon carbide semiconductor device 100 in wafer form.
[0039] A dicing region 134 extending in the X-axis direction, which is the stretching direction of the polymorphic structure 132, may be included within the polymorphic structure 132. The width of the polymorphic structure 132 may be greater than the width of the dicing region 134 extending in the stretching direction of the polymorphic structure 132, and both ends of the dicing region 134 may be inside both ends of the polymorphic structure 132. That is, in the stretching direction of the polymorphic structure 132, the silicon carbide semiconductor device 100 may be fragmented by dicing at least a portion of the polymorphic structure 132.
[0040] The width of the dicing region 134 extending in the Y-axis direction, which is perpendicular to the extension direction of the polymorphic structure 132, is not particularly limited. For example, the width of the dicing region 134 extending in the direction perpendicular to the extension direction of the polymorphic structure 132 may be approximately the same as the width of the dicing region 134 extending in the extension direction of the polymorphic structure 132.
[0041] Figure 1C shows an example of a top view of a silicon carbide semiconductor chip 100a. The silicon carbide semiconductor chip 100a may be a silicon carbide semiconductor device 100 in a fragmented state. The silicon carbide semiconductor chip 100a has a semiconductor substrate 10, and the semiconductor substrate 10 comprises an active portion 110, a voltage-resistant structure portion 120, an element isolation portion 130, and a polymorphic structure portion 132.
[0042] The polymorphic structure 132 is provided on the first end edge 136 and the second end edge 138 opposite the first end edge 136 of the silicon carbide semiconductor chip 100a. The extension direction of the first end edge 136 and the second end edge 138 may be the [11-20] direction of the semiconductor substrate 10. The polymorphic structure 132 may be located on the end edge of the silicon carbide semiconductor chip 100a.
[0043] Figure 2 shows an example of a cross-sectional view of the active portion 110. The active portion 110 includes a first high-concentration base region 13, a second high-concentration base region 14, a base region 15, a contact region 16, a source region 18, an epitaxial region 20, a base region 30, an insulating film 38, a gate trench portion 40, a barrier metal 50, a source electrode 52, and a drain electrode 54. The first high-concentration base region 13, the second high-concentration base region 14, the base region 15, the contact region 16, the source region 18, the epitaxial region 20, and the base region 30 are provided inside the semiconductor substrate 10.
[0044] The active section 110 in this example has a trench-type MOSFET structure, but is not limited thereto. The active section 110 may have a Pin diode structure or an IGBT structure. The active section 110 may have the MOSFET structure shown in Figure 2 repeated. That is, the active section 110 may have a structure in which the MOSFET structure shown in Figure 2 is repeatedly provided, for example, at regular intervals in the Y-axis direction.
[0045] The base region 30 is a region of a first conductivity type provided on the back surface 12 of the semiconductor substrate 10. The base region 30 is, for example, of the N+ type. The base region 30 may be a silicon carbide substrate made of N+ type silicon carbide.
[0046] The epitaxial region 20 includes a buffer region 24, a first drift region 26, and a second drift region 28. The epitaxial region 20 may be formed by epitaxially growing silicon carbide above the base region 30. The lower surface 22 of the epitaxial region 20 may be in contact with the upper surface of the base region 30.
[0047] The buffer region 24 is a first conductivity type region located above the base region 30. The buffer region 24 is, for example, N+ type. The buffer region 24 may be formed by epitaxially growing silicon carbide while doping it with an N-type dopant. The N-type dopant is, for example, a nitrogen atom.
[0048] The first drift region 26 is a region of a first conductivity type located above the buffer region 24. The first drift region 26 is, for example, N-type. The first drift region 26 may be formed by epitaxially growing silicon carbide while doping it with an N-type dopant. The N-type dopant is, for example, a nitrogen atom. The doping concentration of the first drift region 26 may be lower than the doping concentration of the buffer region 24.
[0049] The second drift region 28 is a first-conductivity region located above the first drift region 26. The second drift region 28 is, for example, N-type. The second drift region 28 may be formed by epitaxial growth of silicon carbide while doping with an N-type dopant. The N-type dopant is, for example, a nitrogen atom. Alternatively, the second drift region 28 may be formed by first forming it with the same doping concentration as the first drift region 26, and then injecting an N-type dopant. The doping concentration of the second drift region 28 may be higher than that of the first drift region 26, and lower than that of the buffer region 24.
[0050] The first high-concentration base region 13 is a second conductivity type region provided on the upper surface 21 side of the epitaxial region 20. The first high-concentration base region 13 is, for example, a P+ type. The first high-concentration base region 13 may be provided by forming a second drift region 28 over the entire upper surface of the first drift region 26, and then injecting a P-type dopant using an oxide film with a desired opening as a mask. The P-type dopant is, for example, an aluminum atom.
[0051] The second high-concentration base region 14 is a second conductivity type region located above the first drift region 26. The second high-concentration base region 14 is, for example, P-type. The second high-concentration base region 14 may be formed by first forming the second drift region 28 over the entire upper surface of the first drift region 26, and then injecting a P-type dopant using an oxide film with desired openings as a mask, and may be etched during the formation process of the gate trench portion 40 described later. The P-type dopant is, for example, an aluminum atom. As another example, the second high-concentration base region 14 may be formed by first forming the second drift region 28 over the entire upper surface of the first drift region 26 to a desired height, and then injecting a P-type dopant using an oxide film with desired openings as a mask, and thereafter the second drift region 28 may be further formed above the second high-concentration base region 14.
[0052] The base region 15 is a second conductivity type region located above the epitaxial region 20. The base region 15 is, for example, P-type. The base region 15 may be formed by epitaxially growing silicon carbide above the epitaxial region 20 while doping it with a P-type dopant. The P-type dopant is, for example, an aluminum atom.
[0053] The contact region 16 is a second conductivity type region located above the base region 15. The contact region 16 is, for example, P+ type. The contact region 16 may be formed by injecting a P-type dopant into a portion of the upper surface of the base region 15, using an oxide film with a desired opening as a mask. The P-type dopant is, for example, an aluminum atom.
[0054] The source region 18 is a region of a first conductivity type located above the base region 15. The source region 18 is, for example, of the N+ type. The source region 18 may be formed by injecting an N-type dopant into a portion of the upper surface of the base region 15, using an oxide film with a desired opening as a mask. The N-type dopant is, for example, a nitrogen atom. Alternatively, the source region 18 may be formed by epitaxially growing silicon carbide above the base region 15 while doping it with an N-type dopant.
[0055] The gate trench portion 40 is provided on the front surface 11 of the semiconductor substrate 10. The gate trench portion 40 may be provided so as to penetrate the base region 15 and reach the second drift region 28. The statement that the gate trench portion 40 penetrates the base region 15 is not limited to manufacturing in the order that the base region 15 is formed before the gate trench portion 40 is formed. Even if the base region 15 is formed on the side wall of the gate trench portion 40 after the gate trench portion 40 has been formed, this is also included in the statement that the gate trench portion 40 penetrates the base region 15. The bottom of the gate trench portion 40 may be provided in contact with the second high-concentration base region 14.
[0056] The gate trench portion 40 has a gate insulating film 42 and a gate conductive portion 44. The gate insulating film 42 is formed covering the inner wall of the gate trench portion 40. The gate insulating film 42 may be formed by oxidizing the semiconductor on the inner wall of the gate trench portion 40. The gate conductive portion 44 is formed inside the gate trench portion 40, on the inside of the gate insulating film 42. The gate insulating film 42 insulates the gate conductive portion 44 from the semiconductor substrate 10. The gate conductive portion 44 is formed of a conductive material such as polysilicon. The gate trench portion 40 is covered by an insulating film 38 on the front surface 11 of the semiconductor substrate 10.
[0057] The barrier metal 50 is provided so as to cover the insulating film 38. The material of the barrier metal 50 may include titanium or titanium nitride.
[0058] The source electrode 52 is provided above the semiconductor substrate 10, with the insulating film 38 in between. The source electrode 52 is formed from a material containing metal. At least a portion of the source electrode 52 may be formed from a metal such as aluminum (Al), or a metal alloy such as aluminum-silicon alloy (AlSi) or aluminum-silicon-copper alloy (AlSiCu).
[0059] The drain electrode 54 is formed on the back surface 12 of the semiconductor substrate 10. The drain electrode 54 is made of a conductive material such as metal.
[0060] As described above, the active part 110 may have a trench-type MOSFET structure. Although examples of manufacturing methods for each component of the active part 110 have been described, the manufacturing method of the active part 110 is not limited to the above method. The active part 110 can be manufactured by conventional methods used by those skilled in the art.
[0061] Figure 3 shows an example of a cross-sectional view along line A-A' of the silicon carbide semiconductor device 100 shown in Figure 1B. The breakdown structure 120 in this example has a stepped portion 60, an electric field relaxation region 62, and a junction termination region 64. In other words, the breakdown structure 120 in this example has a junction termination structure.
[0062] The stepped portion 60 is provided on the outer periphery of the base region 15. The stepped portion 60 may be provided in the depth direction of the semiconductor substrate 10 to a position deeper than the bottom surface of the base region 15. The stepped portion 60 may connect the front surface 11 of the semiconductor substrate 10 and the upper surface 21 of the epitaxial region 20. That is, the front surface 11 of the semiconductor substrate 10 and the upper surface 21 of the epitaxial region 20 may coincide in the pressure-resistant structure portion 120 and the element isolation portion 130 outside the end of the stepped portion 60, with the active portion 110 as the center.
[0063] The field relaxation region 62 is a second conductivity type region located near the end of the stepped portion 60, in contact with the first high-concentration base region 13, and above the first drift region 26. The field relaxation region 62 is, for example, P-type. The field relaxation region 62 may be provided by injecting a P-type dopant. The P-type dopant is, for example, an aluminum atom. The doping concentration of the field relaxation region 62 may be lower than the doping concentration of the first high-concentration base region 13.
[0064] The junction termination region 64 is a second conductivity type region located above the first drift region 26 and in contact with the field relaxation region 62. The junction termination region 64 is, for example, P-type. The junction termination region 64 may be provided by injecting a P-type dopant. The P-type dopant is, for example, an aluminum atom. The doping concentration of the junction termination region 64 may be lower than the doping concentration of the field relaxation region 62.
[0065] By lowering the doping concentration in the electric field relaxation region 62 and the junction termination region 64 compared to the doping concentration in the first high-concentration base region 13, the breakdown voltage of the silicon carbide semiconductor device 100 can be increased.
[0066] The boundary between the pressure-resistant structure 120 and the element isolation section 130 may be defined by the ends of the structure of the pressure-resistant structure 120. The boundary between the pressure-resistant structure 120 and the element isolation section 130 may be defined by the end of the structure that is provided on the outermost side of the structure of the pressure-resistant structure 120, centered on the active section 110. In other words, the end of the junction termination region 64 may be the boundary between the pressure-resistant structure 120 and the element isolation section 130.
[0067] As described above, the pressure-resistant structure 120 may have a jointed end structure. Although examples of manufacturing methods for each component of the pressure-resistant structure 120 have been described, the manufacturing method of the pressure-resistant structure 120 is not limited to the above method. The pressure-resistant structure 120 can be manufactured by conventional methods used by those skilled in the art.
[0068] Figure 4A shows an example of a B-B' cross-sectional view of the silicon carbide semiconductor device 100 shown in Figure 1B. The cross-sectional view in Figure 4A is a cross-sectional view of a part of the element isolation section 130. In the element isolation section 130, the semiconductor substrate 10 has an epitaxial region 20 on its front surface 11. That is, the front surface 11 of the semiconductor substrate 10 and the upper surface 21 of the epitaxial region 20 coincide. The element isolation section 130 has a polymorphic structure 132 made of poly-SiC on the upper surface of the epitaxial region 20.
[0069] The polymorphic structure 132 may be formed by laser irradiation of the upper surface 21 of the epitaxial region 20. When the polymorphic structure 132 is formed by laser irradiation, the laser irradiation may be performed along the [11-20] direction of the semiconductor substrate 10. That is, the polymorphic structure 132 may be provided by extending it in the [11-20] direction of the semiconductor substrate 10. In this example, the polymorphic structure 132 is provided by extending it in the X-axis direction perpendicular to the plane of the paper. When the polymorphic structure 132 is formed by laser irradiation, the crystal structure of the portion of the epitaxial region 20 having a 4H-SiC crystal structure that is irradiated with the laser changes, and a polymorphic structure 132 containing a 4H-SiC, 6H-SiC, or 3C-SiC crystal structure may be formed.
[0070] The polymorphic structure 132 may have a thickness greater than 0 in the depth direction of the semiconductor substrate 10 and 50% or less of the thickness of the epitaxial region 20. That is, the thickness Tp of the polymorphic structure 132 may be greater than 0 and 50% or less of the thickness Te of the epitaxial region 20. Furthermore, the polymorphic structure 132 may have a thickness of 5 μm or less from the upper surface 21 of the epitaxial region 20 in the depth direction of the semiconductor substrate 10. That is, the thickness Tp of the polymorphic structure 132 may be 5 μm or less from the upper surface 21 of the epitaxial region 20. By making the thickness Tp of the polymorphic structure 132 thinner than the thickness Te of the epitaxial region 20, the possibility of damage to the semiconductor substrate 10 due to the provision of the polymorphic structure 132 can be reduced.
[0071] The width of the polymorphic structure 132 may be wider than the width of the dicing region 134, and both ends of the dicing region 134 may be located inside both ends of the polymorphic structure 132. Therefore, when the silicon carbide semiconductor device 100 in wafer state is fragmented, the polymorphic structure 132 may remain on the edges of the silicon carbide semiconductor device 100 in chip state. The width of the dicing region is, for example, 100 μm.
[0072] By providing the polymorphic structure 132 in the [11-20] direction of the semiconductor substrate 10, the elongation of interface dislocations that occur during the manufacturing process of the silicon carbide semiconductor device 100 can be prevented. Interface dislocations that occur during the manufacturing process of the silicon carbide semiconductor device 100 elongate in the [1-100] direction of the semiconductor substrate 10. Since the polymorphic structure 132 has a different crystal structure from the crystal structure of the semiconductor substrate 10, there is no crystal orientation corresponding to the [1-100] direction of the semiconductor substrate 10 in the polymorphic structure 132, and therefore the elongation of interface dislocations can be prevented. As a result, even if interface dislocations occur during the manufacturing process of the silicon carbide semiconductor device 100, the elongation of the interface dislocations is blocked by the polymorphic structure 132, thus reducing the number of silicon carbide semiconductor chips that become unusable due to the elongation of interface dislocations. Details of the interface dislocation formation process during the manufacturing process of the silicon carbide semiconductor device 100 will be described later.
[0073] Figure 4B shows a modified example of the B-B' cross-sectional view of the silicon carbide semiconductor device 100 shown in Figure 1B. In this example, the polymorphic structure 132 is provided in two separate locations in the Y-axis direction, which differs from the example in Figure 4A. Other features may be the same as those in the example in Figure 4A.
[0074] In this example, the polymorphic structure 132 is provided outside the dicing region 134, in contact with both ends of the dicing region 134. Even in this case, when the silicon carbide semiconductor device 100 in wafer state is fragmented, the polymorphic structure 132 may remain on the edges of the silicon carbide semiconductor device 100 in chip state. That is, in both examples of Figure 4A and Figure 4B, when the silicon carbide semiconductor device 100 in wafer state is fragmented, the silicon carbide semiconductor device 100a shown in Figure 1C may be obtained.
[0075] Figure 5A shows a modified top view of the silicon carbide semiconductor device 100. This example differs from the example in Figure 1A in that the polymorphic structure 132 is provided in the X-axis and Y-axis directions. Other features may be the same as those of the example in Figure 1A.
[0076] The polymorphic structure 132 may be provided extending in the X-axis direction and the Y-axis direction. That is, the polymorphic structure 132 may be provided extending in the [11-20] direction and the [1-100] direction of the semiconductor substrate 10. By providing the polymorphic structure 132 extending in the [11-20] direction and the [1-100] direction of the semiconductor substrate 10, compared to the case where the polymorphic structure 132 is provided extending only in the [11-20] direction of the semiconductor substrate 10, it is possible to improve the uneven stress distribution within the semiconductor substrate 10 that occurs during the manufacturing process of the silicon carbide semiconductor device 100, and to suppress damage due to stress. The width of the polymorphic structure 132 extending in the [11-20] direction of the semiconductor substrate 10 and the width of the polymorphic structure 132 extending in the [1-100] direction of the semiconductor substrate 10 may be substantially the same.
[0077] Figure 5B shows an example of an enlarged view of the PQRS region of the silicon carbide semiconductor device 100 shown in Figure 5A.
[0078] In either the X-axis or Y-axis direction, the width of the polymorphic structure 132 may be greater than the width of the dicing region 134, and both ends of the dicing region 134 may be inside both ends of the polymorphic structure 132. In other words, the silicon carbide semiconductor device 100 may be fragmented by dicing at least a portion of the polymorphic structure 132.
[0079] Figure 5C shows a modified top view of the silicon carbide semiconductor chip 100a. The polymorphic structure 132 in this example differs from the example in Figure 1C in that it is provided in the X-axis and Y-axis directions. Other features may be the same as those of the example in Figure 1C.
[0080] The polymorphic structure 132 may be provided on all four sides of the silicon carbide semiconductor chip 100a. That is, the polymorphic structure 132 may be provided in the [11-20] direction of the semiconductor substrate 10, or in the [1-100] direction of the semiconductor substrate 10. The polymorphic structure 132 may be located on the edge of the silicon carbide semiconductor chip 100a.
[0081] Figure 6A shows an example flowchart of the manufacturing process for the silicon carbide semiconductor device 100. This example shows an example flowchart of the manufacturing process for the silicon carbide semiconductor device 100, and is not limited to this example.
[0082] In S100, a semiconductor substrate 10 made of silicon carbide is provided. The crystal structure of the semiconductor substrate 10 may be 4H-SiC, and the main surface of the semiconductor substrate 10 may be perpendicular to the [000-1] direction of the semiconductor substrate 10.
[0083] In step S102, alignment marks 150 are formed on the semiconductor substrate 10. The method for forming the alignment marks 150 is not particularly limited and can be formed by conventional methods used by those skilled in the art.
[0084] In S104, a polymorphic structure 132 made of poly-SiC is provided on the upper surface 21 of the epitaxial region 20 of the semiconductor substrate 10. The step of providing the polymorphic structure 132 may include a step of forming the polymorphic structure 132 by laser irradiation of the upper surface 21 of the epitaxial region 20. When the polymorphic structure 132 is formed by laser irradiation, the crystal structure of the portion of the epitaxial region 20 having a 4H-SiC crystal structure that is irradiated with the laser changes, and a polymorphic structure 132 containing a 4H-SiC, 6H-SiC, or 3C-SiC crystal structure may be formed.
[0085] The wavelength of the laser used to create the polymorphic structure 132 may be between 300 nm and 600 nm. For example, the laser wavelength is 352 nm. The pulse width of the laser used to create the polymorphic structure 132 may be between 1 ps and 100 ps. For example, the laser pulse width is 15 ps. The beam diameter of the laser used to create the polymorphic structure 132 may be between 10 μm and 1 mm. For example, the laser beam diameter is 10 μm. The oscillation frequency of the laser used to create the polymorphic structure 132 may be between 1 MHz and 300 MHz. For example, the laser oscillation frequency is 100 MHz. The energy density of the laser used to create the polymorphic structure 132 is 1 mJ / cm². 2 More than 100mJ / cm 2 The following may be true. For example, the energy density of the laser is 20 mJ / cm². 2 The scanning speed of the laser for forming the polymorphic structure 132 may be 1000 μm / s or more and 5000 μm / s or less. For example, the scanning speed of the laser is 2000 μm / s. The conditions for laser irradiation for forming the polymorphic structure 132 are not limited to the above, and appropriate conditions for forming the polymorphic structure 132 may be appropriately selected.
[0086] The step of forming the polymorphic structure 132 by laser irradiation may include the step of irradiating the semiconductor substrate 10 with a laser along the [11-20] direction. By providing the polymorphic structure 132 in the [11-20] direction of the semiconductor substrate 10, the extension of interface dislocations that occur during the manufacturing process of the silicon carbide semiconductor device 100 can be prevented. Interface dislocations that occur during the manufacturing process of the silicon carbide semiconductor device 100 extend in the [1-100] direction of the semiconductor substrate 10. Since the polymorphic structure 132 has a crystal structure different from the crystal structure of the semiconductor substrate 10, there is no crystal orientation corresponding to the [1-100] direction of the semiconductor substrate 10 in the polymorphic structure 132, and therefore the extension of interface dislocations can be prevented. As a result, even if interface dislocations occur during the manufacturing process of the silicon carbide semiconductor device 100, the extension of the interface dislocations is blocked by the polymorphic structure 132, so the number of silicon carbide semiconductor chips that become unusable due to the extension of interface dislocations can be reduced. Details of the formation process of interfacial dislocations during the manufacturing process of the silicon carbide semiconductor device 100 will be described later.
[0087] The step of forming the polymorphic structure 132 by laser irradiation may include the step of irradiating the semiconductor substrate 10 with a laser along the [1-100] direction. By providing the polymorphic structure 132 extending in both the [11-20] and [1-100] directions of the semiconductor substrate 10, the resistance to stress generated during the manufacturing process of the silicon carbide semiconductor device 100 can be improved compared to the case where the polymorphic structure 132 is provided extending only in the [11-20] direction of the semiconductor substrate 10.
[0088] The step of forming alignment marks 150 on the semiconductor substrate (S102) may, but is not limited to, the step of providing the polymorphic structure 132 (S104). By forming the polymorphic structure 132 after forming the alignment marks 150, accurate positioning of the polymorphic structure 132 can be achieved.
[0089] In S106, an active portion 110 is provided on the semiconductor substrate 10. A breakdown structure portion 120 is also provided on the outer periphery of the active portion 110. The active portion 110 may have a MOSFET structure, and the breakdown structure portion 120 may have a junction termination structure, but is not limited to these. The active portion 110 and the breakdown structure portion 120 can be manufactured by conventional methods used by those skilled in the art.
[0090] An element isolation section 130 is provided on the outer circumference of the pressure-resistant structure section 120. The step of providing the element isolation section 130 may be the same step as providing the active section 110 and / or the pressure-resistant structure section 120. That is, the element isolation section 130 may be an area of the semiconductor substrate 10 other than the area where the active section 110 and the pressure-resistant structure section 120 are provided, and the element isolation section 130, which is an area other than the area where the active section 110 and the pressure-resistant structure section 120 are provided, may be provided by providing the active section 110 and the pressure-resistant structure section 120 on the semiconductor substrate 10.
[0091] The step of providing a polymorphic structure 132 made of poly-SiC on the upper surface 21 of the epitaxial region 20 of the semiconductor substrate 10 may be the step of providing a polymorphic structure 132 made of poly-SiC on the upper surface 21 of the epitaxial region 20 of the semiconductor substrate 10 in the element isolation section 130. The provision of the polymorphic structure 132 in the element isolation section 130 is not limited to being manufactured in the order in which the element isolation section 130 is provided and then the polymorphic structure 132 is provided. The provision of the polymorphic structure 132 in the element isolation section 130 is also included in the provision of the polymorphic structure 132 in the element isolation section 130, even if the element isolation section 130 is provided in the region encompassing the polymorphic structure 132 after the polymorphic structure 132 has been provided.
[0092] In S108, after the step of providing the polymorphic structure 132 (S104), the semiconductor substrate 10 is activated annealed. The activation annealing step may include a step of first activating the semiconductor substrate 10 at 1500°C or higher after the step of providing the semiconductor substrate 10 (S100). The manufacturing process of the silicon carbide semiconductor device 100 may include multiple annealing processes for immobilizing the ions implanted in the semiconductor substrate 10. The manufacturing process of the silicon carbide semiconductor device 100 may also include an annealing step before the step of providing the polymorphic structure 132 (S104). In this case, it is preferable that the annealing temperature of the annealing process performed before the step of providing the polymorphic structure 132 (S104) is less than 1500°C. That is, it is preferable that the step of activating the semiconductor substrate 10 at 1500°C or higher is performed for the first time after the step of providing the polymorphic structure 132 (S104).
[0093] Interfacial dislocations that occur during the manufacturing process of the silicon carbide semiconductor device 100 become mobile when the semiconductor substrate 10 is heated to a high temperature. When stress is applied to the semiconductor substrate 10 while the interfacial dislocations are mobile, the interfacial dislocations extend in the [1-100] direction of the semiconductor substrate 10. Therefore, by providing the polymorphic structure 132 before the activation annealing stage of the semiconductor substrate 10 at 1500°C or higher, the extension of the interfacial dislocations can be prevented by the polymorphic structure 132 even if the interfacial dislocations become mobile and extend. This reduces the number of silicon carbide semiconductor chips that become unusable due to the extension of interfacial dislocations. Details of the interfacial dislocation formation process during the manufacturing process of the silicon carbide semiconductor device 100 will be described later.
[0094] Figure 6B shows a modified flowchart of the manufacturing process for the silicon carbide semiconductor device 100. This flowchart differs from the example in Figure 6A in that it includes a step of providing the polymorphic structure 132 (S206) after the step of providing the active part 110 and the pressure-resistant structure 120 (S204). Other features may be the same as the example in Figure 6A. That is, the step of providing the polymorphic structure 132 (S206) may be followed by a step of activating and annealing the semiconductor substrate 10 (S208), and the activation and annealing step (S208) may include a step of first activating and annealing the semiconductor substrate 10 at 1500°C or higher after the step of providing the semiconductor substrate 10 (S200). By providing the polymorphic structure 132 before the step of activating and annealing the semiconductor substrate 10 at 1500°C or higher, even if the interface dislocations that have become mobile extend, the extension of the interface dislocations can be prevented by the polymorphic structure 132.
[0095] Figure 6C shows a modified flowchart of the manufacturing process for the silicon carbide semiconductor device 100. This flowchart differs from the examples in Figures 6A and 6B in that it includes a step of providing the polymorphic structure 132 (S306) in the middle of the step of providing the active part 110 and the pressure-resistant structure 120 (S304). Other features may be the same as those of the examples in Figures 6A and 6B. That is, the step of activating and annealing the semiconductor substrate 10 (S308) may be included after the step of providing the semiconductor substrate 10 (S300), and the activation and annealing step (S308) may include a step of first activating and annealing the semiconductor substrate 10 at 1500°C or higher after the step of providing the semiconductor substrate 10 (S300). By providing the polymorphic structure 132 before the step of activating and annealing the semiconductor substrate 10 at 1500°C or higher, even if the interface dislocations that have become mobile extend, the extension of the interface dislocations can be prevented by the polymorphic structure 132.
[0096] The step of providing the polymorphic structure 132 (S306) may be performed in the middle of the step of providing the active part 110 and the pressure-resistant structure 120 (S304). That is, the step of providing the polymorphic structure 132 (S306) may be performed before or after the step of providing the second drift region 28, before or after the step of providing the first high-concentration base region 13, before or after the step of providing the second high-concentration base region 14, before or after the step of providing the base region 15, before or after the step of providing the contact region 16, and before or after the step of providing the source region 18.
[0097] Figure 6D shows a modified flowchart of the manufacturing process for the silicon carbide semiconductor device 100. This flowchart differs from the examples in Figures 6A to 6C in that it includes a step of providing the polymorphic structure 132 (S402) before the step of forming alignment marks (S404). Other features may be the same as those of the examples in Figures 6A to 6C. That is, the step of activating and annealing the semiconductor substrate 10 (S408) may be included after the step of providing the semiconductor substrate 10 (S400), and the activation and annealing step (S408) may include a step of first activating and annealing the semiconductor substrate 10 at 1500°C or higher after the step of providing the semiconductor substrate 10 (S400). By providing the polymorphic structure 132 before the step of activating and annealing the semiconductor substrate 10 at 1500°C or higher, even if the interface dislocations that have become mobile extend, the extension of the interface dislocations can be prevented by the polymorphic structure 132.
[0098] If the polymorphic structure 132 is provided (S402) before the step of forming alignment marks (S404), the alignment for forming the polymorphic structure 132 may be performed using the orientation flat 152 of the semiconductor substrate 10.
[0099] As described above, the manufacturing method of the silicon carbide semiconductor device 100 of the present invention is characterized by comprising a step of providing the polymorphic structure 132. The order of the steps of providing the polymorphic structure 132 can be freely changed. The step of providing the polymorphic structure 132 may be before the step of first activating and annealing the semiconductor substrate 10 at 1500°C or higher. By providing the polymorphic structure 132 before the step of activating and annealing the semiconductor substrate 10 at 1500°C or higher, even if the interface dislocations that have become mobile extend, the extension of the interface dislocations can be prevented by the polymorphic structure 132.
[0100] Figure 7 shows an example of the formation process of interface dislocation 76. In S500, in the process of forming an epitaxial region 20 above the base region 30 by epitaxial growth, a basal plane dislocation 72 is formed on the base plane 70. In S502, when the semiconductor substrate 10 is subjected to a high-temperature treatment of 1500°C or higher, the basal plane dislocation 72 becomes movable, and both ends of the basal plane dislocation 72 are converted into through-edge dislocations 74, fixing it in place. It then slides through the epitaxial region 20, stops near the upper surface 21 of the epitaxial region 20, and forms an interface dislocation 76. Subsequently, in S504, stress is applied to the semiconductor substrate 10, causing the interface dislocation 76 to extend in the [1-100] direction of the semiconductor substrate 10. The elongation of the interface dislocation 76 may extend to a length of 3 to 5 chips in the silicon carbide semiconductor device 100 in wafer state, which corresponds to the size of individual silicon carbide semiconductor chips when the device is fragmented.
[0101] Figure 8A shows an example of the process of preventing the extension of an interface dislocation 76 in a silicon carbide semiconductor device 100. At S502, an interface dislocation 76 is formed near the upper surface 21 of the epitaxial region 20. In this example, the interface dislocation 76 is formed in a region of the silicon carbide semiconductor device 100 in wafer state that will become a silicon carbide semiconductor chip 100a when it is separated into individual pieces. At S504, when the interface dislocation 76 extends, the extension of the interface dislocation 76 is prevented by the polymorphic structure 132 provided at the boundary between the silicon carbide semiconductor chip 100a and the silicon carbide semiconductor chip 100b. Therefore, the silicon carbide semiconductor device 100 in this example is provided with a polymorphic structure 132 that extends in the [11-20] direction, which is perpendicular to the [1-100] direction of the semiconductor substrate 10, which is the direction in which the interface dislocations 76 extend. This prevents the interface dislocations 76 from extending to the silicon carbide semiconductor chip 100b, thereby reducing the number of silicon carbide semiconductor chips that become unusable due to the extension of the interface dislocations 76.
[0102] Figure 8B shows an example of the formation process of interface dislocations 76 in a silicon carbide semiconductor device according to a comparative example. In the silicon carbide semiconductor device according to the comparative example, since the polymorphic structure portion 132 is not provided, the elongation of interface dislocations 76 cannot be prevented, and the elongation of interface dislocations 76 may render the silicon carbide semiconductor chip 100b unusable.
[0103] Although the present invention has been described above using embodiments, the technical scope of the present invention is not limited to the scope described in the above embodiments. It will be apparent to those skilled in the art that various modifications or improvements can be made to the above embodiments. It will be clear from the claims that such modified or improved forms may also be included in the technical scope of the present invention.
[0104] It should be noted that the execution order of operations, procedures, steps, and stages in the apparatus, systems, programs, and methods shown in the claims, specifications, and drawings is not explicitly stated as "before," "prior to," etc., and that these can be implemented in any order unless the output of a previous process is used in a later process. Even if the operation flow in the claims, specifications, and drawings is described using phrases such as "first," "next," etc. for convenience, it does not mean that it is essential to perform the operations in that order. [Explanation of symbols]
[0105] 10 Semiconductor substrate, 11 Front surface of semiconductor substrate 10, 12 Back surface of semiconductor substrate 10, 13 First high-concentration base region, 14 Second high-concentration base region, 15 Base region, 16 Contact region, 18 Source region, 20 Epitaxial region, 21 Top surface of epitaxial region 20, 22 Bottom surface of epitaxial region 20, 24 Buffer region, 26 First drift region, 28 Second drift region, 30 Basal region, 38 Insulating film, 40 Gate trench portion, 42 Gate insulating film, 44 Gate conductive portion, 50 Barrier metal, 52 Source electrode, 54 Drain electrode, 60 Step portion, 62 Field relaxation region, 64 Junction termination region, 70 Basal plane, 72 Basal plane dislocation, 74 Through-edge dislocation, 76 Interface dislocation, 100 Silicon carbide semiconductor device, 110 Active portion, 120 Pressure-resistant structure, 130 element isolation section, 132 polymorphic structure section, 134 dicing area, 136 first edge, 138 second edge, 150 alignment mark, 152 orientation flat
Claims
1. A silicon carbide semiconductor device comprising a semiconductor substrate made of silicon carbide and having an epitaxial region on its front surface, The semiconductor substrate has an active portion provided on it, In the semiconductor substrate, a pressure-resistant structure is provided on the outer periphery of the active portion, In the semiconductor substrate, an element isolation portion is provided on the outer periphery of the voltage-resistant structure portion, Equipped with, The element isolation portion has a polymorphic structure made of poly-SiC on the upper surface of the epitaxial region. Silicon carbide semiconductor device.
2. The polymorphic structure portion has a crystal structure different from the crystal structure of the semiconductor substrate. The silicon carbide semiconductor device according to claim 1.
3. The silicon carbide semiconductor device according to claim 1, wherein the crystal structure of the polymorphic structure portion includes 4H-SiC, 6H-SiC, or 3C-SiC.
4. The polymorphic structure portion has a thickness greater than 0 in the depth direction of the semiconductor substrate and a thickness of 50% or less of the thickness of the epitaxial region. The silicon carbide semiconductor device according to claim 1.
5. The silicon carbide semiconductor device according to claim 4, wherein the polymorphic structure portion has a thickness of 5 μm or less from the upper surface of the epitaxial region in the depth direction of the semiconductor substrate.
6. The silicon carbide semiconductor device is a silicon carbide semiconductor chip that has been separated from a wafer, The polymorphic structure is provided on the first end edge of the silicon carbide semiconductor chip and on the second end edge opposite to the first end edge. The silicon carbide semiconductor device according to claim 1.
7. The silicon carbide semiconductor device according to claim 6, wherein the extension direction of the first and second edges is the [11-20] direction of the semiconductor substrate.
8. The silicon carbide semiconductor device is a silicon carbide semiconductor chip that has been separated from a wafer, The polymorphic structure is provided on all four sides of the silicon carbide semiconductor chip. The silicon carbide semiconductor device according to claim 1.
9. The silicon carbide semiconductor device according to any one of claims 6 to 8, wherein the polymorphic structure is located on the edge of the silicon carbide semiconductor chip.
10. The steps include providing a semiconductor substrate made of silicon carbide, The steps include providing an active portion to the semiconductor substrate, The steps include providing a pressure-resistant structure on the outer circumference of the active part, The steps include providing an element isolation section on the outer circumference of the pressure-resistant structure, In the element isolation section, the step of providing a polymorphic structure made of poly-SiC on the upper surface of the epitaxial region of the semiconductor substrate, A method for manufacturing a silicon carbide semiconductor device, comprising the features described above.
11. A method for manufacturing a silicon carbide semiconductor device according to claim 10, further comprising the step of activating and annealing the semiconductor substrate after the step of providing the polymorphic structure.
12. The method for manufacturing a silicon carbide semiconductor device according to claim 11, wherein the activation annealing step includes, after the step of providing the semiconductor substrate, the first step of activating annealing the semiconductor substrate at 1500°C or higher.
13. A method for manufacturing a silicon carbide semiconductor device according to claim 10, further comprising the step of forming alignment marks on the semiconductor substrate before the step of providing the polymorphic structure.
14. The method for manufacturing a silicon carbide semiconductor device according to any one of claims 10 to 13, wherein the step of providing the polymorphic structure includes the step of forming the polymorphic structure by irradiating the upper surface of the epitaxial region with a laser.
15. The method for manufacturing a silicon carbide semiconductor device according to claim 14, wherein the step of forming the polymorphic structure by laser irradiation includes the step of irradiating the semiconductor substrate with a laser along the [11-20] direction.
16. The method for manufacturing a silicon carbide semiconductor device according to claim 15, wherein the step of forming the polymorphic structure by laser irradiation includes the step of irradiating the semiconductor substrate with a laser along the [1-100] direction.