Manufacturing method for silicon carbide semiconductor devices

Abstract

To provide a method for manufacturing an SiC semiconductor device in which an energization variation amount is predicted and the predicted energization variation amount is reflected in a manufacturing process.SOLUTION: A method for manufacturing a SiC semiconductor device includes: measuring BPD density that is density of basal plane dislocation in a semiconductor substrate made of silicon carbide; assuming that a semiconductor chip having a switching element constituting a built-in diode is manufactured, and predicting the energization variation amount based on at least BPD density using an amount of variation in electrical characteristics after driving with respect to initial electrical characteristics of the semiconductor chip, as an energization variation amount; and determining whether or not to continue manufacturing of the SiC semiconductor device using the semiconductor substrate based on the predicted energization variation amount.SELECTED DRAWING: Figure 5

Description

[Technical Field]

[0001] The present invention relates to a method for manufacturing a SiC semiconductor device using silicon carbide (hereinafter also referred to as "SiC"). [Background technology]

[0002] Conventionally, SiC semiconductor devices composed of SiC have been proposed, for example, SiC semiconductor devices on which MOSFETs are formed. MOSFET is an abbreviation for Metal Oxide Semiconductor Field Effect Transistor. Specifically, this type of SiC semiconductor device is, for example, n + On a SiC substrate of a certain type, n with a lower impurity concentration than that of the SiC substrate is applied. - A buffer layer of type is formed, and on the buffer layer, n with an impurity concentration lower than that of the buffer layer is added. - A p-type drift layer is formed. A p-type base layer is placed on top of the drift layer. The buffer layer and the drift layer are composed of epitaxial layers.

[0003] The surface layer of the base layer is n + A source region of a specific type is formed. Multiple trenches are then formed so as to penetrate the source region and base layer and reach the drift layer, and a gate insulating film and a gate electrode are sequentially formed in each trench. This forms a MOSFET with a trench gate structure.

[0004] Furthermore, in the SiC semiconductor device described above, the built-in diode is formed by a pn junction between the base layer and the drift layer.

[0005] Now, in this type of SiC semiconductor device, basal plane dislocations (hereinafter referred to as "BPD") may exist in the SiC substrate. Note that BPD is an abbreviation for basal plane dislocation. And in this type of SiC semiconductor device, it is known that when the built-in diode is driven, defects expand in the epitaxial layer starting from BPD, and the current amount during energization decreases. Hereinafter, for the sake of convenience of explanation, the amount of change in the electrical characteristics of the built-in diode after defect expansion caused by BPD with respect to the initial value of the electrical characteristics of the built-in diode at the time of manufacturing the SiC semiconductor device is simply referred to as the "energization change amount".

[0006] In recent years, there has been a demand for SiC semiconductor devices with such suppressed energization change amounts. Therefore, a method has been proposed for determining whether a recombination layer for suppressing the energization change amount should be provided during the formation of the epitaxial layer based on the BPD density of the SiC substrate, and for determining the device configuration of the SiC semiconductor device (for example, Patent Document 1).

Prior Art Documents

Patent Documents

[0007]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] However, in the formation of the epitaxial layer, although adding a formation process of a recombination layer with a higher impurity concentration than the SiC substrate can provide a SiC semiconductor device with suppressed energization change amount, its manufacturing cost increases. And in order to reduce the manufacturing cost, it is desirable to determine whether to continue manufacturing the SiC semiconductor device according to the energization change amount predicted in the manufacturing process, or to classify the SiC chips with MOSFETs formed according to the required performance.

[0009] In view of the above, the present invention aims to provide a method for manufacturing a SiC semiconductor device in which the amount of current fluctuation is suppressed by predicting the amount of current fluctuation and reflecting the predicted amount of current fluctuation in the manufacturing process. [Means for solving the problem]

[0010] To achieve the above objective, the method for manufacturing a silicon carbide semiconductor device described in claim 1 is a method for manufacturing a silicon carbide semiconductor device having a switching element formed on a semiconductor substrate (11) made of silicon carbide and comprising a built-in diode, comprising: measuring the BPD density, which is the density of basal plane dislocations in the semiconductor substrate; assuming that a semiconductor chip (10) having a switching element has been manufactured, using the initial electrical characteristics of the switching element immediately after the manufacture of the semiconductor chip as an initial value, and using the amount of change in said electrical characteristics after driving the switching element for a predetermined time or longer as an energization fluctuation amount, predicting the energization fluctuation amount based at least on the BPD density; and determining whether or not to continue manufacturing the semiconductor device using the semiconductor substrate based on the predicted energization fluctuation amount.

[0011] According to this method, assuming that a semiconductor chip having a switching element is manufactured using a semiconductor substrate made of SiC, the amount of current fluctuation in the semiconductor chip is predicted based on at least the BPD density of the semiconductor substrate. Then, by deciding whether or not to continue manufacturing the SiC semiconductor device using the semiconductor substrate based on the predicted amount of current fluctuation, it becomes possible to efficiently manufacture SiC semiconductor devices with suppressed current fluctuations.

[0012] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]

[0013] [Figure 1] This is a perspective cross-sectional view showing an example of the configuration of a SiC semiconductor device. [Figure 2]This is a cross-sectional view showing the cell portion of a semiconductor chip made of SiC. [Figure 3] Figure 2 is an explanatory diagram of the current path in a semiconductor chip. [Figure 4] This is an explanatory diagram of defect growth caused by BPD (Blemish-Pattern Defect). [Figure 5] This is a flowchart showing part of the manufacturing process for a SiC semiconductor device according to the embodiment. [Figure 6] This figure shows the relationship between the BPD density of a SiC semiconductor substrate and the amount of VON fluctuation in a MOSFET of a semiconductor chip manufactured using that SiC semiconductor substrate. [Figure 7] This figure shows the results of observing band-shaped and triangular defects that grew from BPD using PL imaging. [Figure 8A] This figure shows an example of the distribution of BPD density in a SiC semiconductor substrate. [Figure 8B] This figure shows another example of the BPD density distribution in a SiC semiconductor substrate. [Figure 9] Figure 5 is a flowchart showing the manufacturing process of SiC semiconductor devices. [Figure 10] This figure shows an example of variation in the initial electrical characteristics of semiconductor chips. [Figure 11] This figure corresponds to Figure 2 and is a cross-sectional view showing an example of the configuration of a SiC semiconductor device of another embodiment. [Modes for carrying out the invention]

[0014] The embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0015] (First Embodiment) The first embodiment will be described with reference to the drawings. In this embodiment, for example, as shown in FIG. 1, a SiC semiconductor device using a semiconductor chip 10 in which an inversion-type MOSFET with a trench gate structure is formed as a switching element will be described as a representative example. Although not particularly shown, the semiconductor chip 10 has a cell region and an outer peripheral region formed so as to surround the cell region. The MOSFET shown in FIG. 1 is formed in the cell region of the semiconductor chip 10.

[0016] For the sake of convenience of explanation, as shown in FIG. 1, one direction in the plane direction of the semiconductor substrate 11 to be described later is referred to as the "X-axis direction", a direction orthogonal to the X-axis direction in the plane direction is referred to as the "Y-axis direction", and a direction orthogonal to the plane direction, that is, the XY plane is referred to as the "Z-axis direction".

[0017] 〔SiC Semiconductor Device〕 The SiC semiconductor device is configured using the semiconductor chip 10. Specifically, the semiconductor chip 10 includes, for example, an n + -type semiconductor substrate 11 made of SiC. As the semiconductor substrate 11, for example, a SiC substrate having an off-angle of 0 to 8° with respect to the (0001) Si plane and an n-type impurity concentration of nitrogen, phosphorus, etc. of 1.0×10 19 / cm 3 and a thickness of about 300 μm is used, but it is not limited thereto. The semiconductor substrate 11 constitutes, for example, a drain region.

[0018] On the surface of the semiconductor substrate 11, for example, an n - -type buffer layer 12 made of SiC is formed. The buffer layer 12 is formed by epitaxial growth on the surface of the semiconductor substrate 11. The buffer layer 12 has, for example, an n-type impurity concentration that is the impurity concentration between the semiconductor substrate 11 and the low-concentration layer 13 to be described later, and a thickness of about 1 μm.

[0019] On the surface of the buffer layer 12, for example, the n-type impurity concentration is 5.0 to 10.0×10 15 / cm 3It is said that the n is made of SiC with a thickness of about 10-15 μm. - A low-concentration layer 13 of the type is formed. The low-concentration layer 13 may have a constant impurity concentration in the Z-axis direction, but it is preferable that the concentration distribution is sloped so that the concentration is higher on the semiconductor substrate 11 side of the low-concentration layer 13 than on the side away from the semiconductor substrate 11. For example, the impurity concentration of the low-concentration layer 13 in the portion about 3 to 5 μm from the surface of the semiconductor substrate 11 is 2.0 × 10⁻¹⁶. 15 / cm 3 It is preferable that the concentration is higher than that of other parts. By using this configuration, the internal resistance of the low-concentration layer 13 can be reduced, and the on-resistance can be reduced. Furthermore, the low-concentration layer 13 is composed of an epitaxial layer formed by epitaxial growth.

[0020] On the surface of the low-concentration layer 13, for example, at the connection between the cell portion and the outer peripheral portion (not shown), a JFET portion 14 and a first deep layer 15 are formed. The JFET portion 14 and the first deep layer 15 each have linear portions that extend along the X-axis direction and are arranged alternately in a repeating pattern along the Y-axis direction. In other words, the JFET portion 14 and the first deep layer 15 are configured to be stripes that extend along the X-axis direction in the direction normal to the surface of the semiconductor substrate 11, and are arranged alternately along the Y-axis direction. Hereafter, for the sake of simplicity, the direction normal to the surface of the semiconductor substrate 11 will also be simply referred to as the "normal direction".

[0021] The JFET section 14 is, for example, an n-type material with a higher impurity concentration than the low-concentration layer 13, and has a depth of 0.3 to 1.5 μm. The JFET section 14 has, for example, an n-type impurity concentration of 7.0 × 10⁻⁶ 16 ~5.0×10 17 / cm 3 It is said that the JFET section 14 is an ion-implanted layer formed, for example, by ion-implanting n-type impurities into the low-concentration layer 13.

[0022] The first deep layer 15 has, for example, a p-type impurity concentration of 2.0 × 10⁻¹⁰ such as boron. 17 ~2.0×10 18 / cm 3 It is stated that the first deep layer 15 extends, for example, beyond the JFET portion 14 to the guard ring side of the outer periphery (not shown). The first deep layer 15 is formed to be shallower than the JFET portion 14. In other words, the first deep layer 15 is formed such that its bottom is located within the JFET portion 14, that is, between the JFET portion 14 and the low-concentration layer 13. The first deep layer 15 has a width of 0.9 μm or less in the Y-axis direction. The pitch between adjacent first deep layers 15 in the Y-axis direction is 0.75 to 1.1 μm.

[0023] The surface of the low-concentration layer 13 is provided with multiple p-shaped guard rings (not shown) surrounding the cell portion, for example, on the outer periphery (not shown). The guard rings (not shown) are, for example, square or circular in shape with rounded corners when viewed from the normal direction.

[0024] On the JFET section 14 and the first deep layer 15 in the cell section, for example, a current dispersion layer 16 and a second deep layer 17 are formed.

[0025] The current dispersion layer 16 is composed of, for example, an n-type impurity layer with a thickness of 0.5 to 2 μm. The n-type impurity concentration of the current dispersion layer 16 is, for example, 1.0 × 10⁻⁶ 16 ~5.0×10 17 / cm 3 It is stated that the current dispersion layer 16 is connected to the JFET section 14. Therefore, the low-concentration layer 13, the JFET section 14, and the current dispersion layer 16 are connected, and together they constitute the drift layer 18.

[0026] The second deep layer 17 is formed in the cell portion, for example, when the p-type impurity concentration is 2.0 × 10 17 ~2.0×10 18 / cm 3The second deep layer 17 is formed to be connected to the first deep layer 15.

[0027] The current distribution layer 16 and the second deep layer 17 extend in a direction intersecting the striped portion of the JFET section 14 and the longitudinal direction of the first deep layer 15. In this embodiment, the current distribution layer 16 and the second deep layer 17 extend in the longitudinal direction along the Y-axis, and are arranged in a layout in which multiple layers are alternately placed along the X-axis. The formation pitch of the current distribution layer 16 and the second deep layer 17 is, for example, matched to the formation pitch of the trench gate structure described later, and the second deep layer 17 is formed to sandwich the trench 22 described later.

[0028] A p-type base layer 19 is formed on the current dispersion layer 16 and the second deep layer 17. And, on the surface of the base layer 19 in the cell portion, n + Source region 20 and p of type + A contact region 21 of the type is formed. The source region 20 is formed so as to be in contact with the side surface of the trench 22, which will be described later, and the contact region 21 is formed on the opposite side of the trench 22, with the source region 20 in between. The source region 20 corresponds to the impurity region.

[0029] The base layer 19 has, for example, a p-type impurity concentration of 3.0 × 10 17 / cm 3 The following is stated: The base layer 19 is formed, for example, by ion implantation, and the impurity concentration is higher in the cell portion than in the outer peripheral portion (not shown). In the source region 20, the n-type impurity concentration in the surface layer, i.e., the surface concentration, is for example 1.0 × 10⁻⁶. 21 / cm 3 It is stated that the contact region 21 has a p-type impurity concentration in the surface layer, i.e., a surface concentration of, for example, 1.0 × 10⁻⁶. 21 / cm 3 It is said that...

[0030] The thickness of the base layer 19 and the source region 20 is adjusted, for example, so that the channel length is 0.4 μm or less. The channel length is the length of the portion of the base layer 19 that is along the side surface of the trench 22 in the Z-axis direction.

[0031] The semiconductor chip 10 has a structure in which, for example, a semiconductor substrate 11, a buffer layer 12, a low-density layer 13, a JFET section 14, a first deep layer 15, a current-dispersing layer 16, a second deep layer 17, a base layer 19, a source region 20, a contact region 21, etc. are stacked, as described above. For the sake of explanation, the side of the semiconductor chip 10 that has the source region 20 and the contact region 21 will be referred to as "side 10a" of the semiconductor chip 10, and the side that has the semiconductor substrate 11 will be referred to as "other side 10b" of the semiconductor chip 10. The source region 20 and the contact region 21 are exposed from side 10a of the semiconductor chip 10.

[0032] In the semiconductor chip 10, multiple trenches 22 with a width of 1.4 to 2.0 μm are formed in the cell portion, for example, penetrating the base layer 19 to reach the current dispersion layer 16, with the bottom surface located within the current dispersion layer 16. The trenches 22 are not deep enough to reach the JFET portion 14 and the first deep layer 15, and are formed so that the JFET portion 14 and the first deep layer 15 are located below the bottom surface.

[0033] Multiple trenches 22 are extended along the Y-axis direction, and are also arranged at equal intervals along the X-axis direction to form a stripe-like structure. In other words, the trenches 22 are formed so that their longitudinal direction is perpendicular to the longitudinal direction of the first deep layer 15. The trenches 22 are formed so as to be sandwiched between the second deep layer 17 in the normal direction. Furthermore, the trenches 22 are formed such that, for example, the distance between the centers of adjacent trenches 22, i.e., the trench pitch, is 3.0 μm or less.

[0034] The trench 22 is embedded, for example, by a gate insulating film 23 formed on its inner wall surface and a gate electrode 24 made of doped poly-Si formed on the surface of the gate insulating film 23. This constitutes a trench gate structure. The gate insulating film 23 is formed, for example, on the inner wall surface of the trench 22 by thermal oxidation or CVD. CVD is an abbreviation for chemical vapor deposition. The gate insulating film 23 has a thickness of approximately 100 nm on both the side and bottom surfaces of the trench 22.

[0035] The gate insulating film 23 is also formed on surfaces other than the inner wall surface of the trench 22. Specifically, the gate insulating film 23 is formed to cover, for example, a portion of the surface of the source region 20 on one surface 10a of the semiconductor chip 10. In other words, the gate insulating film 23 has contact holes 23a formed in a portion different from the portion where the gate electrode 24 is located, exposing the contact region 21 and the rest of the source region 20.

[0036] The gate insulating film 23 is also formed on the surface of the base layer 19 in the outer peripheral region (not shown). The gate electrode 24 extends to the surface of the gate insulating film 23 in the outer peripheral region (not shown), similar to the gate insulating film 23. The trench gate structure of this embodiment is configured as described above.

[0037] The semiconductor chip 10 has a mesa structure in which, for example, in the outer peripheral region (not shown), recesses are formed that penetrate the base layer 19 and reach the current dispersion layer 16. In the region of the outer peripheral region (not shown) adjacent to the cell region, a contact region 21 is formed on the surface layer of the base layer 19, similar to the cell region.

[0038] An interlayer insulating film 25 is formed on one surface 10a of the semiconductor chip 10, covering the gate electrode 24, gate insulating film 23, etc. The interlayer insulating film 25 is made of, for example, BPSG. BPSG is an abbreviation for Borophosphosilicate Glass.

[0039] The interlayer insulating film 25 has a contact hole 25a that communicates with the contact hole 23a and exposes the source region 20 and the contact region 21. The contact hole 25a formed in the interlayer insulating film 25 is formed to communicate with the contact hole 23a formed in the gate insulating film 23 and functions together with the contact hole 23a as a single contact hole. Hereinafter, the contact hole 23a and the contact hole 25a will be collectively referred to as "contact hole 23b". The pattern of the contact hole 23b is arbitrary and can be, for example, a pattern of multiple squares arranged in a row, a pattern of rectangular lines arranged in a row, or a pattern of lines lined up. For example, the contact hole 23b may be in the shape of a line along the longitudinal direction of the trench 22.

[0040] A source electrode 26 is formed on the interlayer insulating film 25, electrically connected to the source region 20 and the contact region 21 through a contact hole 23b. The source electrode 26 is also connected to a contact region 21 formed on the base layer 19 (not shown) on the outer periphery. In addition, a gate wiring (not shown) is formed on the interlayer insulating film 25, electrically connected to the gate electrode 24 through a contact hole 27b.

[0041] The source electrode 26 is composed of multiple metals, such as Ni / Al. Of the multiple metals, the n-type SiC, i.e., the portion that contacts the source region 20, is composed of a metal that can make ohmic contact with n-type SiC. In addition, at least the p-type SiC, i.e., the portion that contacts the contact region 21, is composed of a metal that can make ohmic contact with p-type SiC.

[0042] A drain electrode 27 is formed on the other side 10b of the semiconductor chip 10, which is electrically connected to the semiconductor substrate 11. The semiconductor chip 10, for example, is configured as an n-channel inverting trench gate MOSFET with the above-described structure. Furthermore, the semiconductor chip 10 has an internal diode formed by a pn junction between the drift layer 18 and the base layer 19, etc.

[0043] The above is a basic example of the configuration of a semiconductor chip 10 used in a SiC semiconductor device. SiC semiconductor devices are used, for example, to configure inverter circuits that drive three-phase motors, etc., by utilizing the MOSFETs of the semiconductor chip 10, but they are not limited to this application and can of course be applied to other applications as well.

[0044] [Defective growth caused by basal plane dislocations] As shown in Figure 2, for example, the SiC semiconductor device has a built-in diode BD in the cell portion, which is composed of a trench gate structure MOSFET and a pn junction. Furthermore, in the SiC semiconductor device, BPDs are present, for example, in the semiconductor substrate 11, buffer layer 12, and drift layer, and defects can occur due to these BPDs.

[0045] As shown in Figure 3, the SiC semiconductor device has a circuit configuration that includes a MOSFET and an internal diode BD, and when the MOSFET is turned on, an on current I flows from the drain electrode 27 to the source electrode 26. ON This occurs. In Figure 3, "S," "D," and "G" correspond to the source electrode 26, drain electrode 27, and gate electrode 24, respectively. Specifically, when a predetermined voltage such as 20V is applied to the gate electrode 24, a channel is formed on the surface of the base layer 19 that is in contact with the trench 22, and an on current I is generated between the source electrode 26 and the drain electrode 27. ON It plays.

[0046] Subsequently, when the SiC semiconductor device is turned off, a reverse bias is applied, causing it to conduct in reverse. Therefore, the built-in diode BD functions as a freewheeling diode, and a freewheeling current I flows through the built-in diode. OFF A current flows. At this time, as shown in Figure 4, holes that have diffused from the p-type layer side to the n-type layer side of the pn junction constituting the built-in diode BD recombine with electrons in the n-type layer. Because the recombination energy of these holes and electrons is large, the BPD expands in the SiC semiconductor device, resulting in stacking faults D. Hereafter, such stacking faults D will be simply referred to as "defects D". These defects D are caused by the on-current I ON and return current I OFF This hinders performance. As described above, if the semiconductor chip 10 is driven for a predetermined amount of time or longer, a defect D will occur. Therefore, the electrical characteristics after driving will be inferior to those immediately after manufacturing, i.e., before the defect D occurs.

[0047] In recent years, SiC semiconductor devices have been required to reduce the "current fluctuation," which is the amount of change in electrical characteristics after being driven for a predetermined period of time compared to the initial electrical characteristics of the semiconductor chip 10 before defects D occur. The electrical characteristics referred to here include, for example, the forward voltage Vf of the built-in diode BD and the ON voltage V of the MOSFET. DS These are some examples. Since the manufacturing cost of SiC semiconductor devices is higher than that of semiconductor devices mainly composed of Si (silicon), it is important to predict the amount of current fluctuation in the manufacturing process in order to manufacture SiC semiconductor devices with reduced current fluctuations while keeping the increase in manufacturing costs down.

[0048] [Method for manufacturing SiC semiconductor devices] Next, the manufacturing method of the SiC semiconductor device and the prediction of current fluctuations according to this embodiment will be described. Note that the growth of the epitaxial layer made of SiC and the formation of the trench gate structure MOSFET can be done by known SiC semiconductor manufacturing processes, so these details are omitted in this specification.

[0049] For example, the SiC semiconductor device of this embodiment is manufactured through the process shown in Figure 5. In step S110, multiple semiconductor substrates 11 are cut from an ingot made of SiC.

[0050] In the subsequent step S120, for example, the BPD density is measured on at least one representative semiconductor substrate 11 from among the cut-out semiconductor substrates 11. The BPD density can be obtained, for example, by wet etching the surface of the semiconductor substrate 11 using potassium hydroxide (KOH), checking the number of depressions on the surface after etching, i.e., etch pits, and calculating the number per unit area. Specifically, for example, the BPD density can be obtained by imaging the surface of the semiconductor substrate 11 after KOH etching and analyzing the image using a known image analysis technique.

[0051] In step S130, the amount of current fluctuation is predicted, assuming that the semiconductor chip 10 was manufactured using the semiconductor substrate 11 cut out in step S110, based at least on the BPD density. For example, in step S130, the amount of current fluctuation is predicted, at least on the BPD density, using a discriminant model composed of a predetermined calculation formula or machine learning model. Specifically, for example, the BPD density of the semiconductor substrate 11 is measured, and the initial V of the MOSFET of the semiconductor chip 10 manufactured using the semiconductor substrate 11 with that BPD density is... ON V after a predetermined period of operation ON The variation ΔV ON The percentage data is obtained. The BPD density obtained in advance and the initial V of the semiconductor chip 10 are used. ON Variance ΔV ON The relationship with the ratio is shown, for example, in Figure 6. The results shown in Figure 6 show the BPD density of the semiconductor substrate 11 and the ΔV in the semiconductor chip 10 manufactured using the semiconductor substrate 11 with that BPD density. ON / Initial V ONA predetermined correlation exists between the two, suggesting that the amount of current fluctuation can be predicted based on the BPD density. Then, using a discriminant model constructed based on this relationship data between BPD density and current fluctuation, the amount of current fluctuation of the semiconductor chip 10 is predicted during the manufacturing process of the semiconductor chip 10. As the discriminant model, for example, a calculation formula for a multiple regression analysis method that is derived from the above-mentioned relationship data acquired in advance and has BPD density as at least one variable, or any machine learning model that uses the relationship data as training data can be used. As the machine learning model, for example, known methods such as support vector machines, neural networks, random forests, and k-nearest neighbors can be used.

[0052] The discrimination model is stored in the recording medium of an electronic control unit, which is, for example, an electronic control unit on a circuit board (not shown) equipped with various electronic components such as ROM, RAM, and I / O. It is read from the recording medium and executed as needed. In addition, the energization fluctuation amount (e.g., ΔV) is acquired in advance before step S130. ON / Initial V ON The specified driving conditions such as energizing time, voltage, and temperature in the data are set appropriately according to the application, operating environment, and required performance of the SiC semiconductor device. Furthermore, in the above, the data of energizing fluctuations acquired in advance in order to predict the energizing fluctuations is ΔV ON / Initial V ON While I have described an example, it is not limited to this, and other electrical characteristics such as the ΔVf / initial Vf of the built-in diode may also be used.

[0053] In step S140, a determination is made as to whether the current fluctuation amount predicted in step S130 is below a predetermined level. This determination is performed, for example, by a determination program recorded in the electronic control unit where the discrimination model used in step S130 is stored. If the determination in step S140 is positive, that is, if the current fluctuation amount after operation for a predetermined time or longer is small and the reliability of the electrical characteristics is expected to be high, the manufacturing of the SiC semiconductor device using the semiconductor substrate 11 cut out in step S110 is continued. On the other hand, if the determination in step S140 is negative, that is, if the current fluctuation amount after operation for a predetermined time or longer is large and the reliability of the electrical characteristics is expected to be low, the manufacturing of the SiC semiconductor device using the semiconductor substrate 11 cut out in step S110 is stopped. The threshold used for the determination in step S140 is set appropriately according to, for example, the required performance of the SiC semiconductor device to be manufactured. This makes it possible to manufacture SiC semiconductor devices with current fluctuation amounts below a predetermined level while minimizing the manufacturing of SiC semiconductor devices and reducing their manufacturing costs.

[0054] The above describes an example in which the BPD density is measured in step S120 and the amount of current fluctuation is predicted based on at least the BPD density in step S130, but it is not limited to this. In order to further improve the accuracy of predicting the amount of current fluctuation, other parameters can also be measured and the amount of current fluctuation can be predicted using these other parameters in addition to the BPD density.

[0055] For example, by considering the type of BPD in addition to the BPD density, the accuracy of predicting current fluctuations can be further improved. BPDs are classified into a total of 72 types based on the 12 orientations and 6 Burgers vectors b in hexagonal SiC. Specifically, the orientations are the 12 axial directions: [11-20], [-12-10], [-2110], [-1-120], [1-210], [2-1-10], [10-10], [01-10], [1-100], [-1010], [0-110], and [-1100]. There are three Burgers vectors b: (1 / 3)[11-20], (1 / 3)[-2110], and (1 / 3)[1-210], and each of these three further has two types depending on the loop direction. In other words, there are a total of 6 axial directions for Burgers vector b.

[0056] The notations such as [11-20] shown in parentheses above refer to Miller indices. Furthermore, while the hyphen ('-') in these Miller indices should ideally be placed above the desired number, due to limitations on expression imposed by electronic filing, it is placed before the desired number in this specification.

[0057] The orientation of the BPD can be obtained, for example, by observing the surface after etching with KOH. The Burgers vector b can be measured, for example, by non-destructive testing methods such as X-ray topography or PL (photoluminescence) imaging. The type of BPD can be determined, for example, by analyzing images obtained by KOH etching, X-ray topography, or PL imaging using known image recognition techniques. Furthermore, the accuracy of BPD type determination can be further improved by using deep learning models, such as deep learning, with the above images and analysis results obtained by various methods as training data.

[0058] BPDs are classified into those that develop triangular defects D1, those that develop band-shaped defects D2, and those that do not develop defects D, depending on the type described above. In particular, band-shaped defects D2 have a larger area than triangular defects D1, as shown in Figure 7, for example, and therefore have a greater impact on the current fluctuation. For example, for a BPD with a Burgers vector b of (1 / 3)[-2110], band-shaped defects D2 will grow in the directions of [11-20], [-12-10], [2-1-10], [10-10], [01-10], [1-100], and [-1100]. Also, for a BPD with a Burgers vector b of (1 / 3)[1-210], band-shaped defects D2 will grow in the directions of [-2110], [-1-120], [1-210], [1-100], [-1010], [0-110], and [-1100]. In other words, 28 out of 72 types of BPDs grow as band-shaped defects D2. Therefore, the accuracy of the prediction can be further improved by predicting the amount of current fluctuation based on two parameters: BPD density and BPD type.

[0059] For example, in advance, out of the 72 types of BPD, 28 types grow as band-shaped defects D2 and the current fluctuation amount (ΔV ON / Initial V ON Relationship data (such as) is obtained in advance. Furthermore, as a discriminant model, for example, a calculation formula for calculating the current flow fluctuation using multiple regression analysis with BPD density and BPD type as variables, or a machine learning model that predicts the current flow fluctuation using relationship data between BPD density / type and current flow fluctuation as training data is constructed. Then, in step S130, the current flow fluctuation can be predicted based on the BPD density and BPD type of the semiconductor substrate 11 measured in step S120.

[0060] In this case, the BPD density may be calculated using only the 28 types of BPDs in which band-shaped defects D2 grow, but it may also be used if the BPD density is calculated without distinguishing between different types of BPDs. Furthermore, the types of BPDs in which triangular defects D1 grow may be used to predict the current fluctuation.

[0061] Furthermore, the BPD density exhibits a distribution within the plane of the semiconductor substrate 11, as shown, for example, in Figures 8A and 8B. Figures 8A and 8B show the distribution of BPD density within the plane of the semiconductor substrate 11, with areas of lower BPD density shown in a color closer to white and areas of higher BPD density shown in a color closer to black. The BPD density distributions shown in Figures 8A and 8B are from semiconductor substrates 11 cut from different SiC ingots. Thus, when there is a distribution in BPD density, the semiconductor substrate 11 may be in a state where only a portion of the area has a predicted current fluctuation amount below a predetermined threshold. For example, in such a case, a positive determination can be made in step S140, and the manufacturing of the SiC semiconductor device can be continued, picking up semiconductor chips 10 manufactured in the portion where the predicted current fluctuation amount was below the predetermined threshold. Alternatively, if the predicted current fluctuation amount exceeds the predetermined threshold for a certain percentage (not limited to, but for example, 80% or more) of the semiconductor substrate 11, a negative determination can be made in step S140, and the manufacturing of the SiC semiconductor device using that semiconductor substrate 11 can be stopped.

[0062] Furthermore, in step S130, the impurity concentration of the semiconductor substrate 11 may be used as one of the parameters in predicting the current fluctuation. In this case, relationship data between the impurity concentration of the semiconductor substrate 11 and the current fluctuation of the semiconductor chip 10 manufactured using it is obtained in advance, and a discriminant model is constructed using this relationship data. Then, in step S130, the impurity concentration of the semiconductor substrate 11 can be used as one of the parameters in predicting the current fluctuation.

[0063] Next, the manufacturing process of SiC semiconductor devices, following the flowchart shown in Figure 5, will be explained with reference to Figure 9.

[0064] In step S210, an epitaxial layer is grown on the semiconductor substrate 11 where the current fluctuation amount predicted in step S140 is below a threshold or where the region below the threshold accounts for a predetermined proportion or more, thereby forming a buffer layer 12 and a low-concentration layer 13. For the sake of explanation, a semiconductor substrate 11 with an epitaxial layer formed on it will be referred to as a "SiC wafer." A SiC wafer may also be referred to as a SiC epiwafer.

[0065] In the subsequent step S220, the amount of current fluctuation is predicted assuming that the semiconductor chip 10 is manufactured using a SiC wafer. For example, data on the amount of current fluctuation of the semiconductor chip 10 for each parameter of impurity concentration and film thickness in the buffer layer 12, and impurity concentration and film thickness in the low-concentration layer 13 constituting the drift layer 18 is acquired in advance. In addition, the data on the impurity concentration and film thickness in the buffer layer 12 and the low-concentration layer 13 of the SiC wafer formed in step S210 is recorded on a recording medium (not shown), for example. The discriminant model used to predict the amount of current fluctuation in step S220 is configured to use at least one of the impurity concentration and film thickness in the buffer layer 12 and the low-concentration layer 13, in addition to the BPD density, as a parameter for predicting the amount of current fluctuation. The discriminant model used in step S220 is, for example, a multiple regression analysis method or an arbitrary machine learning model, similar to the discriminant model used in step S130.

[0066] In the next step, S230, it is determined whether the current fluctuation predicted in step S220 is below a predetermined level. This determination is performed, for example, by a determination program recorded in the electronic control unit where the discrimination model used in step S220 is stored. If the determination in step S230 is positive, i.e., if the reliability is expected to be high, the process proceeds to step S240, and the manufacturing of the SiC semiconductor device using the SiC wafer formed in step S210 continues. On the other hand, if the determination in step S230 is negative, i.e., if the reliability is expected to be low, the manufacturing of the SiC semiconductor device using the SiC wafer formed in step S210 is stopped. The threshold used for the determination in step S230 is set appropriately according to the required performance of the SiC semiconductor device to be manufactured, similar to the threshold used for the determination in step S140.

[0067] In step S240, for example, a JFET section 14, a first deep layer 15, a current dispersion layer 16, a second deep layer 17, a base layer 19, a source region 20, and a contact region 21 are formed on a SiC wafer. Also in step S240, for example, a trench gate structure, a source electrode 26, a drain electrode 27, and an outer guard ring (not shown) are formed to form multiple semiconductor chips 10 having MOSFETs. The parameters of each layer formed in step S240 are recorded on a recording medium (not shown), for example, and used to predict the amount of current fluctuation in step S260, which will be described later. Examples of parameters for each layer include the impurity concentration and width of the JFET section 14, the pitch between the trench gate structures in the cell section, and the impurity concentration and film thickness of the first deep layer 15 and the second deep layer 17. Other examples of parameters for each layer include the impurity concentration and width of the source region 20 and the contact region 21.

[0068] In step S250, for the multiple semiconductor chips 10 formed in step S240, for example, V f , V ONVarious electrical characteristics, such as IV characteristics, are measured. The initial electrical characteristics of the multiple semiconductor chips 10 obtained in step S250 are recorded on a recording medium (not shown), for example, and used as one of the parameters in predicting the current fluctuation amount in step S260.

[0069] In step S260, for example, a discriminant model is used to predict the current fluctuation for multiple semiconductor chips 10, using BPD density and at least one of the various parameters obtained in steps S240 and S250. Specifically, relationship data between various parameters such as impurity concentration, film thickness and width, and trench gate structure pitch in each layer of the MOSFET formed in step S240 and the actual current fluctuation is acquired in advance. Also, relationship data between the initial values ​​of various electrical characteristics of the semiconductor chip 10 manufactured in step S250 and the actual current fluctuation is acquired in advance. Then, in addition to BPD density, a discriminant model is constructed to predict the current fluctuation using at least one of various parameters such as impurity concentration in each layer on the epiwafer layer and the initial electrical characteristics of the semiconductor chip 10, based on this relationship data. In step S260, the current fluctuation is predicted using such a discriminant model.

[0070] In step S270, the semiconductor chips 10 are classified according to the current fluctuation amount predicted in step S260. This classification process is performed, for example, by a program recorded in the electronic control unit where the discrimination model used in step S260 is stored. Multiple semiconductor chips 10 formed on a single wafer have one of their initial electrical characteristics, as shown in Figure 10, which is the V between the source electrode 26 and the drain electrode 27. ON There is some variation. Note that in the graph shown in Figure 10, the horizontal axis represents the initial V. ON (Unit: V), the vertical axis is the number of chips. Then, as the semiconductor chip 10 is driven, defects D grow inside, V ON The voltage shifts to the high-voltage side. In step S270, for example, the initial V ON and predicted current fluctuation (ΔV ON The resulting V obtained by ) ON "V fluctuation"ON "and the V required for SiC semiconductor devices ON "Requirement V" ON The multiple semiconductor chips 10 are classified according to the difference with ''. For example, requirement V ON V ON The group with the lowest voltage, i.e., the group with the highest performance, is ranked 1, followed by the next group with the lowest voltage (V). ON The groups with low voltages are ranked as rank 2, and so on, with rankings based on the predicted performance after the change. In step S270, the semiconductor chips 10 that did not meet the required performance, i.e., those classified as NG rank, are excluded and the process does not proceed to step S280.

[0071] In step S280, for example, the semiconductor chip 10 classified in step S270 is mounted on a lead frame or the like, and a SiC semiconductor device is manufactured by resin encapsulation or the like. At this time, the semiconductor chip 10 is used in a SiC semiconductor device for an application corresponding to the rank classified in step S270. For example, in step S270, the highest performance rank is applied to automotive applications, but it is not limited to this.

[0072] The above describes the basic manufacturing process of the SiC semiconductor device of this embodiment. In step S270, V is defined as the current fluctuation amount in the classification of the semiconductor chip 10. ON While we have described an example of its use, it is not limited to this, and other electrical characteristics such as current fluctuations may be used as indicators depending on the required performance.

[0073] According to this embodiment, at each stage of cutting the semiconductor substrate 11 from the SiC ingot, growing the epitaxial layer, and forming the trench gate structure MOSFET, the amount of current change in the final manufactured semiconductor chip 10 is predicted based on at least the BPD density. Then, if the predicted amount of current change is below a predetermined level, the manufacturing of the SiC semiconductor device is continued. This allows for the prediction of current change, the reflection of the predicted amount of current change in the manufacturing process to determine whether to continue, and a method for manufacturing a SiC semiconductor device with suppressed current change while keeping manufacturing costs down.

[0074] Furthermore, the following effects can also be obtained in this embodiment.

[0075] (1) By identifying the type of BPD in the semiconductor substrate 11 and predicting the amount of current fluctuation based on the BPD density and BPD type, the prediction of the amount of current fluctuation can be made with higher accuracy.

[0076] (2) In determining the type of BPD, the accuracy of BPD determination is improved by using image recognition with an image obtained by imaging the semiconductor substrate 11.

[0077] (3) The accuracy of predicting the current fluctuation is improved when at least one of the following is used as a parameter: BPD type, impurity concentration in the semiconductor substrate 11, impurity concentration and film thickness in the buffer layer 12, and impurity concentration and film thickness in the drift layer 18, along with the BPD density. Furthermore, the accuracy of predicting the current fluctuation is further improved when at least one of the following is used as a parameter of the discriminant model: impurity concentration and film thickness in the base layer 19, impurity concentration and width in the source region 20 and contact region 21, and the initial electrical characteristics of the semiconductor chip 10. In other words, by predicting the current fluctuation based on two or more parameters, including the BPD density, the current fluctuation can be predicted with higher accuracy than when the prediction is made using only the BPD density.

[0078] (4) In predicting the amount of change in current flow, the accuracy of predicting the amount of change in current flow can be improved by using multiple regression analysis or a discriminant model based on machine learning.

[0079] (5) The manufactured semiconductor chips 10 are classified according to the predicted current fluctuation, and the classified semiconductor chips 10 are used in SiC semiconductor devices for applications corresponding to their classification. This eliminates the need to manufacture SiC semiconductor devices more than necessary, and makes it possible to manufacture SiC semiconductor devices with suppressed current fluctuations while reducing manufacturing costs.

[0080] (Other embodiments) This disclosure is described in accordance with the embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the equivalence range. In addition, various combinations and forms, as well as other combinations and forms including one, more, or less of those elements, fall within the scope and concept of this disclosure.

[0081] In the above embodiment, an example was described in which a semiconductor chip 10 having a JFET section 14 and deep layers 15 and 17 is used as the SiC semiconductor device, but it is not limited to this. For example, as shown in Figure 11, if the semiconductor chip 10 does not have a JFET section 14 or deep layers 15 and 17, the parameters used to predict the current fluctuation amount can be limited to the conditions of the components of the semiconductor chip 10. For example, in addition to the BPD density of the semiconductor substrate 11, at least one of the following can be used as prediction parameters: BPD type, impurity concentration of the semiconductor substrate 11, drift layer 28, base layer 19 and source region 20, and impurity concentration and film thickness or width. Thus, the parameters used to predict the current fluctuation amount may be appropriately changed according to the configuration of the semiconductor chip 10. Note that the drift layer 28 referred to here does not have a JFET section 14.

[0082] The control unit (e.g., an electronic control unit on which a discrimination model is recorded) and the method described herein may be implemented by a dedicated computer provided by configuring a processor and memory programmed to perform one or more functions embodied by a computer program. Alternatively, the control unit and the method described herein may be implemented by a dedicated computer provided by configuring a processor by one or more dedicated hardware logic circuits. Alternatively, the control unit and the method described herein may be implemented by one or more dedicated computers configured by a combination of a processor and memory programmed to perform one or more functions and a processor configured by one or more hardware logic circuits. Furthermore, the computer program may be stored as instructions executed by the computer on a computer-readable non-transitional tangible recording medium.

[0083] It goes without saying that, in each of the above embodiments, the elements constituting the embodiment are not necessarily essential unless explicitly stated to be particularly essential or unless they are clearly considered essential in principle. Furthermore, in each of the above embodiments, when numerical values ​​such as the number, numerical values, quantities, or ranges of the components of the embodiment are mentioned, the embodiment is not limited to those specific numbers unless explicitly stated to be particularly essential or unless it is clearly limited to a specific number in principle. Furthermore, in each of the above embodiments, when the shape, positional relationship, etc., of the components are mentioned, the embodiment is not limited to those shapes, positional relationships, etc., unless explicitly stated or unless it is clearly limited to a specific shape, positional relationship, etc., in principle.

[0084] (Explanation of this disclosure) [First point of view] A method for manufacturing a silicon carbide semiconductor device having a switching element formed on a semiconductor substrate (11) made of silicon carbide, wherein the switching element comprises an internal diode, The BPD density, which is the density of basal plane dislocations in the semiconductor substrate, Assuming that a semiconductor chip (10) having the switching element is manufactured, the initial electrical characteristics of the switching element immediately after the manufacture of the semiconductor chip are taken as the initial value, and the amount of change in the electrical characteristics after driving the switching element for a predetermined time or longer relative to the initial value is taken as the energization fluctuation, and the energization fluctuation is predicted based at least on the BPD density, A method for manufacturing a silicon carbide semiconductor device, comprising determining whether or not to continue manufacturing the silicon carbide semiconductor device using the semiconductor substrate based on the predicted current fluctuation amount. [Second perspective] The method further includes determining the type of BPD, which is the type of basal plane dislocation, A method for manufacturing a silicon carbide semiconductor device according to the first aspect, wherein the prediction of the current fluctuation amount is performed based on the BPD density and the BPD type. [Third perspective] The method for manufacturing a silicon carbide semiconductor device according to the second aspect, wherein the type of BPD is determined by image authentication using an image obtained by imaging the semiconductor substrate. [Fourth perspective] The process further comprises stacking a buffer layer (12) and drift layers (18, 28) on the semiconductor substrate to form a silicon carbide wafer. In predicting the current fluctuation, the current fluctuation is predicted based on at least one of the following: the type of BPD which is the type of basal plane dislocation, the impurity concentration in the semiconductor substrate, the impurity concentration and film thickness in the buffer layer, and the impurity concentration and film thickness in the drift layer, and the BPD density. A method for manufacturing a silicon carbide semiconductor device according to any one of the first to third aspects, which determines whether or not to continue manufacturing the silicon carbide semiconductor device using the silicon carbide wafer. [Fifth perspective] A method for manufacturing a silicon carbide semiconductor device according to any one of the first to fourth aspects, wherein a decision model trained by prior machine learning is used to predict the amount of current fluctuation. [Sixth perspective] A method for manufacturing a silicon carbide semiconductor device according to any one of the first to fourth aspects, wherein, in predicting the current fluctuation, a decision model based on multiple regression analysis having at least the BPD density as one of the variables is used. [Seventh perspective] The process further comprises forming a base layer (19), a source region (20), and a contact region (21) on the silicon carbide wafer to manufacture a plurality of semiconductor chips. A method for manufacturing a silicon carbide semiconductor device according to the fifth or sixth aspect, wherein, in predicting the amount of current fluctuation, the determination model is used to predict the amount of current fluctuation based on at least three of the following: the BPD density and the BPD type, the impurity concentration in the semiconductor substrate, the impurity concentration and film thickness in the buffer layer, the impurity concentration and film thickness in the drift layer, the impurity concentration and width in the source region, the impurity concentration and width in the contact region, and the initial electrical characteristics of the switching element. [Perspective 8] In manufacturing multiple semiconductor chips, a JFET section (14) and deep layers (15, 17) are further formed on the silicon carbide wafer. A method for manufacturing a silicon carbide semiconductor device according to the seventh aspect, wherein, in predicting the amount of current fluctuation, the determination model is used to predict the amount of current fluctuation based on at least three of the following: the BPD density and the BPD type, the impurity concentration in the semiconductor substrate, the impurity concentration and film thickness in the buffer layer, the impurity concentration and film thickness in the drift layer, the impurity concentration and width in the JFET portion, the impurity concentration in the deep layer, the impurity concentration and width in the source region, the impurity concentration and width in the contact region, and the initial electrical characteristics of the switching element. [Perspective 9] A method for manufacturing a silicon carbide semiconductor device according to the seventh or eighth aspect, further comprising classifying a plurality of manufactured semiconductor chips into categories according to the predicted values ​​of the current fluctuations. [Explanation of Symbols]

[0085] 10...Semiconductor chip, 11...Semiconductor substrate, 12...Buffer layer, 14...JFET section 15...1st deep layer, 17...2nd deep layer, 18, 28...drift layer 19...Base layer, 20...Source area, 21...Contact area

Claims

1. A method for manufacturing a silicon carbide semiconductor device having a switching element formed on a semiconductor substrate (11) made of silicon carbide, wherein the switching element comprises an internal diode, The BPD density, which is the density of basal plane dislocations in the semiconductor substrate, Assuming that a semiconductor chip (10) having the switching element is manufactured, the initial electrical characteristics of the switching element immediately after the manufacture of the semiconductor chip are taken as the initial value, and the amount of change in the electrical characteristics after driving the switching element for a predetermined time or longer relative to the initial value is taken as the energization fluctuation, and the energization fluctuation is predicted based at least on the BPD density, A method for manufacturing a silicon carbide semiconductor device, comprising: determining whether or not to continue manufacturing the silicon carbide semiconductor device using the semiconductor substrate based on the predicted current fluctuation amount.

2. The method further includes determining the type of BPD, which is the type of basal plane dislocation. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the prediction of the current fluctuation amount is performed based on the BPD density and the BPD type.

3. The method for manufacturing a silicon carbide semiconductor device according to claim 2, wherein the type of BPD is determined by image authentication using an image obtained by imaging the semiconductor substrate.

4. The process further comprises stacking a buffer layer (12) and drift layers (18, 28) on the semiconductor substrate to form a silicon carbide wafer. In predicting the current fluctuation, the current fluctuation is predicted based on at least one of the following: the type of BPD which is the type of basal plane dislocation, the impurity concentration in the semiconductor substrate, the impurity concentration and film thickness in the buffer layer, and the impurity concentration and film thickness in the drift layer, and the BPD density. The method for manufacturing a silicon carbide semiconductor device according to claim 1, wherein the determination of whether or not to continue manufacturing the silicon carbide semiconductor device is made whether or not to continue manufacturing the silicon carbide semiconductor device using the silicon carbide wafer.

5. The method for manufacturing a silicon carbide semiconductor device according to claim 4, wherein a determination model trained by prior machine learning is used to predict the amount of current fluctuation.

6. The method for manufacturing a silicon carbide semiconductor device according to claim 4, wherein, in predicting the amount of current fluctuation, a determination model based on multiple regression analysis having at least the BPD density as one of the variables is used.

7. The process further comprises forming a base layer (19), a source region (20), and a contact region (21) on the silicon carbide wafer to manufacture a plurality of semiconductor chips, A method for manufacturing a silicon carbide semiconductor device according to claim 5 or 6, wherein, in predicting the amount of current fluctuation, the determination model is used to predict the amount of current fluctuation based on at least three of the following: the BPD density and the BPD type, the impurity concentration in the semiconductor substrate, the impurity concentration and film thickness in the buffer layer, the impurity concentration and film thickness in the drift layer, the impurity concentration and width in the source region, the impurity concentration and width in the contact region, and the initial electrical characteristics of the switching element.

8. In manufacturing multiple semiconductor chips, a JFET section (14) and deep layers (15, 17) are further formed on the silicon carbide wafer. In predicting the current fluctuation, the method for manufacturing a silicon carbide semiconductor device according to claim 7, wherein the determination model is used to predict the current fluctuation based on at least three of the following: the BPD density and the BPD type, the impurity concentration in the semiconductor substrate, the impurity concentration and film thickness in the buffer layer, the impurity concentration and film thickness in the drift layer, the impurity concentration and width in the JFET portion, the impurity concentration in the deep layer, the impurity concentration and width in the source region, the impurity concentration and width in the contact region, and the initial electrical characteristics of the switching element.

9. The method for manufacturing a silicon carbide semiconductor device according to claim 7, further comprising classifying a plurality of manufactured semiconductor chips into categories according to the predicted value of the current fluctuation amount.

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