Semiconductor device and method for manufacturing the same

Abstract

To suppress the occurrence of characteristic variations and characteristic defects.SOLUTION: A manufacturing method of a semiconductor device includes the steps of: preparing a semiconductor substrate 10; arranging an interlayer insulating film 19 formed with a contact hole 20 on one surface 10a of the semiconductor substrate 10; arranging a metal film 250 for first main part on the interlayer insulating film 19; anisotropically etching the metal film 250 for first main part to make a side surface 211a constitute a first main part 211 that has a straight section; arranging a metal film 260 for second main part on the first main part 211; isotropically etching the metal film 212 for second main part so that the side surface 211a of the first main part 211 is exposed and making the side surface 212a constitute the second main part 212 that has a curved section; and using a visual inspection machine 500 to perform a visual inspection on a surface 212b of the second main part 212. In the step of performing the visual inspection, when the surface 211b of the first main part 211 is exposed from the second main part 212, it is determined as defective.SELECTED DRAWING: Figure 4G

Description

Technical Field

[0001] The present invention relates to a semiconductor device in which an electrode connected to a semiconductor substrate is formed on the semiconductor substrate, and a method for manufacturing the same.

Background Art

[0002] Conventionally, a semiconductor device in which an electrode connected to a semiconductor substrate is formed on the semiconductor substrate has been proposed (see, for example, Patent Document 1). Specifically, in this semiconductor device, an IGBT (Insulated Gate Bipolar Transistor) element is formed, and an interlayer insulating film in which a contact hole for exposing the semiconductor substrate is formed is disposed on one surface side of the semiconductor substrate. An upper electrode connected to the semiconductor substrate through the contact hole is disposed on the interlayer insulating film.

[0003] And in this semiconductor device, a wire is connected to the upper electrode so as to be connected to an external member.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] By the way, in the semiconductor device as described above, in order to be applicable to a large current, a configuration in which an external member is disposed on the upper electrode via solder is being studied. In this case, it is preferable that a plating film containing nickel is disposed on the upper electrode in order to improve the bonding property with the solder. Note that the upper electrode is formed by patterning a metal film by etching or the like.

[0006] However, when patterning the upper electrode, etching may create recesses such as cracks and dents in the upper electrode. Furthermore, when a nickel-containing plating film is placed, if recesses are formed in the upper electrode that expose the semiconductor substrate or interlayer insulating film, sodium ions in the plating solution may reach the semiconductor substrate through the recesses, potentially causing performance fluctuations. Additionally, if the plating film is placed so as to contact the semiconductor substrate or interlayer insulating film through the recesses, differences in the coefficient of linear expansion during thermal cycling may cause cracks in the interlayer insulating film or semiconductor substrate, potentially leading to performance defects such as current leakage or poor breakdown voltage.

[0007] In view of the above, the present invention aims to provide a semiconductor device and a method for manufacturing the same that can suppress the occurrence of characteristic fluctuations and characteristic defects. [Means for solving the problem]

[0008] Claim 1, for achieving the above objective, comprises a semiconductor substrate (10), an interlayer insulating film (19) formed on one surface (10a) of the semiconductor substrate and having a contact hole (20) that exposes a predetermined area of ​​the surface, an electrode (21) formed on the interlayer insulating film and electrically connected to the semiconductor substrate through the contact hole, and a nickel-containing plating film (400) disposed on the electrode, wherein the electrode is made of aluminum or an aluminum alloy with elements added to aluminum, and has a first main portion (211) disposed on the semiconductor substrate side and a second main portion (212) disposed on the first main portion, the first main portion having a straight side (211a) along the direction normal to the surface direction of the semiconductor substrate, and the second main portion having a curved side (212a). A method for manufacturing a semiconductor device having a main part, comprising: preparing a semiconductor substrate; arranging an interlayer insulating film with contact holes formed on one surface of the semiconductor substrate; arranging a first main part metal film (250) on the interlayer insulating film; anisotropically etching the first main part metal film to form a first main part having a straight side; arranging a second main part metal film (260) on the first main part; isotropically etching the second main part metal film so that the side of the first main part is exposed to form a second main part having a curved side; and performing an appearance inspection of the surface (212b) of the second main part using an appearance inspection machine (500), wherein the appearance inspection determines that the device is defective if the surface (211b) of the first main part is exposed from the second main part.

[0009] According to this method, since the second main part is formed by isotropic etching, recesses that may be formed during isotropic etching are less likely to reach the first main part. Therefore, when placing the plating film on the electrode, the plating film is less likely to reach the semiconductor substrate or interlayer insulating film through the recesses. As a result, it is possible to suppress the occurrence of characteristic fluctuations and the occurrence of characteristic defects.

[0010] Claim 3 is a semiconductor device comprising: a semiconductor substrate (10); an interlayer insulating film (19) formed on one surface (10a) of the semiconductor substrate and having a contact hole (20) that exposes a predetermined area of ​​the surface; an electrode (21) formed on the interlayer insulating film and electrically connected to the semiconductor substrate through the contact hole; and a nickel-containing plating film (400) disposed on the electrode, wherein the electrode is made of aluminum or an aluminum alloy with added elements, and has a first main portion (211) disposed on the semiconductor substrate side and a second main portion (212) disposed on the first main portion, the first main portion having a straight portion on its side surface (211a) that is in line with the direction normal to the surface direction of the semiconductor substrate, and the second main portion having a curved portion on its side surface (212a). It is arranged such that an interface is formed between it and the first main part. Yes, they are.

[0011] Such semiconductor devices are manufactured by the semiconductor device manufacturing method described above. Therefore, the plating film placed on the electrodes is less likely to reach the semiconductor substrate or interlayer insulating film through the recesses, thereby suppressing the occurrence of characteristic fluctuations and preventing the occurrence of characteristic defects.

[0012] The reference numerals in parentheses attached to each component indicate an example of the correspondence between that component and the specific components described in the embodiments described later. [Brief explanation of the drawing]

[0013] [Figure 1] This is a cross-sectional view of the semiconductor device in the first embodiment. [Figure 2] This is a plan view of a semiconductor device. [Figure 3A] Figure 1 is a cross-sectional view showing the manufacturing process of a semiconductor device. [Figure 3B] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 3A. [Figure 3C] This is a cross-sectional view showing the manufacturing process of a semiconductor device, following Figure 3B. [Figure 3D] This is a cross-sectional view showing the manufacturing process of semiconductor devices, following Figure 3C. [Figure 3E]It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 3D. [Figure 3F] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 3E. [Figure 3G] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 3F. [Figure 3H] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 3G. [Figure 3I] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 3H. [Figure 3J] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 3I. [Figure 3K] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 3J. [Figure 3L] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 3K. [Figure 3M] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 3L. [Figure 3N] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 3M. [Figure 3O] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 3N. [Figure 3P] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 3O. [Figure 3Q] It is a cross-sectional view showing the manufacturing process of a semiconductor device following FIG. 3P. [Figure 4A] It is a cross-sectional view showing the manufacturing process of a semiconductor device corresponding to FIG. 3G. [Figure 4B] It is a cross-sectional view showing the manufacturing process of a semiconductor device corresponding to FIG. 3H. [Figure 4C] It is a cross-sectional view showing the manufacturing process of a semiconductor device corresponding to FIG. 3I. [Figure 4D] It is a cross-sectional view showing the manufacturing process of a semiconductor device corresponding to FIG. 3J. [Figure 4E] It is a cross-sectional view showing the manufacturing process of a semiconductor device corresponding to FIG. 3K. [Figure 4F] It is a cross-sectional view showing the manufacturing process of a semiconductor device corresponding to FIG. 3L. [Figure 4G]A cross-sectional view showing the manufacturing process of a semiconductor device corresponding to Figure 3M. [Figure 4H] A cross-sectional view showing the manufacturing process of a semiconductor device corresponding to Figure 3M. [Figure 5] This is a diagram illustrating the relationship between wet etching and visual inspection. [Modes for carrying out the invention]

[0014] The embodiments of the present invention will be described below with reference to the drawings. In the following embodiments, parts that are the same or equivalent to each other will be denoted by the same reference numerals.

[0015] (First Embodiment) The configuration of the semiconductor device in the first embodiment will be described with reference to Figures 1 and 2. The semiconductor device of this embodiment is preferably used as a device for driving various electronic devices in a vehicle, such as an automobile. In this embodiment, a semiconductor device in which an n-channel type MOSFET (abbreviation for Metal Oxide Semiconductor Field Effect Transistor) is formed will be described as an example. Figure 1 is a cross-sectional view along line II in Figure 2. Figure 2 is a plan view with the protective film 300, which will be described later, omitted.

[0016] The semiconductor device is constructed using a semiconductor substrate 10. The semiconductor substrate 10 is made of a silicon substrate, a silicon carbide substrate, or a gallium nitride substrate, etc. The semiconductor substrate 10 has an n-type drift layer 11, and a p-type base layer 12 with a relatively low impurity concentration is arranged on the drift layer 11. Hereinafter, the side of the semiconductor substrate 10 facing the base layer 12 will be referred to as one side 10a of the semiconductor substrate 10, and the side of the semiconductor substrate 10 facing the drift layer 11 will be referred to as the other side 10b.

[0017] Multiple trenches 13 are formed in the semiconductor substrate 10, penetrating the base layer 12 from one side 10a to reach the drift layer 11, and these trenches 13 separate the base layer 12 into multiple sections. The multiple trenches 13 are arranged so that they form stripes at equal intervals, with one of the plane directions of the semiconductor substrate 10a (i.e., the depth direction in Figure 1) as the longitudinal direction.

[0018] Each trench 13 is filled with an insulating film 14 and an electrode 15. In this embodiment, the insulating film 14 has a configuration that includes a shield insulating film 14a covering the lower portion of the trench 13 and a gate insulating film 14b covering the upper portion of the trench 13.

[0019] Within the trench 13, a shield electrode 15a and a gate electrode 15b, both made of doped poly-Si, are stacked via an insulating film 14. In other words, the semiconductor device of this embodiment has a so-called double-gate configuration. Specifically, the shield electrode 15a is placed on the shield insulating film 14a, and the gate electrode 15b is placed on the gate insulating film 14b. The shield electrode 15a is formed to reduce the gate-drain capacitance and improve the electrical characteristics of the MOSFET by being connected to the upper electrode 21, which will be described later. The gate electrode 15b performs the switching operation of the MOSFET and forms a channel region in the base layer 12 that is in contact with the side surface of the trench 13 when a gate voltage is applied.

[0020] Furthermore, an intermediate insulating film 16 is formed between the shield electrode 15a and the gate electrode 15b, and the intermediate insulating film 16 insulates the shield electrode 15a and the gate electrode 15b. As described above, in this embodiment, the trench gate structure is composed of the trench 13, the shield insulating film 14a, the gate insulating film 14b, the shield electrode 15a, the gate electrode 15b, and the intermediate insulating film 16. This trench gate structure is arranged in a stripe-like layout by arranging multiple trenches side by side.

[0021] The surface layer of the base layer 12 is n + A p-type source region 17 and a p-type contact region 18 are formed. Specifically, the source region 17 is composed of a higher impurity concentration than the drift layer 11, and the contact region 18 is composed of a higher impurity concentration than the base layer 12. In this embodiment, the source region 17 is formed in contact with the side surface of the trench 13, and the contact region 18 is formed on the opposite side of the trench 13, with the source region 17 in between. In this embodiment, the source region 17 constitutes the first impurity region, and the contact region 18 constitutes the second impurity region.

[0022] An interlayer insulating film 19 is formed on one surface 10a of the semiconductor substrate 10. In this embodiment, the interlayer insulating film 19 is constructed by sequentially stacking a first interlayer insulating film 19a, which is made of a TEOS (Tetraethyl orthosilicate) film, and a second interlayer insulating film 19b, which is made of a PSG (Phosphorous Silicate Glass) film, from the side of the one surface 10a of the semiconductor substrate 10.

[0023] Furthermore, contact holes 20 are formed in the interlayer insulating film 19, exposing the source region 17 and the contact region 18. An upper electrode 21 is formed on the interlayer insulating film 19, electrically connected to the source region 17 and the contact region 18 through the contact holes 20. In this embodiment, the source region 17 and the contact region 18 correspond to predetermined regions.

[0024] The configuration of the upper electrode 21 of this embodiment will now be described in detail. The upper electrode 21 of this embodiment has a connection portion 200 which is placed in the contact hole 20 and connected to the semiconductor substrate 10, and a main portion 210 which is placed on the interlayer insulating film 19 and connected to the connection portion 200.

[0025] The connection portion 200 in this embodiment has a barrier metal film 201 arranged along the wall surface of the contact hole 20, and an embedded portion 202 arranged on the barrier metal film 201 to fill the contact hole 20. The barrier metal film 201 is made of titanium or the like, and the embedded portion 202 is made of a tungsten plug or the like.

[0026] The main portion 210 has a first main portion 211 positioned on the semiconductor substrate 10 side on the interlayer insulating film 19, and a second main portion 212 positioned on the first main portion 211. The first main portion 211 and the second main portion 212 are made of aluminum, or an aluminum alloy in which elements are added to aluminum. Examples of aluminum alloys include AlSi, AlCu, and AlSiCu. Furthermore, the first main portion 211 and the second main portion 212 in this embodiment are formed in separate processes. Therefore, a visible interface is formed between the first main portion 211 and the second main portion 212.

[0027] Here, the first main portion 211 is formed by dry etching the metal film 250 for the first main portion after it has been placed, as will be described in detail later. For this reason, the first main portion 211 has a shape in which the side surface 211a is a straight portion that is aligned with the direction normal to the plane direction of the semiconductor substrate 10. The second main portion 212 is formed by wet etching the metal film 260 for the second main portion after it has been placed, as will be described in detail later. For this reason, the second main portion 212 has a shape in which the side surface 212a is a curved portion. Note that the side surface 211a of the first main portion 211 is the surface that connects the surface on the side 10a of the semiconductor substrate 10 and the surface 211b on the side of the second main portion 212. The side surface 212a of the second main part 212 is the surface that connects the surface on the first main part 211 side and the surface 212b on the plating film 400 side, which will be described later.

[0028] Furthermore, the thickness d of the second main part 212 is set to be at least half the minimum detection length L in the detectable range of the visual inspection machine 500, which will be described later. For example, if the minimum detection length in the visual inspection machine 500 is 4 μm, the thickness d of the second main part 212 is set to 2 μm or more. The detectable range in the visual inspection machine 500 may be rectangular or circular, for example.

[0029] Furthermore, gate pads 220 and gate wiring 221 connecting the gate pads 220 and the gate electrode 15b are also formed on the interlayer insulating film 19. Although not specifically shown, the gate electrode 15b is drawn out onto one surface 10a of the semiconductor substrate 10 in a different cross-section than that shown in Figure 1 and connected to the gate wiring 221. The shield electrode 15a is also drawn out onto one surface 10a of the semiconductor substrate 10 in a different cross-section than that shown in Figure 1 and connected to the upper electrode 21.

[0030] Furthermore, a protective film 300 is formed on one surface 10a of the semiconductor substrate 10, covering the interlayer insulating film 19, the upper electrode 21, the gate wiring 221, etc., while having contact holes 301 that expose the inner edge of the upper electrode 21. Although not specifically shown, the protective film 300 is also formed to cover the gate pad 220, and has contact holes that expose the inner edge of the gate pad 220. The protective film 300 is made of, for example, PIQ (an abbreviation for Polyimide-isoindolo quinazolinedione).

[0031] Furthermore, a plating film 400 is provided on the portion of the upper electrode 21 that is exposed from the protective film 300 to improve bonding with solder. In this embodiment, the plating film 400 is constructed by sequentially laminating, for example, a first metal film 401 made of nickel, a second metal film 402 made of palladium, and a third metal film 403 made of gold, from the upper electrode 21 side. In other words, the plating film 400 is composed of nickel. Note that the plating film 400 may be constructed by laminating, for example, a first metal film 401 made of nickel and a third metal film 403 made of gold, and the second metal film 402 made of palladium may not be provided.

[0032] On the drift layer 11 opposite to the base layer 12 (i.e., the other side 10b of the semiconductor substrate 10), n + A drain layer 22 of a certain type is formed. On the opposite side of the drift layer 11, across from the drain layer 22, a lower electrode 23 is formed that is electrically connected to the drain layer 22. In other words, a lower electrode 23 that is electrically connected to the drain layer 22 is formed on the other surface 10b of the semiconductor substrate 10.

[0033] Although the lower electrode 23 is shown in a simplified manner in Figure 1, it is constructed by sequentially stacking nickel film, titanium film, nickel film, and gold film from the other side 10b of the semiconductor substrate 10. In this embodiment, the drain layer 22 constitutes the impurity layer, and the lower electrode 23 corresponds to the second electrode.

[0034] The above describes the configuration of the semiconductor device in this embodiment. In this embodiment, n-type, n + The first conductivity type corresponds to the p-type, and the p-type corresponds to the second conductivity type. In such a semiconductor device, the semiconductor substrate 10 is composed of a drain layer 22, a drift layer 11, a base layer 12, a source region 17, a contact region 18, etc., as described above.

[0035] Next, the manufacturing method of the semiconductor device described above will be explained with reference to Figures 3A to 3Q.

[0036] First, as shown in Figure 3A, a predetermined semiconductor manufacturing process is carried out to prepare a semiconductor substrate 10 in which a base layer 12, source region 17, contact region 18, trench gate structure, etc., are formed. In this case, for example, a semiconductor substrate 10 with a thickness of approximately 725 μm is prepared.

[0037] Next, as shown in Figure 3B, an interlayer insulating film 19 is formed by sequentially arranging a first interlayer insulating film 19a, composed of a TEOS film or the like, and a second interlayer insulating film 19b, composed of a PSG film or the like, on one surface 10a of the semiconductor substrate 10 using a CVD (chemical vapor deposition) method or the like.

[0038] Next, as shown in Figure 3C, a mask (not shown) is placed on the interlayer insulating film 19 and dry etching or the like is performed to form contact holes 20 that expose the source region 17 and the contact region 18 in the interlayer insulating film 19.

[0039] Next, as shown in Figure 3D, a barrier metal film 201 is formed along the wall surface of the contact hole 20 by a vapor deposition method or the like. Then, a filling portion 202 is formed by a CVD method to fill the contact hole 20. After that, the metal films forming the barrier metal film 201 and the filling portion 202 formed on one surface 10a of the semiconductor substrate 10 are removed by a CMP (Chemical Mechanical Polishing) method or the like.

[0040] Next, as shown in Figure 3E, the first main metal film 250 is placed on one surface 10a of the semiconductor substrate 10 by CVD or the like. The first main metal film 250 is for the purpose of forming the first main part 211 and is made of aluminum or an aluminum alloy in which elements have been added to aluminum.

[0041] Then, as shown in Figure 3F, a mask (not shown) is placed, and the first main part metal film 250 is patterned to form the first main part 211 and gate wiring 221. Since the parts that demarcate the first main part 211 and gate wiring 221 require microfabrication, the first main part metal film 250 is patterned by dry etching to form these parts. As a result, the side surface 211a of the first main part 211 has a shape with a linear portion aligned with the direction normal to the plane direction of the semiconductor substrate 10. In this embodiment, dry etching corresponds to anisotropic etching.

[0042] Next, as shown in Figure 3G, the metal film 260 for the second main part is positioned to cover the first main part 211 and the gate wiring 221. The metal film 260 for the second main part is for the purpose of forming the second main part 212 and is made of aluminum or an aluminum alloy with added elements. Furthermore, as described above, the thickness d of the portion of the metal film 260 for the second main part located on the first main part 211 is set to be at least half of the minimum detection length L of the visual inspection machine 500, which will be described later.

[0043] Then, as shown in Figure 3H, the resist 270 is placed on the second main metal film 260. Next, as shown in Figure 3I, the resist 270 is exposed using the photomask 280, and as shown in Figure 3J, the resist 270 is developed and patterned into a predetermined shape. The predetermined shape here is the shape in which the side surface 211a of the first main part 211 is exposed when the second main metal film 260 is patterned by wet etching, as will be described later.

[0044] Next, as shown in Figure 3K, the resist 270 is used as a mask, and the metal film 260 for the second main part is patterned by wet etching so that the side surface 211a of the first main part 211 is exposed, thereby forming the second main part 212. In other words, the metal film 260 for the second main part is patterned by wet etching so that it remains only on the first main part 211, thereby forming the second main part 212. This results in a main part 210 having the first main part 211 and the second main part 212. In this embodiment, the metal film 260 for the second main part formed on the gate wiring 221 is also removed at the same time, but the metal film 260 for the second main part may remain on the gate wiring 221. That is, the gate wiring 221 may be constructed by laminating the metal film 250 for the first main part and the metal film 260 for the second main part. However, even with this configuration, the first main metal film 250 and the second main metal film 260 are patterned so that the upper electrode 21 and the gate wiring 221 are insulated from each other. In this embodiment, wet etching corresponds to isotropic etching.

[0045] Subsequently, as shown in Figure 3L, the resist 270 is removed by ashing or other processes. Then, as shown in Figure 3M, the surface 212b of the second main part 212 is observed using a visual inspection machine 500 to determine whether it is good or bad. The visual inspection will be described in detail later.

[0046] Next, as shown in Figure 3N, a protective film 300 is formed, and a contact hole 301 is formed that exposes the inner edge of the upper electrode 21. In a different cross-section from Figure 3N, a contact hole that exposes the gate pad 220 is also formed.

[0047] Next, as shown in Figure 3O, the semiconductor substrate 10 is polished from the other side 10b to the desired thickness. For example, the semiconductor substrate 10 is thinned to about 70 μm. Subsequently, as shown in Figure 3P, a drain layer 22 is formed by ion implantation or the like from the other side 10b of the semiconductor substrate 10. After that, as shown in Figure 3Q, a lower electrode 23 is formed on the other side 10b of the semiconductor substrate 10 by sputtering or the like.

[0048] Although not shown in the diagrams, the semiconductor device shown in Figure 1 is manufactured by placing the plating film 400 on the upper electrode 21. Next, the visual inspection will be explained in detail.

[0049] First, when forming the second main metal film 260, foreign matter 290 may adhere to the second main metal film 260, as shown in Figure 4A. In this case, as shown in Figure 4B, the resist 270 may not be properly positioned due to the foreign matter 290. Then, as shown in Figure 4C, exposure is performed using the photomask 280 in this state, and as shown in Figure 4D, when the resist 270 is developed, the resist 270 will not be positioned in the areas where the foreign matter 290 was attached. In other words, an unexpectedly exposed region A is formed in the second main metal film 260, where an unexpected portion is exposed from the resist 270.

[0050] Then, as shown in Figure 4E, when the second main metal film 260 is wet-etched in this state, the unexpectedly exposed area A is also wet-etched, and a curved recess 213 is formed in the second main part 212. Since the recess 213 is formed by wet etching, its planar shape is circular, and its cross-section along the thickness direction of the semiconductor substrate 10 is semicircular.

[0051] Subsequently, as shown in Figure 4F, the resist 270 is removed, and as shown in Figures 4G and 4H, a visual inspection is performed using the visual inspection machine 500, resulting in the following: The recess 213 may have a diameter a that is longer than the minimum detection length L of the visual inspection machine 500, as shown in Figure 4G, or a diameter a that is shorter than the minimum detection length L of the visual inspection machine 500, as shown in Figure 4H.

[0052] As shown in Figure 4G, if the diameter a of the recess 213 is longer than the minimum detection length L, the visual inspection machine 500 can detect the presence of the recess 213. Therefore, in the pass / fail judgment, it is determined to be defective.

[0053] On the other hand, as shown in Figure 4H, if the diameter a of the recess 213 is shorter than the minimum detection length L, the visual inspection machine 500 cannot detect the presence of the recess 213, and therefore, in the quality judgment, it is judged as good. However, in this embodiment, the thickness d of the second main portion 212 is set to be more than half of the minimum detection length L. Therefore, when the second main portion 212 is formed by wet etching, the recess 213 with a diameter a shorter than the minimum detection length L will not reach a depth that exposes the first main portion 211. Consequently, even if a plating film 400 is placed on the second main portion 212, it is possible to suppress the plating film 400 from reaching the first main portion 211, the interlayer insulating film 19, and the semiconductor substrate 10 through the recess 213.

[0054] Furthermore, when the first main metal film 250 is placed, there is a possibility that foreign matter may adhere to the first main metal film 250, similar to when the second main metal film 260 is placed. In this case, when the first main metal film 250 is patterned, the foreign matter may form a recess in the first main part 211 similar to the recess 213 described above. However, this recess will be filled in by the second main metal film 260 which is placed afterward. Therefore, even if a recess is formed in the first main metal film 250, no problems will occur with the plating film 400 due to this recess.

[0055] Furthermore, it is conceivable to pattern the second main metal film 260 by dry etching, but with dry etching, the aspect ratio of the recess 213 tends to become large, and even if the diameter a of the recess 213 is shorter than the minimum detection length L, the first main part 211 may be exposed from the recess 213. Therefore, in this embodiment, the second main metal film 260 is patterned using wet etching, which is isotropic etching.

[0056] The above describes the method for manufacturing a semiconductor device according to this embodiment. The relationship between wet etching and visual inspection in the above manufacturing method is summarized in Figure 5.

[0057] In other words, as shown in Figure 5, if the second main portion 212 is formed by wet etching and the diameter a of the recess 213 is less than the minimum detection length L, it is undetectable by the visual inspection machine 500 and is judged as good. If the diameter a of the recess 213 is greater than or equal to the minimum detection length L, it is detectable by the visual inspection machine 500 and is judged as defective.

[0058] Furthermore, the fact that a good result was obtained means that the diameter a of the recess 213 is shorter than the minimum detection length d of the visual inspection machine 500, so the surface 211b of the first main part 211 is not exposed by the recess 213. Therefore, even if the plating film 400 is placed thereafter, sodium ions do not reach the first main part 211, nor do they reach the semiconductor substrate 10. Consequently, sodium ions do not reach the insulating film 14, and the occurrence of characteristic changes due to sodium ions can be suppressed, resulting in no influence from the recess 213. In addition, since the plating film 400 is not placed in contact with the interlayer insulating film 19 or the semiconductor substrate 10, stress due to the thermal cycle is not applied to the interlayer insulating film 19, the semiconductor substrate 10, the gate insulating film 14b, etc. Consequently, cracks do not occur, and the occurrence of characteristic defects such as leakage defects and breakdown voltage defects can be suppressed, resulting in no influence from the recess 213.

[0059] According to the embodiment described above, the main portion 210 is constructed by stacking a first main portion 211 and a second main portion 212. The first main portion 211 has a straight side surface 211a, and the second main portion 212 has a curved side surface 212a. In other words, the first main portion 211 is formed by dry etching, and the second main portion 212 is formed by wet etching. For this reason, firstly, since the first main portion 211 is formed by dry etching, it is easier to accommodate miniaturization. Also, since the second main portion 212 is formed by wet etching, the recesses 213 that may be formed during wet etching are less likely to reach the first main portion 211, and the plating film 400 is less likely to reach the semiconductor substrate 10 or the interlayer insulating film 19 through the recesses 213. For this reason, it is possible to suppress the occurrence of characteristic fluctuations and the occurrence of characteristic defects.

[0060] (1) In this embodiment, the thickness d of the second main portion 212 is greater than half of the minimum detection length L. Therefore, even if a recess 213 is formed during wet etching and this recess 213 cannot be detected by visual inspection, the first main portion 211 can be prevented from being exposed by the recess 213. Thus, the plating film 400 can be further prevented from reaching the semiconductor substrate 10 or the interlayer insulating film 19 through the recess 213.

[0061] (Other embodiments) This disclosure is described in accordance with embodiments, but it is understood that this disclosure is not limited to such embodiments or structures. This disclosure also includes various modifications and variations within the scope of equivalents. In addition, various combinations and forms, as well as other combinations and forms that include only one, more, or fewer of those elements, fall within the scope and idea of ​​this disclosure.

[0062] For example, in the first embodiment described above, an n-channel type trench gate MOSFET with a first conductivity type of n-type and a second conductivity type of p-type was used as an example. However, the semiconductor device may be configured by forming a p-channel type trench gate MOSFET, for example, in which the conductivity types of each component are reversed compared to the n-channel type. Furthermore, the semiconductor device may be configured by forming IGBTs with a similar structure in addition to MOSFETs. In the case of IGBTs, the n + The drain layer 22 of type p + Aside from changing the collector layer to a specific type, it is the same as the MOSFET described in the first embodiment above. Furthermore, the semiconductor device may have a configuration in which diodes and the like are formed.

[0063] Furthermore, although the first embodiment described above describes an example in which the trench gate structure has a double gate, the trench gate structure may also be configured without a shield electrode 15a or the like.

[0064] Furthermore, although the first embodiment described above describes an example in which the second main portion 212 is directly arranged on the first main portion 211, another layer may be arranged between the first main portion 211 and the second main portion 212. [Explanation of Symbols]

[0065] 10 Semiconductor substrates 10a one side 21 Upper electrode 211 First Main Section 211a side 212 Second Main Section 212a side 212b surface 250 Metal film for the first main part 260 Metal film for the second main part 500 Visual Inspection Machines

Claims

1. A semiconductor substrate (10) and An interlayer insulating film (19) is formed on one surface (10a) of the semiconductor substrate, and a contact hole (20) is formed therein that exposes a predetermined area of ​​the one surface, An electrode (21) formed on the interlayer insulating film and electrically connected to the semiconductor substrate through the contact hole, The electrode comprises a nickel-plated film (400) disposed on the electrode, The electrode is made of aluminum or an aluminum alloy to which elements have been added, and has a first main portion (211) disposed on the semiconductor substrate side and a second main portion (212) disposed on the first main portion. The first main portion has a side surface (211a) that is a straight portion aligned with the direction normal to the plane direction of the semiconductor substrate, The second main part is a method for manufacturing a semiconductor device having a curved portion on its side surface (212a), To prepare the aforementioned semiconductor substrate, The interlayer insulating film having the contact holes is placed on one surface of the semiconductor substrate, The first main metal film (250) is placed on the interlayer insulating film, The first main part metal film is anisotropically etched to form the first main part having the linear portion on its side, The metal film (260) for the second main part is placed on the first main part, The metal film for the second main part is isotropically etched so that the side surface of the first main part is exposed, thereby forming the second main part having the curved portion on its side surface. The visual inspection of the surface (212b) of the second main part is performed using a visual inspection machine (500), and A method for manufacturing a semiconductor device, wherein the visual inspection determines that the device is defective if the surface (211b) of the first main part is exposed from the second main part.

2. In configuring the second main part, the thickness (d) of the second main part is made thicker than half the minimum detection length (L) of the visual inspection machine. The method for manufacturing a semiconductor device according to claim 1, wherein the visual inspection is performed such that the diameter (a) of the recess (213) formed in the second main part is greater than or equal to the minimum detection length, and the device is deemed defective.

3. A semiconductor device, A semiconductor substrate (10) and An interlayer insulating film (19) is formed on one surface (10a) of the semiconductor substrate, and a contact hole (20) is formed therein that exposes a predetermined area of ​​the one surface, An electrode (21) formed on the interlayer insulating film and electrically connected to the semiconductor substrate through the contact hole, The electrode comprises a nickel-plated film (400) disposed on the electrode, The electrode is made of aluminum or an aluminum alloy to which elements have been added, and has a first main portion (211) disposed on the semiconductor substrate side and a second main portion (212) disposed on the first main portion. The first main portion has a side surface (211a) that is a straight portion aligned with the direction normal to the plane direction of the semiconductor substrate, The second main part has a curved side surface (212a) and is arranged such that an interface is formed between it and the first main part.