Diagnostic device, diagnostic method, and program

Abstract

It contributes to diagnosing failures in multiple interrupt systems, which consist of interrupt devices and interrupt lines, while maintaining the availability of the computer's processor. [Solution] According to the present disclosure, a diagnostic device is provided comprising one or more processors, wherein the one or more processors generate waveform information showing the waveform of a voltage occurring in an interrupt signal line, determine which of a plurality of events the voltage occurring in the interrupt signal line represents based on the waveform information, and diagnose whether a fault has occurred in the interrupt signal line or any component related to the interrupt signal line based on the number of times each of the determined plurality of events has been determined.

Description

[Technical Field]

[0001] This disclosure relates to a diagnostic device, a diagnostic method, and a program. [Background technology]

[0002] In computers, interrupts are used to temporarily suspend an ongoing process and allow another process to run. Interrupt handling is implemented using interrupt control circuits built into the processor, as well as external interrupt control devices. These interrupt control circuits receive asserted interrupt signals from devices that generate interrupt signals (interrupt devices), such as the processor's built-in timer circuit and input / output devices like hard disks and keyboards, and notify the processor of the occurrence of an interrupt event.

[0003] However, interrupt control circuits and similar systems may experience abnormal operation due to interrupt signals affected by noise and crosstalk superimposed on the interrupt signal line. Furthermore, interrupt control circuits and similar systems may experience spurious interrupts (signals at frequencies not intended in the design) whose cause cannot be identified. In addition, interrupt control circuits and similar systems may experience abnormal interrupts due to the timing of processing by the firmware (FW) that operates the computer's components, even when there are no abnormalities in the interrupt control circuit itself or the interrupt signal.

[0004] When spurious interrupts occur, the processing load on the processor increases, which can negatively affect the overall operation of the computer. To prevent such adverse effects, a method is known to isolate faulty signal lines and other components from the bus, signal lines, and peripheral circuits connected to the processor so as not to affect the processor's processing (Patent Document 1). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Patent No. 6266239 [Overview of the project] [Problems that the invention aims to solve]

[0006] Furthermore, each disclosure in the above prior art documents is incorporated into this document by reference. The following analysis was performed by the inventors.

[0007] The method disclosed in Patent Document 1 includes periodically generating a test interrupt request, executing an interrupt processing routine performed by the processor in response to the occurrence of the interrupt request, and checking the state of an interrupt request flag, such as an interrupt control circuit, while the interrupt routine is being executed. In this method, when the interrupt processing routine is executed and the same interrupt request flag is asserted two or more times in a row, it is determined that there is a high probability that a fault has occurred in the interrupt signal system through which the interrupt signal is generated and transmitted.

[0008] However, this method periodically sends test interrupt requests to all interrupt signal systems, interrupting the processor's ability to accept interrupt signals. Consequently, if the amount of processing performed in response to these test interrupt requests becomes excessive, it can reduce processor availability and degrade the overall performance of the computer. Furthermore, this method does not distinguish between interrupt signal systems and detects all periodic failures. In other words, this method detects failures without distinguishing between interrupt signal systems that experience relatively frequent failures due to individual differences in interrupt devices and the wiring length of interrupt signal lines, and those that experience failures very rarely.

[0009] Therefore, this method requires a significant amount of processing power periodically to detect frequent interrupt signal system failures, and also requires a certain amount of processing power to detect very rare interrupt signal system failures. In other words, this method unnecessarily increases the processor load and unnecessarily reduces its availability because it periodically requires unnecessary processor processing for fault detection even when no abnormalities have occurred in the interrupt signal.

[0010] The purpose of this disclosure is, in view of the above issues, to contribute to the diagnosis of failures in multiple interrupt systems, which consist of interrupt devices and interrupt lines, while maintaining the availability of the computer processor. [Means for solving the problem]

[0011] In a first aspect of this disclosure, a diagnostic device comprising one or more processors is provided. The one or more processors are configured to generate waveform information indicating the waveform of a voltage occurring on an interrupt signal line, to determine which of a plurality of events the voltage occurring on the interrupt signal line represents based on the waveform information, and to diagnose whether a fault has occurred in the interrupt signal line or any component related to the interrupt signal line based on the number of times each of the determined plurality of events has been determined.

[0012] A second aspect of this disclosure provides a diagnostic method performed by a diagnostic device, which includes steps of: generating waveform information showing the waveform of a voltage occurring on an interrupt signal line; determining, based on the waveform information, which of a plurality of events the voltage occurring on the interrupt signal line represents; and diagnosing, based on the number of times each of the determined plurality of events has been determined, which of the interrupt signal line and / or components related to the interrupt signal line has a fault.

[0013] In a third aspect of the present disclosure, a program executed in a diagnostic device including one or more processors is provided. The program causes the one or more processors to perform a process of generating waveform information indicating a waveform of a voltage occurring on an interrupt signal line, a process of determining, based on the waveform information, which of a plurality of events the voltage occurring on the interrupt signal line indicates, and a process of diagnosing which of the interrupt signal line and components related to the interrupt signal line has a failure based on the number of times each of the plurality of determined events has been determined. Note that this program can be recorded on a computer-readable storage medium. The storage medium can be non-transitory, such as a semiconductor memory, a hard disk, a magnetic recording medium, an optical recording medium, etc. The present disclosure can be embodied as a computer program product.

Effects of the Invention

[0014] According to each aspect of the present disclosure, it is possible to contribute to the diagnosis of failures in a plurality of interrupt systems composed of an interrupt device and an interrupt line while maintaining the availability of a computer processor.

Brief Description of the Drawings

[0015] [Figure 1] FIG. 1 is a diagram illustrating an example of a correspondence relationship between a diagnostic device of a first aspect and a computer according to an embodiment. [Figure 2] FIG. 2 is a diagram illustrating a configuration of a computer according to the present disclosure. [Figure 3A] FIG. 3A is a diagram illustrating an example of conditions for assertion and negation of an interrupt signal. [Figure 3B] FIG. 3B is a diagram illustrating an example of a waveform of an interrupt signal measured by an interrupt signal detection circuit of the diagnostic device shown in FIG. 2. [Figure 4A] FIG. 4A is a flowchart illustrating an example of overall processing of a computer. [Figure 4B]Figure 4B is a flowchart showing an example of the processing of a detection and measurement circuit that detects the asserted and negated states of voltages occurring on any of the interrupt signal lines shown in Figure 4A. [Figure 4C] Figure 4C is a flowchart illustrating an example of the processing of an interrupt signal storage circuit and a fault diagnosis circuit that determine the cause of a voltage occurring on any of the interrupt signal lines shown in Figure 4A. [Figure 4D] Figure 4D is a flowchart showing an example of the processing of a fault diagnosis circuit that diagnoses the cause of the fault shown in Figure 4A. [Modes for carrying out the invention]

[0016] Embodiments of this disclosure will be described below with reference to the drawings. However, this disclosure is not limited to the embodiments described below. In each drawing, identical or corresponding elements are appropriately denoted by the same reference numeral, and identical or corresponding processes and communications are appropriately denoted by the same reference numeral. In addition, subscripts may be added to the reference numerals and information symbols of multiple possible components, but subscripts may be omitted when one of the multiple possible components is shown without being specified. Furthermore, it should be noted that the drawings are schematic and the quantities of each element may differ from reality. In addition, the connecting lines between blocks in the drawings and other documents referred to in the following description include both bidirectional and unidirectional lines. Unidirectional arrows schematically indicate the flow of the main signals and data (information) and do not exclude bidirectionality. Also, in the following description, information and data are not strictly distinguished. In comparisons of voltage, etc., there is no substantial difference between "less than" and "less than or equal to," and there is no substantial difference between "greater than or equal to" and "higher than." Furthermore, when voltage can take on positive or negative values, there is no substantial difference between "greater than or equal to," "higher than," "less than," and "less than or equal to" for positive voltages and "greater than or equal to," "higher than," "less than," and "less than or equal to" for the absolute value of negative voltages. Similarly, there is no substantial difference between "greater than or equal to," "higher than," "less than," and "less than or equal to" for negative voltages and "greater than or equal to," "higher than," "less than," and "less than or equal to" for the absolute value of positive voltages.

[0017] Figure 1 illustrates an example of the correspondence between the first viewpoint diagnostic device 2 and the computer 1 according to the embodiment. The correspondence between the first viewpoint diagnostic device 2 and the computer 1, which will be described later with reference to Figure 2 and subsequent figures, is as shown in Figure 1. In other words, the first viewpoint diagnostic device 2 is encompassed within the computer 1 shown in Figure 1.

[0018] Figure 2 is a diagram illustrating one configuration of computer 1 according to this disclosure. For the sake of simplicity, Figure 2 shows a specific example of the configuration in which the diagnostic device 2 of computer 1 processes one of the voltages of interrupt signal lines 118-1 to 118-m and 122-1 to 122-n. However, the diagnostic device 2 can process two or more voltages of interrupt signal lines 118 and 122 by adding appropriate components or increasing the processing speed.

[0019] As shown in Figure 2, the computer 1 comprises a processor 100, main memory 102, auxiliary memory 104, interrupt control device 106, system clock generator 108, input / output interface (input / output IF (InterFace)) device 110, internal interrupt devices 112-1 to 112-m (where m is an integer greater than or equal to 1), interrupt interface devices 114-1 to 114-n (where n is an integer greater than or equal to 1), and a diagnostic device 2. The diagnostic device 2 comprises a detection / measurement circuit 20, an interrupt signal storage circuit 22, a fault diagnosis circuit 24, a PLL circuit 220, a selector circuit (SEL (SELector)) 222, and an interrupt flag circuit 224. The detection / measurement circuit 20 comprises an interrupt signal detection circuit 200 and a voltage value measurement circuit 202.

[0020] Each of the interrupt interface devices 114-1 to 114-n is connected to each of the external interrupt devices 116-1 to 116-n via each of the interrupt signal lines 120-1 to 120-n. Each of the internal interrupt devices 112-1 to 112-m is connected to the diagnostic device 2 via each of the interrupt signal lines 118-1 to 118-m. Each of the external interrupt devices 116-1 to 116-n is connected to the diagnostic device 2 via each of the interrupt signal lines 122-1 to 122-n. Therefore, the diagnostic device 2 is connected to a total of (m+n) interrupt signal lines: m interrupt signal lines 118-1 to 118-m from the interrupt control device 106 and n interrupt signal lines 122-1 to 122-n from the external interrupt devices 116-1 to 116-n.

[0021] In other words, computer 1 is a general-purpose computer such as a typical PC, to which an external interrupt device 116 is connected and which is capable of interrupt processing, or it is a component of an embedded computer that is incorporated into a device. On the other hand, computer 1 does not need to have some of the components shown in Figure 2 if it is not necessary, or computer 1 may have additional components as needed in addition to the components shown in Figure 2.

[0022] Furthermore, the components of computer 1 are connected to each other via buses and signal lines (bus / signal lines) 12, enabling mutual input and output of data and information.Hereafter, when multiple components such as "internal interrupt devices 112-1 to 112-m" are shown without specifying one or more of them, the subscripts ("-1", "-m", etc.) will be omitted as appropriate, and they will simply be written as "internal interrupt device 112", etc.In addition, each component of computer 1, except for those that, by their nature, can only be configured by hardware, can be implemented in software by dedicated hardware, a combination of dedicated hardware and software (FW), or by the execution of a program by a processor.

[0023] Furthermore, when the functions of the entire computer 1 or each component of computer 1 are realized by the execution of one or more programs, such programs are stored in a non-volatile memory element of the auxiliary storage device 104 of computer 1 and executed by the processor 100. Such one or more programs may also be provided as a program product recorded on a non-transitory computer-readable storage medium. Such a program product may also include information and data essential for the execution of one or more programs.

[0024] Computer 1 runs an operating system (OS; not shown) that mediates between the hardware of Computer 1 and the programs executed by Computer 1, such as Windows®, UNIX®, or TRON (The Real-time Operating system Nucleus). Programs that perform various functions of Computer 1 run on the OS. Furthermore, Computer 1 performs interrupt processing based on interrupt signals generated by either the internal interrupt device 112 or the external interrupt device 116. In addition, when an abnormal interrupt signal is generated due to a malfunction or other reason, Computer 1 diagnoses the cause of the malfunction or other reason.

[0025] The processor 100 includes one or more CPUs (Central Processing Units), or at least two combinations of one or more DSPs (Digital Signal Processors), one or more CPUs, and one or more GPUs (Graphics Processing Units). A Micro Processing Unit (MPU) may be used instead of a CPU. The processor 100 executes instructions contained in one or more programs stored in at least one of the main memory 102 and the auxiliary memory 104. The main memory 102 includes, for example, one or more RAMs (Random Access Memory) and one or more ROMs (Read Only Memory), and temporarily stores one or more programs executed by the computer 1, as well as information and data required for program execution.

[0026] The auxiliary storage device 104 includes, for example, a non-volatile computer-readable storage device such as an HDD (Hard Disk Drive), an SSD (Solid State Drive), and flash memory, or one or more of these. The auxiliary storage device 104 stores the program executed by computer 1 and the information and data required for its execution for the medium to long term. In addition, the near-end server location information and the data and information required for various processes are stored in at least one of the main memory device 102 and the auxiliary storage device 104 in advance, before computer 1 starts up.

[0027] The interrupt control device 106 receives interrupt signals and information used for interrupt processing output by the internal interrupt device 112 via the bus / signal line 12. The interrupt control device 106 also receives interrupt signals and information used for interrupt processing output by the external interrupt device 116 via the bus / signal line 12 and the input / output interface device 110. Furthermore, the interrupt control device 106 reads information indicating the interrupt signal event (interrupt cause) corresponding to the asserted interrupt signal from the internal interrupt device 112 and the external interrupt device 116, outputs it to the processor 100, and notifies the processor 100 of the interrupt signal event. In addition, the interrupt control device 106 generates interrupt device information indicating whether the internal interrupt device 112 or the external interrupt device 116 output the interrupt signal, and outputs it to the diagnostic device 2 via the bus / signal line 12. The system clock generator 108 generates a system clock signal that is used to synchronize the timing of processing in each component of the computer 1, to adjust the timing of processing, and to measure the duration of time.

[0028] An output device such as a display is connected to the input / output interface device 110, and the input / output interface device 110 displays the results of processing performed by computer 1 to the output device. In addition, an input device such as a keyboard is connected to the input / output interface device 110, and the input / output interface device 110 accepts user operations on the input device.

[0029] The internal interrupt devices 112 are storage devices such as HDDs (Hard Disk Drives) and SSDs (Solid State Drives) built into the computer 1, as well as communication devices compliant with the Wi-Fi (registered trademark) standard. In addition to realizing the functions of a storage device and a communication device, each of the internal interrupt devices 112 outputs an asserted interrupt signal to the interrupt control device 106 via the bus signal line 12 when interrupt processing is required. Furthermore, when interrupt processing is required, each of the internal interrupt devices 112 asserts an interrupt signal used to diagnose the cause of an abnormal interrupt signal and outputs it to the diagnostic device 2 via the m interrupt signal lines 118.

[0030] Each of the external interrupt devices 116 is a storage device and / or communication device that is externally connected to the computer 1 via a USB (Universal Serial Bus) connector (not shown) or the like. In addition to realizing the functions of a storage device and / or communication device, each of the external interrupt devices 116 asserts an interrupt signal when interrupt processing is required and outputs it to the processor 100 via the interrupt interface device 114 and the interrupt signal line 120, respectively. Furthermore, when interrupt processing is required, each of the external interrupt devices 116 asserts an interrupt signal used to diagnose the cause of an abnormal interrupt signal and outputs it to the diagnostic device 2 via the interrupt signal line 122, respectively.

[0031] In the diagnostic device 2, the voltage measurement circuit 202 measures all voltages on interrupt signal lines 118 and 122 when neither interrupt signal line 118 nor 122 is selected by the selector circuit 222. The voltage measurement circuit 202 determines whether the voltage on either interrupt signal line 118 or 122 is 10% or more of a predetermined peak voltage (first value) that is set in a negated state. The peak voltage is, for example, the positive power supply voltage (Vcc; 5V) of a semiconductor element included as a component of computer 1. When the voltage on either interrupt signal line 118 or 122 becomes 10% or more of the peak voltage, the voltage measurement circuit 202 notifies the interrupt signal detection circuit 200 of this fact.

[0032] Furthermore, the voltage measurement circuit 202, in accordance with the control of the interrupt signal detection circuit 200, measures the voltage value of either the internal interrupt device 112 or the external interrupt device 116 selected by the selector circuit 222 over time using the measurement clock signal input from the PLL circuit 220. The voltage measurement circuit 202 generates waveform information showing the voltage waveform of the interrupt signal obtained from such measurements and outputs it to the voltage measurement circuit 202 and the interrupt signal storage circuit 22. The voltage measurement circuit 202 also controls the selector circuit 222 to select either the interrupt signal line 118 or 122 whose voltage is 10% or more of the peak voltage, and outputs the voltage of the selected interrupt signal line 118 or 122 to the interrupt signal detection circuit 200, etc.

[0033] Furthermore, the interrupt signal detection circuit 200 detects whether the voltage on either the interrupt signal line 118 or 122 is asserted or negated, and notifies the voltage value measurement circuit 202 of the detected state. In addition, the interrupt signal detection circuit 200 sets the value of a bit in the interrupt flag circuit 224 corresponding to either the interrupt signal line 118 or 122 to 1, and stores that an asserted interrupt signal has been input from either the interrupt signal line 118 or 122. Note that the value of the bit set to 1 in the interrupt flag circuit 224 is monitored for t from the time the interrupt signal is asserted. test If the interrupt signal remains asserted after this period has elapsed, the processor 100 resets it to a value of 0 via the bus signal line 12.

[0034] Figure 3A illustrates an example of the conditions for asserting and negating an interrupt signal. Figure 3B illustrates an example of the waveform of an interrupt signal measured by the interrupt signal detection circuit 200 of the diagnostic device 2 shown in Figure 2. For example, the interrupt signal detection circuit 200 detects, using an edge-sense method, that the interrupt signal is in an asserted or negated state when the voltage of either the interrupt signal line 118 or 122, measured by the voltage value measurement circuit 202, changes as shown in Figure 3A.

[0035] According to the edge-sense method, for example, if the voltage measurement circuit 202 measures that the voltage on either interrupt signal line 118 or 122 has changed from less than 10% of the peak voltage to 90% or more of the peak voltage (second value) predetermined for the asserted state, the interrupt signal detection circuit 200 can detect that the interrupt signal input via interrupt signal lines 118 or 122 has entered an asserted state. On the other hand, for example, if the voltage measurement circuit 202 measures that the voltage on either interrupt signal line 118 or 122 has changed from 90% or more of the peak voltage value for the asserted state to less than 10%, the interrupt signal detection circuit 200 can detect that the interrupt signal input via interrupt signal lines 118 or 122 has entered a negated state.

[0036] As illustrated in Figure 3B, for example, at time t1, due to the generation of noise or other factors, the voltage of either interrupt signal line 118 or 122 selected by the selector circuit 222 may satisfy the conditions for changing from the negate state to the assert state shown in Figure 3A. Even in such a case, if the voltage value measurement circuit 202 can measure that this voltage is less than 10% of the peak voltage at time t2, a predetermined time has elapsed from time t1, the generation of abnormal interrupt signals and their processing can be suppressed.

[0037] Similarly, for example, at time t3, even if the voltage on either interrupt signal line 118 or 122 changes from a negate state to an assert state due to the generation of a spurious signal, if the voltage measurement circuit 202 measures that this voltage is less than 10% of the peak voltage at time t4, a predetermined time has elapsed from time t3, the generation and processing of an abnormal interrupt signal are suppressed. Even if the voltage on either interrupt signal line 118 or 122 changes from a negate state to an assert state, the generation of an interrupt is not detected unless the assert state continues for a predetermined time within the designed range, and the generation of a normal interrupt is detected only when it continues for a predetermined time within the designed range.

[0038] The interrupt signal storage circuit 22 stores the voltage obtained as a result of the measurement by the voltage value measurement circuit 202, under a monitoring time t. test The interrupt signal storage circuit 22 stores waveform information over time (for example, 1 second), performs analysis on this waveform information, and makes a judgment based on the results of the analysis. When the interrupt signal storage circuit 22 determines that the waveform signal has been asserted normally, it does not store the waveform information input from the interrupt signal detection circuit 200. On the other hand, when the interrupt signal storage circuit 22 determines that the waveform signal indicates an abnormally asserted interrupt signal, it stores the waveform information indicating the waveform signal measured by the voltage value measurement circuit 202. Furthermore, the interrupt signal storage circuit 22 notifies the fault diagnosis circuit 24 that the waveform signal indicates an abnormally asserted interrupt signal.

[0039] For example, an abnormal interrupt signal is generated when either the internal interrupt device 112 or the external interrupt device 116 fails or is damaged, or when noise or spurious signals occur in computer 1. The waveform information stored in the interrupt signal storage circuit 22 associates the time when the abnormal interrupt signal was detected and the time when it ceased to be detected with identification information that identifies either the internal interrupt device 112 or the external interrupt device 116 that generated the abnormal interrupt signal. The interrupt signal storage circuit 22 outputs the stored waveform information to the fault diagnosis circuit 24 in response to a request from the fault diagnosis circuit 24.

[0040] The fault diagnosis circuit 24 reads waveform information of abnormal interrupt signals stored in the interrupt signal storage circuit 22 in response to a notification from the interrupt signal storage circuit 22. Furthermore, the fault diagnosis circuit 24 analyzes the cause (event) of the abnormal interrupt signal based on the read waveform information. The fault diagnosis circuit 24 outputs the abnormal cause information, which indicates the cause of the abnormal interrupt signal obtained as a result of this analysis, to the processor 100 via the bus signal line 12.

[0041] The PLL circuit 220 receives the system clock signal from the system clock generator 108 via the bus signal line 12. The PLL circuit 220 synchronizes with the received system clock signal and generates a measurement clock signal with a higher frequency than the system clock signal (for example, 1 GHz; a frequency about 10 times that of the system clock signal), and outputs it to each component of the diagnostic device 2. Each component of the diagnostic device 2 uses the measurement clock signal input from the PLL circuit 220 to measure the pulse width of interrupt signals, etc., or operates in synchronization with the system clock signal or the measurement clock signal.

[0042] Next, the operation of the diagnostic device 2 of the computer 1 shown in Figure 2 will be explained with reference to Figures 4A to 4D. Figure 4A is a flowchart illustrating an example of the overall processing (S10) of the computer 1. Figure 4B is a flowchart illustrating an example of the processing (S14) of the detection and measurement circuit 20, which detects the asserted and negated states of the voltage generated on either of the interrupt signal lines 118 or 122 shown in Figure 4A. Figure 4C is a flowchart illustrating an example of the processing (S18) of the interrupt signal storage circuit 22 and the fault diagnosis circuit 24, which determine the cause of the voltage generated on either of the interrupt signal lines 118 or 122 shown in Figure 4A. Figure 4D is a flowchart illustrating an example of the processing (S20) of the fault diagnosis circuit 24, which diagnoses the cause of the fault shown in Figure 4A. Note that multiple S10 to S18 processes may be performed in parallel by methods such as time-division parallel processing. Furthermore, process S14 shown in Figure 4B is executed twice in the process shown in Figure 4A, once between S104 and S106, and again between S110 and S112.

[0043] First, we will explain the overall operation of computer 1, focusing on the operation of diagnostic device 2. As shown in Figure 4A, in S100, diagnostic device 2 performs initialization processing for new interrupt processing, such as enabling the detection and measurement circuit 20 to measure all voltages on interrupt signal lines 118 and 122, and setting variables used for interrupt processing to their initial values.

[0044] In S102, the interrupt signal detection circuit 200 of the detection / measurement circuit 20 measures all voltages on the interrupt signal lines 118 and 122 and determines whether the voltage on either of the interrupt signal lines 118 or 122 is 10% or more of the peak voltage. The diagnostic device 2 proceeds to process S104 if the voltage on either of the interrupt signal lines 118 or 122 is 10% or more of the peak voltage (Y in the process of S102), and remains in process S102 if it is less than 10% (N in the same process).

[0045] In S104, the voltage measurement circuit 202 controls the selector circuit 222 to select either the interrupt signal line 118 or 122 whose voltage is 10% or more of the peak voltage, and outputs the voltage of the selected interrupt signal line 118 or 122 to the interrupt signal detection circuit 200, etc. After the processing in S104, the diagnostic device 2 proceeds to the first processing in S14.

[0046] In S14, the detection and measurement circuit 20 generates waveform information that shows the waveform of either the interrupt signal line 118 or 122 selected in the processing of S104 over time. Details of the processing in S14 will be described later with reference to Figure 4B.

[0047] After the first processing in S14, in S106, the voltage value measurement circuit 202 controls the selector circuit 222 to deselect either of the interrupt signal lines 118 or 122 whose voltage is 10% or more of the peak voltage, so that the voltage value measurement circuit 202 can measure all voltages on the interrupt signal lines 118 and 122. In addition, the interrupt signal detection circuit 200 outputs the waveform information generated in processing S100 to S104 to the interrupt signal storage circuit 22 for storage.

[0048] After processing in S106, the diagnostic device 2 proceeds to processing in S18. In S18, the interrupt signal storage circuit 22 and the fault diagnosis circuit 24 determine whether the waveform information of either of the interrupt signal lines 118 or 122 selected in processing S104 is a normal interrupt signal, an abnormal interrupt signal, a voltage caused by spurious signals, or a voltage caused by noise. Details of the processing in S18 will be described later with reference to Figure 4C.

[0049] After processing in S18, in S108, the voltage value measurement circuit 202 controls the selector circuit 222 to select one of the interrupt signal lines 118 or 122 that indicates the voltage shown by the waveform information that was the subject of processing in S18. The selector circuit 222 outputs the voltage of the selected interrupt signal line 118 or 122 to the voltage value measurement circuit 202.

[0050] In S110, the interrupt signal detection circuit 200 determines whether the voltage of either the interrupt signal line 118 or 122 selected in the S108 process is 10% or more of the peak value. If the voltage of either the selected interrupt signal line 118 or 122 is 10% or more of the peak value (Y in the S110 process), the diagnostic device 2 performs the second S14 process; otherwise, it remains at the S110 process. After the S110 process, the diagnostic device 2 proceeds to the second S14 process.

[0051] After the second processing in S14, in S112, the detection / measurement circuit 20 outputs waveform information of either interrupt signal line 118 or 122, which was generated in the preceding processing in S14, to the interrupt signal storage circuit 22. The interrupt signal storage circuit 22 stores the waveform signal input from the detection / measurement circuit 20.

[0052] In S114, the diagnostic device 2 monitors the process in S104 to S114, with a monitoring time t test The diagnostic device 2 determines whether the time has elapsed. In the processing of S104 to S114, the monitoring time t test When the time limit has elapsed (Y in the S114 process), the process proceeds to S116; otherwise, the process returns to S110.

[0053] In S116, the voltage measurement circuit 202 controls the selector circuit 222 to deselect either of the interrupt signal lines 118 or 122 that was selected in S108, so that the voltage measurement circuit 202 can measure all voltages on the interrupt signal lines 118 and 122. After processing in S116, the diagnostic device 2 proceeds to processing in S20.

[0054] In S20, the fault diagnosis circuit 24 analyzes the waveform information stored in the interrupt signal storage circuit 22 during the processing of S112. Furthermore, if the waveform information analyzed does not indicate a normal interrupt signal, the fault diagnosis circuit 24 diagnoses whether the waveform signal was caused by a fault in the interrupt signal lines 118, 122, a fault in the interrupt signal system, or a fault in the internal interrupt device 112 or the external interrupt device 116. This diagnosis result is output to the processor 100 via the bus signal line 12. Details of the processing in S20 will be described later with reference to Figure 4D.

[0055] After processing in S20, in S118, the diagnostic device 2 determines whether or not to terminate the process due to some reason, such as a power outage of computer 1. If the diagnostic device 2 determines that the process should be terminated (Y in processing S118), it terminates the process; otherwise, it returns to processing S100.

[0056] Next, referring to Figure 4B, the process for measuring the voltage of either of the selected interrupt signal lines 118 or 122 by the detection and measurement circuit 20 will be described. In S140, the interrupt signal detection circuit 200 controls the voltage value measurement circuit 202 to monitor the voltage of either of the interrupt signal lines 118 or 122 selected in the process of S104 (Figure 4A) for a monitoring time t test Start the measurement during the interval shown in (Figure 3B).

[0057] In S142, the voltage value measurement circuit 202 determines whether the voltage measured by the interrupt signal detection circuit 200 is 90% or more of the peak value. The detection and measurement circuit 20 proceeds to process S146 if the voltage value of either of the selected interrupt signal lines 118 or 122 is 90% or more of the peak value (Y in the process of S142), and proceeds to process S144 if it is less than 90% (N in the same process).

[0058] In S144, the interrupt signal detection circuit 200 determines whether the voltage of either the selected interrupt signal line 118 or 122 is less than 10% of the peak value. The detection and measurement circuit 20 terminates processing if the voltage of either the selected interrupt signal line 118 or 122 is less than 10% of the peak value (Y in the processing of S144), and returns to processing S142 if it is 10% or more (N in the same processing).

[0059] In S146, the interrupt signal detection circuit 200 detects the monitoring time t that started in S140. test Stop measuring the voltage of either interrupt signal line 118 or 122 during the following monitoring time t test Start measuring the voltage on either interrupt signal line 118 or 122 between these points (for the next time measurement).

[0060] In S148, the interrupt signal detection circuit 200 determines whether the processor 100 has received interrupts from the internal interrupt device 112 and the external interrupt device 116 and has requested that the numerical value of the bit (flag) of the interrupt flag circuit 224 be cleared to 0 via the bus signal line 12. The detection and measurement circuit 20 proceeds to the process in S152 if the processor 100 has requested that the flag be cleared to 0 (Y in the process of S148), and to the process in S150 if it has not (N in the same process).

[0061] In S150, the interrupt signal detection circuit 200 determines whether the voltage of any of the selected interrupt signal lines 118, 122 is less than 90% of the peak value. When the voltage of any of the selected interrupt signal lines 118, 122 is less than 90% of the peak value (Y in the process of S150), the detection and measurement circuit 20 proceeds to the process of S156, and when it is 90% or more (N in the same), it returns to the process of S148.

[0062] In S152, the detection and measurement circuit 20 performs the same process as in S146. In S154, the detection and measurement circuit 20 makes the same determination as in S150. When the voltage of any of the selected interrupt signal lines 118, 122 is less than 90% of the peak value (Y in the process of S154), the detection and measurement circuit 20 proceeds to the process of S156, and when it is 90% or more (N in the same), it stays in the process of S154.

[0063] In S156, the interrupt signal detection circuit 200 causes the voltage value measurement circuit 202 to measure all the voltages of the interrupt signal lines 118, 122. In S158, the detection and measurement circuit 20 performs the same process as in S144. When all the voltages of the interrupt signal lines 118, 122 are less than 10% of the peak value (Y in the process of S158), the detection and measurement circuit 20 proceeds to the process of S160, and when it is 10% or more (N in the same), it stays in the process of S158.

[0064] In S160, the detection and measurement circuit 20 ends the measurement during the monitoring time t test (Figure 3B). After that, the diagnostic device 2 proceeds to the process of S106 (Figure 4A).

[0065] Next, referring to Figure 4C, a process (S18) for determining whether any of the selected voltages of the interrupt signal lines 118, 122 is caused by a normal interrupt signal, an abnormal interrupt signal, spurious, or noise will be described. As shown in Figure 4C, in S180, the interrupt signal storage circuit 22 of the diagnostic device 2 monitors the voltage of any of the interrupt signal lines 118, 122 for the monitoring time t test(Figure 3B) The waveform signal (Figure 3A) measured over time is processed over a predetermined first time period as described above. The interrupt signal storage circuit 22 processes the waveform signal at the first time t when the waveform signal has risen and reached 10% or more of the peak voltage. u10 And the second time t when the peak voltage exceeds 90% u90 The time t when processor 100 cleared the bit of interrupt flag circuit 224 is... c Then, at the third time t, when the waveform signal has fallen and the peak voltage is less than 90% d90 And the fourth time t when the peak voltage falls below 10% d10 To measure and

[0066] In S182, the interrupt signal storage circuit 22, based on the measurement in the processing of S180, determines the first time t u10 , second time t u90 , third time t d90 and the fourth time t d10 The interrupt signal memory circuit 22 determines whether or not time 4 has been measured. If time 4 has been measured (Y in the process of S182), the interrupt signal memory circuit 22 proceeds to process S184, and if time 3 or less has been measured, it proceeds to process S186.

[0067] In S184, the interrupt signal memory circuit 22 determines that the time difference from the beginning to the end of the measured time 4 is the monitoring time t test Less than (monitoring time t) test The interrupt signal storage circuit 22 determines whether the time difference is within the range of t. test If it is less than (Y in the S184 process), the process proceeds to S190, and the time difference is monitored time t. test In the above case (same N), proceed to processing S188.

[0068] In S186, the interrupt signal memory circuit 22 determines whether or not time 3 was measured based on the measurement taken in processing S180. If time 3 is measured (Y in processing S186), the interrupt signal memory circuit 22 proceeds to processing S192; if time 2 or less is measured (N in the same process), it proceeds to processing S194.

[0069] In S188, the interrupt signal memory circuit 22 determines that the voltage on either interrupt signal line 118 or 122 rose from less than 10% of the peak voltage to more than 90%, and was asserted, but that the asserted state did not continue for a predetermined time period. Based on this determination, the interrupt signal memory circuit 22 determines that the voltage on either interrupt signal line 118 or 122 indicates an abnormal interrupt. This determination result is output to the processor 100 via the bus signal line 12.

[0070] In S190, the interrupt signal memory circuit 22 determines that the voltage on either the interrupt signal line 118 or 122 has risen from less than 10% of the peak voltage to more than 90%, indicating an asserted state, and that this state has continued for a predetermined time. Based on this determination, the interrupt signal memory circuit 22 determines that the voltage on either the interrupt signal line 118 or 122 indicates a normal interrupt. This determination result is output to the processor 100 via the bus signal line 12.

[0071] In S192, the interrupt signal memory circuit 22 entered a state where the voltage on either the interrupt signal line 118 or 122 was asserted, and this state continued for a predetermined time period, but at time t c In this case, the interrupt flag circuit 224's bit was not cleared to the value 0, and it was determined that it did not fall properly. As a result of this determination, the interrupt signal memory circuit 22 determined that the voltage on either the interrupt signal line 118 or 122 was asserted due to a spurious signal. This determination result is output to the processor 100 via the bus signal line 12.

[0072] In S194, the interrupt signal memory circuit 22 determines that the voltage on either interrupt signal line 118 or 122 exceeded 10% of its peak value, but did not exceed 90%, and therefore was not properly asserted, and instead fell below 10%. Based on this determination, the interrupt signal memory circuit 22 determines that either interrupt signal line 118 or 122 was asserted due to noise. This determination result is output to the processor 100 via the bus signal line 12.

[0073] In S196, the fault diagnosis circuit 24 notifies the detection and measurement circuit 20 to continue measuring the voltage of either interrupt signal line 118 or 122, which corresponds to the waveform information recorded in the interrupt signal storage circuit 22. After the processing in S18 described above, the diagnostic device 2 proceeds to the processing in S108 (Figure 4A).

[0074] Next, referring to Figure 4D, the process (S20) for diagnosing the cause of a fault based on the selected voltage of the interrupt signal lines 118 and 122 will be explained. For the sake of simplicity, specific examples will be given where the cause of the fault is a failure in either of the interrupt signal lines 118 or 122, a failure in either of the interrupt signal lines 118 or 122 and the components connected thereto (interrupt signal line system), or a failure in the interrupt control device 106. Furthermore, the first to fourth thresholds shown in Figure 4D are determined by simulation based on the configuration or by experimentation before the actual interrupt processing is performed in computer 1.

[0075] In S200, the fault diagnosis circuit 24 counts the number of abnormal interrupts, the number of assertions due to spurious signals, and the number of assertions due to noise, determined by the processing in S188 to S194 shown in Figure 4C, for a sufficiently longer period than the predetermined first time, during a predetermined second time.

[0076] In S202, the fault diagnosis circuit 24 determines whether the number of abnormal interrupt occurrences exceeds a first threshold. If the number of abnormal interrupt occurrences exceeds the first threshold (Y in the S202 process), the fault diagnosis circuit 24 proceeds to the S206 process; if the number of abnormal interrupt occurrences is less than or equal to the first threshold (N in the S202 process), it proceeds to the S204 process.

[0077] In S204, the fault diagnosis circuit 24 determines whether the number of times an assertion caused by spurious signals occurred on the interrupt signal lines 118 and 122 exceeds a second threshold. If the number of assertions caused by spurious signals exceeds the second threshold (Y in the S204 process), the fault diagnosis circuit 24 proceeds to the S206 process; if the number of assertions caused by spurious signals is less than or equal to the second threshold (N in the S204 process), the circuit proceeds to the S208 process.

[0078] In S206, the fault diagnosis circuit 24 determines whether the number of noise-induced assertions on the interrupt signal lines 118 and 122 exceeds a third threshold. If the number of noise-induced assertions exceeds the third threshold (Y in the S206 process), the fault diagnosis circuit 24 proceeds to the S212 process; if the number of noise-induced assertions is less than or equal to the third threshold (N in the S206 process), it proceeds to the S214 process.

[0079] In S208, the fault diagnosis circuit 24 determines whether the number of times an assertion caused by spurious signals occurred on the interrupt signal lines 118 and 122 exceeds a fourth threshold. If the number of assertions caused by spurious signals exceeds the fourth threshold (Y in the S208 process), the fault diagnosis circuit 24 proceeds to the S210 process; if the number of assertions caused by spurious signals is less than or equal to the fourth threshold (N in the S208 process), the process terminates.

[0080] In S210, the fault diagnosis circuit 24 diagnoses that there is a fault in the interrupt signal lines 118 and 122. In S212, the fault diagnosis circuit 24 diagnoses that there is a fault in the interrupt signal system. In S214, the fault diagnosis circuit 24 diagnoses that there is a fault in the interrupt control device 106. After processing S210 to S214, the diagnostic device 2 completes the process shown in Figure 4D and proceeds to the process shown in Figure 4A, S116.

[0081] Abnormal interrupt signals, spurious signals, and noise in either interrupt signal line 118 or 122 can be caused, for example, by an abnormality in the system clock signal. For instance, if the system clock output from the system clock generator 108 changes, the signal width of the interrupt signal may become longer than the design range, resulting in an abnormal interrupt signal. Alternatively, depending on the nature of the failure of the system clock generator 108, the signal width of the interrupt signal may become shorter than the design range, resulting in a spurious signal. Furthermore, vibrations in the interrupt signal lines 118 or 122, or increased resistance of switch contacts such as keyboard switches due to oxidation, can generate noise. The operation of the fault diagnosis circuit 24 shown in Figure 4D can diagnose the cause of any voltage other than a normal interrupt signal generated in either interrupt signal line 118 or 122.

[0082] More specifically, for example, if the number of occurrences of abnormal interrupt signals, interrupt signals caused by spurious signals, and interrupts caused by noise exceeds predetermined thresholds, it can be determined that there is an abnormality in the interrupt signal lines 118 and 122. Also, for example, when interrupt signals are generated in response to user keyboard operations, thresholds can be set for the number of occurrences of abnormal interrupt signals, interrupt signals caused by noise, and interrupt signals caused by noise, respectively. Such thresholds can be written to the fault diagnosis circuit 24 by the processor 100.

[0083] For example, monitoring time t test The monitoring time t is 1 second, the threshold for the number of abnormal interrupt signals is set to 10, the threshold for the number of interrupt signals caused by spurious signals is set to 10, and the threshold for the number of interrupt signals caused by noise is set to 10. In this case, the monitoring time t test Within (1 second), the interrupt signal line 122 connected to the keyboard as an external interrupt device 116 may generate 11 abnormal interrupt signals, 3 interrupt signals due to spurious signals, and 3 interrupt signals due to noise. In this case, it can be determined that the keyboard, as the external interrupt device 116, is malfunctioning.

[0084] Also, for example, monitoring time t test During this time, the interrupt signal line 122 connected to the keyboard as an external interrupt device 116 may receive 11 abnormal interrupt signals, 3 interrupt signals due to spurious signals, and 31 interrupt signals due to noise. In this case, it may be determined that a malfunction has occurred in the interrupt signal line 122 connected to the keyboard as an external interrupt device 116 via the interrupt interface device 114 and the interrupt signal line 120.

[0085] Furthermore, for example, monitoring time t test During this time, the interrupt signal line 122 connected to the keyboard as an external interrupt device 116 may generate 11 abnormal interrupt signals, 3 interrupt signals due to spurious signals, and 31 interrupt signals due to noise. In this case, it may be determined that a fault has occurred in the interrupt signal system, including the keyboard as an external interrupt device 116, the interrupt interface device 114 and the interrupt signal line 120, and the interrupt signal line 122. The fault diagnosis circuit 24 shown in Figure 4D diagnoses the cause of the abnormal interrupt signals and other issues that occurred in the interrupt signal system based on the judgment criteria described here.

[0086] Some or all of the above embodiments may also be described as follows, but are not limited to the following: [Note 1] (See the first perspective above) [Note 2] The diagnostic device according to Appendix 1, wherein the waveform information includes a first time when the voltage generated on the interrupt signal line rises and becomes equal to or greater than a first peak voltage value of the voltage; a second time when the voltage generated on the interrupt signal line rises and becomes equal to or greater than a second voltage value higher than the first peak voltage value of the voltage; a third time when the voltage generated on the interrupt signal line falls below the second voltage value of the voltage; and a fourth time when the voltage generated on the interrupt signal line falls below the first voltage value of the voltage. [Note 3] The diagnostic device described in Appendix 2, which detects that the interrupt signal line has been asserted when the voltage generated on the interrupt signal line becomes equal to or greater than the first voltage value and then equal to or greater than the second voltage value, and detects that the interrupt signal line has been negated when the voltage generated on the interrupt signal line becomes less than the second voltage value and then less than the first voltage value. [Note 4] The diagnostic device described in Appendix 2, wherein when the time length between the first time and the second time is greater than or equal to a predetermined time length, the voltage of the interrupt signal line is determined to be an abnormal interrupt signal, and when the time length between the first time and the second time is less than a predetermined time length, the voltage of the interrupt signal line is determined to be a normal interrupt signal. [Note 5] The diagnostic device according to Appendix 2, wherein the waveform information indicates the first time, the second time, the third time, and the fourth time, and when the time length between the first time and the second time is greater than or equal to a predetermined time length, the voltage of the interrupt signal line is determined to be an abnormal interrupt signal, and when the time length between the first time and the second time is less than a predetermined time length, the voltage of the interrupt signal line is determined to be a normal interrupt signal. [Note 6] The diagnostic device according to Appendix 5, wherein when the waveform information indicates the first time and two of the second time, third time and fourth time, it is determined that the voltage of the interrupt signal line is due to spurious signals, and when the waveform information indicates the first time and one or zero of the second time, third time and fourth time, it is determined that the voltage of the interrupt signal line is due to noise. [Note 7] A diagnostic device according to Appendix 6, which diagnoses one or more of the following based on the number of occurrences of the abnormal interrupt signal, the number of occurrences of the voltage on the interrupt signal line due to spurious signals, and the number of occurrences of the voltage on the interrupt signal line due to noise: a fault on the interrupt signal line, a fault in the interrupt signal system including the interrupt signal line and components connected to the interrupt signal line, and a fault in an interrupt control device that controls interrupts. [Note 8] (See the second perspective above) [Note 9] (See the third perspective above) It goes without saying that any combination of the forms described in the appendices of this disclosure, or any combination of the elements described in each perspective and embodiment (including the non-selection of some elements), can be made from time to time by those skilled in the art, in accordance with the basic concepts of this disclosure.

[0087] Furthermore, each disclosure of the above-mentioned patent documents and other materials cited is incorporated into this publication by reference. Within the framework of this disclosure (including the claims), further modifications and adjustments to the embodiments or examples are possible based on their fundamental technical concept. Also, within the framework of this disclosure, various combinations or selections (including partial deletions) of various disclosed elements (including each element of each claim, each element of each embodiment or example, each element of each drawing, etc.) are possible. In other words, this disclosure naturally includes various modifications and changes that a person skilled in the art could make in accordance with the entire disclosure, including the claims, and the technical concept. In particular, the numerical ranges described in this publication should be interpreted as specifically describing any numerical value or sub-range included within that range, even if not specifically noted. Furthermore, each disclosure of the above-mentioned cited documents is deemed to be included in the disclosures of this application, which may be used in part or in whole as part of this disclosure, in accordance with the spirit of this disclosure, as necessary. [Explanation of symbols]

[0088] 1 Computer 12 Bus / Signal Lines 100 processors 102 Main storage 104 Auxiliary storage 106 Interrupt control device 108 System Clock Generator 110 Input / Output Interface Device 112 Internal interrupt device 114 Interrupt Interface Device 116 External Interrupt Device 118, 120, 122 Interrupt signal lines 2 Diagnostic devices 20 Detection and Measurement Circuits 200 Interrupt signal detection circuit 202 Voltage Measurement Circuit 22 Interrupt signal memory circuit 24. Diagnostic Circuit 220 PLL circuit 222 Selector Circuit 224 Interrupt Flag Circuit

Claims

1. A diagnostic device comprising one or more processors, The one or more processors mentioned above are: It generates waveform information showing the voltage waveform occurring on the interrupt signal line. Based on the waveform information, it is determined which of the multiple events the voltage generated on the interrupt signal line represents. Based on the number of times each of the multiple events that have been determined has been determined, it is diagnosed whether a fault has occurred in the interrupt signal line or in the components related to the interrupt signal line. It is configured in such a way, The waveform information is The first time when the voltage generated on the interrupt signal line rises to a first value equal to or greater than the peak voltage of the said voltage, When the voltage generated on the interrupt signal line rises, the second time is when the voltage becomes greater than or equal to a second voltage value which is higher than the first peak voltage value of the voltage, The third time when the voltage generated on the interrupt signal line falls below the second voltage value, When the voltage generated on the interrupt signal line falls, the fourth time when the voltage falls below the first voltage value and Diagnostic equipment including.

2. When the voltage generated on the interrupt signal line becomes equal to or greater than the first voltage value, and then equal to or greater than the second voltage value, it is detected that the interrupt signal line has been asserted. When the voltage across the interrupt signal line falls below the second voltage value and then below the first voltage value, it is detected that the interrupt signal line has been negated. The diagnostic device according to claim 1.

3. When the time interval between the first time and the second time is greater than or equal to a predetermined time interval, the voltage of the interrupt signal line is determined to be an abnormal interrupt signal. When the time interval between the first time and the second time is less than a predetermined time interval, the voltage of the interrupt signal line is determined to be a normal interrupt signal. The diagnostic device according to claim 1.

4. The waveform information indicates the first time, the second time, the third time, and the fourth time. When the time interval between the first time and the second time is greater than or equal to a predetermined time interval, the voltage of the interrupt signal line is determined to be an abnormal interrupt signal. When the time interval between the first time and the second time is less than a predetermined time interval, the voltage of the interrupt signal line is determined to be a normal interrupt signal. The diagnostic device according to claim 1.

5. When the waveform information indicates the first time and three of the second, third, and fourth times, it is determined that the voltage of the interrupt signal line is due to a spurious signal. When the waveform information indicates two or less of the first time, second time, third time, and fourth time, it is determined that the voltage of the interrupt signal line is due to noise. The diagnostic device according to claim 4.

6. Based on the number of occurrences of the abnormal interrupt signal, the number of occurrences of voltage on the interrupt signal line due to spurious signals, and the number of occurrences of voltage on the interrupt signal line due to noise, one or more of the following are diagnosed: a fault in the interrupt signal line, a fault in the interrupt signal system including the interrupt signal line and components connected to the interrupt signal line, and a fault in the interrupt control device that controls the interrupt. The diagnostic device according to claim 5.

7. A step performed by a diagnostic device, A step of generating waveform information that shows the voltage waveform occurring on the interrupt signal line, The steps include determining, based on the waveform information, which of the multiple events the voltage generated on the interrupt signal line represents, A step of diagnosing whether a fault has occurred in the interrupt signal line or in any of the components related to the interrupt signal line, based on the number of times each of the multiple events that have been determined has been determined. A diagnostic method that includes, The waveform information is The first time when the voltage generated on the interrupt signal line rises to a first value equal to or greater than the peak voltage of the said voltage, When the voltage generated on the interrupt signal line rises, the second time is when the voltage becomes greater than or equal to a second voltage value which is higher than the first peak voltage value of the voltage, The third time when the voltage generated on the interrupt signal line falls below the second voltage value, When the voltage generated on the interrupt signal line falls, the fourth time when the voltage falls below the first voltage value and Diagnostic methods including those mentioned above.

8. Executed in a diagnostic device equipped with one or more processors, In the above one or more processors, A process for generating waveform information that shows the voltage waveform occurring on the interrupt signal line, A process to determine which of several events the voltage generated on the interrupt signal line represents, based on the waveform information, A process for diagnosing whether a fault has occurred in the interrupt signal line or in any of the components related to the interrupt signal line, based on the number of times each of the multiple events that have been determined has been determined. A program that executes, The waveform information is The first time when the voltage generated on the interrupt signal line rises to a first value equal to or greater than the peak voltage of the said voltage, When the voltage generated on the interrupt signal line rises, the second time is when the voltage becomes greater than or equal to a second voltage value which is higher than the first peak voltage value of the voltage, The third time when the voltage generated on the interrupt signal line falls below the second voltage value, When the voltage generated on the interrupt signal line falls, the fourth time when the voltage falls below the first voltage value and including program.

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