Resistive random-access memory for analog computing

Abstract

A memory device is provided, including methods and structures for forming a resistive random access memory (RRAM) that changes resistance gradually rather than abruptly upon programming, making it suitable for analog computing. In a first embodiment, one electrode of the RRAM of the present invention includes a metal nitride material (e.g., titanium nitride (TiN)) with a gradual change in concentration of a metal component (e.g., titanium). Different Ti concentrations in the electrode result in different concentrations of oxygen vacancies in the corresponding sections of the RRAM, resulting in a gradual change in resistance in response to an applied voltage. The total conductance of the RRAM is the sum of the conductances of each of the sections of the RRAM. In a second embodiment, one electrode of the RRAM is multiply branched with different component concentrations and therefore different switching behaviors. This results in a gradual change in conductance in the RRAM of the present invention rather than abruptly.

Description

[Technical Field]

[0001] This application relates to a semiconductor memory device and a method for forming the semiconductor memory device. More specifically, this application relates to a method for manufacturing an analog resistive random-access memory device structure or an analog resistive random-access memory. [Background technology]

[0002] RRAM is considered a promising technology for electronic synaptic devices or memristors in neuromorphic computing and high-density, high-speed non-volatile memory applications. RRAM is a type of non-volatile random-access memory that functions by varying the resistance across a dielectric solid material. The basic idea is that a dielectric solid material, which is normally insulating, can be made conductive by applying a sufficiently high voltage to form filaments or conduction paths. Conduction paths can arise from various mechanisms, including the movement of vacancies or metallic defects. The formed filaments can be reset (destroyed, resulting in high resistance) or set (reformed, resulting in low resistance) by another voltage. Many current paths, rather than a single filament, may be involved.

[0003] In neuromorphic computing applications, resistive random-access memory (RRAM) devices can be used as connections (i.e., synapses) between pre-neurons and post-neurons, representing connection weights in the form of device resistance. By connecting numerous pre- and post-neurons through the crossbar array of RRAM, fully connected neural networks can be naturally represented.

[0004] Furthermore, non-volatile RRAM memory has emerged as a feasible device for memory and analog computing, particularly due to its suitability for CMOS logic processing.

[0005] However, the resistance of currently designed RRAM devices changes abruptly in response to electrical pulses, making such RRAM devices unsuitable for analog computing in artificial intelligence (AI) applications. [Overview of the project]

[0006] The present invention provides an analog resistive random-access memory device, i.e., a resistive random-access memory (RRAM) cell, in which the composition of at least one electrode is varied so that the resistance of the RRAM changes progressively.

[0007] In one embodiment, the RRAM structure can be made suitable for AI applications by exhibiting a gradual change in resistance, for example, a gradual change in resistance in response to an electrical pulse / voltage level.

[0008] The RRAM structure of this application, which can exhibit a gradual change in resistive operation, is formed as a two-terminal RRAM cell, and the RRAM structure includes electrodes whose composition gradually changes, thereby allowing its resistance to gradually change in accordance with the electrical pulse / voltage level.

[0009] This application provides a method for forming an RRAM structure that can be made suitable for AI applications by exhibiting a gradual change in resistance in response to an electrical pulse / voltage level.

[0010] According to a first embodiment, a resistive random-access memory device is provided. This resistive random-access memory device comprises a first metal electrode layer having a variable composition containing a metallic material, a resistive dielectric material layer on the top surface and sidewall surface of the first electrode, and a second metal electrode on the resistive dielectric material layer.

[0011] According to a further aspect, a resistive change type memory device is provided. This resistive change type memory device is a stack in which an insulating material layer between a first metal electrode material layer and a first electrode material layer forms an interlayer, and the composition containing the metal material of each of the successive first metal electrode material layers in the stack is different. The stack includes a stack, a resistive dielectric material layer on the top surface and side wall surfaces of the stack, and a second metal electrode on the resistive dielectric material layer. When a voltage is applied between the stack of the first metal electrode material layers forming the interlayer and the second metal electrode, the conductance of the resistive change type memory device changes gradually.

[0012] According to another aspect, a method of forming a memory device is provided. This method includes forming a first electrode layer having a varying composition containing a metal material on a substrate, patterning the first electrode to expose side walls, attaching a resistive element to the side walls of the first electrode, and forming a second electrode on the resistive element.

Brief Description of the Drawings

[0013] [Figure 1] It is a diagram showing a resistance (memory storage) element of a RRAM memory device according to an embodiment. [Figure 2] (A) to (C) are diagrams showing the role played by oxygen vacancies in the resistance switching of the RRAM cells shown in these figures. [Figure 3] It is a diagram showing a resistive change type memory cell formed according to the first embodiment. [Figure 4] It is a diagram showing the calculation of the total conductance "G" of a RRAM cell as the sum of the conductances of each of the sections R1, R2,..., Rn of the RRAM cell. [Figure 5] (A) to (C) are diagrams showing method steps for forming the semiconductor RRAM structure of FIG. 3 according to the first embodiment. [Figure 6] It is a schematic diagram of a RRAM array having a plurality of RRAM cells in which each RRAM cell includes the resistive change type memory cell of the embodiment shown in FIG. 3. [Figure 7] This figure shows a resistive random-access memory cell structure according to the second embodiment. [Figure 8] Figures (A) to (C) show the method steps for forming the resistive random-access memory cell structure of Figure 7 according to the second embodiment. [Figure 9] This is a schematic diagram of an RRAM array having multiple RRAM cells, each of which is a resistive random-access memory cell as shown in the embodiment in Figure 7. [Modes for carrying out the invention]

[0014] Next, the present application will be described in more detail by reference to the following discussion and the drawings attached thereto. Note that the drawings of this application are provided for illustrative purposes only, and therefore are not drawn to any particular proportion. Note also that the same elements and corresponding elements are indicated by the same reference numerals.

[0015] The following description provides numerous specific details, including particular structures, components, materials, dimensions, processing steps, and techniques, in order to provide an understanding of the various embodiments of this application. However, those skilled in the art will understand that the various embodiments of this application can be carried out without these specific details. For other reasons, well-known structures or processing steps have not been described in detail to avoid obscuring this application.

[0016] When an element such as a layer, region, or substrate is referred to as being "on top of" or "above" another element, it is understood that the element may be directly on top of that other element, or an intervening element may be present. Conversely, when one element is referred to as being "directly above" or "on top of" another element, no intervening element exists. When one element is referred to as being "below" or "below" another element, it is understood that the element may be directly below or beneath that other element, or an intervening element may be present. Conversely, when one element is referred to as being "directly below" or "below" another element, no intervening element exists.

[0017] Referring first to Figure 1, an exemplary resistive element R 102 of a resistive random-access memory (RRAM) memory device is shown. Such a resistive element 102 is a simple metal-insulator-metal (MIM) structure containing a "high-k" dielectric material, such as a transition metal oxide, formed between the top electrode 172 and the bottom electrode 170. The intermediate layer can be a single material, such as HfO2. In embodiments, the metal electrodes of this memory cell can contain materials such as Pt, TiN, Ti, Ru, Ni, TaN, W, etc., deposited by a physical vapor deposition (PVD) process, while HfO2 x , TiO x NiO x WO x TaO x , VO x CuO x The intermediate layer 171 of such transition metal oxide materials can be deposited by an atomic layer deposition (ALD) process.

[0018] The transition metal oxide formed between the top electrode 172 (e.g., anode) and the bottom electrode (e.g., cathode) of the RRAM device 102 includes a HfOx switching medium located between the two electrodes. By forming a conductive filament between the electrodes, a conductive path is provided between these two electrodes. By applying a voltage of an appropriate value to the RRAM device to form a filament, the resistive element 102 can be programmed to store a logic or weight value corresponding to either a high-resistance cell state, a low-resistance cell state, or other resistance states.

[0019] As can be seen by referring to "Physical Mechanism of HfO2-based Bipolar Resistive Random Access Memory" by H.-L. Chang, Symp. VLSI-TSA, 2011, the resistance switching between the high-resistance state (HRS) and the low-resistance state (LRS) of HfO2-based RRAM is based on the formation and rupture of Hf filaments through an electrochemical redox process in a region of several nanometers near the metal terminal (i.e., anode).

[0020] For example, FIGS. 2(A) to 2(C) show the role played by oxygen vacancies in the resistance switching of the shown RRAM cell. Specifically, there are two types of oxygen vacancies in HfO2, namely (1) HfO when one oxygen atom is missing 2+ (V o 2+ ) and (2) Hf when two oxygen atoms are not in a predetermined position 4+ . Oxygen vacancies with a positive charge are mobile under a high electric field and act like donor dopants that turn HfO2-based RRAM into an n-type semiconductor. As is known, the forming process creates a sufficient amount of oxygen vacancies in HfO2 to initiate resistance switching. As shown in FIGS. 2(B) and 2(C), under a high positive voltage, O 2- ions move into the Ti layer by diffusion or drift or both under a high electric field and then oxidize in an anodic oxidation operation according to the following equation 20 2- →2O+4e - On the other hand, Hf4+ ions (a type of oxygen vacancy) are reduced at the cathode by the reduction process shown in the following equation. Hf 4+ +4e - →Hf

[0021] As shown in Figure 2(B), one or more Hf filaments grow from the cathode to the anode, and after formation, the RRAM exhibits LRS. Under a negative voltage, a reverse redox process occurs near the anode. The reduction operation according to the following equation reduces the O in the Ti layer, and O 2- By releasing ions and returning to HfO2, 2O+4e - →2O 2- On the other hand, Hf filaments are oxidized by the oxidation process shown in the following equation, 4+ It becomes ion-bearing. Hf→Hf 4+ +4e - Hf according to the following formula 4+ and O 2- Recombination Hf 4+ +2O 2- →HfO2 As a result, the filament partially breaks (a few nanometers) near the anode, and after a reset, the RRAM shows HRS. When a positive voltage (<formation voltage) is applied, the filament reforms in the broken region, and after a reset, the RRAM returns to LRS. The fast (<5 nanoseconds) switching of the RRAM is due to the Hf filament breaking and reforming occurring a few nanometers near the anode.

[0022] Therefore, the initial state of most RRAM devices is the high-resistance state (HRS), in which the RRAM resistance is considered to be higher than a certain value. The first operation to bring the RRAM device to the low-resistance state (LRS) is the "forming" operation. Preferably, the LRS resistance is small enough that the support circuit can clearly distinguish the RRAM state from the HRS resistance. In the "forming" operation, when the applied voltage across the device exceeds a certain level, i.e., the forming voltage, the RRAM cell responds by beginning to change its state from HRS to LRS. In some circuits, the maximum current of the RRAM device can be limited by a current limiter, such as a transistor (not shown).

[0023] After the forming operation to set the RRAM device to LRS, a reset operation is performed in which the voltage applied across the device is swept negatively to transition the RRAM device operation between a low-resistance state and a high-resistance state. When a certain "reset" voltage limit is exceeded, the RRAM device changes state back from LRS to HRS. This process is called the RESET operation. When the voltage changes positive again and exceeds another "set" voltage limit, the RRAM changes state from HRS to LRS. This process is called the SET operation. The corresponding RESET and SET operations allow the RRAM device to operate back and forth between HRS and LRS, where the device can be RESET at a sufficiently low negative voltage and SET at a sufficiently high positive voltage.

[0024] This embodiment provides a method and structure for forming a resistive random-access memory (RRAM) cell. With respect to HfOx-based RRAM, the resistance change of HfOx is achieved by adding oxygen vacancies to or extracting oxygen vacancies from HfOx.

[0025] In one embodiment of this specification, an RRAM cell is formed in which the Ti% (Ti% is the titanium concentration) of a TiN (titanium nitride) electrode is progressively varied. Generally, the principle of this specification is applicable to RRAM cells having metal nitride material electrodes in which the metal concentration is progressively varied. In the case of a TiN material electrode, the varying titanium (Ti) concentrations in the electrode result in varying oxygen vacancy concentrations in the corresponding sections of the RRAM. The total resistance of the RRAM of the present invention is equivalent to having many RRAMs with varying oxygen vacancy concentrations (and therefore varying (non-uniform) resistance changes as a response to the number of pulses or voltage).

[0026] In one embodiment, a semiconductor manufacturing method is provided, comprising the first step of attaching a TiN bottom electrode in which the Ti% gradually changes, patterning the TiN bottom electrode, and then forming HfOx on the TiN sidewall such that the HfOx is in contact with sections of the TiN bottom electrode with different Ti% at different heights.

[0027] A resistive random-access memory cell formed according to the first embodiment is shown in Figure 3. The resistive random-access memory cell 200 in Figure 3 shows a structure having a first electrode 270 of a metal nitride material with a progressively changing metal concentration, i.e., titanium nitride (TiN) with a progressively changing Ti% concentration, and a second electrode 272 with a uniform TiN concentration. The cell includes an intermediate layer of an oxide material, such as HfO2. Although the resistive random-access memory cell 200 in Figure 3 is shown as a planar device, it is understood that this memory cell can be a vertically arranged material stack having a first bottom electrode TiN layer with a progressively changing Ti concentration, an intermediate resistive switching layer positioned above the first electrode, and a top electrode with a uniform concentration formed on this intermediate layer. In this first embodiment, it is understood that this memory cell can be in the reverse configuration, for example, a bottom metal nitride electrode (e.g., a TiN layer) with a uniform concentration and a top electrode TiN layer with a progressively changing Ti concentration.

[0028] As a result of different concentrations of 270Ti in the first electrode, the oxygen vacancy concentrations in the corresponding sections of the RRAM cell differ. The total resistance of the formed RRAM is equivalent to having many parallel RRAMs with different oxygen vacancy concentrations (and therefore different (non-uniform) resistance changes in response to the number of pulses or voltage applied).

[0029] Such RRAMs are usable in several applications (e.g., analog computing or neuromorphic applications) where a gradual change in RRAM resistance is desired instead of a simple binary resistance (high resistance / low resistance) state.

[0030] As conceptually shown in Figure 4, the total conductance "G" of RRAM cell 300 is the sum of the conductances (G1, G2, ..., Gn) of each section R1, R2, ..., Rn of the RRAM cell. That is, the total conductance is G total =G1+G2+...+G n It is calculated as follows.

[0031] Based on the first embodiment in Figure 3, in the circuit diagram of Figure 4, the conductance of each mini-conductor R1, R2, etc. is infinitely small, and there are countless mini-conductors. The same circuit diagram in Figure 4 also applies to the second embodiment in Figure 7, but in the second embodiment, there is a slight difference in that conductors R1, R2, etc. correspond to the conductances of RRAMs having different bottom electrode layers.

[0032] During the RESET operation, the conductance "G" does not decrease rapidly because Ti% (oxygen vacancy concentration, and therefore the RESET characteristic) is non-uniform.

[0033] Figures 5(A) to 5(C) show the method step 500 for forming the semiconductor RRAM structure 200 of Figure 3 according to the first embodiment.

[0034] First, a semiconductor substrate 505 is provided, for example, at a front-end-of-the-line (FEOL) level including one or more semiconductor devices (not shown) formed on the surface of the semiconductor substrate. These one or more semiconductor devices may include, but are not limited to, transistors, resistors, isolation structures, contacts, or diodes, or combinations thereof. This FEOL level may be formed using techniques well known to those skilled in the art.

[0035] In other embodiments of this application, the substrate 505 is a lower back-end-of-the-line (BEOL) level comprising one or more conductive structures embedded in one or more interconnect dielectric materials. In such embodiments, the FEOL level is typically located below the lower interconnect level.

[0036] The semiconductor substrate 505 includes a bulk semiconductor substrate which may include semiconductor materials or stacks of semiconductor materials, such as Si, Ge, SiGe, SiC, SiGeC, Ge alloys, GaAs, InAs, InP, and other III / V or II / VI compound semiconductors. In one embodiment, this bulk semiconductor substrate includes a single-crystal semiconductor material, such as single-crystal silicon. The thickness of the bulk semiconductor substrate can be from 30 μm to about 2 mm, but smaller and larger thicknesses can also be used. The bulk semiconductor substrate may be doped with p-type or n-type dopants. The term "p-type" refers to the addition of impurities to an intrinsic semiconductor that create valence electron deficiencies. Examples of p-type dopants, i.e., impurities, include, but are not limited to, boron, aluminum, gallium, and indium. "n-type" refers to the addition of impurities to an intrinsic semiconductor that contribute to free electrons. Examples of n-type dopants, i.e., impurities, include, but are not limited to, antimony, arsenic, and phosphorus. The dopant concentration of the bulk semiconductor substrate is 1 × 10⁻⁶. 14 atoms / cm 3 ~3×10 17 atoms / cm 3 It can be set to the range of

[0037] Alternatively, a semiconductor-on-insulator substrate can be used instead of the bulk semiconductor substrate shown in Figure 5(A).

[0038] After providing the semiconductor substrate as described above, a bottom electrode material layer 510 is formed on the surface of the semiconductor substrate. In one embodiment, the electrode material layer 510, which serves as the bottom electrode of the RRAM memory device, can be positioned horizontally. Each electrode material layer (e.g., electrode material layer 510) consists of a first electrode material such as titanium nitride (TiN), tantalum nitride (TaN), tungsten (W), or tungsten nitride (WN), or other materials, but not limited to tantalum carbide (TaC), titanium carbide (TiC), and titanium aluminum carbide (TiAlC). In the exemplary embodiment shown in Figure 3, the first electrode material is TiN, in which the percentage (%) concentration of Ti changes progressively. For example, as shown in 511, the % concentration of Ti in the TiN layer increases with the height of the layer 510. The increment of Ti% as a function of the height of the layer 510 can be linear, sublinear, superlinear, or other appropriate form.

[0039] The electrode material layer 510 can be formed using an adhesion process including, for example, CVD, PECVD, atomic layer deposition (ALD), sputtering, or plating. In one embodiment, the percentage concentration of Ti increases per unit of time as the TiN layer 510 is grown vertically. When formed, the bottom electrode material layer 510 may have a thickness (i.e., height) in the range of 30 nm to 300 nm, more preferably 50 nm to 200 nm, and most preferably 60 nm to 100 nm, although greater and smaller thicknesses may be intended.

[0040] In one embodiment, a gradual change in the Ti content of a metal, such as a TiN material, can be achieved by thermally decomposing a tetrakisdimethylaminotitanium (TDMAT) precursor in a nitrogen (N2) environment in an exemplary CVD process and depositing a TiN film in a reaction chamber. Various Ti% can be achieved by progressively adjusting the gas flow ratio of TDMAT to N2. In one embodiment, the process forms a bottom (first) electrode material layer 510 vertically, and a change in Ti% concentration is achieved, ranging from 15% (atomic concentration) to 85%, more preferably from 30% to 70%.

[0041] In the case of a vertically formed TaN bottom electrode 510, this process enables changes in Ta% concentration ranging from 25% to 75%.

[0042] The bottom electrode serves a dual purpose: (1) it is an electrode, and (2) it is an oxygen scavenging layer. Specifically, the bottom electrode interacts with the dielectric layer (e.g., HfOx) to create oxygen vacancies at the interface between the bottom electrode and HfOx.

[0043] In one embodiment, a hard mask layer 515 is formed above the bottom electrode 510. This hard mask layer 515 may be made of SiN, but other suitable hard mask dielectric materials such as silicon carbide (SiC), silicon oxynitride (SiON), carbon-doped silicon oxide (SiOC), fluorine-doped silicon oxide (SiO:F), silicon-carbon nitride (SiCN), boron nitride (BN), silicon boron nitride (SiBN), silicon boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), silicon oxide, and combinations thereof may also be used. The hard mask layer 515 can be formed using an deposition process including, for example, CVD, PECVD, ALD, PVD, sputtering, chemical solution deposition, or plating. The hard mask layer 515 may have a thickness of 20 nm to 100 nm, and other thicknesses are possible and applicable for the hard mask layer in this application.

[0044] Figure 5(B) shows further processing steps for forming a vertical stack memory cell structure including a bottom electrode 510 and a hard mask layer 515. Although not shown, such processing steps resulting in the structure shown in Figure 5(B) may include patterning a photoresist layer (not shown) above the hard mask layer 515 to expose the vertical sidewalls 560 of the bottom electrode of the RRAM memory cell. This patterned photoresist can be used as an etching mask at this step of the present application and may be made of conventional photoresist material. In one embodiment, this etching mask can be formed by depositing layers of photoresist material and photolithography. Then, in one embodiment, an anisotropic etching process can be performed to selectively remove physically exposed portions of the structure not protected by the photoresist layer, forming the sidewalls 560 of the bottom electrode and exposing portions 507 of the substrate surface. In one example, reactive ion etching can be used to remove physically exposed portions of the hard mask 510 and the underlying bottom electrode layer 505 that are not protected by a patterned photoresist layer (not shown). Hereinafter, the portion of the patterned RRAM cell stack remaining beneath the patterned photoresist may be referred to as the patterned bottom electrode portion 525. The remaining patterned photoresist layer can be removed using a stripping process, such as ashing.

[0045] Figure 5(C) shows an RRAM structure 575 formed as a result of further deposition, lithography, and etching of various material layers, including deposition of a high-k dielectric material layer (e.g., hafnium oxide (HfOx)) 540 on the top surface 530 of the hard mask layer, as well as on the aligned and exposed side walls of the hard mask layer and the side walls 560 of the bottom electrode. The deposition of the high-k dielectric material intermediate layer 540 includes deposition of a thin layer portion 541 on the exposed surface portion 507 of the substrate remaining after the preceding anisotropic etching. Subsequently, the top electrode layer 550 of the RRAM cell is formed on the outer surfaces of the high-k dielectric material intermediate layers 540, 541.

[0046] In this embodiment, the RRAM cell dielectric intermediate layers 540 and 541 can be made of a high-k gate dielectric. When referring to the dielectric layers 540 and 541, the term "high-k" refers to HfO x , TiO x NiO x WO x TaO x , VO x CuO x This refers to transition metal oxide materials such as HfOx, which can be deposited by atomic layer deposition (ALD) processes, or by other suitable processes or any suitable combination of many processes, including, but not limited to, thermal oxidation, chemical oxidation, thermal nitride formation, plasma oxidation, plasma nitriding, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source mist chemical deposition (LSMCD), and other similar deposition processes. In some embodiments, this HfOx dielectric material layer is conformal. "Conformal layer" means that the thickness of the layer is substantially the same on all surfaces (i.e., within the range of + / - 10%), or the variation is less than 15% of the nominal thickness. In one embodiment, the hafnium oxide dielectric layers 540, 541 have a thickness in the range of 2 nm to 20 nm, more preferably 3 nm to 10 nm, and even more preferably 4 nm to 6 nm, although smaller and larger thicknesses are also possible.

[0047] Figure 5(C) also shows the RRAM structure 575 formed as a result of further attaching and patterning the top electrode 550. In one embodiment, it is preferable that the top electrode serves the sole purpose of being an "inert" conductor, i.e., being a conductor. The top electrode 550 can be formed by attaching a conductive material or a number of conductive layers on top of the high-k dielectric intermediate layers 540, 541 and then patterning them.

[0048] In one embodiment, the top electrode 550 may include, but is not limited to, a material comprising tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), nickel (Ni), titanium (Ti), ruthenium (Ru), molybdenum (Mo), platinum (Pt), or other suitable conductive material. This metal contact may further include a barrier layer. This barrier layer may be titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), niobium nitride (NbN), tungsten nitride (WN), tungsten carbon nitride (WCN), or a combination thereof. In various embodiments, this barrier layer may be deposited in the trench by ALD, CVD, MOCVD, PECVD, or a combination thereof. In various embodiments, the electrical contact may be formed by forming a metal filler by ALD, CVD, PVD, plating, or a combination thereof.

[0049] Regarding the formation of the apical electrode 550, there is further a patterning step for patterning the apical electrode. Patterning can be performed by appropriate patterning techniques, but are not limited to, lithography and subsequent etching (e.g., reactive ion etching), sidewall image transfer (SIT), self-aligned double patterning (SADP), self-aligned quadruple patterning (SAQP), self-aligned multiple patterning (SAMP), etc.

[0050] In one embodiment, the hard mask layer 515 can be removed before the dielectric layer 540 is attached. When the hard mask layer is removed, a mini RRAM is formed between the top surface of the bottom electrode and the top electrode. In this case, the Ti% of the bottom electrode of the mini RRAM is uniform.

[0051] Figure 6 shows a schematic diagram of an RRAM array 600 having multiple RRAM cells 575, each RRAM cell 575 comprising a TiN bottom electrode with progressively increasing Ti% concentration, a uniform top TiN electrode, and an intermediate HfOx layer between the bottom and top electrodes. In this array, each RRAM cell is located at the intersection of word line rows WL1, WL2, ..., WLn connected to a column selection circuit 125 and bit line row conductors BL1, BL2, ..., BLn connected to a row selection circuit 126. As shown in Figure 6, the top electrode of a memory cell 575 along a single row is electrically connected to the bit line (BL) of that row in the array, for example, when programming the cell or reading a programmed value from the cell. Similarly, the bottom electrode of a memory cell 575 along a single column is electrically connected to the word line (WL) of that column in the array, for example, when programming the cell or reading a programmed value from the cell. The RRAM memory cell 575 is programmable to store resistance (or conductance) values ​​at array locations addressed by the column selection circuit 125 and the row selection circuit 126. Further sense circuits (not shown) can be implemented within the RRAM memory array to read the voltage or resistance values ​​programmed into the addressed RRAM cell 575. In detail, because the composition of the bottom electrodes of cell 575 differs, the oxygen vacancy concentrations of the corresponding sections of the RRAM differ, the total conductance of the RRAM cell is the sum of the conductances of each section of the RRAM cell, and the total resistance of the RRAM cell is equivalent to having many RRAM sections with different oxygen vacancy concentrations (thus resulting in non-uniform resistance changes in response to the number of pulses or voltage levels applied via connected word lines / bit lines). The RRAM cell 575 can be programmed such that conductive filaments can be progressively formed in different RRAM sections depending on the amplitude and duration of the applied electrical pulse or voltage, due to the different concentrations of oxygen vacancies in different RRAM sections having different Ti% within the bottom electrode. As a result, the total conductance of the RRAM cell 575 can be progressively adjusted to different values.Using Cell 575 for AI applications allows the weights of a neural network to be represented by the cell's conductance. This is advantageous because the gradual change in Cell 575's conductance enables gradual adjustment of the neural network's weights.

[0052] Figure 7 shows a resistive random-access memory cell structure 700 according to the second embodiment.

[0053] The RRAM cell structure 700 in Figure 7 includes a bottom electrode, which includes a stack 770 of bottom electrode portions containing three parallel-oriented bottom electrode portions or layers, for example, the shown metal nitride layers 702A, 702B, and 702C. This second embodiment may include a stack 770 of multiple layers, such as metal nitride material layers, where the metallic material concentration is uniform (fixed), but the value increases with each successive level, or the metallic material concentration gradually increases with each successive level. The RRAM structure 700 of the second embodiment is not limited to the three layers shown, and many layers are possible. In the illustrated embodiment, each layer may include a metallic nitride material, such as a TiN material layer. Each layer has a different Ti concentration, similar to the first RRAM cell structure in the embodiment of Figure 3. That is, the bottom layer 702A has a fixed value for the Ti element percentage concentration, or it increases continuously as the height of layer 702A increases. The fixed or continuously increasing percentage concentration of Ti element in the second layer 702B is greater than the Ti metal concentration in the preceding first layer 702A, and the Ti metal element percentage concentration in layer 702B can be increased as the height of layer 702B increases. The fixed or continuously increasing percentage concentration of Ti element in the top bottom electrode layer 702C is greater than the Ti metal concentration in the preceding layer 702B, and the Ti metal element percentage concentration in layer 702C can be increased as the height of layer 702C increases.

[0054] To prevent the interaction of metallic materials (e.g., Ti) between adjacent RRAM portions, an insulating layer 704, such as an insulating material insulating layer 704, is formed between each of the successive metal nitride material layers. In one embodiment, each insulating layer is a metal nitride insulator such as SiN, but other insulators can also be inserted between adjacent sections of the bottom electrode 770 where the Ti% varies.

[0055] Next to each of the bottom electrode layers 702A, 702B, and 702C, an intermediate layer 771 of a resistive switching dielectric material, such as a transition metal oxide such as HfO2, is formed to connect the sidewalls of each bottom electrode layer of the bottom electrode stack 770. Above the intermediate layer 771, a second (top) electrode 772 with a uniform concentration of metal nitride (e.g., TiN) is formed. In one embodiment, the second (top) electrode 772 layer has a high nitride concentration. In a second embodiment, it is understood that this memory cell can be configured in reverse, for example, with a bottom metal nitride electrode (e.g., TiN layer) with a uniform concentration and a top electrode TiN layer having multiple sections in which the Ti concentration gradually changes.

[0056] As shown in the RRAM bottom electrode structure 770, the oxygen vacancy concentration in the corresponding section of the RRAM cell varies as a result of different Ti concentrations in the first bottom electrode 770 section, and therefore the oxygen vacancy concentration in each TiN material layer with varying Ti% also varies. That is, as shown in Figure 7, the bottom electrode layer 702A with the lowest progressive Ti% concentration has the lowest amount of oxygen vacancies 712A, the subsequent bottom electrode layer 702B with the next highest progressive Ti% concentration has an increased amount of oxygen vacancies 712B, which is greater than the amount of oxygen vacancies 712A in the previous level, and the subsequent bottom electrode layer 702C with the next highest progressive Ti% concentration has an increased amount of oxygen vacancies 712C, which is greater than the amount of oxygen vacancies 712B in the previous level.

[0057] Given that the different Ti concentrations in the first bottom electrode stack structure 770 result in different oxygen vacancy concentrations in the corresponding layers 702A, 702B, and 702C of the RRAM cell, the total resistance of the formed RRAM is equivalent to having many parallel RRAMs with different oxygen vacancy concentrations (and therefore different resistance changes in response to the number of pulses or voltage applied), as shown in the equivalent conductance circuit configuration of Figure 4. The total conductance "G" of the RRAM cell 700 is the sum of the conductances (G1, G2, ..., Gn) of each section R1, R2, ..., Rn of the RRAM cell.

[0058] Each of the bottom electrode layers constituting the interlayer serves a dual purpose: (1) to be an electrode and (2) to be an oxygen scavenging layer. In other words, the bottom electrode interacts with the dielectric layer (e.g., HfOx) to create oxygen vacancies at the interface between the bottom electrode and HfOx.

[0059] Such RRAMs can be used in several applications (e.g., analog computing or neuromorphic applications) where a gradual change in RRAM resistance is desired instead of a simple binary resistance (high resistance / low resistance) state.

[0060] Figures 8(A) to 8(C) show a method step 800 for forming the semiconductor RRAM structure 700 of Figure 7 according to a second embodiment.

[0061] Figure 8(A) shows an exemplary structure formed by the initial steps of forming a material stack 800 in which bottom electrode material layers (e.g., bottom metal nitride electrode material layers 802, 804, 806; the corresponding metal material concentration increases in each layer) and hard mask dielectric material layers (e.g., dielectric material layers 803, 805) placed on a substrate 801 form alternating layers.

[0062] The material stack 800 present on the substrate 801 is formed BEOL. As described above, the material stack 800 consists of alternating layers of bottom electrode material layers (e.g., bottom metal nitride electrode material layers 802, 804, 806; the corresponding metal material concentration increases in each layer) and hard mask dielectric material layers (e.g., dielectric material layers 803, 805). In this application, the number of bottom electrode material layers and dielectric hard mask material layers in the material stack 800 can vary, as long as each hard mask insulating material layer is sandwiched between successive bottom electrode material layers. In the illustrated second embodiment, a top insulating material layer 807 is formed above the uppermost bottom electrode material layer 806.

[0063] Each hard mask insulating material layer may be made of a dielectric material such as silicon nitride, and is not limited to, but may also be other suitable dielectric materials including silicon carbide (SiC), silicon oxynitride (SiON), carbon-doped silicon oxide (SiOC), fluorine-doped silicon oxide (SiO:F), silicon-carbon nitride (SiCN), boron nitride (BN), silicon-boron nitride (SiBN), silicon-boron carbonitride (SiBCN), silicon oxycarbonitride (SiOCN), silicon oxide, and combinations thereof. Each hard mask layer 803, 805, and 807 may have a thickness of 20 nm to 100 nm, but other thicknesses are possible and can be used for the hard mask layers in this application.

[0064] Each bottom electrode material layer (e.g., electrode material layers 802, 804, 806) consists of a first electrode material such as tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), nickel (Ni), titanium (Ti), ruthenium (Ru), molybdenum (Mo), platinum (Pt), or other suitable conductive material. This metal contact may further include a barrier layer. This barrier layer may be titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), niobium nitride (NbN), tungsten nitride (WN), tungsten carbon nitride (WCN), or a combination thereof. In the exemplary second embodiment shown in Figure 7, the electrode material layers 802, 804, 806 constituting the interlayers are TiN with varying percentage (%) Ti concentrations, where the Ti material concentration gradually increases with each successive layer 802, 804, 806. For example, the Ti% of each successive layer can be fixed. For example, the bottom layer 802 has a Ti% concentration of 30%, the middle layer 804 has a Ti% concentration of 50%, and the top layer 806 has a Ti% concentration of 70%. In alternative embodiments, the Ti% can be further varied within each of layers 802, 804, and 806. For example, the increment of Ti% as a function of the height of layer 510 can be linear, sublinear, hyperlinear, or other appropriate form.

[0065] Each of the bottom electrode material layers 802, 804, and 806 can be formed using an adhesion process including, for example, CVD, PECVD, atomic layer deposition (ALD), sputtering, or plating. In one embodiment, the percentage concentration of Ti per unit of time is increased as each of the TiN layers 802, 804, and 806 grows vertically. The formed individual bottom electrode material layers 802, 804, and 806 can have a thickness (height) in the range of 5 nm to 60 nm, more preferably 10 nm to 30 nm, and most preferably 20 nm to 30 nm. The thicknesses of each of the TiN electrode material layers 802, 804, and 806 may be the same or different.

[0066] Figure 8(B) shows further processing steps for forming a vertical stack memory cell structure, including a bottom electrode stack 800 comprising bottom electrode layers 802, 804, 806, an intermediate layer 810, and hard mask layers 803, 805, 807. Although not shown, such processing steps resulting in the structure shown in Figure 8(B) may include patterning a photoresist layer (not shown) above the top hard mask layer 807 to expose the vertical sidewalls 860 of the bottom electrodes of the RRAM memory cell. This patterned photoresist can be used as an etching mask at this step of the present application and can be made of conventional photoresist material. In one embodiment, this etching mask can be formed by depositing layers of photoresist material and photolithography. Then, in one embodiment, by performing an anisotropic etching process, physically exposed portions of the structure not protected by the photoresist layer can be selectively removed to form the sidewalls 860 of the bottom electrodes and expose portions 817 of the substrate surface. In one example, reactive ion etching can remove the physically exposed portions of the bottom electrode layers 802, 804, and 806, the intermediate layer 810, and the hard mask layers 803, 805, and 807 that constitute the interlayers not protected by the patterned photoresist layer (not shown). In this specification, the patterned portion of the RRAM cell stack remaining beneath the patterned photoresist may be referred to as the patterned bottom electrode portion 825. The remaining patterned photoresist layer can be removed using a stripping process, such as ashing.

[0067] Figure 8(C) shows an RRAM structure 875 formed as a result of further deposition, lithography, and etching of various material layers, including deposition of a high-k dielectric material layer (e.g., hafnium oxide (HfOx)) 840 onto the top surface 830 of the uppermost hard mask layer 807, and onto the aligned and exposed sidewalls of the hard mask layer and the sidewalls of the bottom electrode 860, which were formed by etching the hard mask and bottom electrode layers constituting the interlayers. The deposition of the high-k dielectric material intermediate layer 840 includes deposition of a thin layer portion 841 onto the exposed surface portion 817 of the substrate remaining after the preceding anisotropic etching. Subsequently, the top electrode layer 850 of the RRAM cell 700 is formed on the outer surfaces of the high-k dielectric material intermediate layers 840, 841.

[0068] In this embodiment, the RRAM cell dielectric intermediate layers 840 and 841 can be made of a high-k gate dielectric. When referring to the dielectric layers 840 and 841, the term "high-k" refers to HfO x , TiO x NiO x WO x TaO x , VO x CuO x This refers to transition metal oxide materials such as HfOx, which can be deposited by atomic layer deposition (ALD) processes, or by other suitable processes or any suitable combination of many processes, including but not limited to thermal oxidation, chemical oxidation, thermal nitride formation, plasma oxidation, plasma nitriding, atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam deposition (MBD), pulsed laser deposition (PLD), liquid source mist chemical deposition (LSMCD), and other similar deposition processes. In some embodiments, the HfOx dielectric material layers 840, 841 are conformal layers having a thickness in the range of 2 nm to 20 nm, more preferably 3 nm to 10 nm, and even more preferably 4 nm to 6 nm, although smaller and larger thicknesses are also possible.

[0069] Figure 8(C) further shows the RRAM structure 875 that results from further deposition and patterning of the top electrode 850. In one embodiment, it is preferable that the top electrode is an "inert" conductor, i.e., the sole purpose of the top electrode is to be a conductor. The top electrode 850 can be formed by depositing a conductive material or a number of conductive layers on top of the high-k dielectric intermediate layers 840, 841 and then patterning them.

[0070] In one embodiment, the top electrode 850 may include, but is not limited to, materials comprising tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), nickel (Ni), titanium (Ti), ruthenium (Ru), molybdenum (Mo), platinum (Pt), or other suitable conductive materials. This metal contact may further include a barrier layer. This barrier layer may be titanium nitride (TiN), tantalum nitride (TaN), hafnium nitride (HfN), niobium nitride (NbN), tungsten nitride (WN), tungsten carbon nitride (WCN), or a combination thereof. In various embodiments, this barrier layer may be deposited in the trench by ALD, CVD, MOCVD, PECVD, or a combination thereof. In various embodiments, the electrical contact may be formed by forming a metal filler by ALD, CVD, PVD, plating, or a combination thereof.

[0071] Figure 9 shows a schematic diagram of an RRAM array 900 having multiple RRAM cells 875, each RRAM cell 875 consisting of a stack of interlayers of TiN material, each of which has a fixed (or fluctuating) Ti% concentration, a bottom metal nitride electrode, a uniform top TiN electrode, and an intermediate HfOx layer between the bottom and top electrodes. In this array, each RRAM cell is located at the intersection of word line columns WL1, WL2, ..., WLn connected to a column selection circuit 125 and bit line row conductors BL1, BL2, ..., BLn connected to a row selection circuit 126. As shown in Figure 9, the top electrode of a memory cell 875 along a single row is electrically connected to the bit line (BL) of that row in the array, for example, when programming the cell or reading a programmed value from the cell. Similarly, the bottom electrode layers of a memory cell 875 along a single column are electrically connected to the word line (WL) of that column in the array, for example, when programming the cell or reading a programmed value from the cell. In one embodiment, a wire network 905 is formed that electrically connects all of the TiN electrode layers 802, 804, and 806 of the cell together to the word line, respectively. The RRAM memory cell 875 is programmable to store resistance (or conductance) values ​​at array locations addressed, for example, by a column selection circuit 125 and a row selection circuit 126. Further sense circuits (not shown) can be implemented within the RRAM memory array to read the programmed voltage or resistance values ​​from the addressed RRAM cell 875. Because the composition of the respective bottom electrode layers 802, 804, and 806 of cell 875 is different, the oxygen vacancy concentrations in the corresponding sections of the RRAM are different, the total conductance of the RRAM cell is the sum of the conductances of each section of the RRAM cell, and the total resistance of the RRAM cell is equivalent to having many RRAM sections with different oxygen vacancy concentrations (and thus non-uniform resistance changes are realized in response to the number of pulses or voltage levels applied via the connected word lines / bit lines).The RRAM cell 875 can be programmed such that conductive filaments can be progressively formed in different RRAM sections depending on the amplitude and duration of the applied electrical pulse or voltage, due to the different concentrations of oxygen vacancies in different RRAM sections having different Ti% within the bottom electrode. As a result, the total conductance of the RRAM cell 875 can be progressively adjusted to different values. When the cell 875 is used for AI applications, the cell's conductance can represent the weights of the neural network. The progressive change in the conductance of the cell 875 is advantageous because it allows for progressive adjustment of the neural network weights.

[0072] Advantageously, the RRAM array embodiments shown in Figures 6 and 9 are used in neuromorphic computing applications, where resistive random-access memory devices are used as connections (i.e., synapses) between preneurons and postsneurons, representing connection weights in the form of device resistance. By connecting a large number of preneurons and postsneurons via a crossbar array of RRAM, fully connected neural networks can be naturally represented.

[0073] Although this application has been shown and described in particular with respect to its preferred embodiments, those skilled in the art will understand that the above-mentioned and other modifications to the form and details can be carried out without departing from the spirit and scope of this application. Accordingly, this application is intended to be within the scope of the appended claims, but is not limited to the exact form and details described and illustrated.

Claims

1. A resistive random-access memory device, A first electrode layer with a variable composition containing a metallic material, A resistive switching material layer on the side wall surface of the first electrode layer, The second electrode on the resistive switching material layer and Equipped with, The first electrode layer contains a metal nitride material, and the variation in the composition containing the metal material includes a gradual increase in the percentage concentration of the metal material in the first electrode layer in a direction parallel to the sidewall surface. Resistive random-access memory device.

2. The memory device according to claim 1, wherein the resistive switching material layer is made of a transition metal oxide material.

3. The first electrode layer further comprises a hard mask insulating layer formed on the surface of the first electrode layer, and the resistive switching material layer is further disposed on the top surface and side wall surface of the hard mask insulating layer. The memory device according to claim 1.

4. A memory device according to claim 1, comprising an array of addressable resistive random-access memory cells having selectable word line conductors and bit line conductors, wherein the selectable word line conductors and bit line conductors are connected to a circuit for programming the resistive random-access memory cells in the array, the first electrode layer is electrically connected to the word line conductors, and the second electrode is electrically connected to the bit line conductors.

5. The memory device according to claim 4, wherein the percentage concentration of the metallic material fluctuates in a direction parallel to the sidewall surface of the first electrode layer, resulting in different concentrations of oxygen vacancies in the corresponding sections of the memory device, so that the total conductance of the memory device is the sum of the conductances of each section of the memory device, and the memory device achieves non-uniformity of resistance changes in response to the number of pulses or voltage levels applied via connected word lines / bit lines.

6. A resistive random-access memory device, A stack in which a first electrode material layer and an insulating material layer between the first electrode material layers form an alternating layer, wherein the composition of each successive first electrode material layer in the stack, including the metal material, is different. A resistive switching material layer on the top surface and side wall surface of the stack, The second electrode on the resistive switching material layer and The resistive memory device is provided such that when a voltage is applied between the stack, which includes the first electrode material layer constituting the interlayer, and the second electrode, the conductance of the resistive memory device changes gradually. Resistive random-access memory device.

7. The memory device according to claim 6, wherein each of the first electrode material layers constituting the interlayers of the stack contains a metal nitride material, and the composition of the metal material differs, wherein the percentage concentration of the metal material changes and differs for each successive first electrode material layer constituting the interlayers.

8. The memory device according to claim 7, wherein the fixed percentage concentration of the metal material increases with each successive first electrode material layer constituting the interlayer.

9. The memory device according to claim 8, wherein the percentage concentration of the metal material is fixed at 15% in the first electrode material layer and fixed at 85% in the last electrode material layer.

10. The memory device according to claim 7, wherein the percentage concentration of the metal material gradually increases in each of the successive first electrode material layers constituting the interlayer.

11. A memory device according to claim 6, comprising an array of addressable resistive random-access memory cells having selectable word line conductors and bit line conductors, wherein the selectable word line conductors and bit line conductors are connected to a circuit for programming the resistive random-access memory cells in the array, each of the first electrode material layers constituting the interlayers of the stack is electrically connected to a word line conductor, and the second electrode is electrically connected to a bit line conductor.

12. A method for forming a memory device, A first electrode layer containing a metal material and having a variable composition is formed on the substrate. Patterning the first electrode layer to expose the side wall, The resistive switching material layer is attached to the side wall of the first electrode layer, and Forming a second electrode on the aforementioned resistance switching material layer. Includes, The first electrode layer contains a metal nitride material, and the variation in the composition containing the metal material includes a gradual increase in the percentage concentration of the metal material in the first electrode layer in a direction parallel to the sidewall surface. method.

13. The formation of a first electrode layer on the substrate further includes forming a hard mask insulating layer with its sidewalls exposed on the surface of the first electrode layer, wherein the resistive switching material layer is further disposed on the top surface and sidewall surface of the hard mask insulating layer. The method according to claim 12.

14. A method for forming a memory device, A first electrode layer containing a metal material and having a variable composition is formed on the substrate. Patterning the first electrode layer to expose the side wall, The resistive switching material layer is attached to the side wall of the first electrode layer, and Forming a second electrode on the aforementioned resistance switching material layer. Includes, The formation of a first electrode layer on the substrate includes forming a stack in which the first electrode layer and the hard mask insulating material layer between the first electrode layers form an alternating layer, wherein the composition of each of the successive first electrode layers in the stack, including the metal material, is different. method.

15. The method according to claim 14, wherein each of the first electrode layers constituting the interlayers of the stack contains a metal nitride material, and the composition of the metal material differs, wherein the percentage concentration of the metal material changes for each successive first electrode layer constituting the interlayers.

16. The successive first electrode layers constituting the interlayer are formed such that the percentage concentration of the metal material fixed to each first electrode layer increases, or the percentage concentration of the metal material gradually increases in each of the first electrode layers. The method according to claim 15, further comprising:

17. The formed memory device has selectable word line conductors and bit line conductors and is connected in an array of addressable resistive random-access memory cells, the selectable word line conductors and bit line conductors are connected to a circuit for programming the resistive random-access memory cells in the array, and the method is Connecting the first electrode layer to the word line conductor, and Connecting the second electrode to the bit wire conductor. The method according to claim 12, further comprising:

18. The method according to claim 17, wherein the first electrode layer comprises a metal nitride material, and the percentage concentration of the metal material varies vertically from the bottom to the top of the first electrode layer, so that the oxygen vacancy concentrations in the corresponding sections of the memory device are different, the total conductance of the memory device is the sum of the conductances of each section of the memory device, and the formed memory device exhibits non-uniformity of resistance changes in response to the number of pulses or voltage levels applied via connected word lines / bit lines.

19. The formed memory device has selectable word line conductors and bit line conductors and is connected in an array of addressable resistive random-access memory cells, the selectable word line conductors and bit line conductors are connected to a circuit for programming the resistive random-access memory cells in the array, and the method is Connecting each of the first electrode layers constituting the interlayers of the stack to a single word wire conductor, Connecting the second electrode to the bit wire conductor. The method according to claim 16, further comprising:

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