Semiconductor equipment

Abstract

Provided is a semiconductor device that enables miniaturization and high integration. The semiconductor device has: a first transistor that includes a first conductor, a first insulator, a first metal oxide, a second insulator, and a second conductor layered in this order from the bottom, and a third conductor and a fourth conductor covering part of the upper surface and the sides surfaces of the first metal oxide; a second transistor that includes a fifth conductor, a first insulator, a second metal oxide, a third insulator, and a sixth conductor layered in this order from the bottom, and a seventh conductor and an eighth conductor covering part of the upper surface and the side surfaces of the second metal oxide; and a third transistor that includes a ninth conductor, a first insulator, a second metal oxide, a fourth insulator, a tenth conductor, and an eighth conductor layered in this order from the bottom, and an eleventh conductor covering part of the upper surface and the side surfaces of the second metal oxide. One of the electrodes of a capacitor containing a material capable of exhibiting ferroelectric properties is electrically connected with the third conductor and the sixth conductor.

Description

[Technical Field]

[0001] One aspect of the present invention relates to a semiconductor device, a memory device, and an electronic device. Another aspect of the present invention relates to a method for manufacturing a semiconductor device.

[0002] It should be noted that one aspect of the present invention is not limited to the above-mentioned technical field. Examples of technical fields of one aspect of the present invention include semiconductor devices, display devices, light-emitting devices, energy storage devices, memory devices, electronic devices, lighting devices, input devices (e.g., touch sensors), input / output devices (e.g., touch panels), methods for driving them, or methods for manufacturing them.

[0003] In this specification, the term "semiconductor device" refers to any device that can function by utilizing semiconductor properties. Semiconductor elements such as transistors, as well as semiconductor circuits, computing devices, and memory devices, are all forms of semiconductor devices. Display devices (liquid crystal displays, light-emitting displays, etc.), projection devices, lighting devices, electro-optical devices, energy storage devices, memory devices, semiconductor circuits, imaging devices, and electronic devices may also be considered to have semiconductor devices. [Background technology]

[0004] In recent years, development of semiconductor devices such as LSIs (Large Scale Integrations), CPUs (Central Processing Units), and memory (storage devices) has progressed. These semiconductor devices are used in various electronic devices such as computers and personal digital assistants. In addition, various types of memory have been developed depending on the application, such as temporary storage during arithmetic processing and long-term data storage. Representative memory types include DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), and flash memory.

[0005] In addition, with the increase in the amount of data to be processed, semiconductor devices having a larger memory capacity are required. In Patent Document 1 and Non-Patent Document 1, memory cells formed by stacking transistors are disclosed.

Prior Art Documents

Patent Documents

[0006]

Patent Document 1

Non-Patent Documents

[0007]

Non-Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0008] One aspect of the present invention is to provide a semiconductor device capable of miniaturization or high integration as one of the problems. One aspect of the present invention is to provide a semiconductor device with a high operating speed as one of the problems. One aspect of the present invention is to provide a semiconductor device having good electrical characteristics as one of the problems. One aspect of the present invention is to provide a semiconductor device with little variation in the electrical characteristics of transistors as one of the problems. One aspect of the present invention is to provide a highly reliable semiconductor device as one of the problems. One aspect of the present invention is to provide a semiconductor device with a large on-current as one of the problems. One aspect of the present invention is to provide a semiconductor device with low power consumption as one of the problems. One aspect of the present invention is to provide a novel semiconductor device as one of the problems.

[0009] One aspect of the present invention is to provide a method for manufacturing a semiconductor device with a small number of process steps as one of the problems.

[0010] One aspect of the present invention aims to provide a storage device with a large storage capacity. Another aspect of the present invention aims to provide a storage device with a small footprint. Another aspect of the present invention aims to provide a highly reliable storage device. Another aspect of the present invention aims to provide a storage device with low power consumption. Another aspect of the present invention aims to provide a novel storage device.

[0011] Furthermore, the description of these problems does not preclude the existence of other problems. One aspect of the present invention solves one or more of these problems, but it is not necessary to solve all of them. It is possible to extract other problems from the description, drawings, and claims. [Means for solving the problem]

[0012] One aspect of the present invention comprises a first transistor, a second transistor, and a capacitor, wherein the first transistor comprises a first insulator, a first metal oxide on the first insulator, a second insulator on the first metal oxide, a first conductor on the second insulator, a second conductor covering a portion of the upper surface and a portion of the side surface of the first metal oxide, and a third conductor covering a portion of the upper surface and a portion of the side surface of the first metal oxide, and the second transistor comprises a first insulator, a first metal oxide on the first insulator, a third insulator on the first metal oxide, a fourth conductor on the third insulator, a third conductor, and a portion of the upper surface of the first metal oxide A semiconductor device comprising a fifth conductor covering part of its surface and sides, a third conductor shared by a first transistor and a second transistor, a first metal oxide shared by a first transistor and a second transistor, the first metal oxide having a channel-forming region of the first transistor and a channel-forming region of the second transistor, a first insulator having a region superimposed on the first metal oxide, and a capacitance comprising a sixth conductor, a seventh conductor, and a ferroelectric material located between the sixth and seventh conductors, wherein the first and sixth conductors are electrically connected.

[0013] Furthermore, in the above configuration, materials that may possess ferroelectric properties include hafnium oxide, zirconium oxide, and HfZrO X It is preferable that X is one or more, selected from (where X is a real number greater than 0).

[0014] Furthermore, in the above configuration, the material that may have ferroelectric properties is preferably a material containing oxygen, hafnium, and zirconium.

[0015] Furthermore, in the above configuration, the material that may have ferroelectric properties is preferably a material obtained by adding one or more elements selected from zirconium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium to hafnium oxide.

[0016] Furthermore, in the above configuration, the material that may have ferroelectric properties is preferably a material obtained by adding one or more elements selected from hafnium, silicon, aluminum, gadolinium, yttrium, lanthanum, and strontium to zirconium oxide.

[0017] Furthermore, in the above configuration, it is preferable that the eighth conductor has a region sandwiched between the sixth conductor and the tenth conductor in a plan view.

[0018] Furthermore, in the above configuration, it is preferable to have a third transistor, the first insulator being made of a material capable of ferroelectricity, the third transistor comprising an eighth conductor, a first insulator on the eighth conductor, a second metal oxide on the first insulator, a fifth insulator on the second metal oxide, a ninth conductor on the fifth insulator, and a sixth conductor covering a part of the upper surface and a part of the side surface of the second metal oxide, wherein the sixth conductor has a region in contact with the upper surface of the first insulator, the seventh conductor has a region in contact with the lower surface of the first insulator, the eighth conductor has a region in contact with the lower surface of the first insulator, and the first insulator having a region superimposed on the second metal oxide and a region superimposed on the seventh conductor.

[0019] Furthermore, in the above configuration, it is preferable that the seventh conductor and the eighth conductor have titanium nitride.

[0020] Furthermore, in the above configuration, it is preferable to have a plurality of sequentially stacked memory layers, each of the plurality of memory layers having a first transistor, a second transistor, and a capacitor, and the fifth conductor of the second transistor in each of the plurality of memory layers being electrically connected to one another. [Effects of the Invention]

[0021] According to one aspect of the present invention, a semiconductor device that can be miniaturized or highly integrated can be provided. According to one aspect of the present invention, a semiconductor device with a high operating speed can be provided. According to one aspect of the present invention, a semiconductor device having good electrical characteristics can be provided. According to one aspect of the present invention, a semiconductor device with less variation in the electrical characteristics of transistors can be provided. According to one aspect of the present invention, a highly reliable semiconductor device can be provided. According to one aspect of the present invention, a semiconductor device with a large on-current can be provided. According to one aspect of the present invention, a semiconductor device with low power consumption can be provided. According to one aspect of the present invention, a novel semiconductor device can be provided.

[0022] According to one aspect of the present invention, a method for manufacturing semiconductor devices with a reduced number of steps can be provided.

[0023] According to one aspect of the present invention, a storage device with a large storage capacity can be provided. According to one aspect of the present invention, a storage device with a small footprint can be provided. According to one aspect of the present invention, a storage device with high reliability can be provided. According to one aspect of the present invention, a storage device with low power consumption can be provided. According to one aspect of the present invention, a novel storage device can be provided.

[0024] Furthermore, the description of these effects does not preclude the existence of other effects. One aspect of the present invention solves one or more of these effects, but does not necessarily have to have all of them. It is possible to extract other effects from the description, drawings, and claims. [Brief explanation of the drawing]

[0025] Figures 1A and 1B show examples of storage devices. Figure 2A shows an example of a memory cell circuit configuration. Figure 2B is a graph showing the amount of polarization. Figures 3A, 3B, 3C, 3D, and 3E show examples of memory cell operation. Figure 4 shows an example of memory cell operation. Figures 5A, 5B, and 5C show examples of memory cell operation. Figures 6A, 6B, and 6C show examples of memory cell operation. Figure 7 shows an example of memory cell operation. Figure 8 is a cross-sectional view showing an example of the configuration of a semiconductor device. Figure 9 is a cross-sectional view showing an example of the configuration of a semiconductor device. Figure 10A is a cross-sectional view showing an example of the configuration of a semiconductor device. Figure 10B is a cross-sectional view showing an example of the configuration of a transistor. Figure 11 is a cross-sectional view showing an example of the configuration of a semiconductor device. Figure 12 is a cross-sectional view showing an example of the configuration of a semiconductor device. Figure 13 shows an example of a semiconductor device configuration. Figure 14 shows an example of the configuration of a semiconductor device. Figure 15 is a cross-sectional view showing an example of the configuration of a semiconductor device. Figures 16A and 16B are plan views showing examples of semiconductor device configurations. Figures 17A and 17B are plan views showing examples of semiconductor device configurations. Figures 18A and 18B show examples of semiconductor devices. Figures 19A and 19B show examples of electronic components. Figures 20A to 20J show examples of electronic devices. Figures 21A to 21E show examples of electronic devices. Figures 22A to 22C show examples of electronic devices. Figure 23 shows an example of space equipment. [Modes for carrying out the invention]

[0026] Embodiments will be described in detail with reference to the drawings. However, it will be readily apparent to those skilled in the art that the present invention is not limited to the following description, and that its form and details can be modified in various ways without departing from the spirit and scope of the present invention. Accordingly, the present invention shall not be construed as being limited to the descriptions of the embodiments shown below.

[0027] In the invention described below, the same reference numerals are used in common across different drawings for identical parts or parts having similar functions, and repeated explanations are omitted. Furthermore, when referring to similar functions, the same hatching pattern may be used, and reference numerals may not be assigned.

[0028] Furthermore, the position, size, and scope of each component shown in the drawings may not represent the actual position, size, and scope for the sake of ease of understanding. Therefore, the disclosed invention is not necessarily limited to the position, size, and scope disclosed in the drawings.

[0029] In this specification, the ordinal numbers "first," "second," etc., are used for convenience only and do not limit the number of components or the order of components (for example, process order or stacking order). Also, the ordinal numbers attached to components in one part of this specification may not be the same as the ordinal numbers attached to those components in other parts of this specification or in the claims.

[0030] It should be noted that the terms "film" and "layer" can be interchanged depending on the context or situation. For example, the term "conductive layer" can be changed to "conductive film." Or, for example, the term "insulating film" can be changed to "insulating layer."

[0031] In this specification, phrases indicating arrangement such as "above," "below," "upward," or "downward" are sometimes used for convenience to explain the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the phrases explained in this specification are not limited to those described and can be appropriately rephrased depending on the situation. For example, the expression "insulator located above the conductor" can be rephrased as "insulator located below the conductor" by rotating the orientation of the drawing shown by 180 degrees.

[0032] (Embodiment 1) In this embodiment, a storage device according to one aspect of the present invention will be described with reference to the drawings.

[0033] Figure 1A shows a schematic perspective view of a storage device according to one embodiment of the present invention. Figure 1B shows a block diagram of a storage device according to one embodiment of the present invention.

[0034] The storage device 100 shown in Figures 1A and 1B includes a drive circuit layer 50 and an n-layer storage layer 11. Each storage layer 11 has a memory cell array 15. The memory cell array 15 has a plurality of memory cells 10.

[0035] The n-layer storage layer 11 is provided on the drive circuit layer 50. By providing the n-layer storage layer 11 on the drive circuit layer 50, the occupied area of ​​the storage device 100 can be reduced. In addition, the storage capacity per unit area can be increased.

[0036] In this embodiment, the first memory layer 11 is referred to as memory layer 11_1, the second memory layer 11 as memory layer 11_2, and the third memory layer 11 as memory layer 11_3. Furthermore, the kth memory layer 11 (where k is an integer between 1 and n) is referred to as memory layer 11_k, and the nth memory layer 11 as memory layer 11_n. In this embodiment and others, when describing matters relating to the entire n-layer memory layer 11, or when referring to matters common to each layer of the n-layer memory layer 11, it may simply be written as "memory layer 11".

[0037] <Example of configuration of the drive circuit layer 50> The drive circuit layer 50 includes a PSW22 (power switch), a PSW23, and a peripheral circuit 31. The peripheral circuit 31 includes a peripheral circuit 41, a control circuit 32, and a voltage generation circuit 33.

[0038] In the storage device 100, each circuit, each signal, and each voltage can be appropriately selected or omitted as needed. Alternatively, other circuits or other signals may be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are external input signals, and signal RDA is an external output signal.

[0039] Signal CLK is the clock signal. Signals BW, CE, and GW are control signals. Signal CE is the chip enable signal, signal GW is the global write enable signal, and signal BW is the byte write enable signal. Signal ADDR is the address signal. Signal WDA is the write data, and signal RDA is the read data. Signals PON1 and PON2 are power gating control signals. Signals PON1 and PON2 may be generated by the control circuit 32.

[0040] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the storage device 100. For example, the control circuit performs logical operations on signals CE, GW, and BW to determine the operating mode of the storage device 100 (e.g., write operation, read operation). Alternatively, the control circuit 32 generates control signals for the peripheral circuit 41 so that this operating mode is executed.

[0041] The voltage generation circuit 33 has the function of generating a negative voltage. The signal WAKE has the function of controlling the input of the signal CLK to the voltage generation circuit 33. For example, when a high-level signal is applied to the signal WAKE, the signal CLK is input to the voltage generation circuit 33, and the voltage generation circuit 33 generates a negative voltage.

[0042] The peripheral circuit 41 is a circuit for writing and reading data to and from the memory cell 10. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0043] The row decoder 42 and column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying the row to access, and the column decoder 44 is a circuit for specifying the column to access. The row driver 43 has the function of selecting the wiring WWL (write word line) or wiring RWL (read word line) specified by the row decoder 42. The column driver 45 has the function of writing data to the memory cell 10, reading data from the memory cell 10, and holding the read data. The column driver 45 has the function of selecting the wiring WBL (write bit line) and wiring RBL (read bit line) specified by the column decoder 44.

[0044] The input circuit 47 has the function of holding the signal WDA. The data held by the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) to be written to the memory cell 10. The data (Dout) read by the column driver 45 from the memory cell 10 is output to the output circuit 48. The output circuit 48 has the function of holding Dout. The output circuit 48 also has the function of outputting Dout to the outside of the storage device 100. The data output from the output circuit 48 is the signal RDA.

[0045] PSW22 has the function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has the function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 100 is VDD, and the low power supply voltage is GND (ground potential). VHM is a high power supply voltage used to raise the word line to a high level, and is higher than VDD. The on / off state of PSW22 is controlled by signal PON1, and the on / off state of PSW23 is controlled by signal PON2. In Figure 1B, the number of power supply domains to which VDD is supplied in the peripheral circuit 31 is set to 1, but it can be multiple. In this case, a power switch can be provided for each power supply domain.

[0046] <Example configuration of memory layer 11> An example configuration of a storage layer 11 with n layers will be described. Each of the n layers of the storage layer 11 has a memory cell array 15. The memory cell array 15 has multiple memory cells 10. Figure 1(B) shows an example in which the memory cell array 15 has multiple memory cells 10 arranged in a matrix of p rows and q columns (where p and q are integers of 2 or more).

[0047] Note that rows and columns extend in mutually orthogonal directions. In this embodiment, the X direction is defined as "rows" and the Y direction as "columns," but the X direction may be defined as "columns" and the Y direction as "rows."

[0048] In Figure 1B, the memory cell 10 located in the 1st row and 1st column is shown as memory cell 10[1,1], and the memory cell 10 located in the pth row and qth column is shown as memory cell 10[p,q]. Furthermore, the memory cell 10 located in the ith row and jth column (where i is an integer between 1 and p, and j is an integer between 1 and q) is shown as memory cell 10[i,j].

[0049] An example of a memory cell circuit configuration is shown in Figure 2A.

[0050] The memory cell 10 has transistors M1, M2, M3, and capacitance C1. A memory cell composed of three transistors and one capacitance is also called a 3Tr1C type memory cell. Therefore, the memory cell 10 shown in this embodiment is a 3Tr1C type memory cell. Here, it is preferable to use a ferroelectric material as the dielectric of capacitance C1.

[0051] In memory cell 10[i,j], the gate of transistor M1 is electrically connected to wiring WWL[j], and either the source or drain is electrically connected to wiring WBL[i,s]. Wiring WBL[i,s] is electrically connected to either the source or drain of transistor M1 in memory cell 10[i,j] of another stacked memory layer 11. Figure 2A shows an example configuration where wiring WWL[j] has the function of supplying the gate potential of transistor M1. Capacitor C1 has a pair of electrodes. One electrode of capacitor C1 is electrically connected to wiring PL[j], and the other electrode is electrically connected to the other source or drain of transistor M1. Figure 2A shows an example configuration where wiring PL[j] has the function of supplying potential to one electrode of capacitor C1. Furthermore, the gate of transistor M2 is electrically connected to the other electrode of capacitor C1, one of its source or drain is electrically connected to one of its source or drain of transistor M3, and the other of its source or drain is electrically connected to wiring SL[i,s]. Wiring SL[i,s] is electrically connected to the other of its source or drain of transistor M2 in memory cell 10[i,j] of another stacked memory layer 11. Also, the gate of transistor M3 is electrically connected to wiring RWL[j], and the other of its source or drain is electrically connected to wiring RBL[i,s]. Wiring RBL[i,s] is electrically connected to the other of its source or drain of transistor M3 in memory cell 10[i,j] of another stacked memory layer 11.

[0052] In memory cell 10[i,j], the region where the other electrode of capacitance C, the other source or drain of transistor M1, and the gate of transistor M2 are electrically connected to each other and always at the same potential is called the "node SN".

[0053] In memory cell 10[i,j+1], the gate of transistor M1 is electrically connected to wiring WWL[j+1], and either the source or drain is electrically connected to wiring WBL[i,s+1]. Wiring WBL[i,s+1] is electrically connected to either the source or drain of transistor M1 in memory cell 10[i,j+1] of another stacked memory layer 11. Figure 2A shows an example configuration where wiring WWL[j+1] has the function of supplying the gate potential of transistor M1. One electrode of capacitor C1 is electrically connected to wiring PL[j+1], and the other electrode is electrically connected to the other source or drain of transistor M1. For example, Figure 2A shows an example configuration where wiring PL[j+1] has the function of supplying potential to one electrode of capacitor C1. Furthermore, the gate of transistor M2 is electrically connected to the other electrode of capacitor C1, one of its source or drain is electrically connected to one of its source or drain of transistor M3, and the other of its source or drain is electrically connected to wiring SL[i,s+1]. Wiring SL[i,s+1] is electrically connected to the other of the source or drain of transistor M2 in memory cell 10[i,j+1] of the other stacked memory layer 11. Also, the gate of transistor M3 is electrically connected to wiring RWL[j+1], and the other of its source or drain is electrically connected to wiring RBL[i,s]. Wiring RBL[i,s] is electrically connected to the other of the source or drain of transistor M3 in memory cell 10[i,j+1] of the other stacked memory layer 11.

[0054] As described above, wiring RBL[i,s] is electrically connected to the other source or drain of transistor M3 of memory cell 10[i,j] and to the other source or drain of transistor M3 of memory cell 10[i,j+1]. Therefore, wiring RBL[i,s] functions as wiring that transmits signals to memory cells 10 located in adjacent rows. In Figure 2A, wiring RBL[i,s] functions as wiring that transmits signals to memory cells 10[i,j] and memory cells 10[i,j+1]. Although not shown, wiring WBL[i,s] functions as wiring that transmits signals to memory cells 10 located in adjacent rows, in this case for example, memory cell 10[i,j-1] and memory cell 10[i,j], and wiring WBL[i,s+1] functions as wiring that transmits signals to memory cells 10 located in adjacent rows, in this case for example, memory cell 10[i,j+1] and memory cell 10[i,j+2]. Although not shown in the diagram, wiring SL[i,s] functions as wiring that transmits signals to memory cells 10 located in adjacent rows, for example, memory cell 10[i,j-1] and memory cell 10[i,j], and wiring SL[i,s+1] functions as wiring that transmits signals to memory cells 10 located in adjacent rows, for example, memory cell 10[i,j+1] and memory cell 10[i,j+2].

[0055] In memory cell 10[i,j+1], the region where the other electrode of capacitance C1, the other source or drain of transistor M1, and the gate of transistor M2 are electrically connected to each other and are always at the same potential is called node SN.

[0056] Furthermore, as shown in Figure 2A, transistors M1, M2, and M3 may each be transistors having back gates. The gate and back gate are arranged so as to sandwich the semiconductor channel formation region between them. The gate and back gate are formed of a conductor. The back gate can be made to function in the same way as the gate. Also, the threshold voltage of the transistor can be changed by changing the potential of the back gate. The potential of the back gate may be the same as the gate potential, or it may be the ground potential or any other potential.

[0057] Note that transistors M1, M2, and M3 do not necessarily need to have back gates.

[0058] Furthermore, since the gate and back gate are formed from a conductor, they also have the function of preventing electric fields generated outside the transistor from acting on the semiconductor in which the channel is formed (particularly an electrostatic shielding function against static electricity). In other words, it is possible to suppress fluctuations in the electrical characteristics of the transistor due to the influence of external electric fields such as static electricity. In addition, by providing a back gate, the change in the threshold voltage of the transistor before and after BT (Bias Temperature) testing can be reduced.

[0059] For example, by using a transistor with a back gate in transistor M1, the influence of the external electric field is reduced, and transistor M1 can stably maintain the off state. Therefore, the data written to node SN can be stably retained. By providing a back gate, the operation of the memory cell 10 is stabilized, and the reliability of the memory device including the memory cell 10 can be improved.

[0060] Similarly, by using a transistor with a back gate for transistor M3, the influence of the external electric field is reduced, and transistor M3 can stably maintain the off state. Therefore, the leakage current between wiring RBL and wiring SL is reduced, and the power consumption of the memory device including memory cell 10 can be reduced.

[0061] A semiconductor device according to one aspect of the present invention has a transistor (also called an "OS transistor") in which an oxide semiconductor, a type of metal oxide, is used in the semiconductor layer where the channel is formed. Compared to a transistor (also called a Si transistor) that uses silicon in the semiconductor layer where the channel is formed, the OS transistor has a higher dielectric breakdown voltage between the source and drain. By using an OS transistor for transistor M1, sufficient resistance to the inversion polarization voltage of the ferroelectric layer can be achieved, and the rewrite endurance of the memory cell 10 can be improved. Furthermore, because the frequency characteristics of the OS transistor are high, the semiconductor device can read and write data at high speed.

[0062] It is preferable to use OS transistors as transistors M1, M2, and M3. Since oxide semiconductors have a bandgap of 2 eV or more, the off-current is significantly low. Therefore, the power consumption of the memory cell 10 can be reduced. Therefore, the power consumption of the storage device 100 including the memory cell 10 can be reduced.

[0063] The semiconductor layer on which the channels of transistors M1, M2, and M3 are formed may be a single-crystal semiconductor, a polycrystalline semiconductor, a microcrystalline semiconductor, or an amorphous semiconductor, either individually or in combination. Examples of semiconductor materials include silicon or germanium. Compound semiconductors such as silicon-germanium, silicon carbide, gallium arsenide, oxide semiconductors, or nitride semiconductors may also be used.

[0064] Furthermore, a memory cell containing an OS transistor can be called an "OS memory." Similarly, a storage device 100 containing such memory cells can also be called an "OS memory."

[0065] Furthermore, OS transistors operate stably even in high-temperature environments and exhibit minimal characteristic fluctuations. For example, the off-current hardly increases even in high-temperature environments. Specifically, the off-current hardly increases even at ambient temperatures between room temperature and 200°C. Also, the on-current does not decrease significantly even in high-temperature environments. Therefore, OS memory operates stably even in high-temperature environments, resulting in high reliability.

[0066] Furthermore, OS transistors have superior electrical characteristics compared to Si transistors in high-temperature environments. Specifically, even at high temperatures of 100°C to 200°C, preferably 125°C to 150°C, the ratio of on-current to off-current is large, enabling good switching operation.

[0067] In one embodiment of the present invention, it is preferable to use a ferroelectric material as the dielectric material of capacitance C1.

[0068] By using a ferroelectric material as the dielectric of capacitance C1, the amount of charge that can be held in capacitance C1 can be increased compared to when a paraelectric material is used as the dielectric. Therefore, a memory device according to one aspect of the present invention can retain data for a long period of time. This reduces the frequency of refresh (rewriting data to the cell), and thus reduces the power consumption of the memory device according to one aspect of the present invention. Furthermore, a capacitance with a ferroelectric layer between the first electrode and the second electrode can retain data for a long period of time without adopting a structure to increase capacitance, such as a trench structure. This makes it possible to create a memory device with an easy-to-manufacture structure. A capacitance equipped with a ferroelectric layer is sometimes called a ferroelectric capacitance (ferroelectric capacitor).

[0069] In a capacitor equipped with a ferroelectric layer, when a voltage (electric field) is applied between the two electrodes flanking the ferroelectric layer, the polarization direction and amount of the ferroelectric layer change according to the direction and amount of the applied voltage. By utilizing the change in the polarization state of the ferroelectric layer, a signal (data) is stored (written) between the two electrodes flanking the ferroelectric layer. After storage (writing) to the capacitor, even if the voltage between the two electrodes flanking the ferroelectric layer is reduced to zero, polarization remains within the ferroelectric layer (residual polarization). To rewrite the polarization, a voltage to reverse the polarization (polarization reversal voltage) is applied.

[0070] Figure 2B is a graph showing the magnitude of polarization (amount of polarization) in the ferroelectric layer in response to the electric field. In Figure 2B, the horizontal axis represents the electric field E applied to the ferroelectric layer, and the vertical axis represents the amount of polarization P of the ferroelectric layer.

[0071] As the electric field applied to the ferroelectric layer increases, the polarization of the ferroelectric layer increases. H After applying an electric field E, if the electric field applied to the ferroelectric layer is gradually reduced, the positive charge will be biased towards one electrode of the capacitor and the negative charge towards the other electrode of the capacitor, so that a positive polarization remains when the electric field becomes 0. As the electric field applied to the ferroelectric layer is reduced, the polarization of the ferroelectric layer decreases. L After applying the electric field E, as the electric field applied to the ferroelectric layer is increased, the positive charge becomes biased towards the other electrode side of the capacitance C1, and the negative charge becomes biased towards the one electrode side of the capacitance. Therefore, when the electric field becomes 0, negative polarization remains. H and electric field E L The voltage applied to this can be called the polarization reversal voltage. By applying the polarization reversal voltage to the capacitor C1, data can be written to the memory cell 10.

[0072] When reading data from the memory cell 10, if a voltage exceeding the polarization inversion voltage is applied to the capacitor C1, the polarization state (polarization direction of the remanent polarization) of the ferroelectric layer changes, so an operation for returning the polarization state again becomes necessary. That is, when reading data from the memory cell 10 by applying a voltage exceeding the polarization inversion voltage to the capacitor C1, data refresh is required.

[0073] In one aspect of the present invention, when reading data from the memory cell 10, a voltage not exceeding the polarization inversion voltage is applied to the capacitor 101, and the polarization state of the ferroelectric layer is operated so as to return to the original state even when the electric field returns to 0. Specifically, when reading data from the memory cell 10, an electric field E R is applied, and the change amount of polarization (P R , P H , P L ) when the electric field E R is used to read data from the memory cell 10. The electric field E

[0074] can be, for example, an electric field (anti-electric field) where the polarization becomes 0. R The voltage for applying the electric field E H to the ferroelectric layer can be a voltage that does not cause polarization inversion. By applying a voltage that does not cause polarization inversion to the capacitor C1, the change in potential corresponding to the change amount of polarization (P L , P R ) can be amplified to read data from the memory cell 10. In FIG. 2B, a negative electric field is illustrated as the electric field E

[0075] , but a positive electric field may also be used.In other words, in one aspect of the present invention, in addition to the advantages of ferroelectric capacitance, such as the ability to retain data for a long period of time, data can be read from the memory cell 10 without so-called destructive reading. In other words, since there is no change in the polarization state before and after data reading, data refreshing is not necessary, and data can be retained for a long period of time. Therefore, a storage device equipped with the memory cell 10 has excellent reliability in the data that is read. Furthermore, a storage device equipped with the memory cell 10 can achieve low power consumption. In addition, the area of ​​the capacitance can be reduced compared to capacitances having paraelectric properties.

[0076] Materials that can be used in ferroelectric layers and possess ferroelectric properties include hafnium oxide, zirconium oxide, and HfZrO X Examples include materials obtained by adding element J1 (where element J1 is zirconium (Zr), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to hafnium oxide, and materials obtained by adding element J2 (where element J2 is hafnium (Hf), silicon (Si), aluminum (Al), gadolinium (Gd), yttrium (Y), lanthanum (La), strontium (Sr), etc.) to zirconium oxide.

[0077] Here, the ratio of the number of hafnium atoms to the number of atoms of element J1 can be set as appropriate. For example, the ratio of hafnium atoms to zirconium atoms can be set to 1:1 or close to it. Similarly, the ratio of zirconium atoms to the number of atoms of element J2 can be set as appropriate; for example, the ratio of zirconium atoms to the number of atoms of element J2 can be set to 1:1 or close to it.

[0078] Furthermore, as a material that can possess ferroelectric properties, PbTiO XPiezoelectric ceramics having a perovskite structure, such as barium strontium titanate (BST), strontium titanate, lead zirconate titanate (PZT), strontium bismuth tantalate (SBT), bismuth ferrite (BFO), and barium titanate, may also be used. Furthermore, as a material capable of ferroelectricity, for example, a plurality of materials selected from the materials listed above, or a laminated structure consisting of a plurality of materials selected from the materials listed above, may be used. Incidentally, hafnium oxide, zirconium oxide, HfZrO X Materials such as hafnium oxide with added element J1 may have different crystal structures (properties) depending not only on the film deposition conditions but also on various processes. Therefore, in this specification, we refer not only to materials that exhibit ferroelectricity as ferroelectrics, but also to materials that can possess ferroelectricity or materials that are made to possess ferroelectricity.

[0079] Furthermore, aluminum scandium nitride (Al) is an example of a material that may possess ferroelectric properties. 1-a Sc a N b(where a is a real number greater than 0 and less than 0.5, and b is 1 or a value in its vicinity. Hereinafter simply referred to as AlScN.)) Al-Ga-Sc nitride, Ga-Sc nitride, etc., can be used. In addition, as a material that may possess ferroelectricity, a metal nitride having element M1, element M2, and nitrogen can be used. Here, element M1 is one or more selected from aluminum (Al), gallium (Ga), indium (In), etc. Furthermore, element M2 is one or more selected from boron (B), scandium (Sc), yttrium (Y), lanthanides (lanthanum (La), cerium (Ce), praseodymium (Pr), neodymium (Nd), promethium (Pm), samarium (Sm), europium (Eu), gadolinium (Gd), terbium (Tb), dysprosium (Dy), holmium (Ho), erbium (Er), thulium (Tm), ytterbium (Yb), and lutetium (Lu)), actinides (15 elements from actinium (Ac) to lawrencium (Lr)), titanium (Ti), zirconium (Zr), hafnium (Hf), vanadium (V), niobium (Nb), tantalum (Ta), chromium (Cr), etc. The ratio of the number of atoms of element M1 to the number of atoms of element M2 can be set as appropriate. Furthermore, metal oxides containing element M1 and nitrogen may exhibit ferroelectric properties even without containing element M2. Additionally, as a material that can exhibit ferroelectric properties, a material to which element M3 is added to the above metal nitride can be used. Element M3 is one or more selected from magnesium (Mg), calcium (Ca), strontium (Sr), zinc (Zn), cadmium (Cd), etc. Here, the ratio of the number of atoms of element M1, the number of atoms of element M2, and the number of atoms of element M3 can be set as appropriate. Since the above metal nitride contains at least a group 13 element and nitrogen, which is a group 15 element, such metal nitrides are sometimes called group 13-15 ferroelectrics or group 13 nitride ferroelectrics.

[0080] Furthermore, perovskite-type oxynitrides such as SrTaO2N and BaTaO2N, and GaFeO3 with a κ-alumina structure can be used as materials that may possess ferroelectric properties.

[0081] Furthermore, a material that may possess ferroelectric properties can be, for example, a mixture or compound consisting of multiple materials selected from the materials listed above. Alternatively, a material that may possess ferroelectric properties can be a laminated structure consisting of multiple materials selected from the materials listed above. Incidentally, the materials listed above are also sometimes referred to as materials that may possess ferroelectric properties or materials that are made to possess ferroelectric properties.

[0082] Among these, a hafnium oxide layer, or a layer containing both hafnium oxide and zirconium oxide, is preferred as a ferroelectric layer because it can exhibit ferroelectric properties even when processed into a thin film of a few nanometers. By using a ferroelectric layer that can be made into a thin film, it can be used as a memory device combined with miniaturized transistors.

[0083] Furthermore, HfZrO is a material that can possess ferroelectric properties. X When using this method, it is preferable to deposit the film using atomic layer deposition (ALD), particularly thermal ALD. Furthermore, when depositing a ferroelectric material using thermal ALD, it is preferable to use a precursor that does not contain hydrocarbons (also called Hydrocarbon, HC). If the ferroelectric material contains hydrogen and / or carbon, it may inhibit the crystallization of the ferroelectric material. For this reason, as described above, it is preferable to reduce the concentration of hydrogen and / or carbon in the ferroelectric material by using a hydrocarbon-free precursor. For example, chlorine-based materials can be used as hydrocarbon-free precursors. Materials containing hafnium oxide and zirconium oxide (HfZrO) are also suitable as ferroelectric materials. x When using ), either HfCl4 or ZrCl4, or both, can be used as the precursor. The ALD method is a film deposition method that involves alternately introducing a precursor and a reactant (e.g., an oxidizing agent), and the film thickness can be adjusted by the number of times this cycle is repeated, thus enabling precise film thickness control.

[0084] Furthermore, it is preferable to heat-treat the film formed by the ALD method. For example, the heat treatment can be performed using an RTA (Rapid Thermal Annealing) apparatus, a resistance heating furnace, or a microwave heating apparatus. In particular, using an RTA apparatus is preferable because it may result in a film with particularly excellent ferroelectric properties.

[0085] Furthermore, when forming a film using a material capable of ferroelectricity, a film with high purity intrinsic ferroelectricity can be formed by thoroughly eliminating impurities in the film, in this case, hydrogen, hydrocarbons, and at least one of carbon. Moreover, the manufacturing process compatibility between a film with high purity intrinsic ferroelectricity and the high purity intrinsic oxide semiconductor shown in the embodiments described later is very high. Therefore, a method for manufacturing memory devices with high productivity can be provided.

[0086] Furthermore, HfZrO is a material that can possess ferroelectric properties. X When using this method, it is preferable to alternately deposit hafnium oxide and zirconium oxide in a 1:1 composition using the thermal ALD method.

[0087] Furthermore, when depositing a ferroelectric material using the thermal ALD method, H2O or O3 can be used as the oxidizing agent. However, the oxidizing agent for the thermal ALD method is not limited to these. For example, the oxidizing agent for the thermal ALD method may include one or more selected from O2, O3, N2O, NO2, H2O, and H2O2.

[0088] Furthermore, the crystal structure of a material that may possess ferroelectricity is not particularly limited. For example, the crystal structure of a material that may possess ferroelectricity may be one or more selected from cubic, tetragonal, orthorhombic, and monoclinic systems. In particular, a material that may possess ferroelectricity is preferred if it has an orthorhombic crystal structure, as this is because ferroelectricity is exhibited in such materials. Alternatively, a material that may possess ferroelectricity may have a composite structure having both an amorphous structure and a crystalline structure.

[0089] Wiring WBL is a wire that receives a signal (data signal) corresponding to the data to be written to the memory cell 10. Wiring WBL is sometimes also called the write bit line. Wiring WBL can be shared with other wires, such as wiring RBL.

[0090] The WWL wiring is the wiring that provides the signal (selection signal) for writing data to the memory cell 10. The WWL wiring is sometimes also called the write word line.

[0091] The wiring PL is a wiring to which signals (control signals) for writing data to the memory cell 10 and signals (control signals) for reading data from the memory cell 10 are supplied. The wiring PL has the function of controlling the polarization state of the ferroelectric layer of the capacitor C1, and is sometimes called a polarization control line.

[0092] Wiring SL is a wire that is supplied with a constant potential for reading data from memory cell 10. Wiring SL has the function of supplying current to wiring RBL according to the data stored in memory cell 10, and is sometimes called a source wire.

[0093] The RBL wiring is a wiring to which signals corresponding to data read from the memory cell 10 are supplied. The RBL wiring is sometimes also called the read bit line. The RBL wiring can be shared with other wiring, such as the WBL wiring.

[0094] In the memory cell 10 shown in Figure 2A, each transistor is assumed to be an n-channel transistor. For example, if transistor M1 is an n-channel transistor, setting the wiring WWL to a high potential (H-level potential, also called H-level) will turn transistor M1 ON. Conversely, setting the wiring WWL to a low potential (L-level potential, also called L-level) will turn transistor M1 OFF. The same applies to transistor M3.

[0095] Data is written to the memory cell 10 according to the direction of the electric field applied to the ferroelectric layer of the capacitor C1, which is given by the potential of node SN and the potential of wiring PL. As will be described in detail later, the data signal to be written applies a polarization reversal voltage to the capacitor C1. The ferroelectric layer of the capacitor C1 can take on different polarization states depending on the data signal. This polarization state can cause the capacitance value of the capacitor C1 to differ. This difference in polarization state and capacitance value of the capacitor C1 is maintained even when the electric field applied to the capacitor C1 is zero.

[0096] Data is read from the memory cell 10 by utilizing capacitive coupling at capacitance C1 when the potential of wiring PL is changed. The potential of wiring PL is set so that the voltage applied to capacitance C1 does not reverse the polarization of the ferroelectric layer. By setting node SN to an electrically floating state and changing the potential of wiring PL, capacitive coupling occurs at capacitance C1. Therefore, the potential of node SN changes in accordance with the change in the potential of wiring PL. The change in the potential of node SN differs depending on the capacitance value of capacitance C1. Therefore, the gate potential of transistor M2 can be made different depending on the stored data. The difference in the gate potential of the transistor results in a difference in the amount of current flowing between the source and drain of transistor M2. Data can be read from the memory cell 10 due to this difference in current.

[0097] Figure 3A is a timing chart illustrating the data writing operation in the memory cell 10 shown in Figure 2A. Figure 3A shows the signals or potentials of wiring WWL, WBL, PL, node SN, RBL, RWL, and SL in the memory cell 10. Figure 3A also shows "data1" and "data0" as the data to be written to the memory cell 10. "data1" is shown as a high-level signal, and "data0" is shown as a low-level signal.

[0098] In period P11 shown in Figure 3A, wiring WWL is set to the H level. Wiring WBL is supplied with a signal corresponding to data1 or data0 to be written to memory cell 10, and a potential corresponding to this signal is supplied to node SN. Wiring PL is set to the H level. Wirings RBL, RWL, and SL are set to the L level.

[0099] H-level signals applied to wiring WBL, wiring PL, and node SN are shown as potential VPL1, and L-level signals are shown as potential 0V. Potential VPL1 is the potential at which a reversal polarization voltage is applied to the ferroelectric layer of capacitance C1 when potential VPL1 is applied to one electrode of capacitance C1 and potential 0V is applied to the other electrode. Potential VPL1 is preferably 2.5V or higher.

[0100] When a potential VPL1 is applied and a voltage exceeding the inversion polarization voltage is applied to the capacitor C1, transistors M1 to M3 are preferably transistors with excellent resistance to high voltages (voltage withstand voltage). By configuring transistors M1 to M3 with OS transistors, which have superior voltage withstand voltage characteristics compared to Si transistors, the rewrite endurance of the memory cell 10 can be improved.

[0101] During period P11, when wiring PL is at the H level and node SN is at the H level, the potential shown in Figure 3B is applied to the electrodes of capacitor C1. As shown in Figure 3B, both electrodes at both ends of capacitor C1 are at the same potential as potential VPL1, so no voltage exceeding the reversal polarization voltage is applied, and no electric field is generated in the ferroelectric layer. On the other hand, during period P11, when wiring PL is at the H level and node SN is at the L level, the potential shown in Figure 3C is applied to the electrodes of capacitor C1. As shown in Figure 3C, the electrode of capacitor C1 is subjected to a voltage VPL1 which is the reversal polarization voltage, and an electric field E is generated in the ferroelectric layer. L This occurs. Therefore, the polarization state corresponding to data0 is written to the capacitor C1.

[0102] In period P12 shown in Figure 3A, the wiring WWL is kept at the H level, as in period P11. The wiring WBL is supplied with a signal corresponding to data1 or data0 to be written to the memory cell 10, as in period P11, and a potential corresponding to this signal is supplied to node SN. The wiring PL is kept at the L level. The wirings RBL, RWL, and SL are kept at the L level.

[0103] During period P12, when the wiring PL is at the L level and the node SN is at the H level, the potential shown in Figure 3D is applied to the electrodes of capacitor C1. As shown in Figure 3D, an electric field opposite to that in period P11 is applied to the pair of electrodes of capacitor C1, and a voltage VPL1 that becomes a reversal polarization voltage is applied to the electrodes of capacitor C1, and an electric field E is applied to the ferroelectric layer. H This occurs. As a result, the polarization state corresponding to data1 is written to capacitor C1. On the other hand, during period P12, when wiring PL is at the L level and node SN is at the L level, as shown in Figure 3E, both electrodes of capacitor C1 are at the same potential as 0V, so no voltage exceeding the reversal polarization voltage is applied, and no electric field is generated for the ferroelectric layer.

[0104] Figure 4 is a timing chart illustrating the data read operation in the memory cell 10 shown in Figure 2. Figure 4 shows the signals or potentials of wiring WWL, WBL, PL, node SN, RBL, RWL, and SL in the memory cell 10. Figure 4 also shows "data1" and "data0" as data read from the memory cell 10. "data1" and "data0" correspond to the data stored as the polarization state of the ferroelectric layer with capacitance C1 during the data write operation.

[0105] In period P21 shown in Figure 4, wiring WWL is at the L level. Nodes SN are electrically floating. Wiring PL is set to potential VPL2. Wirings WBL, RWL, and SL are at the L level. Wiring RBL is precharged to a potential that fluctuates due to the current flowing through transistors M2 and M3 during periods prior to P21. For example, it is precharged to a potential lower than potential VPL1.

[0106] As shown in Figure 5A, node SN in the memory cell 10 has a parasitic capacitance C2, such as the gate capacitance of transistor M2. When node SN is in an electrically floating state and the potential of one electrode of capacitance C1 is changed, the capacitive coupling between capacitance C1 and capacitance C2 causes the potential of node SN to fluctuate.

[0107] Potential V at node SN SN Change ΔV SN The capacity value C of capacity C1 is FE Capacity C2, capacity value C S This is determined by the change in voltage VPL2, which corresponds to the voltage across capacitance C1, and can be expressed by equation (1).

[0108]

number

[0109] Capacity value C of capacity C1 FE This is determined by the polarization state of the ferroelectric layer of capacitance C1. This polarization state differs depending on the written data "data1" or "data0". Therefore, the potential V of node SN depends on the written data "data1" or "data0". SN This can be made different. The capacity value C of the parasitic capacity (capacity C2) of node SN. S The capacitance value C of the capacitor C1 having a ferroelectric layer FE It is smaller in comparison. The potential difference due to the difference in capacitance value corresponding to the polarization state of capacitance C1 is expressed as Vdata0 or Vdata1, and the potential V of node SN is smaller. SN It appears there.

[0110] During period P22 shown in Figure 4, the wiring RWL is set to the H level. The source and drain of transistor M3 become conductive. A current flows through transistor M2 corresponding to the potential of node SN.

[0111] By setting the voltage of wiring PL to VPL2, the potential of node SN can take on two states: potential Vdata0 or potential Vdata1 (>Vdata0), as shown in Figures 5B and 5C. A current Idata0 or Idata1 (>Idata0) flows through transistor M2, corresponding to the potential Vdata0 or Vdata1. The flow of current Idata0 or Idata1 changes the potential of the pre-charged wiring RBL. The potential of wiring RBL after the change is determined by the magnitude of the current (Idata0 or Idata1) that flowed through transistor M2. The potential of wiring RBL after the change and the reference voltage V REF By comparing the magnitude of these values, it is possible to determine whether the written data is "data1" or "data0" and read the data from the memory cell 10. In Figure 4, when current Idata0 flows through transistor M2, for example, the potential of wiring RBL is the reference voltage V REF If the current Idata1 becomes higher, for example, the potential of wiring RBL will reach the reference voltage V after a certain period of time. REF It will become lower.

[0112] Furthermore, it is preferable that the potential of the pre-charged wiring RBL be lower than the potential VPL1. This configuration reduces fluctuations in the potential of the wiring RBL. Therefore, even if the circuit having a transistor electrically connected to the wiring RBL is a miniaturized transistor such as a Si transistor with a low breakdown voltage, it can still operate without problems.

[0113] Note that the operation of reading data from memory cell 10 in Figure 2A can be configured in a different way. For example, it may be operated as shown in the timing chart in Figure 6A. In Figure 6A, unlike Figure 4, the potential of wiring SL is increased, and with wiring RBL precharged to 0V, a current corresponding to the potential of node SN is flowed. In other words, as shown in Figures 6B and 6C, a current Idata0 or Idata1 (>Idata0) corresponding to the potential Vdata0 or Vdata1 flows through transistor M2 from wiring SL to wiring RBL. The potential of wiring RBL and the reference voltage V REF By comparing the magnitudes of these values, data can be read from the memory cell 10. In Figure 6A, when current Idata0 flows through transistor M2, for example, the potential of wiring RBL is the reference voltage V REF When the current Idata1 becomes lower, for example, the potential of wiring RBL will be lower than the reference voltage V after a certain period of time. REF It will get higher.

[0114] Furthermore, the data reading operation of the memory cell 10 in Figure 2A can be performed using a different method. For example, it may be operated as shown in the timing chart in Figure 7.

[0115] Figure 7 corresponds to the operation method in Figure 4 with the addition of the operation of setting the potential of node SN. During period P20 in Figure 7, the potential V of the wiring WBL is the potential to be set. PRE_SN The wiring WWL is set to the H level. The potential of node SN is potential V. PRE_SN This is how it works. Afterwards, the wiring WWL is set to an L level, and node SN is left electrically floating. By doing this, it becomes easier to set the fluctuating potential of node SN, which changes when the potential of wiring PL is changed during period P21, to the current through which transistor M2 flows.

[0116] This embodiment can be combined with other embodiments as appropriate.

[0117] (Embodiment 2) In this embodiment, a semiconductor device according to one aspect of the present invention will be described with reference to the drawings.

[0118] One aspect of the present invention relates to a semiconductor device having a memory layer on a substrate. The memory layer includes a first transistor, a second transistor, a third transistor, and a capacitor, which together constitute a memory cell. Since the semiconductor device according to one aspect of the present invention has a memory cell, it has the function of storing data. Therefore, the semiconductor device according to one aspect of the present invention can be called a memory device.

[0119] In one embodiment of the present invention, a plurality of memory layers having the above configuration are stacked and provided. That is, a plurality of memory layers having the above configuration are provided, for example, in a direction perpendicular to the substrate surface. This makes it possible to increase the storage capacity of the semiconductor device without increasing the occupied area of ​​the memory cells compared to the case where there is only one memory layer. Therefore, the occupied area per bit is reduced, and a small semiconductor device with a large storage capacity can be realized. OS transistors can be formed by thin-film methods such as sputtering in the semiconductor layer on which the channel is formed. Furthermore, OS transistors can be formed at low temperatures, for example, at temperatures of 750°C or lower. Therefore, a plurality of layers having OS transistors can be stacked and provided. OS transistors can be suitably used in the memory layers that are stacked and provided in plurality.

[0120] OS transistors can be freely arranged by stacking them on circuits using Si transistors, making integration easy. Examples of silicon that can be used include amorphous silicon (sometimes called hydrogenated amorphous silicon), microcrystalline silicon, polycrystalline silicon, and monocrystalline silicon. Furthermore, OS transistors can be manufactured using the same manufacturing equipment as Si transistors, thus enabling low-cost production.

[0121] Gain cell type memory cells require at least two transistors per memory cell, making it difficult to increase the number of memory cells that can be placed per unit area. However, by using OS transistors for the transistors that make up the memory cell 10, multiple memory cell arrays 15 can be stacked. In other words, the amount of data that can be stored per unit area can be increased.

[0122] When multiple memory layers are stacked, the write bit lines and read bit lines can be provided, for example, in a direction perpendicular to the substrate surface. For example, when forming a semiconductor device having n layers (where n is an integer of 2 or more), the write bit lines and read bit lines can be formed by providing an opening that penetrates the n layers of memory and forming a conductor inside the opening. In one embodiment of the present invention, a conductor is provided having a region that functions as a write bit line, such that it has regions in contact with the upper surface and side surface of the first conductor.

[0123] <Example of semiconductor device configuration> The following describes an example of the configuration of a semiconductor device according to one aspect of the present invention.

[0124] Figure 8 is a cross-sectional view showing an example of the configuration of a semiconductor device according to one embodiment of the present invention. The semiconductor device shown in Figure 8 can be applied to the circuit configuration of the memory cell shown in the previous embodiment.

[0125] The semiconductor device shown in Figure 8 includes an insulator 210 on a substrate (not shown), a conductor 209a and a conductor 209b embedded in the insulator 210, an insulator 212 on the insulator 210, an insulator 214 on the insulator 212, an n-layer memory layer 11 on the insulator 214, a conductor 240a extending in the Z direction (the Z direction will be explained later) so as to penetrate the n-layer, and a conductor 240b electrically connected to the conductor 209a, an insulator 181 on the memory layer 11_n, an insulator 183 on the insulator 181, the conductor 240a, and the conductor 240b, and an insulator 185 on the insulator 183. The components of the semiconductor device in this embodiment may each have a single-layer structure or a multilayer structure.

[0126] Hereafter, when describing common features of components distinguished by letters of the alphabet, the letters may be omitted and a symbol may be used. For example, when describing features common to conductor 209a and conductor 209b, it may be written as conductor 209.

[0127] Each of the memory layers 11_1 to 11_n is provided with a memory cell array having multiple memory cells. Each memory cell has transistors 201, 202, 203, and capacitors 101. Conductor 240a has a region that functions as a write bit line, and conductor 240b has a region that functions as a read bit line. Transistors 201, 202, 203, and capacitor 101 can correspond to transistors M1, M2, M3, and capacitor C1 of the memory cell 10 shown in the previous embodiment, respectively. Conductor 240a and conductor 240b can correspond to wiring WBL and wiring RBL, respectively.

[0128] In this specification, the direction parallel to the channel length of the illustrated transistor is defined as the X direction, and the direction parallel to the channel width of the illustrated transistor is defined as the Y direction. The X and Y directions can be perpendicular to each other. Furthermore, the direction perpendicular to both the X and Y directions, i.e., perpendicular to the XY plane, is defined as the Z direction. The X and Y directions can be, for example, parallel to the substrate surface, and the Z direction can be perpendicular to the substrate surface.

[0129] Conductors 209a and 209b function as parts of circuit elements such as switches, transistors, capacitors, inductors, resistors, and diodes, as well as wiring, electrodes, or terminals.

[0130] Figure 8 shows the bottom memory layer 11_1, the memory layer 11_2 above memory layer 11_1, and the top memory layer 11_n, among the n memory layers.

[0131] Conductors 209a and 209b are electrically connected to a drive circuit for driving memory cells provided in the memory layer 11. The drive circuit is provided below conductors 209a and 209b. By increasing the number of stacked memory layers 11 (the number of n), the storage capacity of the memory device can be increased without increasing the area occupied by the memory cells. Therefore, the area occupied per bit is reduced, and a small semiconductor device with a large storage capacity can be realized.

[0132] Transistors 201, 202, and 203 are provided on an insulator 214. Here, transistors 202 and 203 share a portion of the layer. Capacitors 101 are provided above transistors 201 to 203.

[0133] Figure 9 shows an example in which connecting electrodes 240c and 240d are present instead of conductors 240a and 240b. The memory layer 11 has a conductor 233a that is electrically connected to a conductor 242a (detailed in Figure 10) of transistor 201, and a conductor 233b that is electrically connected to a conductor 242e (detailed in Figure 10) of transistor 203. The conductors 233a and 233b of the k-th memory layer 11 (where k is an integer between 1 and n) are denoted as conductor 233a[k] ​​and conductor 233b[k], respectively. The connecting electrode 240c has conductors 233a[1] to conductor 233a[n] (not shown), which are electrically connected. Furthermore, the connecting electrode 240d has conductors 233b[1] to 233b[n] (not shown), which are electrically connected.

[0134] Figure 10A is a cross-sectional view showing an example configuration of conductor 209a, conductor 209b, insulator 210, insulator 212, insulator 214, and memory layer 11_1. As shown in Figure 10A, insulator 282 is provided on transistors 201 to 203, and insulator 285 is provided on insulator 282.

[0135] Transistors 201, 202, and 203 each have a conductor 205a1 on an insulator 214, an insulator 222 on the conductor 205a1, an insulator 224 on the insulator 222, a metal oxide 230 (metal oxide 230a and metal oxide 230b) on the insulator 224, a conductor 242 covering a part of the side surface of the insulator 224, and a part of the top surface and part of the side surface of the metal oxide 230, an insulator 253 on the metal oxide 230, an insulator 254 on the insulator 253, and a conductor 260 on the insulator 254. Here, transistor 201 has conductors 242a and 242b as conductors 242, transistor 202 has conductors 242c and 242d as conductors 242, and transistor 203 has conductors 242d and 242e as conductors 242. Transistors 202 and 203 share metal oxide 230 and conductor 242d, respectively. In Figure 10, etc., the conductors 205a1 of transistors 201, 202, and 203 are shown as conductor 205a1_1, conductor 205a1_2, and conductor 205a1_3, respectively. Also, the conductors 260 of transistors 201, 202, and 203 are shown as conductor 260_1, conductor 260_2, and conductor 260_3, respectively. Furthermore, the metal oxide 230 possessed by transistor 201 is denoted as 230_1, and the metal oxide 230 shared by transistor 202 is denoted as 230_2. The insulator 222 has a region sandwiched between the conductor 205a1 and the metal oxide 230 of transistor 201 and overlapping with the conductor 260 of transistor 201, a region sandwiched between the conductor 205a1 and the metal oxide 230 of transistor 202 and overlapping with the conductor 260 of transistor 202, and a region sandwiched between the conductor 205a1 and the metal oxide 230 of transistor 203 and overlapping with the conductor 260 of transistor 203. In addition, in the configuration shown in Figure 10A, it is preferable that the conductor 205a1 has a region in contact with the lower surface of the insulator 222.

[0136] An insulator 216a with an opening is provided on the insulator 214, and a conductor 205a1 is embedded inside the opening. An insulator 222 is provided on the conductor 205a1 and on the insulator 216a. Insulators 275 are provided on conductors 242a to 242e, and an insulator 280 is provided on the insulator 275. Insulators 253, 254, and 260 are embedded inside the openings provided in insulators 280 and 275. An insulator 282 is provided on the insulator 280 and on the conductor 260. The conductor 205a1 may have a region in contact with the side surface of insulator 216a. Insulator 253 may have a region in contact with at least a portion of the side surface of conductor 242, the side surface of insulator 275, and the side surface of insulator 280.

[0137] The metal oxide 230 has a region that functions as a channel-forming region for transistor 201, transistor 202, or transistor 203. Note that for transistors 201, 202, and 203, semiconductors such as single-crystal silicon, polycrystalline silicon, or amorphous silicon may be used instead of the metal oxide 230, for example, low-temperature polysilicon (LTPS).

[0138] Conductor 242a has a region that functions as either the source electrode or the drain electrode of transistor 201. Conductor 242b has a region that functions as either the source electrode or the drain electrode of transistor 201. Conductor 242c has a region that functions as either the source electrode or the drain electrode of transistor 202. Conductor 242d has a region that functions as either the source electrode or the drain electrode of transistor 202, and as either the source electrode or the drain electrode of transistor 203. Conductor 242e has a region that functions as either the source electrode or the drain electrode of transistor 203.

[0139] The conductor 260 has a region that functions as the first gate electrode of transistor 201, transistor 202, or transistor 203. The insulators 253 and 254 each have a region that functions as the first gate insulator of transistor 201, transistor 202, or transistor 203.

[0140] The conductor 205a1 has a region that functions as the second gate electrode of transistor 201, transistor 202, or transistor 203. The insulator 222 has a region that functions as the second gate insulator of transistor 201, a region that functions as the second gate insulator of transistor 202, and a region that functions as the second gate insulator of transistor 203. The insulator 224 has a region that functions as the second gate insulator of transistor 201, transistor 202, or transistor 203.

[0141] In this specification, the first gate electrode may be referred to as the front gate electrode or simply the gate electrode, and the second gate electrode may be referred to as the back gate electrode. Alternatively, the first gate electrode may be referred to as the back gate electrode, and the second gate electrode as the front gate electrode or simply the gate electrode.

[0142] Transistors 202 and 203 are adjacent to each other and, as mentioned above, share the metal oxide 230 and the conductor 242d, respectively. This allows two transistors (transistors 202 and 203) to be formed in an area smaller than the area of ​​two transistors (for example, the area of ​​1.5 transistors). Therefore, transistors can be arranged at a higher density than when transistors 202 and 203 do not share the metal oxide 230 and the conductor 242d, enabling high integration in semiconductor devices.

[0143] Furthermore, the conductor 242d is positioned in the region between the conductor 260 of transistor 202 and the conductor 260 of transistor 203. Therefore, an n-type region (low-resistance region) can be formed in the region overlapping with the conductor 242d of the metal oxide 230. In particular, an n-type region can be formed in the region overlapping with the conductor 242d of the metal oxide 230b. Also, current can be passed between transistor 202 and transistor 203 through the conductor 242d. Therefore, compared to a configuration in which two Si transistors are connected in series, the resistance component between transistor 202 and transistor 203 can be made extremely small.

[0144] The conductor 242d covers a portion of the side surface of the metal oxide 230. For example, although not shown, in a cross-section of the transistor 202 in the channel width direction, including the conductor 242d, the conductor 242d covers the side surface of the metal oxide 230.

[0145] An insulator 285 is provided on the insulator 282. The insulators 280, 282, and 285 are provided with openings that reach the conductor 242b, and the conductor 231 is embedded inside these openings. In addition, the insulators 282 and 285 are provided with openings that reach the conductor 260 of the transistor 202, and the conductor 232 is provided inside these openings.

[0146] Capacitor 101 comprises an insulator 285, a conductor 231, a conductor 161 on the conductor 232, an insulator 163 on the conductor 161, and a conductor 162 on the insulator 163.

[0147] The insulator 163 has a region sandwiched between the conductor 161 and the conductor 162.

[0148] The conductor 161 has a region that functions as one electrode (also called the lower electrode) of the capacitor 101. The insulator 163 has a region that functions as the dielectric of the capacitor 101. The conductor 162 has a region that functions as the other electrode (also called the upper electrode) of the capacitor 101. The capacitor 101 constitutes a MIM capacitor.

[0149] Conductor 231 electrically connects conductor 242b and conductor 161. Conductor 232 electrically connects conductor 260 of transistor 202 and conductor 161. Thus, conductor 242b, which has a region that functions as either the source electrode or the other drain electrode of transistor 201, is electrically connected to conductor 260, which has a region that functions as the gate electrode of transistor 202, via conductors 231, 161, and 232.

[0150] An insulator 287 is provided on the conductor 162 and the insulator 163. An insulator 215 is provided on the insulator 287. An insulator 216b with an opening is provided on the insulator 215, and a conductor 205a2 is embedded inside the opening.

[0151] Hereafter, when describing matters common to conductor 205a1 and conductor 205a2, the term "conductor 205a" may be used.

[0152] Conductors 242a, 242b, 242c, and 242e extend beyond the metal oxide 230, which functions as a semiconductor layer, and cover a portion of the top and side surfaces of the metal oxide 230. Therefore, conductors 242a, 242b, 242c, and 242e also function as wiring. For example, conductor 240a is provided with a region that functions as a write bit line, having a region that contacts a portion of the top, side, and bottom surfaces of conductor 242a. Similarly, conductor 240b is provided with a region that functions as a read bit line, having a region that contacts a portion of the top, side, and bottom surfaces of conductor 242e. Conductor 242d can also function as wiring. Other wiring may also function as wiring.

[0153] Since the conductor 240a, which functions as a write bit line, has a region that contacts part of the top, side, and bottom surfaces of the conductor 242a, it is not necessary to provide a separate connecting electrode between the write bit line and the conductor 242a. Similarly, since the conductor 240b, which functions as a read bit line, has a region that contacts part of the top, side, and bottom surfaces of the conductor 242e, it is not necessary to provide a separate connecting electrode between the read bit line and the conductor 242e. Therefore, the occupied area of ​​the memory cell array can be reduced. In addition, the integration density of memory cells can be improved, and the storage capacity can be increased. Note that the conductor 240a has a region that contacts one or more, more preferably two or more, of the top, side, and bottom surfaces of the conductor 242a, and the conductor 240b has a region that contacts one or more, more preferably two or more, of the top, side, and bottom surfaces of the conductor 242e. By having the conductor 240a in contact with multiple surfaces of the conductor 242a, the contact resistance between the conductor 240a and the conductor 242a can be reduced, and by having the conductor 240b in contact with multiple surfaces of the conductor 242e, the contact resistance between the conductor 240b and the conductor 242e can be reduced.

[0154] Here, the insulator 212 and the insulator 214 are provided with an opening 291a having a region overlapping with the conductor 209a, and an opening 291b having a region overlapping with the conductor 209b. The insulator 222 is provided with an opening 292a having a region overlapping with the conductor 209a and the opening 291a, and an opening 292b having a region overlapping with the conductor 209b and the opening 291b. The insulator 282 is provided with an opening 293a having a region overlapping with the conductor 209a, the opening 291a, and the opening 292a, and an opening 293b having a region overlapping with the conductor 209b, the opening 291b, and the opening 292b. Furthermore, the insulator 215 is provided with an opening 294a having a region that overlaps with the conductors 209a, opening 291a, opening 292a, and opening 293a, and an opening 294b having a region that overlaps with the conductors 209b, opening 291b, opening 292b, and opening 293b. Conductors 240a are provided inside openings 291a to 294a, and conductors 240a are provided inside openings 291b to 294b. Note that the insulator 212 does not necessarily need to have an opening 291a.

[0155] Furthermore, in openings 291a and 291b, the sides of insulator 212 and insulator 214 are covered by insulator 216a. Also, in opening 292a, the sides of insulator 222 are covered by conductor 242a, and in opening 292b, the sides of insulator 222 are covered by conductor 242b. Also, in openings 293a and 293b, the sides of insulator 282 are covered by insulator 285. Furthermore, in openings 294a and 294b, the sides of insulator 215 are covered by insulator 216b.

[0156] Based on the above, it can be said that the insulator 216a is provided so as to cover the upper surface and a portion of the side surface of the insulator 214. Furthermore, it can be said that the conductors 242a and 242e are provided so as to cover the upper surface and a portion of the side surface of the insulator 222. In addition, it can be said that the insulator 285 is provided so as to cover the upper surface and a portion of the side surface of the insulator 282, and the insulator 216b is provided so as to cover the upper surface and a portion of the side surface of the insulator 215.

[0157] In a semiconductor device according to one aspect of the present invention, the conductors 240a and 240b are provided such that they have regions in contact with at least a portion of the sides of insulator 212, insulator 216a, insulator 275, insulator 285, insulator 287, and insulator 216b. Furthermore, as described above, the conductors 240a and 240b are provided such that they have regions in contact with the sides of conductor 242a and conductor 242e. In addition, the conductors 240a and 240b are provided so as not to be in contact with insulator 212, insulator 214, insulator 282, and insulator 215.

[0158] By configuring the semiconductor device according to one aspect of the present invention as described above, when creating an opening that penetrates the memory layers 11_1 to 11_n and reaches the conductor 209a after forming the memory layer 11_n shown in Figure 8, it becomes unnecessary to process the insulators 212, 282, and 215. Therefore, even if materials with different processing conditions than the other insulators are used for insulators 212, 282, and 215, the above opening can be formed under a single condition. As a result, the range of materials that can be used for the insulator can be broadened. Furthermore, by embedding a conductive film inside the above opening, conductors 240a and 240b can be formed.

[0159] Figure 10B is a cross-sectional view showing an example of the configuration of the transistor shown in Figure 10A in the channel width direction, or Y direction.

[0160] In the example shown in Figure 10B, an insulator 212 is provided on an insulator 210, an insulator 214 is provided on an insulator 212, an insulator 216a is provided on an insulator 214, and a conductor 205a1 is provided inside an opening in an insulator 216a. In addition, an insulator 222 is provided on the conductor 205a1 and on an insulator 216a, an insulator 224 and an insulator 275 are provided on an insulator 222, and a metal oxide 230 is provided on an insulator 224. The sides of the insulator 224, and the top and sides of the metal oxide 230 are covered by insulators 253, 254, and conductor 260. Insulators 253, 254, and conductor 260 are provided inside an opening 258 of an insulator 280 provided on an insulator 275. Insulators 282 are provided on insulator 253, insulator 254, conductor 260, and insulator 280, and insulator 285 is provided on insulator 282.

[0161] Here, the metal oxide 230 is covered not only on its top surface but also on its sides by the conductor 260, which has a region that functions as a first gate electrode.

[0162] In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric field of at least the first gate electrode is called a surrounded channel (S-channel) structure. Furthermore, the S-channel structure disclosed in this specification has a structure different from that of the Fin-type structure and the planar-type structure. On the other hand, the S-channel structure disclosed in this specification can also be considered as a type of Fin-type structure. In this specification, the Fin-type structure refers to a structure in which the gate electrode is arranged to surround at least two or more sides (specifically, two, three, or four sides) of the channel. By adopting the Fin-type structure and the S-channel structure, it is possible to increase resistance to short-channel effects, or in other words, to create a transistor in which short-channel effects are less likely to occur.

[0163] By making the transistor in the semiconductor device of this embodiment an S-channel structure, the channel formation region can be electrically surrounded. Since the S-channel structure electrically surrounds the channel formation region, it can be said to be substantially equivalent to a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By making the transistor an S-channel, GAA, or LGAA structure, the channel formation region formed at or near the interface between the oxide and the gate insulator can be made the entire bulk of the oxide. Therefore, it becomes possible to improve the current density flowing through the transistor, which can be expected to improve the on-current of the transistor or increase the field-effect mobility of the transistor.

[0164] Although Figure 10B illustrates an S-channel transistor, the semiconductor device according to one aspect of the present invention is not limited to this. For example, the transistor structure that can be used in one aspect of the present invention may be one or more selected from the planar structure, fin structure, and GAA structure.

[0165] The cross-sectional shape of the metal oxide 230 is not limited to the configuration shown in Figure 10B. For example, the metal oxide 230 may have a curved surface between its side and top surfaces. This can improve the coverage of the film formed on the metal oxide 230.

[0166] Next, the transistors in the semiconductor device of this embodiment will be described in detail.

[0167] Preferably, the metal oxide 230 has a metal oxide 230a on the insulator 224 and a metal oxide 230b on the metal oxide 230a. By having the metal oxide 230a below the metal oxide 230b, the diffusion of impurities from structures formed below the metal oxide 230a to the metal oxide 230b can be suppressed.

[0168] In this embodiment, the metal oxide 230 is shown as having a two-layer structure of metal oxide 230a and metal oxide 230b, but it is not limited to this. The metal oxide 230 may be, for example, a single-layer structure of metal oxide 230b, or a laminated structure of three or more layers.

[0169] The metal oxide 230b has a channel-forming region in the transistor, and a source region and a drain region provided so as to sandwich the channel-forming region. At least a portion of the channel-forming region overlaps with the conductor 260. The source region overlaps with one of the pair of conductors 242, and the drain region overlaps with the other of the pair of conductors 242.

[0170] The channel-forming region is a high-resistance region with a lower carrier concentration due to fewer oxygen vacancies or lower impurity concentrations compared to the source and drain regions. Therefore, the channel-forming region can be said to be type i (intrinsic) or substantially type i.

[0171] Furthermore, the source and drain regions are low-resistance regions with high carrier concentrations due to a high oxygen deficiency or high concentrations of impurities such as hydrogen, nitrogen, and metallic elements. In other words, the source and drain regions are n-type regions (low-resistance regions) with higher carrier concentrations compared to the channel-forming region.

[0172] The carrier concentration in the channel-forming region is 1 × 10⁻⁶. 18 cm -3 Below, 1 x 10 17 cm -3 Less than 1 × 10 16 cm -3 Less than 1 × 10 15 cm -3 Less than 1 × 10 14 cm -3 Less than 1 × 10 13 cm -3 Less than 1 × 10 12 cm -3 Less than 1 × 10 11 cm -3 Less than, or 1 × 10 10 cm -3 It is preferable that it be less than . Furthermore, there are no particular limitations on the lower limit of the carrier concentration in the channel-forming region, but for example, 1 × 10 -9 cm -3 It can be done this way.

[0173] Furthermore, when the carrier concentration of metal oxide 230b is reduced, the impurity concentration in metal oxide 230b is reduced, and the defect level density is reduced. In this specification, a low impurity concentration and a low defect level density are referred to as high-purity intrinsic or substantially high-purity intrinsic. Note that oxide semiconductors (or metal oxides) with low carrier concentrations may be referred to as high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors (or metal oxides).

[0174] To stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the metal oxide 230b. Furthermore, in order to reduce the impurity concentration in the metal oxide 230b, it is preferable to also reduce the impurity concentration in adjacent films. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon. Note that impurities in the metal oxide 230b refer to elements other than the main components that make up the metal oxide 230b. For example, elements with a concentration of less than 0.1 atomic percent can be considered impurities.

[0175] Furthermore, the channel-forming region, source region, and drain region may each have metal oxide 230a formed in addition to metal oxide 230b.

[0176] Furthermore, in metal oxide 230, it may be difficult to clearly detect the boundaries between each region. The concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen, detected within each region may not be limited to stepwise changes between regions, but may also change continuously within each region. In other words, the closer a region is to the channel formation region, the lower the concentrations of metal elements, as well as impurity elements such as hydrogen and nitrogen may be.

[0177] It is preferable to use a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor) for the metal oxide 230.

[0178] The band gap of the metal oxide that functions as a semiconductor is preferably 2 eV or more, and more preferably 2.5 eV or more. By using a metal oxide with a large band gap, the off-current of the transistor can be reduced.

[0179] As the metal oxide 230, it is preferable to use a metal oxide such as indium oxide, gallium oxide, and zinc oxide. Alternatively, it is preferable to use a metal oxide having two or three elements selected from indium, element M, and zinc as the metal oxide 230. Element M is one or more selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium. In particular, it is preferable that element M is one or more selected from aluminum, gallium, yttrium, and tin. A metal oxide having indium, element M, and zinc may be referred to as In-M-Zn oxide.

[0180] The metal oxide 230 preferably has a laminated structure of multiple oxide layers with different chemical compositions. For example, in the metal oxide used for metal oxide 230a, it is preferable that the atomic ratio of element M to the main metal element is greater than the atomic ratio of element M to the main metal element in the metal oxide used for metal oxide 230b. Furthermore, in the metal oxide used for metal oxide 230a, it is preferable that the atomic ratio of element M to In is greater than the atomic ratio of element M to In in the metal oxide used for metal oxide 230b. This configuration suppresses the diffusion of impurities and oxygen from structures formed below metal oxide 230a into metal oxide 230b.

[0181] Furthermore, it is preferable that the atomic ratio of In to element M in the metal oxide 230b is greater than the atomic ratio of In to element M in the metal oxide 230a. With this configuration, the transistor can obtain a large on-current and high frequency characteristics.

[0182] Furthermore, because metal oxides 230a and 230b share a common element as a main component in addition to oxygen, the defect level density at the interface between metal oxides 230a and 230b can be reduced. Therefore, the influence of interfacial scattering on carrier conduction is reduced, allowing the transistor to achieve a large on-current and high frequency characteristics.

[0183] Specifically, as metal oxide 230a, a metal oxide with a composition of In:M:Zn=1:3:4 [atomic ratio] or close to it, or In:M:Zn=1:1:0.5 [atomic ratio] or close to it can be used. Furthermore, as metal oxide 230b, a metal oxide with a composition of In:M:Zn=1:1:1 [atomic ratio] or close to it, In:M:Zn=1:1:1.2 [atomic ratio] or close to it, In:M:Zn=1:1:2 [atomic ratio] or close to it, or In:M:Zn=4:2:3 [atomic ratio] or close to it can be used. Note that "close to it" includes a range of ±30% of the desired atomic ratio. Also, it is preferable to use gallium as element M. Furthermore, when a single layer of metal oxide 230b is provided as metal oxide 230, the metal oxides that can be used for metal oxide 230a may be applied as metal oxide 230b.

[0184] Furthermore, when depositing metal oxide films by sputtering, the above atomic ratio is not limited to the atomic ratio of the deposited metal oxide film, but may also be the atomic ratio of the sputtering target used for depositing the metal oxide film.

[0185] The metal oxide 230b is preferably crystalline. In particular, it is preferable to use CAAC-OS (c-axis aligned crystalline oxide semiconductor) as the metal oxide 230b.

[0186] CAAC-OS is a metal oxide with a highly crystalline, dense structure and few impurities and defects (e.g., oxygen vacancies). In particular, by heat-treating the metal oxide after its formation at a temperature that does not cause polycrystallization of the metal oxide (e.g., between 400°C and 600°C), the CAAC-OS can be made to have an even more crystalline and dense structure. By increasing the density of CAAC-OS in this way, the diffusion of impurities or oxygen within the CAAC-OS can be further reduced.

[0187] Furthermore, because it is difficult to identify clear grain boundaries in CAAC-OS, a decrease in electron mobility due to grain boundary issues is less likely to occur. Therefore, metal oxides containing CAAC-OS have stable physical properties. Consequently, metal oxides containing CAAC-OS are highly heat-resistant and reliable.

[0188] Furthermore, by using a crystalline oxide such as CAAC-OS as the metal oxide 230b, the extraction of oxygen from the metal oxide 230b by the source electrode or drain electrode can be suppressed. As a result, even when heat treatment is performed, the extraction of oxygen from the metal oxide 230b is reduced, making the transistor stable against the high temperatures (so-called thermal budget) in the manufacturing process.

[0189] In transistors using oxide semiconductors, the electrical properties tend to fluctuate and reliability may be poor if impurities and oxygen vacancies are present in the region where the channel is formed in the oxide semiconductor. Furthermore, hydrogen near the oxygen vacancy can fill the oxygen vacancy, creating a defect (hereinafter referred to as V). O Oxygen vacancies (sometimes called H) can form and generate electron carriers. Therefore, if the region where channels are formed in an oxide semiconductor contains oxygen vacancies, the transistor is likely to exhibit normally-on characteristics (a characteristic in which channels exist and current flows through the transistor even without applying voltage to the gate electrode). Consequently, in the region where channels are formed in an oxide semiconductor, impurities, oxygen vacancies, and V are likely to be present. OIt is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where the channel is formed has a reduced carrier concentration and is type i (intrinsed) or substantially type i.

[0190] In contrast, by placing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen is supplied from the insulator to the oxide semiconductor, eliminating oxygen deficiencies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source or drain region, it may cause a decrease in the transistor's on-current or a decrease in its field-effect mobility. Furthermore, variations in the amount of oxygen supplied to the source or drain region within the substrate surface can lead to variations in the characteristics of the semiconductor device containing the transistor. In addition, if the oxygen supplied from the insulator to the oxide semiconductor diffuses into conductors such as the gate electrode, source electrode, and drain electrode, these conductors may oxidize, impairing their conductivity and potentially adversely affecting the transistor's electrical characteristics and reliability.

[0191] Therefore, in oxide semiconductors, the channel formation region is preferably i-type or substantially i-type with reduced carrier concentration, while the source and drain regions are preferably n-type with high carrier concentration. In other words, oxygen vacancies in the channel formation region of oxide semiconductors, and V O It is preferable to reduce H. Also, ensure that an excessive amount of oxygen is not supplied to the source and drain regions, and that the V of the source and drain regions is not reduced. O It is preferable to prevent an excessive reduction in the amount of H. Furthermore, it is preferable to have a configuration that suppresses a decrease in the conductivity of conductors 260 and 242, etc. For example, it is preferable to have a configuration that suppresses oxidation of conductors 260 and 242, etc. Note that hydrogen in oxide semiconductors is V. O Since H can be formed, V O To reduce the amount of H, it is necessary to reduce the hydrogen concentration.

[0192] Therefore, in this embodiment, the semiconductor device is configured to reduce the hydrogen concentration in the channel formation region, suppress oxidation of the conductor 242 and conductor 260, and further suppress the reduction of hydrogen concentration in the source region and drain region.

[0193] The insulator 253 in contact with the channel-forming region in the metal oxide 230b preferably has the function of capturing and fixing hydrogen. This makes it possible to reduce the hydrogen concentration in the channel-forming region of the metal oxide 230b. Therefore, the V in the channel-forming region O By reducing H, the channel-forming region can be made i-type or substantially i-type.

[0194] Examples of insulators having the function of capturing and fixing hydrogen include metal oxides having an amorphous structure. It is preferable to use a metal oxide such as magnesium oxide, or an oxide containing one or both of aluminum and hafnium, as the insulator 253. In such amorphous metal oxides, oxygen atoms have dangling bonds, and these dangling bonds may have the property of capturing or fixing hydrogen. In other words, amorphous metal oxides have a high ability to capture or fix hydrogen.

[0195] Furthermore, it is preferable to use a high-dielectric constant (high-k) material for the insulator 253. An example of a high-k material is an oxide containing either or both aluminum and hafnium. By using a high-k material as the insulator 253, it becomes possible to reduce the gate potential applied during transistor operation while maintaining the physical thickness of the gate insulator. Additionally, it becomes possible to thin the equivalent oxide film thickness (EOT) of the insulator that functions as a gate insulator.

[0196] Based on the above, it is preferable to use an oxide containing one or both of aluminum and hafnium as the insulator 253, and it is more preferable to use an oxide containing one or both of aluminum and hafnium having an amorphous structure, and it is even more preferable to use hafnium oxide having an amorphous structure. In this embodiment, hafnium oxide is used as the insulator 253. In this case, the insulator 253 is an insulator having at least oxygen and hafnium. Furthermore, the hafnium oxide has an amorphous structure. In this case, the insulator 253 has an amorphous structure.

[0197] In addition, the insulator 253 may be an insulator with a thermally stable structure, such as silicon oxide or silicon oxide-nitride. For example, the insulator 253 may be a laminated structure having aluminum oxide and silicon oxide or silicon oxide-nitride on aluminum oxide. Alternatively, the insulator 253 may be a laminated structure having aluminum oxide, silicon oxide or silicon oxide-nitride on aluminum oxide and hafnium oxide on silicon oxide or silicon oxide-nitride.

[0198] To suppress oxidation of conductors 242 and 260, it is preferable to provide oxygen barrier insulators near conductors 242 and 260, respectively. In the semiconductor device described in this embodiment, the insulators are, for example, insulators 253, 254, and 275.

[0199] In this specification, a barrier insulator refers to an insulator that has barrier properties. In this specification, barrier properties refer to the function of suppressing the diffusion of the corresponding substance (also called low permeability), or the function of capturing and fixing the corresponding substance (also called gettering).

[0200] Examples of oxygen barrier insulators include oxides containing one or both aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. Examples of oxides containing one or both aluminum and hafnium include aluminum oxide, hafnium oxide, oxides containing aluminum and hafnium (hafnium aluminate), and oxides containing hafnium and silicon (hafnium silicate). For example, insulators 253, 254, and 275 are preferably single-layer or multi-layer structures of the above-mentioned oxygen barrier insulators.

[0201] The insulator 253 preferably has barrier properties against oxygen. It is preferable that the insulator 253 is at least less permeable to oxygen than the insulator 280. The insulator 253 has a region that contacts the side surface of the conductor 242. The oxygen barrier properties of the insulator 253 suppress oxidation of the side surface of the conductor 242 and the formation of an oxide film on that surface. This suppresses a decrease in the transistor's on-current or a decrease in its field-effect mobility.

[0202] Furthermore, the insulator 253 is provided in contact with the upper and side surfaces of the metal oxide 230b, the side surfaces of the metal oxide 230a, the side surfaces of the insulator 224, and the upper surface of the insulator 222. The insulator 253 has an oxygen barrier property, which suppresses the detachment of oxygen from the channel-forming region of the metal oxide 230b, for example, when heat treatment is performed. Therefore, the formation of oxygen vacancies in the metal oxide 230a and metal oxide 230b can be reduced.

[0203] Conversely, even if the insulator 280 contains an excess amount of oxygen, it is possible to suppress the excessive supply of that oxygen to the metal oxides 230a and 230b. Therefore, it is possible to suppress excessive oxidation of the source and drain regions, which can lead to a decrease in the transistor's on-current or a decrease in its field-effect mobility.

[0204] Oxides containing either or both aluminum and hafnium have barrier properties against oxygen and can therefore be suitably used as insulator 253.

[0205] The insulator 254 preferably has barrier properties against oxygen. The insulator 254 is provided between the channel-forming region of the metal oxide 230 and the conductor 260, and between the insulator 280 and the conductor 260. This configuration suppresses the diffusion of oxygen contained in the channel-forming region of the metal oxide 230 into the conductor 260, thereby preventing the formation of oxygen vacancies in the channel-forming region of the metal oxide 230. Furthermore, it suppresses the diffusion of oxygen contained in the metal oxide 230 and the oxygen contained in the insulator 280 into the conductor 260, thereby preventing the oxidation of the conductor 260. The insulator 254 preferably has lower oxygen permeability than at least the insulator 280. For example, it is preferable to use silicon nitride as the insulator 254. In this case, the insulator 254 is an insulator containing at least nitrogen and silicon.

[0206] Furthermore, it is preferable that the insulator 254 has barrier properties against hydrogen. This prevents impurities such as hydrogen contained in the conductor 260 from diffusing into the metal oxide 230b.

[0207] The insulator 275 preferably has barrier properties against oxygen. The insulator 275 is provided between the insulator 280 and the conductor 242. This configuration suppresses the diffusion of oxygen contained in the insulator 280 into the conductor 242. Therefore, it is possible to suppress the oxidation of the conductor 242 by the oxygen contained in the insulator 280, which increases its resistivity and reduces the on-current. The insulator 275 preferably has lower oxygen permeability than at least the insulator 280. For example, it is preferable to use silicon nitride as the insulator 275. In this case, the insulator 275 is an insulator having at least nitrogen and silicon.

[0208] To suppress the reduction of hydrogen concentration in the source and drain regions of the metal oxide 230, it is preferable to provide a hydrogen barrier insulator near the source and drain regions, respectively. In the semiconductor device described in this embodiment, the hydrogen barrier insulator is, for example, an insulator 275. The hydrogen barrier properties of the insulator 275 suppress the capture and deposition of hydrogen in the source and drain regions by the insulator 253. Therefore, the source and drain regions can be of the n-type.

[0209] By adopting the above configuration, the channel formation region can be made i-type or substantially i-type, and the source and drain regions can be made n-type, thereby providing a semiconductor device with good electrical characteristics. Furthermore, by adopting the above configuration, good electrical characteristics can be maintained even when the semiconductor device is miniaturized or highly integrated. In addition, high-frequency characteristics can be improved by miniaturizing the transistor. Specifically, the cutoff frequency can be improved.

[0210] Examples of barrier insulators against hydrogen include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 is preferably a single-layer or multi-layer structure of the above-mentioned barrier insulator against hydrogen.

[0211] Insulators 253 and 254 each function as part of the gate insulator. Insulators 253 and 254 are provided together with the conductor 260 in an opening formed in the insulator 280, etc. In order to miniaturize the transistor, it is preferable that the film thickness of insulator 253 and insulator 254 be thin. The film thickness of insulator 253 is preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 5.0 nm, more preferably 1.0 nm to less than 5.0 nm, and even more preferably 1.0 nm to 3.0 nm. The film thickness of insulator 254 is preferably 0.1 nm to 5.0 nm, more preferably 0.5 nm to 3.0 nm, and even more preferably 1.0 nm to 3.0 nm. Note that insulators 253 and 254 each only need to have a region with the above-mentioned film thickness in at least a part of it.

[0212] To achieve the thin film thickness of insulator 253 as described above, it is preferable to deposit the film using atomic layer deposition (ALD). ALD methods include thermal ALD, which uses only thermal energy for the reaction between the precursor and reactant, and plasma-enhanced ALD (PEALD), which uses plasma-excited reactants. PEALD is preferable in some cases because the use of plasma allows for film deposition at lower temperatures.

[0213] The ALD method allows for the deposition of atoms layer by layer, resulting in several advantages: the ability to deposit extremely thin films, films on structures with high aspect ratios, films with fewer defects such as pinholes, films with excellent coverage, and films at low temperatures. Therefore, the insulator 253 can be deposited with good coverage and a thin film thickness as described above on the sides of openings formed in the insulator 280, the side edges of the conductor 242, etc.

[0214] Furthermore, precursors used in the ALD method include, for example, carbon. Therefore, films formed by the ALD method may contain more impurities such as carbon compared to films formed by other film deposition methods. The quantity of impurities can be quantified using secondary ion mass spectrometry (SIMS), X-ray photoelectron spectroscopy (XPS), or Auger electron spectroscopy (AES).

[0215] For example, silicon nitride deposited by the PEALD method can be used as the insulator 254.

[0216] Furthermore, by using an insulator 253 that has the function of suppressing the permeation of impurities such as hydrogen and oxygen, such as hafnium oxide, the insulator 253 can also perform the function of the insulator 254. In such a case, by omitting the insulator 254, the manufacturing process of the semiconductor device can be simplified and productivity can be improved.

[0217] Furthermore, in this embodiment, it is preferable to configure the semiconductor device to suppress hydrogen from entering the transistor, in addition to the above configuration. For example, it is preferable to provide an insulator having the function of suppressing hydrogen diffusion so as to cover one or both of the top and bottom of the transistor. In the semiconductor device described in this embodiment, the insulator is, for example, insulator 212.

[0218] It is preferable to use an insulator 212 that has the function of suppressing hydrogen diffusion. This suppresses the diffusion of hydrogen from below the insulator 212 to the transistor. As the insulator 212, an insulator that can be used for the insulator 275 described above can be used.

[0219] It is preferable that one or more of insulators 212, 214, and 282 function as a barrier insulating film that suppresses the diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor into the transistor. Therefore, it is preferable that one or more of insulators 212, 214, and 282 are insulating materials that have the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms (the above impurities are less permeable). Alternatively, it is preferable that they are insulating materials that have the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms and oxygen molecules) (the above oxygen is less permeable).

[0220] Insulators 212, 214, and 282 preferably each have an insulator that has the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, silicon nitride, which has higher hydrogen barrier properties, is preferably used as insulator 212. Also, for example, insulators 212, 214, and 282 preferably each have aluminum oxide or magnesium oxide, which have high hydrogen capture and hydrogen fixation functions. This makes it possible to suppress the diffusion of impurities such as water and hydrogen from the substrate side to the transistor side via insulators 212 and 214. Alternatively, it is possible to suppress the diffusion of impurities such as water and hydrogen from the interlayer insulating film etc. located outside of insulator 282 to the transistor side. Alternatively, it is possible to suppress the diffusion of oxygen contained in insulator 224 etc. to the substrate side. Alternatively, the diffusion of oxygen contained in the insulator 280, etc., upward from the transistor via the insulator 282, etc., can be suppressed. Thus, it is preferable to have a structure in which the top and bottom of the transistor are surrounded by an insulator that has the function of suppressing the diffusion of impurities such as water and hydrogen, and oxygen.

[0221] The conductor 205a is arranged to overlap with the metal oxide 230 and the conductor 260. Here, it is preferable that the conductor 205a is embedded in an opening formed in the insulator 216a. In some cases, a portion of the conductor 205a may be embedded in the insulator 214.

[0222] The conductor 205a may have a single-layer structure or a multi-layer structure. For example, Figure 10A shows an example in which the conductor 205a has a two-layer multi-layer structure consisting of a first conductor and a second conductor. The first conductor of the conductor 205a is provided in contact with the bottom surface and side wall of an opening provided in the insulator 216a. The second conductor of the conductor 205a is provided so as to be embedded in a recess formed in the first conductor of the conductor 205a. Here, the height of the upper surface of the second conductor of the conductor 205a is approximately the same as the height of the upper surface of the first conductor of the conductor 205a and the height of the upper surface of the insulator 216a.

[0223] Here, it is preferable that the first conductor of the conductor 205a is a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, or NO2, etc.), or copper atoms. Alternatively, it is preferable that it is a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms and oxygen molecules).

[0224] By using a conductive material having the function of reducing hydrogen diffusion for the first conductor of conductor 205a, it is possible to prevent impurities such as hydrogen contained in the second conductor of conductor 205a from diffusing into the metal oxide 230 via the insulator 216a and insulator 224, etc. Furthermore, by using a conductive material having the function of suppressing oxygen diffusion for the first conductor of conductor 205a, it is possible to suppress oxidation of the second conductor of conductor 205a and a decrease in conductivity. Examples of conductive materials having the function of suppressing oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. The first conductor of conductor 205a can be a single-layer structure or a multi-layer structure of the above conductive material. For example, it is preferable that the first conductor of conductor 205a has titanium nitride.

[0225] Furthermore, the second conductor of conductor 205a is preferably a conductive material mainly composed of tungsten, copper, or aluminum. For example, the second conductor of conductor 205a is preferably tungsten.

[0226] The conductor 205a can function as a second gate electrode. In this case, the transistor's threshold voltage (Vth) can be controlled by independently changing the potential applied to the conductor 205a, rather than in conjunction with the potential applied to the conductor 260. In particular, applying a negative potential to the conductor 205a makes it possible to increase the transistor's Vth and reduce the off-current. Therefore, applying a negative potential to the conductor 205a reduces the drain current when the potential applied to the conductor 260 is 0V compared to not applying a negative potential.

[0227] Furthermore, the electrical resistivity of the conductor 205a is designed considering the potential applied to the conductor 205a, and the film thickness of the conductor 205a is set to match this electrical resistivity. Also, the film thickness of the insulator 216a is approximately the same as that of the conductor 205a. Here, it is preferable to make the film thicknesses of both the conductor 205a and the insulator 216a as thin as possible within the limits permitted by the design of the conductor 205a. By making the film thickness of the insulator 216a thin, the absolute amount of impurities such as hydrogen contained in the insulator 216a can be reduced, thereby reducing the diffusion of these impurities into the metal oxide 230.

[0228] Insulators 222 and 224 function as gate insulators.

[0229] Preferably, the insulator 222 has the function of suppressing the diffusion of hydrogen (for example, at least one such as hydrogen atoms and hydrogen molecules). Furthermore, preferably, the insulator 222 has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms and oxygen molecules). For example, it is preferable that the insulator 222 has the function of suppressing the diffusion of one or both of hydrogen and oxygen more effectively than the insulator 224.

[0230] The insulator 222 preferably has an insulator containing an oxide of one or both of the insulating materials aluminum and hafnium. It is preferable to use aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc., as the insulator. Alternatively, it is preferable to use an oxide containing hafnium and zirconium, such as hafnium-zirconium oxide. When the insulator 222 is formed using such a material, the insulator 222 functions as a layer that suppresses the release of oxygen from the metal oxide 230 to the substrate side, and the diffusion of impurities such as hydrogen from the periphery of the transistor to the metal oxide 230. Therefore, by providing the insulator 222, the diffusion of impurities such as hydrogen into the inside of the transistor can be suppressed, and the generation of oxygen vacancies in the metal oxide 230 can be suppressed. Furthermore, the reaction of the first conductor of the conductor 205a with the oxygen present in the insulator 224 and the metal oxide 230 can be suppressed.

[0231] Alternatively, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide may be added to the above insulator. Alternatively, these insulators may be subjected to nitriding treatment. Furthermore, insulator 222 may be used by laminating silicon oxide, silicon oxide nitride, or silicon nitride onto the above insulator.

[0232] Furthermore, the insulator 222 may be a single-layer or multilayer structure of an insulator containing so-called high-k materials such as aluminum oxide, hafnium oxide, tantalum oxide, zirconium oxide, or hafnium-zirconium oxide. As transistors become smaller and more integrated, thinning of the gate insulator can lead to problems such as leakage current. By using a high-k material as the insulator that functions as the gate insulator, it is possible to reduce the gate potential during transistor operation while maintaining the physical film thickness. In addition, materials with high dielectric constants such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST) can also be used as the insulator 222.

[0233] The insulator 224 in contact with the metal oxide 230 is preferably, for example, silicon oxide or silicon oxide-nitride.

[0234] Furthermore, the insulators 222 and 224 may each have a laminated structure of two or more layers. In that case, the laminated structure is not limited to being made of the same material, but may be made of different materials.

[0235] It is preferable to use conductive materials that are resistant to oxidation or conductive materials that have a function to suppress the diffusion of oxygen as conductor 242 and conductor 260, respectively. Examples of such conductive materials include conductive materials containing nitrogen and conductive materials containing oxygen. This can suppress a decrease in the conductivity of conductor 242 and conductor 260. When conductive materials containing metal and nitrogen are used as conductor 242 and conductor 260, conductor 242 and conductor 260 will be conductors containing at least metal and nitrogen.

[0236] The conductor 242 may have a single-layer structure or a multi-layer structure. Similarly, the conductor 260 may have a single-layer structure or a multi-layer structure.

[0237] For example, in Figure 10A, the conductor 242 is shown as a two-layer structure consisting of a first conductor and a second conductor on the first conductor. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the first conductor of the conductor 242 that is in contact with the metal oxide 230b. This can suppress a decrease in the conductivity of the conductor 242. Furthermore, it is preferable to use a material that readily absorbs (extracts) hydrogen as the first conductor of the conductor 242, as this can reduce the hydrogen concentration of the metal oxide 230.

[0238] Furthermore, it is preferable that the second conductor of conductor 242 has higher conductivity than the first conductor of conductor 242. For example, it is preferable that the film thickness of the second conductor of conductor 242 be greater than the film thickness of the first conductor of conductor 242.

[0239] For example, tantalum nitride or titanium nitride can be used as the first conductor of the conductor 242, and tungsten can be used as the second conductor of the conductor 242.

[0240] To suppress a decrease in the conductivity of the conductor 242, it is preferable to use a crystalline oxide such as CAAC-OS as the metal oxide 230b. In particular, it is preferable to use a metal oxide having indium, zinc, and one or more selected from gallium, aluminum, and tin. By using CAAC-OS, the abstraction of oxygen from the metal oxide 230b by the conductor 242 can be suppressed. Furthermore, a decrease in the conductivity of the conductor 242 can be suppressed.

[0241] As the conductor 242, it is preferable to use, for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum. In one embodiment of the present invention, a nitride containing tantalum is particularly preferred. Alternatively, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferred because they are conductive materials that are resistant to oxidation or maintain conductivity even when absorbing oxygen.

[0242] Furthermore, hydrogen contained in, for example, the metal oxide 230b may diffuse into the conductor 242. In particular, by using a tantalum-containing nitride for the conductor 242, hydrogen contained in, for example, the metal oxide 230b, diffuses easily into the conductor 242, and the diffused hydrogen may combine with the nitrogen present in the conductor 242. In other words, hydrogen contained in, for example, the metal oxide 230b, may be absorbed by the conductor 242.

[0243] The conductor 260 is positioned such that its upper surface is approximately the same height as the top of the insulator 254, the top of the insulator 253, and the upper surface of the insulator 280.

[0244] The conductor 260 functions as the first gate electrode of the transistor. Preferably, the conductor 260 has a first conductor and a second conductor on the first conductor. For example, it is preferable that the first conductor of the conductor 260 is arranged to enclose the bottom and sides of the second conductor of the conductor 260.

[0245] For example, in Figure 10A, the conductor 260 is shown as a two-layer structure. In this case, it is preferable to use a conductive material that is resistant to oxidation or a conductive material that has the function of suppressing oxygen diffusion as the first conductor of the conductor 260.

[0246] The first conductor of the conductor 260 is preferably a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, or copper atoms. Alternatively, it is preferable to use a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one such as oxygen atoms and oxygen molecules).

[0247] Furthermore, since the first conductor of the conductor 260 has the function of suppressing oxygen diffusion, it is possible to suppress the oxidation of the second conductor of the conductor 260 by oxygen contained in the insulator 280, for example, and the decrease in conductivity. As a conductive material that has the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, or ruthenium oxide.

[0248] Furthermore, it is preferable to use a highly conductive material for the conductor 260. For example, the second conductor of the conductor 260 can be a conductive material mainly composed of tungsten, copper, or aluminum. The second conductor of the conductor 260 may also be a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive material.

[0249] Furthermore, in the transistor, the conductor 260 is formed self-aligningly, for example, to fill an opening formed in the insulator 280. By forming the conductor 260 in this way, it can be reliably positioned in the region between the pair of conductors 242 without the need for alignment.

[0250] Furthermore, the upper surfaces of insulators 216a, 280, 285, 287, 216b, 181, and 185 may each be flattened.

[0251] It is preferable that the concentration of impurities such as water and hydrogen in the insulator 280 is reduced. For example, it is preferable that the insulator 280 has a silicon-containing oxide such as silicon oxide or silicon oxidnitride.

[0252] Furthermore, at the opening of the insulator 280, the side wall of the insulator 280 may be approximately perpendicular to the upper surface of the insulator 222, or it may be tapered. By making the side wall tapered, for example, the covering of the insulator 253 provided at the opening of the insulator 280 can be improved, and defects such as porosity can be reduced.

[0253] In this specification, a tapered shape refers to a shape in which at least a portion of the side surface of a structure is inclined with respect to the substrate surface or the surface to be formed. For example, it is preferable to have a region in which the angle between the inclined side surface and the substrate surface or the surface to be formed (hereinafter sometimes referred to as the taper angle) is less than 90°. The side surface of the structure and the substrate surface do not necessarily have to be perfectly flat, and may be substantially planar with fine curvature, or substantially planar with fine irregularities.

[0254] The conductors 161 and 162 in capacity 101 can each be made of materials that can be used for conductor 205a, conductor 242, or conductor 260, respectively.

[0255] It is preferable to deposit the conductor 161 and the conductor 162 using a film deposition method that provides good coverage, such as the ALD method or the CVD method.

[0256] As the conductors 161 and 162, metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, and alloys mainly composed of the metals can be mentioned. Alternatively, metal nitride films (titanium nitride film, molybdenum nitride film, tungsten nitride film) containing the above-mentioned elements as components can be used. Further, films containing these materials can be used as a single layer or in a laminated structure.

[0257] It is preferable that the conductor contacts the ferroelectric material because polarization is likely to occur in the ferroelectric material. As the conductors 161 and 162, it is preferable to use a material in which polarization is likely to occur in the ferroelectric material.

[0258] In addition, after laminating the conductor 161, the insulator 163, and the conductor 162 in this order and performing heat treatment, there may be a case where the ferroelectricity of the insulator 163 can be improved, which is preferable. For heat treatment, for example, an RTA apparatus, a resistance heating furnace, or a microwave heating apparatus can be used. In particular, by using an RTA apparatus, a film particularly excellent in ferroelectricity may be obtained, which is preferable. As the RTA apparatus, a GRTA (Gas Rapid Thermal Anneal) apparatus or an LRTA (Lamp Rapid Thermal Anneal) apparatus can be used.

[0259] It is preferable to use titanium nitride for each of the conductors 161 and 162.

[0260] In the conductor​​​In the conductor 162, it is preferable to use titanium nitride for the surface in contact with the insulator 163 (for example, the bottom surface in the configuration of Figure 10). That is, when the conductor 162 has a laminated structure, it is preferable that the bottom layer is a titanium nitride layer.

[0262] It is preferable to use a ferroelectric material for the insulator 163 of capacitance 101. As a ferroelectric material, the materials shown in the previous embodiment can be used.

[0263] Here, the thickness of the ferroelectric layer is preferably 200 nm or less, and more preferably 150 nm or less.

[0264] Furthermore, when a layer containing hafnium, zirconium, and oxygen is used as the ferroelectric layer, the thickness of the ferroelectric layer can be, for example, 100 nm or less, preferably 50 nm or less, more preferably 20 nm or less, even more preferably 15 nm or less, for example 2 nm to 15 nm, or for example 8 nm to 12 nm.

[0265] The insulator 163 is preferably formed using a film deposition method that provides good coverage, such as the ALD method or the CVD method, and is particularly preferably formed using the thermal ALD method.

[0266] The conductor 240 is preferably a laminated structure of a first conductor and a second conductor. For example, as shown in Figure 10A, the conductor 240 can be structured such that the first conductor is provided in contact with the inner wall of the opening, and the second conductor is provided further inside. The first conductor of the conductor 240 has a region that is in contact with at least a portion of the upper surface of the conductor 209, the side surface of the insulator 212, the side surface of the insulator 216a, the upper and side surfaces of the conductor 242, the side surface of the insulator 280, the side surface of the insulator 285, the side surface of the insulator 287, and the side surface of the insulator 216b.

[0267] As the first conductor of the conductor 240, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen. The first conductor of the conductor 240 can be a single-layer structure or a multilayer structure using one or more of the following: tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide. This makes it possible to suppress the mixing of impurities such as water and hydrogen into the metal oxide 230 through the conductor 240.

[0268] Furthermore, since the conductor 240 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the second conductor of the conductor 240 can be a conductive material mainly composed of tungsten, copper, or aluminum.

[0269] For example, it is preferable to use titanium nitride as the first conductor of the conductor 240 and tungsten as the second conductor of the conductor 240. In this case, the first conductor of the conductor 240 will be a conductor having titanium and nitrogen, and the second conductor of the conductor 240 will be a conductor having tungsten.

[0270] The conductor 240 may be a single-layer structure or a laminated structure of three or more layers. Also, for example, Figure 8 shows an example where the height of the top surface of the conductor 240 is the same as the height of the top surface of the insulator 181, but the height of the top surface of the conductor 240 may be higher than, for example, the height of the top surface of the insulator 181.

[0271] It is preferable that insulators 216a, 280, 285, 287, 216b, 181, and 185 each have a lower dielectric constant than insulator 163. Furthermore, it is preferable that insulator 222 has a higher dielectric constant than, for example, insulators 216a, 280, 285, 287, 216b, 181, and 185. By using materials with low dielectric constants as the interlayer films for insulators 216a, 280, 285, 287, 216b, 181, and 185, parasitic capacitance between wiring can be reduced.

[0272] The dielectric constant of an insulator made from a material capable of ferroelectricity is preferably higher than the dielectric constant of insulator 222. For example, the dielectric constant of insulator 163 is preferably higher than the dielectric constant of insulator 222.

[0273] For example, it is preferable that insulators 216a, 280, 285, 287, 216b, 181, and 185 each contain one or more of the following: silicon oxide, silicon oxynitride, silicon oxide with added fluorine, silicon oxide with added carbon, silicon oxide with added carbon and nitrogen, and silicon oxide with voids.

[0274] In particular, silicon oxide and silicon oxide-nitride are preferred because they are thermally stable. Materials such as silicon oxide, silicon oxide-nitride, and silicon oxide with vacancies are especially preferred because they can easily form regions containing oxygen that is desorbed by heating.

[0275] The memory layer 11 shown in Figure 11 has a capacitor 101b, a transistor 201, a transistor 202, and a transistor 203. Figure 11 differs from Figure 10 in that the memory layer 11 has a conductor 205b, a conductor 160, and an insulator 222F instead of an insulator 222.

[0276] Capacitance 101b can correspond to capacitance C1 shown in the previous embodiment. Also, similar to Figure 10, transistors 201, 202, and 203 can correspond to transistors M1, M2, and M3 of the memory cell 10 shown in the previous embodiment, and conductors 240a and 240b can correspond to wiring WBL and wiring RBL, respectively.

[0277] In Figure 11, the conductor 205b is embedded in the opening of the insulator 216a. The conductor 205b has a region that overlaps with the conductor 242b, with the insulator 222F in between. The insulator 222F has a region that is sandwiched between the conductor 205b and the conductor 242b. Furthermore, in the configuration shown in Figure 11, it is preferable that the conductor 205b has a region that is in contact with the lower surface of the insulator 222F.

[0278] The conductor 205b has a region that functions as one electrode (also called the lower electrode) of capacitance 101b. The insulator 222F has a region that functions as the dielectric of capacitance 101. The conductor 242b has a region that functions as the other electrode (also called the upper electrode) of capacitance 101b.

[0279] It is preferable to use a material that can possess ferroelectric properties for the insulator 222F. Furthermore, the description of insulator 163 above can be used as the insulator 222F.

[0280] An insulator 287 is provided on the insulator 285. An opening is provided in the insulator 287, and a conductor 160 is embedded inside the opening. Then, an insulator 288 is provided on the conductor 160 and on the insulator 287. An insulator 215 is provided on the insulator 288. An insulator 216b with an opening is provided on the insulator 215, and conductors 205a2 and 205b are embedded inside the opening. Conductor 160 may have a region in contact with the side surface of insulator 288. Conductors 205a2 and 205b may also have regions in contact with the side surface of insulator 216b.

[0281] It is preferable that the dielectric constant of insulator 288 is lower than that of insulator 163. Furthermore, it is preferable that the dielectric constant of insulator 214 is higher than that of insulator 288. By using a material with a low dielectric constant as the interlayer film for insulator 288, parasitic capacitance between wirings can be reduced, thereby suppressing the impact on the operating performance of the memory cell 10. For example, the descriptions of insulator 216a, insulator 280, insulator 285, insulator 287, insulator 216b, insulator 181, and insulator 185 can be used as examples for insulator 288.

[0282] Hereinafter, when explaining matters common to the conductor 205a1 and the conductor 205a2, it may be described as the conductor 205a. Further, when explaining matters common to the conductor 205a and the conductor 205b, it may be described as the conductor 205.

[0283] The conductor 231 electrically connects the conductor 242b and the conductor 160. Also, the conductor 232 electrically connects the conductor 260 included in the transistor 202 and the conductor 160. From the above, the conductor 242b having a region that functions as the other of the source electrode or the drain electrode of the transistor 201 is electrically connected to the conductor 260 having a region that functions as the gate electrode of the transistor 202 via the conductor 231, the conductor 160, and the conductor 232.

[0284] The conductor 160 has a first conductor and a second conductor on the first conductor. For example, titanium nitride formed by using the ALD method can be used as the first conductor of the conductor 160, and tungsten formed by using the CVD method can be used as the second conductor of the conductor 160. When the adhesion of tungsten to the insulator 285 is sufficiently high, a single-layer structure of tungsten formed by using the CVD method may be used as the conductor 160.

[0285] Note that there may be a case where one of the insulator 288 or the insulator 215 does not need to be provided.

[0286] The memory layer 11 shown in FIG. 12 is different from FIG. 11 in that it has an insulator 215F instead of the insulator 215, has an insulator 222 instead of the insulator 222F, and does not have the insulator 288.

[0287] It is preferable to use a material that may have ferroelectricity for the insulator 215F. Also, as the insulator 215F, reference can be made to the description of the insulator 163 above.

[0288] In Figure 12, for example, it is preferable that the film thickness of insulator 222 be greater than or equal to the film thickness of insulator 215F. In some cases, insulator 222F may be used instead of insulator 222.

[0289] Figures 13 and 14 show examples of configurations in which the memory layer 11 shown in Figure 12 is stacked in n layers, respectively. Figure 13 shows a configuration in which the conductors 240a and 240b shown in Figure 8 are applied. Figure 14 shows a configuration in which the connecting electrodes 240c and 240d shown in Figure 9 are applied.

[0290] In the memory layer 11 shown in Figures 12 and 13, in addition to the capacitance 101, a conductor 205b, a conductor 242b, and an insulator 222 sandwiched between the conductors 205b and 242b may form a second capacitance. Conductors 205b and 242b can each function as electrodes for the second capacitance, and the insulator 222 can function as a dielectric. In the memory layer 11, a combined capacitance of capacitance 101 and the second capacitance may be formed. Furthermore, in the memory layer 11, the upper electrode of capacitance 101 can be considered to be shared with the lower electrode of the second capacitance in the memory layer 11 of the layer above.

[0291] When a combined capacity of capacity 101 and the second capacity is formed, for example, in a stacked multi-layer storage layer 11, the influence of the second capacity can be reduced by configuring the storage layers adjacent to each other vertically so that they do not share the wiring RBL[i,s] shown in Figure 2.

[0292] Specifically, for example, two RBL[i,s] wirings can be provided (for example, RBL[i,s,A] and RBL[i,s,B]), and in the stacked multiple layers of storage layers 11, RBL[i,s,A] can be connected to the odd-numbered storage layers 11 and RBL[i,s,B] can be connected to the even-numbered storage layers 11. Alternatively, RBL[i,s,B] can be connected to the odd-numbered storage layers 11 and RBL[i,s,A] can be connected to the even-numbered storage layers 11.

[0293] For example, the memory cell 10[i,j] in memory layer 11_h is electrically connected to wiring WBL[i,s] and wiring RBL[i,s,A]. Also, the memory cell 10[i,j+1] in memory layer 11_h is electrically connected to wiring WBL[i,s+1] and wiring RBL[i,s,A]. Also, the memory cell 10[i,j] in memory layer 11_h+1 is electrically connected to wiring WBL[i,s] and wiring RBL[i,s,B]. Also, the memory cell 10[i,j+1] in memory layer 11_h+1 is electrically connected to wiring WBL[i,s+1] and wiring RBL[i,s,B].

[0294] Furthermore, as one of the wiring RBL[i,s,A] and RBL[i,s,B], for example, a connecting electrode can be used that includes the conductors 233b of the odd-numbered memory layers 11 from among the conductors 233b of each of the n-layer memory layers 11, and in this connecting electrode, the conductors 233b of the odd-numbered memory layers 11 are electrically connected to each other. Furthermore, as the other of the wiring RBL[i,s,A] and RBL[i,s,B], for example, a connecting electrode can be used that includes the conductors 233b of the even-numbered memory layers 11 from among the conductors 233b of each of the n-layer memory layers 11, and in this connecting electrode, the conductors 233b of the even-numbered memory layers 11 are electrically connected to each other.

[0295] Figure 15 is a cross-sectional view showing an example of the configuration of a semiconductor device according to one aspect of the present invention. The semiconductor device shown in Figure 15 shows an example in which a layer having, for example, a transistor 300 is provided below the configuration shown in Figure 8. The transistor 300 can be provided, for example, in a drive circuit for a memory cell formed in the layer above the insulator 210. Note that the configuration of the layer above the insulator 210 in Figure 15 is the same as in Figure 8, so a detailed explanation is omitted.

[0296] Figure 15 illustrates a transistor 300. The transistor 300 is provided on a substrate 311 and has a conductor 316 that functions as a gate, an insulator 315 that functions as a gate insulator, a semiconductor region 313 that includes a part of the substrate 311, and low-resistance regions 314a and 314b that function as a source region or drain region. The transistor 300 may be either a p-channel transistor or an n-channel transistor. For example, a single-crystal silicon substrate can be used as the substrate 311.

[0297] In Figure 15, the transistor 300 has a convex shape in the semiconductor region 313 (part of the substrate 311) where the channel is formed. Furthermore, the sides and top surface of the semiconductor region 313 are covered by a conductor 316 via an insulator 315. The conductor 316 may be made of a material that adjusts the work function. Such a transistor 300 is also called a FIN-type transistor because it utilizes the convex portion of the semiconductor substrate. It may also have an insulator in contact with the top of the convex portion, functioning as a mask for forming the convex portion. While this example shows the formation of the convex portion by processing a part of the semiconductor substrate, a semiconductor film with a convex shape may also be formed by processing an SOI (Silicon on Insulator) substrate.

[0298] Note that the transistor 300 shown in Figure 15 is just one example, and its structure is not limited to this example; an appropriate transistor can be used depending on the circuit configuration or driving method.

[0299] A wiring layer containing an interlayer film, wiring, and plugs may be provided between each structure. Furthermore, multiple wiring layers may be provided depending on the design. Also, in this specification, the wiring and the plugs electrically connected to the wiring may be integrated into a single unit. That is, a portion of the conductor may function as wiring, and a portion of the conductor may function as a plug.

[0300] For example, on transistor 300, insulators 320, 322, 324, and 326 are layered in sequence as interlayer films. Conductors such as 328 are embedded in insulators 320 and 322. Conductors such as 330 are embedded in insulators 324 and 326. Conductors 328 and 330 function as contact plugs or wiring.

[0301] Furthermore, the insulator functioning as an interlayer film may also function as a planarizing film that covers the uneven shape beneath it. For example, the upper surface of the insulator 322 may be planarized by a planarizing treatment, such as chemical mechanical polishing (CMP), to improve its flatness.

[0302] Figures 16A and 16B are plan views showing an example of a semiconductor device having the configuration shown in Figure 10A, illustrating an example of an XY plane configuration.

[0303] Figure 16A shows transistors 201, 202, 203, conductor 240a, and conductor 240b. Figure 16B shows Figure 16A with the addition of capacitor 101. In Figure 16B, the memory cell 10 is formed by transistors 201, 202, 203, and capacitor 101. Note that components other than the conductors are omitted in Figures 16A and 16B.

[0304] In Figure 16A, the conductor 260 of transistor 201 has a region sandwiched between conductors 242a and 242b. The conductor 260 of transistor 202 has a region sandwiched between conductors 242c and 242d. The conductor 260 of transistor 203 has a region sandwiched between conductors 242d and 242e.

[0305] Furthermore, Figures 17A and 17B show examples of different shapes for the conductor 162 in Figure 16B, respectively. The conductor 162 shown in Figure 17A can reduce the area in which it overlaps with the conductor 205a1. Therefore, for example, the parasitic capacitance between the conductor 162 and the conductor 205a1 can be reduced. Also, in Figure 17A, the width of the conductor 162 changes in a plan view, whereas in Figure 16B, the width of the conductor 162 can be increased, thereby reducing the wiring resistance. Alternatively, as shown in Figure 17B, the width of the conductor 162 can be reduced to decrease the area in which the conductor 162 and the conductor 205a1 overlap.

[0306] <Method for fabricating semiconductor devices> Insulating materials for forming insulators, conductive materials for forming conductors, or semiconductor materials for forming semiconductors can be deposited using methods such as sputtering, CVD, MBE, PLD, and ALD as appropriate.

[0307] Sputtering methods include RF sputtering, which uses a high-frequency power supply; DC sputtering, which uses a direct current power supply; and pulsed DC sputtering, which changes the voltage applied to the electrodes in pulses. RF sputtering is mainly used for depositing insulating films, while DC sputtering is mainly used for depositing conductive metal films. Pulsed DC sputtering is mainly used when depositing compounds such as oxides, nitrides, or carbides using reactive sputtering.

[0308] Furthermore, CVD methods can be classified into plasma CVD (PECVD), which utilizes plasma; thermal CVD (TCVD), which utilizes heat; and photo CVD (Photo CVD), which utilizes light. They can also be further divided into metal CVD (MCVD) and metal-organic CVD (MOCVD) depending on the source gas used.

[0309] Plasma CVD allows for the production of high-quality films at relatively low temperatures. Thermal CVD, on the other hand, does not use plasma, thus minimizing plasma damage to the workpiece. For example, wiring, electrodes, and components (transistors, capacitors, etc.) in semiconductor devices can be charged up by receiving charge from the plasma. This accumulated charge can damage the wiring, electrodes, or components in the semiconductor device. In contrast, thermal CVD, which does not use plasma, avoids such plasma damage, resulting in a higher yield for semiconductor devices. Furthermore, thermal CVD produces films with fewer defects because it avoids plasma damage during deposition.

[0310] Furthermore, ALD methods such as thermal ALD, which carries out the reaction of the precursor and reactant using only thermal energy, and PEALD, which uses plasma-excited reactants, can be used.

[0311] CVD and ALD methods differ from sputtering, where particles emitted from a target or other source are deposited. Therefore, they are less affected by the shape of the workpiece and provide good step-level coating. In particular, the ALD method offers excellent step-level coating and superior thickness uniformity, making it suitable, for example, for coating the surface of an opening with a high aspect ratio. However, since the ALD method has a relatively slow deposition rate, it may be preferable to use it in combination with other deposition methods such as the CVD method, which has a faster deposition rate.

[0312] Furthermore, the CVD method allows for the deposition of films with any desired composition by changing the flow rate ratio of the raw material gases. For example, in the CVD method, films with continuously changing compositions can be deposited by changing the flow rate ratio of the raw material gases while the film is being deposited. When depositing films while changing the flow rate ratio of the raw material gases, the time required for film deposition can be shortened compared to depositing films using multiple deposition chambers, because time spent on transport or pressure adjustment is eliminated. Therefore, it may be possible to increase the productivity of semiconductor devices.

[0313] Furthermore, the ALD method allows for the deposition of films of any composition by simultaneously introducing multiple different types of precursors. Alternatively, when introducing multiple different types of precursors, films of any composition can be deposited by controlling the number of cycles for each precursor.

[0314] The insulator 222 can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, hafnium oxide is deposited as the insulator 222 using the ALD method. Alternatively, the insulator 222 may be a laminated structure of silicon nitride deposited using the PEALD method and hafnium oxide deposited using the ALD method.

[0315] Heat treatment may be performed after the deposition of the insulator 222. The heat treatment temperature is preferably 250°C to 650°C, more preferably 300°C to 500°C, and even more preferably 320°C to 450°C. The heat treatment is preferably performed in an atmosphere of nitrogen gas or an inert gas, or in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas.

[0316] Metal oxides 230a and 230b can be deposited using, for example, sputtering, CVD, MBE, PLD, or ALD. In this embodiment, sputtering is used to deposit metal oxides 230a and 230b.

[0317] For example, when depositing metal oxide 230a and metal oxide 230b by sputtering, oxygen or a mixture of oxygen and a noble gas is used as the sputtering gas. By increasing the proportion of oxygen in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. Also, when depositing metal oxide 230a and metal oxide 230b by sputtering, an In-M-Zn oxide target can be used, for example.

[0318] The insulator 253 can be deposited using, for example, ALD, sputtering, CVD, MBE, or PLD.

[0319] Furthermore, when forming the insulating film that will become the insulator 253 using the ALD method, ozone (O3), oxygen (O2), or water (H2O) can be used as the oxidizing agent. By using hydrogen-free ozone (O3) or oxygen (O2) as the oxidizing agent, the amount of hydrogen diffusing into the metal oxide 230b can be reduced.

[0320] This embodiment can be combined with other embodiments as appropriate. Furthermore, if multiple configuration examples are shown within a single embodiment in this specification, these configuration examples can be combined as appropriate.

[0321] (Embodiment 3) In this embodiment, an example of a chip on which a storage device according to one aspect of the present invention is mounted will be described with reference to the drawings.

[0322] The chip 1200 shown in Figures 18A and 18B has multiple circuits (systems) mounted on it. This technology of integrating multiple circuits (systems) onto a single chip is sometimes called a System on Chip (SoC).

[0323] As shown in Figure 18A, the chip 1200 includes a CPU 1211, a GPU 1212, one or more analog processing units 1213, one or more memory controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0324] The chip 1200 is provided with bumps (not shown) and connects to the first surface of the package substrate 1201, as shown in Figure 18B. In addition, multiple bumps 1202 are provided on the back surface of the first surface of the package substrate 1201 and connect to the motherboard 1203.

[0325] The motherboard 1203 may be equipped with storage devices such as DRAM 1221 and flash memory 1222. For example, the storage circuit shown in the previous embodiment can be used for DRAM 1221. This makes it possible to increase the capacity, speed, and power consumption of DRAM 1221.

[0326] The CPU 1211 preferably has multiple CPU cores. Similarly, the GPU 1212 preferably has multiple GPU cores. The CPU 1211 and GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory common to the CPU 1211 and GPU 1212 may be provided on the chip 1200. The memory can use the storage circuit described above. The GPU 1212 is suitable for parallel computation of a large amount of data and can be used for image processing or multiply-accumulate operations. By providing the GPU 1212 with an image processing circuit or multiply-accumulate operation circuit using OS transistors, it becomes possible to perform image processing or multiply-accumulate operations with low power consumption.

[0327] Furthermore, because the CPU 1211 and GPU 1212 are located on the same chip, the wiring between the CPU 1211 and GPU 1212 can be shortened, enabling high-speed data transfer from the CPU 1211 to the GPU 1212, data transfer between the memories of the CPU 1211 and GPU 1212, and transfer of calculation results from the GPU 1212 to the CPU 1211 after calculations have been performed by the GPU 1212.

[0328] The analog arithmetic unit 1213 includes one or both of an A / D (analog-to-digital) conversion circuit and a D / A (digital-to-analog) conversion circuit. Alternatively, the analog arithmetic unit 1213 may also be provided with the above-mentioned sum-of-accumulate circuit.

[0329] The memory controller 1214 has a circuit that functions as a controller for the DRAM 1221 and a circuit that functions as an interface for the flash memory 1222.

[0330] Interface 1215 has interface circuits for external devices such as display devices, speakers, microphones, cameras, and controllers. Controllers include mice, keyboards, and game controllers. Such interfaces can include USB (Universal Serial Bus) or HDMI (High-Definition Multimedia Interface), etc.

[0331] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network). It may also include a circuit for network security.

[0332] The above-mentioned circuits (systems) can be formed on chip 1200 using the same manufacturing process. Therefore, even if the number of circuits required for chip 1200 increases, there is no need to increase the number of manufacturing processes, and chip 1200 can be manufactured at a low cost.

[0333] A package substrate 1201 on which a chip 1200 having a GPU 1212 is provided, a motherboard 1203 on which a DRAM 1221 and a flash memory 1222 are provided can be called a GPU module 1204.

[0334] The GPU module 1204 has a chip 1200 that uses SoC technology, which allows for a smaller size. Furthermore, its excellent image processing capabilities make it suitable for use in portable electronic devices such as smartphones, tablet devices, laptop PCs, or portable game consoles. Additionally, the multiply-accumulate circuit using the GPU 1212 enables the execution of techniques such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN), allowing the chip 1200 to be used as an AI chip, or the GPU module 1204 as an AI system module.

[0335] This embodiment can be combined with other embodiments as appropriate.

[0336] (Embodiment 4) This embodiment shows an example of an electronic component incorporating a storage device according to one aspect of the present invention.

[0337] [Electronic components] Figure 19A shows a perspective view of an electronic component 700 and a circuit board (mounted board 704) on which the electronic component 700 is mounted. The electronic component 700 shown in Figure 19A has a storage device 100, which is a storage device according to one aspect of the present invention, within a mold 711. Some details have been omitted in Figure 19A to show the inside of the electronic component 700. The electronic component 700 has a land 712 on the outside of the mold 711. The land 712 is electrically connected to an electrode pad 713, and the electrode pad 713 is electrically connected to the storage device 100 via a wire 714. The electronic component 700 is mounted, for example, on a printed circuit board 702. Multiple such electronic components are combined and electrically connected on the printed circuit board 702 to complete the mounted board 704.

[0338] As shown in the above embodiment, the storage device 100 includes a drive circuit layer 50 and a storage layer 11 (including a memory cell array 15).

[0339] Figure 19B shows a perspective view of the electronic component 730. The electronic component 730 is an example of a SiP (System in Package) or MCM (Multi Chip Module). The electronic component 730 has an interposer 731 on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of storage devices 100 are provided on the interposer 731.

[0340] Electronic component 730 shows an example where the storage device 100 is used as a high-bandwidth memory (HBM). Furthermore, the semiconductor device 735 can be an integrated circuit (semiconductor device) such as a CPU, GPU, or FPGA.

[0341] The package substrate 732 can be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 can be, for example, a silicon interposer or a resin interposer.

[0342] The interposer 731 has multiple wirings and functions to electrically connect multiple integrated circuits with different terminal pitches. The multiple wirings are provided in a single layer or multiple layers. The interposer 731 also functions to electrically connect integrated circuits provided on the interposer 731 to electrodes provided on the package substrate 732. For these reasons, the interposer is sometimes called a "redistribution board" or "intermediate board". In addition, through electrodes may be provided on the interposer 731, and these through electrodes may be used to electrically connect the integrated circuits and the package substrate 732. Furthermore, in silicon interposers, TSVs (Through Silicon Vias) can also be used as through electrodes.

[0343] It is preferable to use a silicon interposer as the interposer 731. Since silicon interposers do not require active elements, they can be manufactured at a lower cost than integrated circuits. On the other hand, since the wiring of a silicon interposer can be formed using a semiconductor process, it is easy to form fine wiring, which is difficult with resin interposers.

[0344] In HBMs, many connections are necessary to achieve a wide memory bandwidth. Therefore, the interposer on which the HBM is mounted requires fine and high-density wiring. For this reason, it is preferable to use a silicon interposer for mounting the HBM.

[0345] Furthermore, in SiP and MCM using silicon interposers, reliability degradation due to differences in expansion coefficients between the integrated circuit and the interposer is less likely to occur. In addition, because silicon interposers have high surface flatness, connection failures between the integrated circuit and the silicon interposer are less likely to occur. In particular, in 2.5D packages (2.5-dimensional packaging) where multiple integrated circuits are arranged side by side on the interposer, it is preferable to use a silicon interposer.

[0346] Alternatively, a heat sink (heat dissipation plate) may be provided on top of the electronic component 730. If a heat sink is provided, it is preferable to align the heights of the integrated circuits provided on the interposer 731. For example, in the electronic component 730 shown in this embodiment, it is preferable to align the heights of the memory device 100 and the semiconductor device 735.

[0347] To mount the electronic component 730 onto another substrate, electrodes 733 may be provided at the bottom of the package substrate 732. Figure 19B shows an example where the electrodes 733 are formed with solder balls. By providing solder balls in a matrix at the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrodes 733 may be formed with conductive pins. By providing conductive pins in a matrix at the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0348] The electronic component 730 can be mounted on other boards using various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0349] This embodiment can be combined with other embodiments as appropriate.

[0350] (Embodiment 5) This embodiment describes an application example of a storage device according to one aspect of the present invention.

[0351] A storage device according to one aspect of the present invention can be applied to storage devices of various electronic devices (e.g., information terminals, computers, smartphones, e-book readers, digital still cameras, video cameras, recording and playback devices, navigation systems, and game consoles). It can also be used in image sensors, IoT (Internet of Things), or healthcare-related equipment. Here, "computer" includes tablet computers, notebook computers, and desktop computers, as well as large computers such as server systems.

[0352] An example of an electronic device having a storage device according to one embodiment of the present invention will be described. Figures 20A to 20J and 21A to 21E illustrate how the electronic component 700 or electronic component 730 having the storage device described in the previous embodiment is included in each electronic device.

[0353] [mobile phone] The information terminal 5500 shown in Figure 20A is a type of information terminal, specifically a mobile phone (smartphone). The information terminal 5500 has a housing 5510 and a display unit 5511. For input interfaces, a touch panel is provided on the display unit 5511, and buttons are provided on the housing 5510.

[0354] The information terminal 5500 can store temporary files generated during application execution (for example, cache when using a web browser) by applying a storage device according to one aspect of the present invention.

[0355] [Wearable devices] Figure 20B shows an information terminal 5900, which is an example of a wearable device. The information terminal 5900 has a housing 5901, a display unit 5902, an operation switch 5903, an operation switch 5904, and a band 5905.

[0356] Similar to the information terminal 5500 described above, a wearable device can store temporary files generated during application execution by applying a storage device according to one aspect of the present invention.

[0357] [Information terminal] Figure 20C shows a desktop information terminal 5300. The desktop information terminal 5300 comprises a main unit 5301, a display unit 5302, and a keyboard 5303.

[0358] The desktop information terminal 5300, like the information terminal 5500 described above, can store temporary files generated during application execution by applying a storage device according to one aspect of the present invention.

[0359] Figures 20A to 20C illustrate smartphones, wearable devices, and desktop information terminals as electronic devices. Other information terminals include, for example, PDAs (Personal Digital Assistants), notebook computers, and workstations.

[0360] [electric appliances] Figure 20D shows an electric refrigerator-freezer 5800 as an example of an electrical appliance. The electric refrigerator-freezer 5800 has a casing 5801, a refrigerator door 5802, and a freezer door 5803, etc. For example, the electric refrigerator-freezer 5800 is an electric refrigerator-freezer compatible with IoT (Internet of Things).

[0361] A storage device according to one aspect of the present invention can be applied to an electric refrigerator 5800. The electric refrigerator 5800 can send and receive information such as the food stored in the electric refrigerator 5800 and the expiration date of that food to an information terminal, for example, via the Internet. The electric refrigerator 5800 can store temporary files generated when transmitting such information in a storage device according to one aspect of the present invention.

[0362] Figure 20D describes electric refrigerators as electrical appliances, but other electrical appliances include, for example, vacuum cleaners, microwave ovens, electric ovens, rice cookers, water heaters, induction cooktops, water dispensers, heating and cooling appliances including air conditioners, washing machines, dryers, and audiovisual equipment.

[0363] [Game console] Figure 20E shows a portable game console 5200, which is an example of a game console. The portable game console 5200 has a housing 5201, a display unit 5202, and buttons 5203, etc.

[0364] Figure 20F also shows a home console 7500, which is an example of a game console. The home console 7500 can be specifically described as a home console. The home console 7500 has a main unit 7520 and a controller 7522. The controller 7522 can be connected to the main unit 7520 wirelessly or wired. Although not shown in Figure 20F, the controller 7522 may also be equipped with a display unit for displaying game images, and input interfaces other than buttons, such as a touch panel, a joystick, a rotary knob, or a sliding knob. Furthermore, the shape of the controller 7522 is not limited to the shape shown in Figure 20F, and the shape of the controller 7522 may be changed in various ways depending on the genre of game. For example, in shooting games such as FPS (First Person Shooter), a controller with triggers as buttons and a shape that mimics a gun can be used. Also, for example, in music games, a controller that mimics a musical instrument or musical equipment can be used. Furthermore, home game consoles may not use controllers, but instead be equipped with one or more cameras, depth sensors, and microphones, and operated by the game player's gestures or voice.

[0365] Furthermore, the video from the aforementioned game console can be output by display devices such as television equipment, personal computer displays, game displays, or head-mounted displays.

[0366] By applying a storage device according to one aspect of the present invention to a portable game console 5200 or a home game console 7500, power consumption can be reduced. Furthermore, by reducing power consumption, heat generation from the circuit can be reduced, thereby minimizing the impact of heat on the circuit itself, peripheral circuits, and modules.

[0367] Furthermore, by applying a storage device according to one aspect of the present invention to a portable game console 5200 or a home game console 7500, it is possible to retain temporary files and the like necessary for calculations that occur during game execution.

[0368] Figures 20E and 20F illustrate portable game consoles and home console game consoles as examples of game machines. Other examples of game machines include arcade game machines installed in entertainment facilities (game centers, amusement parks, etc.) and pitching machines for batting practice installed in sports facilities.

[0369] [Mobile] A storage device according to one aspect of the present invention can be applied to a mobile vehicle and the area around the driver's seat of the vehicle.

[0370] Figure 20G shows an example of a mobile device, an automobile 5700.

[0371] The driver's seat area of ​​the automobile 5700 is equipped with an instrument panel that displays various information such as the speedometer, tachometer, mileage, fuel gauge, gear status, and air conditioning settings. A storage device that displays this information may also be provided around the driver's seat.

[0372] In particular, by displaying images from an imaging device (not shown) installed in the automobile 5700, the display device can compensate for, for example, blind spots obstructed by pillars or the driver's seat, thereby enhancing safety. That is, by displaying images from an imaging device installed on the outside of the automobile 5700, blind spots can be compensated for and safety can be enhanced.

[0373] A storage device according to one aspect of the present invention can temporarily hold information, and therefore, for example, can be used to hold necessary temporary information in a system that performs autonomous driving, road guidance, or hazard prediction for a vehicle 5700. Furthermore, a storage device according to one aspect of the present invention may be configured to hold video footage from a driving recorder installed in the vehicle 5700.

[0374] While the above explanation uses automobiles as an example of a moving object, the definition of a moving object is not limited to automobiles. For example, other examples of moving objects include trains, monorails, ships, and flying objects (helicopters, unmanned aerial vehicles (drones), airplanes, and rockets).

[0375] [camera] A storage device according to one aspect of the present invention can be applied to a camera.

[0376] Figure 20H shows a digital camera 6240, which is an example of an imaging device. The digital camera 6240 has a housing 6241, a display unit 6242, an operation switch 6243, and a shutter button 6244, and a detachable lens 6246 is attached to the digital camera 6240. In this example, the digital camera 6240 is configured so that the lens 6246 can be removed from the housing 6241 and replaced, but the lens 6246 and housing 6241 may be integrated. The digital camera 6240 may also be configured to allow for the attachment of a strobe device or a viewfinder separately.

[0377] By applying a storage device according to one aspect of the present invention to the digital camera 6240, power consumption can be reduced. Furthermore, reduced power consumption can reduce heat generation from the circuit, thereby minimizing the impact of heat on the circuit itself, peripheral circuits, and modules.

[0378] [Video camera] A storage device according to one aspect of the present invention can be applied to a video camera.

[0379] Figure 20I shows a video camera 6300, which is an example of an imaging device. The video camera 6300 has a first housing 6301, a second housing 6302, a display unit 6303, an operation switch 6304, a lens 6305, and a connection unit 6306. The operation switch 6304 and the lens 6305 are provided in the first housing 6301, and the display unit 6303 is provided in the second housing 6302. The first housing 6301 and the second housing 6302 are connected by the connection unit 6306, and the angle between the first housing 6301 and the second housing 6302 can be changed by the connection unit 6306. The image on the display unit 6303 may be switched according to the angle between the first housing 6301 and the second housing 6302 at the connection unit 6306.

[0380] When recording video footage captured by the video camera 6300, encoding is required according to the data recording format. By using a storage device according to one aspect of the present invention, the video camera 6300 can retain temporary files generated during encoding.

[0381] [ICD] A memory device according to one aspect of the present invention can be applied to an implantable cardioverter-defibrillator (ICD).

[0382] Figure 20J is a schematic cross-sectional view showing an example of an ICD. The ICD unit 5400 includes at least a battery 5401, electronic components 700, a regulator, a control circuit, an antenna 5404, a wire 5402 to the right atrium, and a wire 5403 to the right ventricle.

[0383] The ICD unit 5400 is surgically implanted in the body, and two wires are routed through the subclavian vein 5405 and superior vena cava 5406 so that one wire tip is placed in the right ventricle and the other wire tip is placed in the right atrium.

[0384] The ICD unit 5400 functions as a pacemaker, pacing the heart if the heart rate falls outside the specified range. If pacing does not improve the heart rate (e.g., in cases of rapid ventricular tachycardia or ventricular fibrillation), treatment with an electric shock is administered.

[0385] The ICD unit 5400 needs to constantly monitor the heart rate in order to properly perform pacing and electric shocks. Therefore, the ICD unit 5400 has a sensor for detecting the heart rate. In addition, the ICD unit 5400 can store, for example, heart rate data acquired by the sensor, the number of times pacing treatment was performed, or the duration in the electronic component 700.

[0386] Furthermore, the antenna 5404 can receive power, which is then used to charge the battery 5401. The ICD unit 5400 also benefits from having multiple batteries, thus enhancing safety. Specifically, even if some of the batteries in the ICD unit 5400 fail, the remaining batteries can still function, thus acting as an auxiliary power source.

[0387] In addition to the antenna 5404 that can receive power, the system may also have an antenna that can transmit physiological signals. For example, a system may be configured to monitor cardiac activity so that physiological signals such as pulse rate, respiratory rate, heart rate, and body temperature can be checked on an external monitoring device.

[0388] [Extension devices for PCs] A storage device according to one aspect of the present invention can be applied to computers such as PCs (Personal Computers) and expansion devices for information terminals.

[0389] Figure 21A shows an example of such an expansion device, a portable expansion device 6100 that connects to a PC externally and is equipped with a chip capable of storing information. The expansion device 6100 can store information using the chip by connecting to the PC, for example, via USB (Universal Serial Bus). Although Figure 21A illustrates a portable form of the expansion device 6100, the expansion device according to one aspect of the present invention is not limited to this, and may be a relatively large form of expansion device equipped with a cooling fan, for example.

[0390] The expansion device 6100 comprises a housing 6101, a cap 6102, a USB connector 6103, and a circuit board 6104. The circuit board 6104 is housed in the housing 6101. The circuit board 6104 is provided with, for example, a circuit for driving a storage device according to one aspect of the present invention. For example, electronic components 700 and a controller chip 6106 are mounted on the circuit board 6104. The USB connector 6103 functions as an interface for connecting to an external device.

[0391] [SD card] A storage device according to one aspect of the present invention can be applied to an SD card that can be attached to an electronic device such as an information terminal or a digital camera.

[0392] Figure 21B is a schematic diagram of the external appearance of an SD card, and Figure 21C is a schematic diagram of the internal structure of an SD card. The SD card 5110 has a housing 5111, a connector 5112, and a circuit board 5113. The connector 5112 functions as an interface for connecting to an external device. The circuit board 5113 is housed in the housing 5111. The circuit board 5113 is provided with a storage device and a circuit for driving the storage device. For example, an electronic component 700 and a controller chip 5115 are mounted on the circuit board 5113. Note that the circuit configurations of the electronic component 700 and the controller chip 5115 are not limited to those described above, and the circuit configurations may be changed as appropriate depending on the situation. For example, the writing circuit, load driver, or reading circuit provided in the electronic component may be incorporated into the controller chip 5115 instead of the electronic component 700.

[0393] By providing electronic components 700 on the back side of the circuit board 5113, the capacity of the SD card 5110 can be increased. Alternatively, a wireless chip with wireless communication capabilities may be provided on the circuit board 5113. This allows for wireless communication between an external device and the SD card 5110, enabling the reading and writing of data to and from the electronic components 700.

[0394] [SSD] A storage device according to one aspect of the present invention can be applied to an SSD (Solid State Drive) that can be attached to an electronic device such as an information terminal.

[0395] Figure 21D is a schematic diagram of the external appearance of the SSD, and Figure 21E is a schematic diagram of the internal structure of the SSD. The SSD 5150 has a housing 5151, a connector 5152, and a circuit board 5153. The connector 5152 functions as an interface for connecting to external devices. The circuit board 5153 is housed in the housing 5151. The circuit board 5153 is equipped with a storage device and a circuit for driving the storage device. For example, electronic components 700, a memory chip 5155, and a controller chip 5156 are mounted on the circuit board 5153. The capacity of the SSD 5150 can be increased by also providing electronic components 700 on the back side of the circuit board 5153. Work memory is incorporated into the memory chip 5155. For example, a DRAM chip can be used for the memory chip 5155. The controller chip 5156 incorporates a processor and an ECC (Error-Correcting Code) circuit, etc. The circuit configurations of the electronic component 700, the memory chip 5155, and the controller chip 5115 are not limited to those described above, and may be modified as appropriate depending on the circumstances. For example, the controller chip 5156 may also be provided with memory that functions as work memory.

[0396] [Calculator] The computer 5600 shown in Figure 22A is an example of a large-scale computer. The computer 5600 houses multiple rack-mount type computers 5620 in rack 5610.

[0397] Computer 5620 can have a configuration similar to the perspective view shown in Figure 22B. In Figure 22B, computer 5620 has a motherboard 5630, which has multiple slots 5631 and multiple connection terminals. A PC card 5621 is inserted into slot 5631. In addition, the PC card 5621 has connection terminals 5623, 5624, and 5625, which are each connected to the motherboard 5630.

[0398] The PC card 5621 shown in Figure 22C is an example of a processing board equipped with a CPU, GPU, and storage device. The PC card 5621 has a board 5622. The board 5622 also has connection terminals 5623, 5624, and 5625, as well as semiconductor devices 5626, 5627, 5628, and 5629. Although Figure 22C shows semiconductor devices other than semiconductor devices 5626, 5627, and 5628, for details on these semiconductor devices, please refer to the descriptions of semiconductor devices 5626, 5627, and 5628 below.

[0399] The connector 5629 has a shape that allows it to be inserted into slot 5631 of the motherboard 5630, and the connector 5629 functions as an interface for connecting the PC card 5621 and the motherboard 5630. A PCIe standard is one example of a connector 5629.

[0400] Terminals 5623, 5624, and 5625 can serve as interfaces for, for example, supplying power or inputting signals to the PC card 5621. They can also serve as interfaces for outputting signals calculated by the PC card 5621. Examples of the standards for terminals 5623, 5624, and 5625 include USB (Universal Serial Bus), SATA (Serial ATA), and SCSI (Small Computer System Interface). When outputting video signals from terminals 5623, 5624, and 5625, an example of the standard for each terminal is HDMI (registered trademark).

[0401] The semiconductor device 5626 has terminals (not shown) for inputting and outputting signals, and the semiconductor device 5626 and the board 5622 can be electrically connected by inserting these terminals into sockets (not shown) provided on the board 5622.

[0402] The semiconductor device 5627 has multiple terminals, and the semiconductor device 5627 and the board 5622 can be electrically connected by, for example, reflow soldering, to the wiring provided on the board 5622 using these terminals. Examples of semiconductor devices 5627 include FPGAs (Field Programmable Gate Arrays), GPUs, and CPUs. For example, an electronic component 730 can be used as the semiconductor device 5627.

[0403] The semiconductor device 5628 has multiple terminals, and the semiconductor device 5628 and the board 5622 can be electrically connected by, for example, reflow soldering, to the terminals on the board 5622. Examples of the semiconductor device 5628 include a memory device. For example, an electronic component 700 can be used as the semiconductor device 5628.

[0404] Computer 5600 can also function as a parallel computer. By using Computer 5600 as a parallel computer, it is possible to perform large-scale calculations necessary for, for example, artificial intelligence training and inference.

[0405] By using a memory device according to one aspect of the present invention in the various electronic devices described above, it is possible to miniaturize and reduce the power consumption of the electronic devices. Furthermore, because the memory device according to one aspect of the present invention consumes little power, it is possible to reduce heat generation from the circuit. Therefore, adverse effects on the circuit itself, peripheral circuits, and modules due to such heat generation can be reduced. In addition, by using a memory device according to one aspect of the present invention, it is possible to realize electronic devices that operate stably even in high-temperature environments. Therefore, the reliability of electronic devices can be improved.

[0406] This embodiment can be combined with other embodiments as appropriate.

[0407] (Embodiment 6) In this embodiment, a specific example of applying a semiconductor device according to one aspect of the present invention to space equipment will be explained with reference to Figure 23.

[0408] One embodiment of the present invention includes an OS transistor. The OS transistor exhibits small fluctuations in electrical properties due to radiation exposure. In other words, it has high resistance to radiation and can therefore be suitably used in environments where radiation may be incident. For example, the OS transistor can be suitably used in outer space.

[0409] Figure 23 shows satellite 6800 as an example of space equipment. Satellite 6800 comprises a body 6801, solar panels 6802, an antenna 6803, a secondary battery 6805, and a control device 6807. In Figure 23, planet 6804 is shown as an example in outer space. Outer space refers to, for example, an altitude of 100 km or more, but outer space as described herein may include one or more of the thermosphere, mesosphere, and stratosphere.

[0410] Furthermore, outer space is an environment with radiation levels more than 100 times higher than those on Earth. Examples of radiation include electromagnetic waves (electromagnetic radiation) such as X-rays and gamma rays, as well as particle radiation such as alpha rays, beta rays, neutrons, protons, heavy ions, and mesons.

[0411] When sunlight shines on the solar panel 6802, the power necessary for the satellite 6800 to operate is generated. However, if, for example, the solar panel does not receive sunlight, or if the amount of sunlight hitting the solar panel is low, the amount of power generated will decrease. Therefore, there is a possibility that the power necessary for the satellite 6800 to operate may not be generated. To operate the satellite 6800 even under conditions of low power generation, it is advisable to install a secondary battery 6805 on the satellite 6800. Note that solar panels are sometimes called solar cell modules.

[0412] Satellite 6800 can generate a signal. This signal is transmitted via antenna 6803, and can be received by, for example, a receiver on the ground or another satellite. By receiving the signal transmitted by satellite 6800, the position of the receiver that received the signal can be measured. Thus, satellite 6800 can constitute a satellite positioning system.

[0413] Furthermore, the control device 6807 has the function of controlling the artificial satellite 6800. The control device 6807 is configured using one or more selected from, for example, a CPU, a GPU, and a memory device. It is preferable to use a semiconductor device including an OS transistor, which is one embodiment of the present invention, for the control device 6807. Compared to Si transistors, OS transistors exhibit less fluctuation in electrical characteristics due to radiation irradiation. In other words, they are highly reliable and can be suitably used even in environments where radiation may be incident.

[0414] Furthermore, the satellite 6800 can be configured to include sensors. For example, by configuring it to include a visible light sensor, the satellite 6800 can have the function of detecting sunlight reflected off objects on the ground. Alternatively, by configuring it to include a thermal infrared sensor, the satellite 6800 can have the function of detecting thermal infrared radiation emitted from the Earth's surface. Thus, the satellite 6800 can function, for example, as an Earth observation satellite.

[0415] In this embodiment, an artificial satellite was used as an example of space equipment, but the invention is not limited to this. For example, a semiconductor device according to one aspect of the present invention can be suitably used in space equipment such as spacecraft, space capsules, and space probes. [Explanation of symbols]

[0416] 10: Memory cell, 11: Memory layer, 15: Memory cell array, 22: PSW, 23: PSW, 31: Peripheral circuit, 32: Control circuit, 33: Voltage generation circuit, 41: Peripheral circuit, 42: Row decoder, 43: Row driver, 44: Column decoder, 45: Column driver, 46: Sense amplifier, 47: Input circuit, 48: Output circuit, 50: Drive circuit layer, 100: Memory device, 101: Capacitance, 101b: Capacitance, 160: Conductor, 161: Conductor, 162: Conductor, 163: Insulator, 181: Insulator, 183: Insulator, 185: Insulator, 201: Transistor, 202: Transistor 203: Transistor, 205a: Conductor, 205b: Conductor, 205: Conductor, 209a: Conductor, 209b: Conductor, 209: Conductor, 210: Insulator, 212: Insulator, 214: Insulator, 215: Insulator, 215F: Insulator, 216a: Insulator, 216b: Insulator, 222: Insulator, 222F: Insulator, 224: Insulator, 230a: Metal oxide, 230b: Metal oxide, 230: Metal oxide, 231: Conductor, 232: Conductor, 233a: Conductor, 233b: Conductor, 240a: Conductor, 240b: Conductor, 240c: Connecting electrode, 24 0d: connecting electrode, 240: conductor, 242a: conductor, 242b: conductor, 242c: conductor, 242d: conductor, 242e: conductor, 242: conductor, 253: insulator, 254: insulator, 258: opening, 260: conductor, 275: insulator, 280: insulator, 282: insulator, 285: insulator, 287: insulator, 288: insulator, 291a: opening, 291b: opening, 292a: opening, 292b: opening, 293a: opening, 293b: opening, 294a: opening, 294b: opening, 300: transistor, 311: substrate, 313: semiconductor region, 314a: low resistance Region, 314b: Low resistance region, 315: Insulator, 316: Conductor, 320: Insulator, 322: Insulator, 324: Insulator, 326: Insulator, 328: Conductor, 330: Conductor, 700: Electronic component, 702: Printed circuit board, 704: Mounted circuit board, 711: Mold, 712: Land, 713: Electrode pad, 714: Wire, 730: Electronic component, 731: Interposer, 732: Package substrate, 733: Electrode, 735: Semiconductor device, 1200: Chip, 1201: Package substrate, 1202: Bump, 1203: Motherboard, 1204: GPU module,1211: CPU, 1212: GPU, 1213: Analog processing unit, 1214: Memory controller, 1215: Interface, 1216: Network circuit, 1221: DRAM, 1222: Flash memory, 5110: SD card, 5111: Enclosure, 5112: Connector, 5113: Circuit board, 5115: Controller chip, 5150: SSD, 5151: Enclosure, 5152: Connector, 5153: Circuit board, 5155: Memory chip, 5156: Controller chip, 5200: Portable game console, 5201: Enclosure, 5202: Front Display unit, 5203: Button, 5300: Desktop information terminal, 5301: Main unit, 5302: Display unit, 5303: Keyboard, 5400: ICD main unit, 5401: Battery, 5402: Wire, 5403: Wire, 5404: Antenna, 5405: Subclavian vein, 5406: Superior vena cava, 5500: Information terminal, 5510: Enclosure, 5511: Display unit, 5600: Computer, 5610: Rack, 5620: Computer, 5621: PC card, 5622: Board, 5623: Connection terminal, 5624: Connection terminal, 5625: Connection terminal, 5626: Half Conductor device, 5627: Semiconductor device, 5628: Semiconductor device, 5629: Connector terminal, 5630: Motherboard, 5631: Slot, 5700: Automobile, 5800: Electric refrigerator / freezer, 5801: Enclosure, 5802: Door for refrigerator compartment, 5803: Door for freezer compartment, 5900: Information terminal, 5901: Enclosure, 5902: Display unit, 5903: Operation switch, 5904: Operation switch, 5905: Band, 6100: Expansion device, 6101: Enclosure, 6102: Cap, 6103: USB connector, 6104: Circuit board, 6106: Controller chip, 6 240: Digital camera, 6241: Casing, 6242: Display unit, 6243: Operation switch, 6244: Shutter button, 6246: Lens, 6300: Video camera, 6301: First casing, 6302: Second casing, 6303: Display unit, 6304: Operation switch, 6305: Lens, 6306: Connection unit, 6800: Artificial satellite, 6801: Aircraft, 6802: Solar panel, 6803: Antenna, 6804: Planet, 6805: Rechargeable battery, 6807: Control unit, 7500: Home game console, 7520: Main unit, 7522: Controller,

Claims

[Claim 1] A device comprising a first transistor, a second transistor, and a capacitor, The first transistor comprises a first insulator, a first metal oxide on the first insulator, a second insulator on the first metal oxide, a first conductor on the second insulator, a second conductor covering a portion of the upper surface and a portion of the side surface of the first metal oxide, and a third conductor covering a portion of the upper surface and a portion of the side surface of the first metal oxide. The second transistor comprises the first insulator, the first metal oxide on the first insulator, the third insulator on the first metal oxide, the fourth conductor on the third insulator, the third conductor, and the fifth conductor covering a portion of the upper surface and a portion of the side surface of the first metal oxide. The third conductor is shared by the first transistor and the second transistor. The first metal oxide is shared between the first transistor and the second transistor. The first metal oxide has a channel formation region for the first transistor and a channel formation region for the second transistor. The first insulator has a region that overlaps with the first metal oxide, The aforementioned capacitance comprises a sixth conductor, a seventh conductor, and a ferroelectric material located between the sixth and seventh conductors. The first conductor and the sixth conductor are electrically connected semiconductor device, It has a third transistor, The first insulator has a material that may have ferroelectric properties, The third transistor comprises an eighth conductor, a first insulator on the eighth conductor, a second metal oxide on the first insulator, a fifth insulator on the second metal oxide, a ninth conductor on the fifth insulator, and a sixth conductor covering a portion of the upper surface and a portion of the side surface of the second metal oxide. The sixth conductor has a region that is in contact with the upper surface of the first insulator, The seventh conductor has a region that is in contact with the lower surface of the first insulator. The eighth conductor has a region that is in contact with the lower surface of the first insulator, The semiconductor device has a first insulator having a region superimposed on the second metal oxide and a region superimposed on the seventh conductor.

Images