Magnetic domain wall moving element and magnetic array

Abstract

This domain wall displacement element comprises a first magnetoresistance effect element and a first transistor. A first domain displacement layer of the first domain displacement layer is electrically connected to the first active region of the first transistor. The length in a first direction of the first magnetoresistance effect element is greater than the length in a second direction. The length in the first direction of the first gate is greater than the length in the second direction. The length in the first direction of the first magnetoresistance effect element is greater than the length in the first direction of the first gate. A first gate length direction that joins the first active region and the second active region crosses the first direction.

Description

[Technical Field]

[0001] The present invention relates to a magnetic domain wall moving element and a magnetic array. [Background technology]

[0002] A magnetoresistive element that utilizes the change in resistance (magnetoresistance change) based on the change in the relative angle of magnetization between two ferromagnetic layers is known. For example, Patent Document 1 discloses a magnetic domain wall-moving type magnetoresistive element. In a magnetic domain wall-moving type magnetoresistive element, the resistance value in the stacking direction changes depending on the position of the magnetic domain wall, and data can be recorded in multi-level or analog format.

[0003] Magnetic domain wall-moving magnetoresistive elements can be used in neuromorphic devices that mimic brain function, as described in, for example, Patent Document 2. [Prior art documents] [Patent Documents]

[0004] [Patent Document 1] Patent No. 5441005 [Patent Document 2] Japanese Patent Publication No. 2020-053660 [Overview of the project] [Problems that the invention aims to solve]

[0005] Magnetoresistive elements are often used as magnetic arrays, which integrate multiple elements. To process a large amount of information in a small area, high integration of magnetic arrays is required. For magnetic domain wall movement type magnetoresistive elements, the wider the domain wall movement range, the more states can be represented. To widen the domain wall movement range, the shape of the magnetoresistive element becomes elongated in one direction. Furthermore, the write current of magnetic domain wall movement type magnetoresistive elements is greater than the read current. To ensure a sufficient write current, it is necessary to use transistors with high rated current, which increases the gate width of the transistors. In other words, there are limitations on the shape and size of both the magnetoresistive elements and the transistors that make up the magnetic array.

[0006] This invention has been made in view of the above problems, and aims to provide a magnetic domain wall moving element and a magnetic array that can be highly integrated. [Means for solving the problem]

[0007] (1) A magnetic domain wall moving element according to a first embodiment comprises a first magnetoresistive element and a first transistor. The first magnetoresistive element has a first magnetic domain wall moving layer, a first ferromagnetic layer, and a first non-magnetic layer sandwiched between the first magnetic domain wall moving layer and the first ferromagnetic layer. The first transistor comprises a first active region, a second active region, and a first gate that controls the current between the first active region and the second active region. The first magnetic domain wall moving layer is electrically connected to the first active region. The length of the first magnetoresistive element in a first direction is longer than the length of the first gate in a second direction perpendicular to the first direction. The length of the first gate in a first direction is longer than the length of the first gate in a first direction. The direction of the first gate length connecting the first active region and the second active region intersects the first direction.

[0008] (2) The domain wall moving element according to the above embodiment may further include a second magnetoresistive element. The second magnetoresistive element has a second domain wall moving layer, a second ferromagnetic layer, and a second non-magnetic layer sandwiched between the second domain wall moving layer and the second ferromagnetic layer. The first transistor further includes a third active region and a second gate that controls the current between the second active region and the third active region. The second domain wall moving layer is electrically connected to the third active region.

[0009] (3) The magnetic domain wall moving element according to the above embodiment may further include a second transistor. The second transistor includes a fourth active region, a fifth active region, a sixth active region, a third gate for controlling the current between the fourth active region and the fifth active region, and a fourth gate for controlling the current between the fifth active region and the sixth active region. The fourth active region is electrically connected to the first magnetic domain wall moving layer. The sixth active region is electrically connected to the second magnetic domain wall moving layer.

[0010] (4) The domain wall moving element according to the above embodiment may further include a second transistor and a third magnetoresistive element. The second transistor includes a fourth active region, a fifth active region, a sixth active region, a third gate for controlling the current between the fourth active region and the fifth active region, and a fourth gate for controlling the current between the fifth active region and the sixth active region. The third magnetoresistive element has a third domain wall moving layer, a third ferromagnetic layer, and a third non-magnetic layer sandwiched between the third domain wall moving layer and the third ferromagnetic layer. The fourth active region is electrically connected to the second domain wall moving layer. The sixth active region is electrically connected to the third domain wall moving layer.

[0011] (5) The magnetic domain wall moving element according to the above embodiment may further include a substrate. The first ferromagnetic layer may be closer to the substrate than the first magnetic domain wall moving layer. The first conductive layer electrically connected to the first active region may be connected to the upper surface of the first magnetic domain wall moving layer.

[0012] (6) In the magnetic wall movement element according to the above aspect, at least a part of the first active region may not overlap with the first magnetic wall movement layer when viewed from the stacking direction.

[0013] (7) The magnetic wall movement element according to the above aspect may further include a second transistor. The second transistor includes a fourth active region, a fifth active region, and a third gate that controls the current between the fourth active region and the fifth active region. The length of the third gate in the first direction is longer than the length in the second direction. The length of the first magnetic resistance effect element in the first direction is shorter than the sum of the lengths of the first gate and the third gate in the first direction.

[0014] (8) In the magnetic wall movement element according to the above aspect, the first channel between the first active region and the second active region may include an oxide containing any one or more elements selected from the group consisting of In, Ga, Zn, and Al.

[0015] (9) The magnetic wall movement element according to the above aspect may further include a second magnetic resistance effect element. The second magnetic resistance effect element has a second magnetic wall movement layer, a second ferromagnetic layer, and a second non-magnetic layer sandwiched between the second magnetic wall movement layer and the second ferromagnetic layer. The first magnetic resistance effect element and the second magnetic resistance effect element may be at different positions in the stacking direction.

[0016] (10) The magnetic wall movement element according to the above aspect may further include a second magnetic resistance effect element. The second magnetic resistance effect element has a second magnetic wall movement layer, a second ferromagnetic layer, and a second non-magnetic layer sandwiched between the second magnetic wall movement layer and the second ferromagnetic layer. At least one of the transistors connected to the first magnetic resistance effect element or the second magnetic resistance effect element may have a channel connecting two active regions formed in the stacking direction.

[0017] (11) The magnetic array according to the second aspect includes the magnetic wall movement element according to the above aspect.

Advantages of the Invention

[0018] The magnetic domain wall moving element and magnetic array according to the above embodiment offer excellent integration. [Brief explanation of the drawing]

[0019] [Figure 1] This is a block diagram of a magnetic array according to the first embodiment. [Figure 2] This is a circuit diagram of the integrated region of the magnetic array according to the first embodiment. [Figure 3] This is a plan view of the magnetic domain wall moving element according to the first embodiment. [Figure 4] This is a cross-sectional view of the magnetic domain wall moving element according to the first embodiment. [Figure 5] This is a cross-sectional view of a magnetoresistive element according to the first embodiment. [Figure 6] This is a cross-sectional view of the magnetic domain wall moving element according to the first embodiment. [Figure 7] This is a cross-sectional view of the magnetic domain wall moving element according to the first embodiment. [Figure 8] This is a plan view of the magnetic domain wall moving element according to the second embodiment. [Figure 9] This is a plan view of the magnetic domain wall moving element according to the third embodiment. [Figure 10] This is a cross-sectional view of the magnetic domain wall moving element according to the third embodiment. [Figure 11] This is a cross-sectional view of the magnetic domain wall moving element according to the third embodiment. [Figure 12] This is a plan view of the magnetic domain wall moving element according to the fourth embodiment. [Figure 13] This is a plan view of the magnetic domain wall moving element according to the fifth embodiment. [Figure 14] This is a cross-sectional view of the magnetic domain wall moving element according to the fifth embodiment. [Figure 15] This is a cross-sectional view of the magnetic domain wall moving element according to the sixth embodiment. [Figure 16] This is a cross-sectional view of the magnetic domain wall moving element according to the seventh embodiment. [Modes for carrying out the invention]

[0020] The present embodiment will be described in detail below with reference to the drawings as appropriate. The drawings used in the following description may be enlarged for convenience to clearly illustrate the features of the present invention, and the dimensional ratios of each component may differ from those of the actual components. The materials, dimensions, etc., exemplified in the following description are examples only, and the present invention is not limited to them. It is possible to modify and implement the present invention as appropriate within the scope of achieving its effects.

[0021] First, let's define the directions. The x and y directions are approximately parallel to one surface of the substrate Sub (see Figure 4), which will be described later. The x direction is the longitudinal direction of the magnetic domain wall moving layer 10, which will be described later, and is sometimes referred to as the first direction. The y direction is perpendicular to the x direction. The y direction is sometimes referred to as the second direction. The z direction is the direction from the substrate Sub towards the magnetoresistive element 100, which will be described later. The z direction is sometimes referred to as the stacking direction. In this specification, the +z direction may be expressed as "up" and the -z direction as "down," but these expressions are for convenience only and do not define the direction of gravity. Also, in this specification, "connected" is not limited to direct connections, but also includes cases where connections are made via other objects in between.

[0022] [First Embodiment] Figure 1 is a block diagram of a magnetic array MA according to the first embodiment. The magnetic array MA has an integration region 1 and a peripheral region 2. The magnetic array MA can be used, for example, in magnetic memory, multiply-accumulate units, neuromorphic devices, spin memristors, and magneto-optical elements.

[0023] The integration region 1 is a region in which multiple magnetic domain wall moving elements are integrated. Each magnetic domain wall moving element comprises a magnetoresistive element and a transistor connected to the magnetoresistive element. When the magnetic array MA is used as a memory, data is stored in the integration region 1. When the magnetic array MA is used as a neuromorphic device, learning is performed in the integration region 1.

[0024] Peripheral region 2 is a region where control elements that control the operation of the magnetic domain wall moving elements within the integrated region 1 are mounted. Peripheral region 2 includes, for example, a pulse application device 3, a resistance detection device 4, and an output unit 5.

[0025] The pulse application device 3 is configured to apply a pulse to at least one of the multiple magnetic wall moving elements within the integrated region 1. The pulse application device 3 includes, for example, a control unit 6 and a power supply 7.

[0026] The control unit 6 includes, for example, a processor and memory. The processor is, for example, a CPU (Central Processing Unit). The processor operates based on an operation program stored in memory. The control unit 6 controls, for example, the address of the magnetic domain wall moving element to which pulses are applied, the magnitude of the pulses applied to a predetermined magnetic domain wall moving element (voltage, pulse length), etc. The control unit 6 may also include a clock, a counter, a random number generator, etc. The clock serves as an indicator of the timing for applying pulses, and the counter counts the number of times pulses have been applied, etc. The power supply 7 applies pulses to the magnetic domain wall moving element according to instructions from the control unit 6.

[0027] The resistance detection device 4 is configured to detect the resistance values ​​of magnetoresistive elements within the integrated region 1. The resistance detection device 4 may detect the resistance of each magnetoresistive element within the integrated region 1, or it may detect the sum of the resistances of magnetoresistive elements belonging to the same row, for example. The resistance detection device 4 may, for example, have a comparator that compares the magnitudes of the detected resistance values. The comparator may, for example, compare the detected resistance values ​​with each other, or it may compare the detected resistance values ​​with a pre-set reference resistance value.

[0028] The output unit 5 is connected to the resistance detection device 4. The output unit 5 includes, for example, a processor, output capacitor, amplifier, converter, etc. When the magnetic array MA is used as a neuromorphic device, the output unit 5 may perform a calculation to substitute the detection result of the resistance detection device 4 into the activation function. This calculation is performed, for example, by a processor. The output unit 5 outputs the calculation result to the outside. When the magnetic array MA is used as a neuromorphic device, the output unit 5 may perform operations such as outputting the calculation result as an input signal to another magnetic array, or outputting it to the outside as an identification rate. The output unit 5 may also feed the calculation result back to the pulse application device 3.

[0029] Figure 2 is a circuit diagram of the integrated region 1 according to the first embodiment. The integrated region 1 comprises a plurality of magnetic domain wall moving elements 200, a plurality of first wirings WL, a plurality of second wirings CL, and a plurality of third wirings RL. Each magnetic domain wall moving element 200 comprises a magnetoresistive element 100, a first transistor Tr1, and a second transistor Tr2. The third transistor Tr3 belongs, for example, to the pulse application device 3 of the peripheral region 2.

[0030] The multiple magnetic domain wall moving elements 200 are arranged, for example, in a matrix. The multiple magnetic domain wall moving elements 200 are not limited to actual elements arranged in a matrix, but may also be arranged in a matrix in the circuit diagram.

[0031] Each of the first wirings WL is, for example, a write wiring. Each of the first wirings WL electrically connects the pulse application device 3 to one or more magnetoresistive elements 100. Each of the second wirings CL is, for example, a common wiring that can be used both when writing and reading data. Each of the second wirings CL is connected to, for example, a resistance detection device 4. The second wirings CL may be provided on each of the multiple magnetoresistive elements 100, or they may be provided across the multiple magnetoresistive elements 100. Each of the third wirings RL is, for example, a read wiring. Each of the third wirings RL electrically connects the pulse application device 3 to one or more magnetoresistive elements 100.

[0032] The first transistor Tr1, the second transistor Tr2, and the third transistor Tr3 are elements that control the flow of current. The first transistor Tr1 is a field-effect transistor. The second transistor Tr2 and the third transistor Tr3 may be field-effect transistors or other elements that control the flow of current. Other elements that control the flow of current include, for example, elements that utilize phase changes in the crystal layer, such as ovonic threshold switches (OTS), elements that utilize changes in band structure, such as metal-insulator transition (MIT) switches, elements that utilize breakdown voltage, such as Zener diodes and avalanche diodes, and elements whose conductivity changes with changes in atomic position.

[0033] The first transistor Tr1 and the second transistor Tr2 are connected, for example, to each magnetoresistive element 100. The first transistor Tr1 is connected, for example, between the magnetoresistive element 100 and the first wiring WL. The second transistor Tr2 is connected, for example, between the magnetoresistive element 100 and the second wiring CL. The third transistor Tr3 is connected, for example, across multiple magnetoresistive elements 100. The third transistor Tr3 is connected, for example, to the third wiring RL.

[0034] The relative positions of the second transistor Tr2 and the third transistor Tr3 are not limited to those shown in Figure 2. For example, the second transistor Tr2 may be connected across multiple magnetoresistive elements 100 and connected to one end of the second wiring CL. Alternatively, for example, the third transistor Tr3 may be connected to each of the magnetoresistive elements 100 individually.

[0035] Figure 3 is a plan view of the magnetic domain wall moving element 200 according to the first embodiment. Figure 4 is a cross-sectional view of the magnetic domain wall moving element 200 according to the first embodiment. Figure 4 is a cross-sectional view taken along line AA in Figure 3.

[0036] The magnetic domain wall moving element 200 comprises a magnetoresistive element 100, a first transistor Tr1, and a second transistor Tr2.

[0037] The magnetoresistive element 100 and the first transistor Tr1 are electrically connected via vertical wiring Vw1 and in-plane wiring IPw1. The magnetoresistive element 100 and the second transistor Tr2 are electrically connected via vertical wiring Vw2 and in-plane wiring IPw2. Vertical wiring Vw1 and vertical wiring Vw2 are wirings that extend in the z direction. In-plane wiring IPw1 and in-plane wiring IPw2 are wirings that extend in either direction within the xy plane. Vertical wiring Vw1, vertical wiring Vw2, in-plane wiring IPw1 and in-plane wiring IPw2 are conductors.

[0038] The magnetoresistive element 100 is surrounded by an insulating layer 90. The insulating layer 90 is an insulating layer that insulates between wirings in multilayer wiring and between elements. The insulating layer 90 is made of, for example, silicon oxide (SiO x ), silicon nitride (SiN x ), silicon carbide (SiC), chromium nitride, silicon carbonitride (SiCN), silicon oxynitride (SiON), aluminum oxide (Al2O3), zirconium oxide (ZrO3) x ) etc.

[0039] Figure 5 is a cross-sectional view of the magnetoresistive element 100 according to the first embodiment. Figure 5 is a cross-sectional view taken along line AA in Figure 3. The arrows shown in the figure are examples of the orientation direction of the magnetization of the ferromagnetic material.

[0040] The magnetoresistive element 100 includes, for example, a magnetic domain wall movement layer 10, a non-magnetic layer 20, a ferromagnetic layer 30, a first conductive layer 40, a second conductive layer 50, and a third conductive layer 60.

[0041] Viewed from the z-direction, the length L1 in the x-direction of the magnetoresistive element 100 is longer than the length L2 in the y-direction (see Figure 3). Hereafter, the length of the magnetoresistive element is defined as the length of the portion where the first ferromagnetic layer, the non-magnetic layer, and the ferromagnetic layer overlap when viewed from the z-direction.

[0042] The magnetic wall movement layer 10 has a length in the x direction longer than that in the y direction. The magnetic wall movement layer 10 has a plurality of magnetic domains inside and has a magnetic wall DW at the boundary of the plurality of magnetic domains. The magnetic wall movement layer 10 is, for example, a layer capable of magnetically recording information by a change in magnetic state. The magnetic wall movement layer 10 is also called an analog layer or a magnetic recording layer.

[0043] The magnetic wall movement layer 10 has a first region A1, a second region A2, and a third region A3. The first region A1 is a region overlapping with the first conductive layer 40 when viewed from the z direction. The second region A2 is a region overlapping with the second conductive layer 50 when viewed from the z direction. The third region A3 is a region other than the first region A1 and the second region A2 of the magnetic wall movement layer 10. The third region A3 is, for example, sandwiched between the first region A1 and the second region A2 in the x direction.

[0044] The magnetization M of the first region A1 A1 is fixed by the first conductive layer 40. The magnetization M of the second region A2 A2 is fixed by the second conductive layer 50. That the magnetization is fixed means that the magnetization does not reverse in the normal operation of the magnetoresistive element 100 (when no external force exceeding the assumption is applied). The magnetization M of the first region A1 A1 and the magnetization M of the second region A2 A2 are, for example, oriented in opposite directions.

[0045] The third region A3 is a region where the direction of magnetization changes and the magnetic wall DW can move. The third region A3 is referred to as a magnetic wall movable region. The third region A3 has a first magnetic domain A3 and a second magnetic domain A32. The first magnetic domain A31 and the second magnetic domain A32 have opposite magnetization orientation directions. The boundary between the first magnetic domain A31 and the second magnetic domain A32 is the magnetic wall DW. The magnetization M of the first magnetic domain A31 A31 is, for example, oriented in the same direction as the magnetization M of the first region A1 A1 The magnetization M of the second magnetic domain A32 A32 is, for example, oriented in the same direction as the magnetization M of the adjacent second region A2 A2 The magnetic wall DW generally moves within the third region A3 and does not penetrate into the first region A1 and the second region A2.

[0046] When the ratio of the volumes of the first magnetic domain A31 and the second magnetic domain A32 within the third region A3 changes, the magnetic domain wall DW moves. The magnetic domain wall DW moves when a writing current is passed in the x direction of the third region A3, or when an external magnetic field is applied to the third region A3. For example, when a writing current (e.g., a current pulse) is applied to the third region A3 in the +x direction, electrons flow in the opposite direction to the current, -x, so the magnetic domain wall DW moves in the -x direction. When a current flows from the first magnetic domain A31 to the second magnetic domain A32, the spin-polarized electrons in the second magnetic domain A32 move towards the magnetization M of the first magnetic domain A31. A31 The magnetization is reversed. Magnetization M of the first magnetic domain A31 A31 As the vector reverses, the magnetic domain wall DW moves in the -x direction.

[0047] The magnetic domain wall movement layer 10 is composed of a magnetic material. The magnetic domain wall movement layer 10 may be a ferromagnetic material, a ferrimagnetic material, or a combination of these with an antiferromagnetic material whose magnetic state can be changed by electric current. Preferably, the magnetic domain wall movement layer 10 has at least one element selected from the group consisting of Co, Ni, Fe, Pt, Pd, Gd, Tb, Mn, Ge, and Ga. Examples of materials used for the magnetic domain wall movement layer 10 include a Co and Ni laminated film, a Co and Pt laminated film, a Co and Pd laminated film, a MnGa-based material, a GdCo-based material, and a TbCo-based material. Ferrimagnetic materials such as MnGa-based materials, GdCo-based materials, and TbCo-based materials have low saturation magnetization, resulting in a low threshold current required to move the magnetic domain wall DW. Also, Co and Ni laminated films, Co and Pt laminated films, and Co and Pd laminated films have high coercivity, resulting in a slower movement speed of the magnetic domain wall DW. Examples of antiferromagnetic materials include Mn3X (where X is Sn, Ge, Ga, Pt, Ir, etc.), CuMnAs, and Mn2Au. The same material as the ferromagnetic layer 30 described later can also be applied to the magnetic domain wall migration layer 10.

[0048] The non-magnetic layer 20 is located between the magnetic domain wall movement layer 10 and the ferromagnetic layer 30. The non-magnetic layer 20 is laminated on one surface of the ferromagnetic layer 30.

[0049] The non-magnetic layer 20 is made of, for example, a non-magnetic insulator, semiconductor, or metal. Non-magnetic insulators include, for example, Al2O3, SiO2, MgO, MgAl2O4, and materials in which some of the Al, Si, and Mg are replaced with Zn, Be, etc. These materials have a large band gap and excellent insulating properties. When the non-magnetic layer 20 is made of a non-magnetic insulator, the non-magnetic layer 20 is a tunnel barrier layer. Non-magnetic metals include, for example, Cu, Au, Ag, etc. Non-magnetic semiconductors include, for example, Si, Ge, CuInSe2, CuGaSe2, Cu(In,Ga)Se2, etc.

[0050] The thickness of the non-magnetic layer 20 is, for example, 20 Å or more, and may also be 25 Å or more. A thicker non-magnetic layer 20 increases the resistive area area (RA) of the magnetoresistive element 100. The resistive area area area (RA) of the magnetoresistive element 100 is 1 × 10⁻¹⁰. 4 Ωμm 2 It is preferable that the above is true, 5 × 10 4 Ωμm 2 The above is more preferable. The resistive area product (RA) of the magnetoresistive element 100 is expressed as the product of the element resistance of one magnetoresistive element 100 and the element cross-sectional area of ​​the magnetoresistive element (the area of ​​the cross-section obtained by cutting the non-magnetic layer 20 in the xy plane).

[0051] The ferromagnetic layer 30, together with the magnetic domain wall movement layer 10, sandwiches the non-magnetic layer 20. At least a portion of the ferromagnetic layer 30 is positioned to overlap with the magnetic domain wall movement layer 10 in the z direction. The magnetization M of the ferromagnetic layer 30 30 This is the magnetization M of the third region A3 of the magnetic domain wall migration layer 10. A31 M A32 It is less prone to reversal. Magnetization M of the ferromagnetic layer 30 30 The ferromagnetic layer 30 remains fixed and does not change direction when an external force is applied that is sufficient to reverse the magnetization of the third region A3. The ferromagnetic layer 30 is sometimes referred to as a fixed layer or reference layer.

[0052] The ferromagnetic layer 30 shown in Figure 5 is located closer to the substrate Sub than the magnetic domain wall moving layer 10. A structure in which the fixed layer, the ferromagnetic layer 30, is located closer to the substrate Sub than the magnetic domain wall moving layer 10 is called a bottom pin structure. In a bottom pin structure, the magnetization M of the ferromagnetic layer 30 30It has high stability.

[0053] The ferromagnetic layer 30 contains a ferromagnetic material. The ferromagnetic layer 30 contains, for example, a material that readily exhibits a coherent tunneling effect with respect to the magnetic domain wall migration layer 10. The ferromagnetic layer 30 includes, for example, a metal selected from the group consisting of Cr, Mn, Co, Fe, and Ni, an alloy containing one or more of these metals, an alloy containing these metals and at least one of the elements B, C, and N, etc. Examples of the ferromagnetic layer 30 include Co-Fe, Co-Fe-B, and Ni-Fe.

[0054] The ferromagnetic layer 30 may be, for example, a Heusler alloy. Heusler alloys are half-metals and have high spin polarizability. A Heusler alloy is an intermetallic compound with a chemical composition of XYZ or X2YZ, where X is a transition metal element or noble metal element of group Co, Fe, Ni, or Cu on the periodic table, Y is a transition metal or element species of X of group Mn, V, Cr, or Ti, and Z is a typical element of group III to V. Examples of Heusler alloys include Co2FeSi, Co2FeGe, Co2FeGa, Co2MnSi, and Co2Mn 1-a Fe a Al b Si 1-b Co2FeGe 1-c Ga c These are some examples.

[0055] The first conductive layer 40 is connected to the upper surface 10A of the magnetic domain wall moving layer 10. The first conductive layer 40 is electrically connected to the first active region AA1 of the first transistor Tr1.

[0056] The first conductive layer 40 is, for example, a ferromagnetic material. The first conductive layer 40 can be made of the same material as the magnetic domain wall migration layer 10 and the ferromagnetic layer 30. The magnetization M of the first conductive layer 40... 40 The magnetization M of the first region A1 A1 Secure it.

[0057] Furthermore, the first conductive layer 40 is not limited to a ferromagnetic material. The current density of the current flowing through the magnetic domain wall movement layer 10 changes abruptly at the position from the third region A3 to the first region A1. Because the abrupt change in the current density of the current flowing through the magnetic domain wall movement layer 10 can limit the movement range of the magnetic domain wall DW, the first conductive layer 40 does not have to be a ferromagnetic material.

[0058] The second conductive layer 50 is connected to the upper surface 10A of the magnetic domain wall movement layer 10. The first conductive layer 40 and the second conductive layer 50 are spaced apart in the x-direction. The second conductive layer 50 is electrically connected to the fourth active region AA4 of the second transistor Tr2.

[0059] The second conductive layer 50 is, for example, a ferromagnetic material. The second conductive layer 50 can be made of, for example, the same material as the first conductive layer 40. The magnetization M of the second conductive layer 50... 50 The magnetization M of the second region A2 A2 The second conductive layer 50 may have a different thickness than the first conductive layer 40. If the thickness of the second conductive layer 50 and the thickness of the first conductive layer 40 are different, a difference will be created between the coercivity of the second conductive layer 50 and the coercivity of the first conductive layer 40, making it easier to fix the magnetization orientation direction in opposite directions. The second conductive layer 50 is not limited to a ferromagnetic material.

[0060] The third conductive layer 60 is in contact with the ferromagnetic layer 30. The third conductive layer 60 electrically connects the ferromagnetic layer 30 and the third wiring RL. The third conductive layer 60 is a conductor.

[0061] The magnetoresistive element 100 may have layers other than the domain wall movement layer 10, the non-magnetic layer 20, and the ferromagnetic layer 30. For example, a magnetic layer may be provided on the side of the ferromagnetic layer 30 opposite to the non-magnetic layer 20, via a spacer layer. The ferromagnetic layer 30, the spacer layer, and the magnetic layer form a synthetic antiferromagnetic structure (SAF structure). The synthetic antiferromagnetic structure consists of two magnetic layers flanking a non-magnetic layer. The antiferromagnetic coupling between the ferromagnetic layer 30 and the magnetic layer increases the coercivity of the ferromagnetic layer 30 compared to the case without a magnetic layer. The magnetic layer may include, for example, a ferromagnetic material and an antiferromagnetic material such as IrMn or PtMn. The spacer layer may include, for example, at least one selected from the group consisting of Ru, Ir, and Rh.

[0062] For example, the magnetoresistive element 100 may also have a base layer and a cap layer. The base layer is the lower layer in the stacking direction and enhances the crystallinity of the ferromagnetic layer 30 and the magnetic domain wall movement layer 10. The cap layer is the upper layer in the stacking direction and enhances the crystallinity and magnetic anisotropy of the ferromagnetic layer 30 and the magnetic domain wall movement layer 10.

[0063] The direction of magnetization in each layer of the magnetoresistive element 100 can be confirmed, for example, by measuring the magnetization curve. The magnetization curve can be measured, for example, using MOKE (Magneto-Optical Kerr Effect). MOKE measurement is a measurement method that uses the magneto-optical effect (magnetic Kerr effect), which occurs when linearly polarized light is incident on the object to be measured and the direction of polarization is rotated.

[0064] Figures 6 and 7 are cross-sectional views of the magnetic wall moving element 200 according to the first embodiment. Figure 6 is a cross-sectional view taken along line BB in Figure 3. Figure 7 is a cross-sectional view taken along line CC in Figure 3. Vertical wiring Vw1 on the near side of the page is also shown as a dotted line in Figure 6. Vertical wiring Vw2 on the far side of the page is also shown as a dotted line in Figure 7.

[0065] The first transistor Tr1 and the second transistor Tr2 are formed on a substrate Sub. The substrate Sub is a semiconductor. Semiconductors are, for example, silicon, silicon carbide, gallium nitride, and oxides (IGO, IZO, IGZO, IAZO, etc.) containing one or more elements selected from the group consisting of In, Ga, Zn, and Al. When an oxide containing one or more elements selected from the group consisting of In, Ga, Zn, and Al is applied to a transistor, the transistor can operate with low power consumption even when the gate width of the transistor is wide (when the rated current is high). This is because oxides containing one or more elements selected from the group consisting of In, Ga, Zn, and Al have a low off-current.

[0066] The first transistor Tr1 comprises a first active region AA1, a second active region AA2, a first gate G1, and a gate insulating film 91. The second transistor Tr2 comprises a fourth active region AA4, a fifth active region AA5, a third gate G3, and a gate insulating film 92.

[0067] The first active region AA1, the second active region AA2, the fourth active region AA4, and the fifth active region AA5 are sometimes referred to as the source and drain, respectively, depending on the direction of current flow. The first active region AA1, the second active region AA2, the fourth active region AA4, and the fifth active region AA5 are, for example, carrier-doped semiconductors.

[0068] The first active region AA1 is electrically connected to the magnetic domain wall migration layer 10. The second active region AA2 is electrically connected to, for example, the first wiring WL. The fourth active region AA4 is electrically connected to the magnetic domain wall migration layer 10. The fifth active region AA5 is electrically connected to, for example, the second wiring CL.

[0069] At least a portion of the first active region AA1 is located in a position that does not overlap with the magnetic domain wall movement layer 10 when viewed from the z direction. This region is called the non-overlapping region. The first active region AA1 is connected to the vertical wiring Vw1 in the non-overlapping region. The vertical wiring Vw1 and the first conductive layer 40 are electrically connected by the in-plane wiring IPw1. By providing the vertical wiring Vw1 in the non-overlapping region, the electrical connection between the upper surface 10A of the magnetic domain wall movement layer 10 and the first active region AA1 is facilitated.

[0070] Similarly, at least a portion of the fourth active region AA4 is located in a position that does not overlap with the magnetic domain wall moving layer 10 when viewed from the z direction. The fourth active region AA4 is connected to the vertical wiring Vw2 in the non-overlapping region. The vertical wiring Vw2 and the second conductive layer 50 are electrically connected by the in-plane wiring IPw2.

[0071] The first gate G1 controls the current between the first active region AA1 and the second active region AA2. The first gate G1 controls the current flowing through the first channel C1 by applying a voltage to the first channel C1 via the gate insulating film 91. The first channel C1 includes, for example, a semiconductor used in the substrate Sub. The gate insulating film 91 includes a material similar to that of the insulating layer 90. The first gate G1 is a conductor.

[0072] The first gate G1 is located between the first active region AA1 and the second active region AA2 in the y-direction when viewed from the z-direction (see Figure 3). The shortest distance between the first active region AA1 and the second active region AA2 is called the first gate length L4, and the width of the first gate G1 in the direction perpendicular to the first gate length direction and the z-direction is called the first gate width L3. The direction connecting the shortest distance between the first active region AA1 and the second active region AA2 is called the first gate length direction, and the direction perpendicular to the first gate length direction and the z-direction is called the first gate width direction.

[0073] The third gate G3 controls the current between the fourth active region AA4 and the fifth active region AA5. The third gate G3 controls the current flowing through the third channel C3 by applying a voltage to the third channel C3 via the gate insulating film 92. The third channel C3 includes, for example, a semiconductor used in the substrate Sub. The gate insulating film 92 includes a material similar to that of the insulating layer 90. The third gate G3 is a conductor.

[0074] The third gate G3 is located between the fourth active region AA4 and the fifth active region AA5 in the y-direction when viewed from the z-direction. The shortest distance between the fourth active region AA4 and the fifth active region AA5 is called the third gate length L6, and the width of the third gate G3 in the direction perpendicular to the third gate length direction and the z-direction is called the third gate width L5. The direction connecting the shortest distance between the fourth active region AA4 and the fifth active region AA5 is called the third gate length direction, and the direction perpendicular to the third gate length direction and the z-direction is called the third gate width direction.

[0075] The length of the third gate G3 in the x-direction is longer than its length in the y-direction. The x-direction approximately coincides with the width direction of the third gate and intersects (approximately orthogonal to) the length direction of the third gate. The length of the magnetoresistive element 100 in the x-direction is longer than the length of the third gate G3 in the x-direction. Also, the length L1 of the magnetoresistive element 100 in the x-direction is shorter than the sum of the width of the first gate L3 and the width of the third gate L5.

[0076] If the sum of the first gate width L3 and the third gate width L5 is longer than the x-direction length L1 of the magnetoresistive element 100, then a portion of the first active region AA1 of the first transistor Tr1 and a portion of the fourth active region AA4 of the second transistor Tr2 will protrude from the magnetoresistive element 100 in the x-direction when viewed from the z-direction. That is, non-overlapping regions are formed in the first active region AA1 and the fourth active region AA4 that do not overlap with the magnetoresistive element 100 when viewed from the z-direction. Using non-overlapping regions facilitates electrical connection between the upper surface 10A of the magnetic domain wall movement layer 10 and the first active region AA1 or the fourth active region AA4. Furthermore, by placing the transistors in the portion of the substrate Sub that overlaps with the magnetoresistive element 100 when viewed from the z-direction, the effective area can be efficiently utilized while increasing the rated current of the transistors.

[0077] The magnetic domain wall moving element 200 according to this embodiment can be fabricated by known methods. The first transistor Tr1 and the second transistor Tr2 can be fabricated, for example, using photolithography. The first transistor Tr1 and the second transistor Tr2 may be fabricated on commercially available semiconductor substrates on which transistors are formed.

[0078] The magnetoresistive element 100 is formed by a layer stacking process and a processing process in which a portion of each layer is shaped into a predetermined form. Layer stacking can be performed using sputtering, chemical vapor deposition (CVD), electron beam deposition (EB deposition), atomic laser deposition, etc. Processing of each layer can be performed using photolithography and etching (e.g., Ar etching), etc.

[0079] In this embodiment, the magnetic domain wall moving element 200 has a longitudinal direction that substantially coincides with the longitudinal direction of the magnetoresistive element 100 and the longitudinal direction of the first transistor Tr1. Therefore, the magnetic domain wall moving element 200 can be compactly housed within a limited area. Furthermore, because the longitudinal direction of the magnetoresistive element 100 and the longitudinal direction of the first transistor Tr1 substantially coincide, the first gate width L3 of the first transistor Tr1 can be widened. A first transistor Tr1 with a wide first gate width L3 has a high rated current. A transistor with a high rated current can supply a sufficient amount of writing current to the magnetic domain wall moving layer 10. In other words, the magnetic domain wall moving element 200 in this embodiment can be highly integrated and can obtain the functions required of a magnetic domain wall moving element 200.

[0080] "Second Embodiment" Figure 8 is a plan view of the magnetic domain wall moving element 201 according to the second embodiment. The positional relationship of the first transistor Tr1 and the second transistor Tr2 with respect to the magnetoresistive element 100 differs between the magnetic domain wall moving element 201 and the magnetic domain wall moving element 200. Components similar to those in the first embodiment are denoted by the same reference numerals and their descriptions are omitted.

[0081] The first transistor Tr1 and the second transistor Tr2 are positioned so as not to overlap with the magnetoresistive element 100 when viewed from the z direction. Figure 8 shows an example where the first transistor Tr1 and the second transistor Tr2 are positioned in opposite directions with respect to the magnetoresistive element 100, but the first transistor Tr1 and the second transistor Tr2 may also be positioned in the same direction with respect to the magnetoresistive element 100.

[0082] If the first transistor Tr1 and the magnetoresistive element 100 are positioned so as not to overlap when viewed from the z direction, electrical connection between the first conductive layer 40 connected to the upper surface 10A of the magnetic domain wall movement layer 10 and the first active region AA1 becomes easier. Similarly, if the second transistor Tr2 and the magnetoresistive element 100 are positioned so as not to overlap when viewed from the z direction, electrical connection between the second conductive layer 50 connected to the upper surface 10A of the magnetic domain wall movement layer 10 and the fourth active region AA4 becomes easier.

[0083] The magnetic domain wall moving element 201 according to the second embodiment provides the same effects as the magnetic domain wall moving element 200 according to the first embodiment. Furthermore, the magnetic domain wall moving element 201 according to the second embodiment can replace the magnetic domain wall moving element 200 in the integrated region 1 shown in Figure 2.

[0084] "Third Embodiment" Figure 9 is a plan view of the magnetic domain wall moving element 202 according to the third embodiment. Figures 10 and 11 are cross-sectional views of the magnetic domain wall moving element 202 according to the third embodiment. Figure 10 is a cross-sectional view taken along line BB in Figure 9. Figure 11 is a cross-sectional view taken along line CC in Figure 9.

[0085] The magnetic domain wall moving element 202 comprises a first magnetoresistive effect element 101, a second magnetoresistive effect element 102, a first transistor Tr1', and a second transistor Tr2'.

[0086] The first magnetoresistive element 101 includes, for example, a domain wall movement layer 11, a non-magnetic layer 21, a ferromagnetic layer 31, a first conductive layer 41, a second conductive layer 51, and a third conductive layer 61. The second magnetoresistive element 102 includes, for example, a domain wall movement layer 12, a non-magnetic layer 22, a ferromagnetic layer 32, a first conductive layer 42, a second conductive layer 52, and a third conductive layer 62.

[0087] The magnetic domain wall movement layers 11 and 12 correspond to the magnetic domain wall movement layer 10. The non-magnetic layers 21 and 22 correspond to the non-magnetic layer 20. The ferromagnetic layers 31 and 32 correspond to the ferromagnetic layer 30. The first conductive layers 41 and 42 correspond to the first conductive layer 40. The second conductive layers 51 and 52 correspond to the second conductive layer 50. The third conductive layers 61 and 62 correspond to the third conductive layer 60. The detailed configuration of each layer is the same as that of each layer in the first embodiment.

[0088] Viewed from the z direction, the x-direction length L7 of the first magnetoresistance element 101 is longer than the y-direction length L8. Viewed from the z direction, the x-direction length L9 of the second magnetoresistance element 102 is longer than the y-direction length L10.

[0089] The first transistor Tr1' comprises a first active region AA1, a second active region AA2, a third active region AA3, a first gate G1, a second gate G2, a gate insulating film 91, and a gate insulating film 93. The first active region AA1, the second active region AA2, the first gate G1, and the gate insulating film 91 are the same as in the first embodiment.

[0090] The third active region AA3 is located opposite the first active region AA1 when viewed from the z direction, with reference to the second active region AA2. The first active region AA1 and the third active region AA3 sandwich the second active region AA2 in the y direction when viewed from the z direction. The third active region AA3 contains the same material as the first active region AA1. The third active region AA3 is electrically connected to the magnetic domain wall moving layer 12 via vertical wiring Vw3, in-plane wiring IPw3, and the first conductive layer 42. At least a portion of the third active region AA3 is located in a position that does not overlap with the magnetic domain wall moving layer 12 when viewed from the z direction.

[0091] The second gate G2 controls the current between the second active region AA2 and the third active region AA3. The second gate G2 controls the current flowing through the second channel C2 by applying a voltage to the second channel C2 via the gate insulating film 93. The second channel C2 includes, for example, a semiconductor used in the substrate Sub. The gate insulating film 93 includes a material similar to that of the gate insulating film 91. The second gate G2 is a conductor.

[0092] The second gate G2 is located between the second active region AA2 and the third active region AA3 in the y-direction when viewed from the z-direction. The shortest distance between the second active region AA2 and the third active region AA3 is called the second gate length L12, and the width of the second gate G2 in the direction perpendicular to the second gate length and the z-direction is called the second gate width L11. The second gate width L11 is longer than the second gate length L12.

[0093] The second transistor Tr2' comprises a fourth active region AA4, a fifth active region AA5, a sixth active region AA6, a third gate G3, a fourth gate G4, a gate insulating film 92, and a gate insulating film 94. The fourth active region AA4, the fifth active region AA5, the third gate G3, and the gate insulating film 92 are the same as in the first embodiment.

[0094] The sixth active region AA6 is located opposite the fourth active region AA4 when viewed from the z direction, with reference to the fifth active region AA5. The fourth active region AA4 and the sixth active region AA6 sandwich the fifth active region AA5 in the y direction when viewed from the z direction. The sixth active region AA6 contains the same material as the first active region AA1. The sixth active region AA6 is electrically connected to the magnetic domain wall moving layer 12 via vertical wiring Vw4, in-plane wiring IPw4, and the second conductive layer 52. At least a portion of the sixth active region AA6 is located in a position that does not overlap with the magnetic domain wall moving layer 12 when viewed from the z direction.

[0095] The fourth gate G4 controls the current between the fifth active region AA5 and the sixth active region AA6. The fourth gate G4 controls the current flowing through the fourth channel C4 by applying a voltage to the fourth channel C4 via the gate insulating film 94. The fourth channel C4 includes, for example, a semiconductor used in the substrate Sub. The gate insulating film 94 includes a material similar to that of the gate insulating film 91. The fourth gate G4 is a conductor.

[0096] The fourth gate G4 is located between the fifth active region AA5 and the sixth active region AA6 in the y-direction when viewed from the z-direction. The shortest distance between the fifth active region AA5 and the sixth active region AA6 is called the fourth gate length L14, and the width of the fourth gate G4 in the direction perpendicular to the fourth gate length direction and the z-direction is called the fourth gate width L13. The fourth gate width L13 is longer than the fourth gate length L14. Also, the x-direction lengths L7 and L9 of the first magnetoresistive element 101 and the second magnetoresistive element 102 are shorter than the sum of the second gate width L11 and the fourth gate width L13, respectively.

[0097] The domain wall moving element 202 according to the third embodiment provides the same effects as the domain wall moving element 200 according to the first embodiment. The first magnetoresistive element 101 and the second magnetoresistive element 102 share the first wiring WL and the second wiring CL. The first magnetoresistive element 101 and the second magnetoresistive element 102 also share the second active region AA2 and the fifth active region AA5. In other words, the domain wall moving element 202 according to the third embodiment can reduce the number of transistors required to operate the two magnetoresistive elements, enabling higher integration.

[0098] "Fourth Embodiment" Figure 12 is a plan view of the magnetic domain wall moving element 203 according to the fourth embodiment. The magnetic domain wall moving element 203 comprises a first magnetoresistive element 101, a second magnetoresistive element 102, a third magnetoresistive element 103, a first transistor Tr1', and a second transistor Tr2'.

[0099] The configurations of the first magnetoresistive element 101, the second magnetoresistive element 102, the first transistor Tr1', and the second transistor Tr2' are the same as in the third embodiment. However, the fourth active region AA4 of the second transistor Tr2' is connected to the domain wall movement layer 12 of the second magnetoresistive element 102, and the sixth active region AA6 of the second transistor Tr2' is connected to the domain wall movement layer 13 of the third magnetoresistive element 103.

[0100] The third magnetoresistive element 103 includes, for example, a domain wall movement layer 13, a non-magnetic layer 23, a ferromagnetic layer 33, a first conductive layer 43, a second conductive layer 53, and a third conductive layer 63. The domain wall movement layer 13 corresponds to the domain wall movement layer 10. The non-magnetic layer 23 corresponds to the non-magnetic layer 20. The ferromagnetic layer 33 corresponds to the ferromagnetic layer 30. The first conductive layer 43 corresponds to the first conductive layer 40. The second conductive layer 53 corresponds to the second conductive layer 50. The third conductive layer 63 corresponds to the third conductive layer 60. The detailed configuration of each layer is the same as that of each layer in the first embodiment.

[0101] The first magnetoresistive element 101 and the second magnetoresistive element 102 share a second active region AA2 and a first wiring WL connected to the second active region AA2. The second magnetoresistive element 102 and the third magnetoresistive element 103 share a fifth active region AA5 and a second wiring CL connected to the fifth active region AA5.

[0102] The domain wall moving element 203 according to the fourth embodiment provides the same effects as the domain wall moving element 200 according to the first embodiment. Furthermore, the domain wall moving element 203 according to the fourth embodiment can reduce the number of transistors by sharing a portion of the transistor with two magnetoresistive effect elements, enabling higher integration. In addition, because the first transistor Tr1' and the second transistor Tr2' are positioned offset in the y direction, interference between the first wiring WL connected to the second active region AA2 and the second wiring CL connected to the fifth active region AA5 is less likely, making wiring easier.

[0103] "Fifth Embodiment" Figure 13 is a plan view of the magnetic domain wall moving element 204 according to the fifth embodiment. Figure 14 is a cross-sectional view of the magnetic domain wall moving element 204 according to the fifth embodiment. Figure 14 is a cross-sectional view taken along line AA in Figure 13.

[0104] The magnetic domain wall moving element 204 comprises a magnetoresistive element 105, a first transistor Tr1, and a second transistor Tr2. The specific configurations of the first transistor Tr1 and the second transistor Tr2 are the same as in the first embodiment.

[0105] The magnetoresistive element 105 includes a domain wall movement layer 15, a non-magnetic layer 25, a ferromagnetic layer 35, a first conductive layer 45, a second conductive layer 55, and a third conductive layer 65. The domain wall movement layer 15 corresponds to the domain wall movement layer 10. The non-magnetic layer 25 corresponds to the non-magnetic layer 20. The ferromagnetic layer 35 corresponds to the ferromagnetic layer 30. The first conductive layer 45 corresponds to the first conductive layer 40. The second conductive layer 55 corresponds to the second conductive layer 50. The third conductive layer 65 corresponds to the third conductive layer 60.

[0106] The magnetoresistive element 105 differs from the magnetoresistive element 100 according to the first embodiment in the stacking order of each layer. The magnetoresistive element 105 is stacked in the order of magnetic domain wall movement layer 15, non-magnetic layer 25, and ferromagnetic layer 35 from the substrate Sub side. The magnetoresistive element 105 is said to have a top-pin structure.

[0107] When viewed from the z-direction, the x-direction length L15 of the magnetoresistive element 105 is longer than the y-direction length L16. In the case of a top-pin structure, the x-direction length of the ferromagnetic layer 35 and the x-direction length of the domain wall movement layer 15 may differ. The x-direction length L15 of the magnetoresistive element 105 is, as defined above, the length of the overlapping portion of the domain wall movement layer 15, the non-magnetic layer 25, and the ferromagnetic layer 35 when viewed from the z-direction.

[0108] The first conductive layer 45, which is electrically connected to the first active region AA1, is connected to the lower surface of the magnetic domain wall movement layer 15. In the case of a top-pin structure, since the magnetic domain wall movement layer 15 is closer to the substrate Sub than the ferromagnetic layer 35, the magnetoresistive element 105 and the first transistor Tr1 may be connected only by vertical wiring Vw1. Also, since the magnetoresistive element 105 can ensure an electrical connection with the first transistor Tr1 on the lower surface of the magnetic domain wall movement layer 15, the first active region AA1 may be covered by the magnetic domain wall movement layer 15 when viewed from the z direction.

[0109] Similarly, the second conductive layer 55, which is electrically connected to the fourth active region AA4, is connected to the lower surface of the magnetic domain wall movement layer 15. The magnetoresistive element 105 and the second transistor Tr2 may be connected only by vertical wiring Vw2. Also, when viewed from the z direction, the fourth active region AA4 may be covered by the magnetic domain wall movement layer 15.

[0110] The x-direction length L15 of the magnetoresistive element 105 may be longer than the sum of the first gate width L3 of the first transistor Tr1 and the third gate width L5 of the second transistor Tr2. Since the magnetoresistive element 105 can secure electrical connections with the first transistor Tr1 and the second transistor Tr2 on the lower surface of the magnetic domain wall moving layer 15, even if the x-direction length L15 of the magnetoresistive element 105 is longer than the sum of the first gate width L3 and the third gate width L5, the wiring connecting the magnetoresistive element 105 to the first transistor Tr1 or the second transistor Tr2 does not become complicated. In addition, transistors can be placed in the portion of the substrate Sub that overlaps with the magnetoresistive element 105 when viewed from the z-direction, allowing for efficient use of the effective area.

[0111] The domain wall moving element 204 according to the fifth embodiment provides the same effects as the domain wall moving element 200 according to the first embodiment. Furthermore, the domain wall moving element 204 according to the fifth embodiment simplifies the wiring between the magnetoresistive element 105 and the first transistor Tr1 or the second transistor Tr2.

[0112] "Sixth Embodiment" Figure 15 is a cross-sectional view of the magnetic domain wall moving element 205 according to the sixth embodiment. Figure 15 is a cross-sectional view of the xz plane passing through the center in the y direction of the magnetic domain wall moving layer 11.

[0113] The magnetic domain wall moving element 205 according to the sixth embodiment comprises a first magnetoresistive effect element 101, a second magnetoresistive effect element 102, a first transistor Tr1, and a second transistor Tr2. In Figure 15, components similar to those in the embodiments described above are denoted by the same reference numerals and their descriptions are omitted.

[0114] The first magnetoresistive element 101 and the second magnetoresistive element 102 are located at different positions in the z-direction. For example, the first magnetoresistive element 101 and the second magnetoresistive element 102 partially overlap when viewed from the z-direction.

[0115] The magnetic domain wall moving element 205 according to the sixth embodiment provides the same effects as the magnetic domain wall moving element 200 according to the first embodiment. Furthermore, since the elements of the magnetic domain wall moving element 205 can be arranged three-dimensionally, it offers superior integration.

[0116] "Seventh Embodiment" Figure 16 is a cross-sectional view of the magnetic domain wall moving element 206 according to the seventh embodiment. Figure 16 is a cross-sectional view of the xz plane passing through the center in the y direction of the magnetic domain wall moving layer 10.

[0117] The magnetic domain wall moving element 206 according to the seventh embodiment comprises a magnetoresistive element 100, a first transistor Tr1, and a vertical transistor VTr. In Figure 16, components similar to those in the above-described embodiments are denoted by the same reference numerals and their descriptions are omitted.

[0118] In the magnetic domain wall moving element 206, the second transistor Tr2 of the magnetic domain wall moving element 200 is replaced by a vertical transistor VTr. The vertical transistor VTr comprises, for example, a core 81, a gate insulating film 82, and a gate 83.

[0119] The core 81 is a semiconductor. The gate insulating film 82 covers the periphery of the core 81. The gate insulating film 82 contains the same material as the gate insulating film 91. The gate 83 covers the periphery of the gate insulating film 82. The gate 83 controls the current flowing through the core 81 by applying a voltage to the core 81 through the gate insulating film 82. When a voltage is applied to the gate 83, a channel connecting two active regions AA7 and AA8 is formed in the z direction inside the core 81.

[0120] The magnetic domain wall moving element 206 according to the seventh embodiment provides the same effects as the magnetic domain wall moving element 200 according to the first embodiment. Furthermore, the magnetic domain wall moving element 206 has superior integration because one of its transistors is arranged vertically. In addition, the vertical transistor VTr only needs to be applied to one of the multiple magnetic domain wall moving elements, and does not need to be applied to all of them.

[0121] Although preferred embodiments of the present invention have been described in detail above, the present invention is not limited to these embodiments. For example, characteristic configurations of each embodiment may be combined, or parts may be modified without changing the essence of the invention. [Explanation of symbols]

[0122] 1...Integration region, 2...Peripheral region, 3...Pulse application device, 4...Resistance detection device, 5...Output section, 6...Control section, 7...Power supply, 10,11,12,13,15...Magnetic wall moving layer, 10A...Top surface, 20,21,22,23,25...Non-magnetic layer, 30,31,32,33,35...Ferromagnetic layer, 40,41,42,43,45...First conductive layer, 50,51,52,53,55...Second conductive layer, 60,61,62,63,65...Third conductive layer, 81...Core, 82,91,92,93,94...Gate insulating film, 83...Gate, 90...Insulating layer, 100,105...Magnetoresistive effect element, 101...First magnetoresistive effect element, 102...Second Magnetoresistive element, 103...Third magnetoresistive element, 200, 201, 202, 203, 204, 205, 206...Denomination wall moving elements, AA1...First active region, AA2...Second active region, AA3...Third active region, AA4...Fourth active region, AA5...Fifth active region, AA6...Sixth active region, AA7, AA8...Active regions, C1...First channel, C2...Second channel, C3...Third channel, C4...Fourth channel, G1...First gate, G2...Second gate, G3...Third gate, G4...Fourth gate, Tr1, Tr1'...First transistor, Tr2, Tr2'...Second transistor, VTr...Vertical transistor

Claims

1. It comprises a first magnetoresistive element, a first transistor, a second magnetoresistive element, a second transistor, and a third magnetoresistive element. The first magnetoresistive element comprises a first magnetic domain wall moving layer, a first ferromagnetic layer, and a first non-magnetic layer sandwiched between the first magnetic domain wall moving layer and the first ferromagnetic layer. The second magnetoresistive element comprises a second magnetic domain wall migration layer, a second ferromagnetic layer, and a second non-magnetic layer sandwiched between the second magnetic domain wall migration layer and the second ferromagnetic layer. The third magnetoresistive element comprises a third magnetic domain wall moving layer, a third ferromagnetic layer, and a third non-magnetic layer sandwiched between the third magnetic domain wall moving layer and the third ferromagnetic layer. The first transistor comprises a first active region, a second active region, a first gate for controlling the current between the first active region and the second active region, a third active region, and a second gate for controlling the current between the second active region and the third active region. The second transistor comprises a fourth active region, a fifth active region, a sixth active region, a third gate for controlling the current between the fourth active region and the fifth active region, and a fourth gate for controlling the current between the fifth active region and the sixth active region. The first magnetic domain wall moving layer is electrically connected to the first active region, The second magnetic domain wall migration layer is electrically connected to the third active region, The fourth active region is electrically connected to the second magnetic domain wall migration layer, The sixth active region is electrically connected to the third magnetic domain wall moving layer, The first magnetoresistive element has a length in the first direction that is longer than the length in the second direction perpendicular to the first direction. The first gate has a length in the first direction that is longer than the length in the second direction. The length of the first magnetoresistive element in the first direction is longer than the length of the first gate in the first direction. A magnetic domain wall moving element in which the first gate length direction connecting the first active region and the second active region intersects the first direction.

2. It comprises a first magnetoresistive element, a first transistor, and a second transistor, The first magnetoresistive element comprises a first magnetic domain wall moving layer, a first ferromagnetic layer, and a first non-magnetic layer sandwiched between the first magnetic domain wall moving layer and the first ferromagnetic layer. The first transistor comprises a first active region, a second active region, and a first gate that controls the current between the first active region and the second active region. The second transistor comprises a fourth active region, a fifth active region, and a third gate that controls the current between the fourth active region and the fifth active region. The first magnetic domain wall moving layer is electrically connected to the first active region, The first magnetic domain wall moving layer is electrically connected to the fourth active region at a position different from the point where it is electrically connected to the first active region. The first magnetoresistive element has a length in the first direction that is longer than the length in the second direction perpendicular to the first direction. The first gate has a length in the first direction that is longer than the length in the second direction. The third gate has a length in the first direction that is longer than the length in the second direction. The length of the first magnetoresistive element in the first direction is longer than the length of the first gate in the first direction. The first gate length direction connecting the first active region and the second active region intersects with the first direction. A magnetic domain wall moving element wherein the length of the first magnetoresistive element in the first direction is shorter than the sum of the lengths of the first gate and the third gate in the first direction.

3. It comprises a first magnetoresistive element, two first transistors, two second transistors, and a second magnetoresistive element. The first magnetoresistive element comprises a first magnetic domain wall moving layer, a first ferromagnetic layer, and a first non-magnetic layer sandwiched between the first magnetic domain wall moving layer and the first ferromagnetic layer. The second magnetoresistive element comprises a second magnetic domain wall migration layer, a second ferromagnetic layer, and a second non-magnetic layer sandwiched between the second magnetic domain wall migration layer and the second ferromagnetic layer. Each of the two first transistors comprises a first active region, a second active region, and a first gate that controls the current between the first active region and the second active region. Each of the two second transistors comprises a fourth active region, a fifth active region, and a third gate that controls the current between the fourth active region and the fifth active region. The first magnetic domain wall migration layer is electrically connected to the first active region of the first transistor and the fourth active region of the first second transistor. The second magnetic domain wall migration layer is electrically connected to the first active region of the second first transistor and the fourth active region of the second second transistor. The first magnetoresistive element has a length in the first direction that is longer than the length in the second direction perpendicular to the first direction. The first gate has a length in the first direction that is longer than the length in the second direction. The length of the first magnetoresistive element in the first direction is longer than the length of the first gate in the first direction. The first gate length direction connecting the first active region and the second active region intersects with the first direction. The first magnetoresistive element and the second magnetoresistive element are located at different positions in the stacking direction. The first active region of the second first transistor is a magnetic wall moving element located between the first active region of the first first transistor and the fourth active region of the first second transistor in the first direction.

4. Further comprising a second magnetoresistive element, The second magnetoresistive element comprises a second magnetic domain wall migration layer, a second ferromagnetic layer, and a second non-magnetic layer sandwiched between the second magnetic domain wall migration layer and the second ferromagnetic layer. The first transistor further comprises a third active region and a second gate that controls the current between the second active region and the third active region. The magnetic domain wall moving element according to claim 2, wherein the second magnetic domain wall moving layer is electrically connected to the third active region.

5. The second transistor further comprises a sixth active region and a fourth gate that controls the current between the fifth active region and the sixth active region. The fourth active region is electrically connected to the first magnetic domain wall moving layer, The magnetic wall moving element according to claim 4, wherein the sixth active region is electrically connected to the second magnetic wall moving layer.

6. It further has a substrate, The first ferromagnetic layer is located closer to the substrate than the first magnetic domain wall moving layer. The magnetic wall moving element according to claim 1, wherein the first conductive layer electrically connected to the first active region is connected to the upper surface of the first magnetic wall moving layer.

7. The magnetic wall moving element according to claim 6, wherein, when viewed from the stacking direction, at least a portion of the first active region does not overlap with the first magnetic wall moving layer.

8. The magnetic domain wall moving element according to claim 1, wherein the first channel between the first active region and the second active region comprises an oxide containing one or more elements selected from the group consisting of In, Ga, Zn, and Al.

9. The magnetic domain wall moving element according to claim 3, wherein the transistor connected to the second magnetoresistive element has a channel connecting the two active regions formed in the stacking direction.

10. A magnetic array comprising the magnetic domain wall moving element described in claim 1.

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