Method and apparatus for reducing coding wait time for decoder-side motion refinement

Decoder-side motion vector refinement techniques enhance video coding efficiency by refining motion vectors using spatial and temporal prediction, addressing the limitations of HEVC and aligning with the VVC standard, achieving up to 40% improved compression efficiency.

JP7883001B2Active Publication Date: 2026-06-30INTERDIGITAL VC HOLDINGS INC
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Patent Information

Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
INTERDIGITAL VC HOLDINGS INC
Filing Date
2025-02-06
Publication Date
2026-06-30

AI Technical Summary

Technical Problem

Existing video coding standards like HEVC face limitations in achieving superior coding efficiency, and new techniques are needed to enhance compression efficiency beyond what is offered by HEVC, particularly in refining motion vectors for improved video quality and reduced latency.

Method used

Implement decoder-side motion vector refinement (DMVR) techniques, including spatial and temporal motion vector prediction, to refine unrefined motion vectors into refined motion vectors for dual prediction, using methods such as AMVP, TMVP, and optical flow models to enhance coding efficiency and reduce latency.

Benefits of technology

The proposed methods significantly improve coding efficiency by approximately 40% over HEVC, reducing coding latency and enhancing video quality through refined motion vectors, aligning with the goals of the Versatile Video Coding (VVC) standard.

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Abstract

To provide video coding systems and methods for reducing coding latency introduced by DMVR.SOLUTION: Two non-refined motion vectors are identified for coding of a first block of samples (e.g., a first coding unit) using bi-prediction. One or both of the non-refined motion vectors are used to predict motion information for a second block of samples (e.g., a second coding unit). The two non-refined motion vectors are refined using DMVR, and the refined motion vectors are used to generate a prediction signal of the first block of samples. Such embodiments allow the second block of samples to be coded substantially in parallel with the first block without waiting for completion of DMVR on the first block.SELECTED DRAWING: Figure 13
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