Fluorine-doped silicon-containing material

Abstract

An exemplary semiconductor processing method may include delivering one or more deposition precursors to a processing region of a semiconductor processing chamber. The method may include contacting a substrate contained in the processing region with the one or more deposition precursors. The method may include forming a silicon-containing material on the substrate. The method may include delivering a fluorine-containing precursor to a processing region of a semiconductor processing chamber. The method may include contacting the silicon-containing material on the substrate with the fluorine-containing precursor to form a fluorine-treated silicon-containing material. The method may include contacting the fluorine-treated silicon-containing material with plasma effluents of argon or diatomic nitrogen.

Description

[Technical Field]

[0001] Cross-reference with related applications

[0001] This application claims the benefits and priority of U.S. Patent Application No. 17 / 941,347, filed September 9, 2022, entitled "FLUORINE-DOPED SILICON-CONTAINING MATERIALS," the contents of which are incorporated herein by reference in their entirety.

[0002]

[0002] This technology relates to a deposition process and a chamber. More specifically, this technology relates to a method for producing a fluorine-doped silicon-containing material. [Background technology]

[0003]

[0003] Integrated circuits are made possible by a process of fabricating intricately patterned material layers on a substrate surface. Fabricating patterned material on a substrate requires controlled methods for forming and removing the material. The properties of the material can affect the operation of the device and can also affect how the film is removed from each other. Plasma deposition can be used to fabricate films with specific properties. Many of the formed films require additional processing to adjust or enhance the material properties of the film in order to provide the desired properties.

[0004]

[0004] Therefore, there is a need for improved systems and methods that can be used to manufacture high-quality devices and structures. These and other needs are addressed by this technology. [Overview of the project]

[0005]

[0005] An exemplary semiconductor processing method may include supplying one or more deposition precursors to a processing area of ​​a semiconductor processing chamber. The method may include bringing a substrate housed in the processing area into contact with one or more deposition precursors. The method may include forming a silicon-containing material on the substrate. The method may include supplying a fluorine-containing precursor to a processing area of ​​a semiconductor processing chamber. The method may include bringing a silicon-containing material on a substrate into contact with a fluorine-containing precursor in order to form a fluorine-treated silicon-containing material. The method may include bringing the fluorine-treated silicon-containing material into contact with argon or diatomic nitrogen plasma emissions.

[0006]

[0006] In some embodiments, one or more deposition precursors include a silicon-containing precursor and a boron-containing precursor. During the semiconductor processing method, the temperature in the semiconductor processing chamber may be maintained at about 550°C or less. The substrate may include features characterized by an aspect ratio of about 3:1 or greater. The method may include stopping the flow of one or more deposition precursors after the formation of the silicon-containing material on the substrate. The method may include reducing the pressure in the semiconductor processing chamber before supplying the fluorine-containing precursor to the processing area of ​​the semiconductor processing chamber. While the silicon-containing material on the substrate is in contact with the fluorine-containing precursor, the pressure in the semiconductor processing chamber may be maintained at about 15 Torr or less. The method may include forming an argon or diatomic nitrogen plasma emitter before contacting the fluorinated silicon-containing material with an argon or diatomic nitrogen plasma emitter. The argon or diatomic nitrogen plasma emitter may be formed at a plasma output of about 750 W or less. This method may include forming a fluorine-doped silicon-boron-nitrogen-containing material by contacting a fluorine-treated silicon-containing material with argon or diatomic nitrogen plasma emissions. The fluorine-doped silicon-boron-nitrogen-containing material may be characterized by conformality of about 90% or more. The fluorine-doped silicon-boron-nitrogen-containing material may be characterized by a thickness of about 750 Å or less. The fluorine-doped silicon-boron-nitrogen-containing material may be characterized by a dielectric constant of about 4.6 or less.

[0007]

[0007] Some embodiments of the present technology include a semiconductor processing method. The method may include i) forming a silicon-containing material on a substrate. The method may include ii) contacting the silicon-containing material on the substrate with a fluorine-containing precursor to form a fluorine-treated silicon-containing material. The method may include iii) contacting the fluorine-treated silicon-containing material with a plasma emission of argon or diatomic nitrogen to form a fluorine-doped silicon-boron-nitrogen-containing material. The method may include iv) repeating steps i) to iii) for at least 5 cycles.

[0008]

[0008] In some embodiments, steps i) and ii) are performed in a plasma-free manner. The substrate may include features characterized by an aspect ratio of about 3:1 or greater. The fluorine-doped silicon-boron-nitrogen-containing material may be characterized by conformality of about 90% or greater. During the semiconductor processing method, the temperature may be maintained at about 550°C or less. During the semiconductor processing method, the pressure may be maintained at about 40 Torr or less. The method may include v) annealing the substrate and the fluorine-doped silicon-boron-nitrogen-containing material.

[0009]

[0009] Some embodiments of the present technology include a semiconductor processing method. The method may include supplying one or more deposition precursors to a processing area of ​​a semiconductor processing chamber. The one or more deposition precursors may include a silicon-containing precursor. The method may include bringing a substrate housed in the processing area into contact with one or more deposition precursors. The method may include thermally forming a layer of silicon-containing material on the substrate. The method may include supplying a fluorine-containing precursor to a processing area of ​​a semiconductor processing chamber. The method may include thermally bringing a layer of silicon-containing material on a substrate into contact with a fluorine-containing precursor to form a layer of fluorine-doped silicon-containing material. The method may include supplying argon, diatomic nitrogen, or both to a processing area of ​​a semiconductor processing chamber. The method may include forming plasma emitters of argon, diatomic nitrogen, or both. The method may include bringing a layer of fluorine-doped silicon-containing material into contact with plasma emitters of argon, diatomic nitrogen, or both to form a layer of fluorine-doped silicon-containing material.

[0010]

[0010] In some embodiments, the layer of fluorine-doped silicon-containing material is characterized by conformality of about 90% or more. Plasma emissions of argon, diatomic nitrogen, or both can be formed at a plasma output of about 750 W or less. The layer of fluorine-doped silicon-containing material has a dielectric constant of about 4.6 or less and a dielectric constant of about 5.0 E-08 A / cm². 2It can be characterized by the following leakage currents.

[0011]

[0011] The above technology can offer many advantages over conventional systems and techniques. For example, the deposition properties can be improved by performing fluorine treatment and plasma treatment. For example, by performing fluorine treatment, the conformability of the deposited material can be improved, the dielectric constant of the deposited material can be reduced, and / or the leakage current of the deposited material can be reduced. Furthermore, by performing plasma treatment, the material may be densified, the conformability may be further improved, and / or the dielectric constant may be reduced. These and other embodiments will be described in more detail below, along with their many advantages and features, in conjunction with the accompanying figures.

[0012]

[0012] A further understanding of the nature and advantages of the disclosed technology can be obtained by referring to the remainder of this specification and the drawings. [Brief explanation of the drawing]

[0013] [Figure 1] This is a top view showing an exemplary processing system according to several embodiments of this technology. [Figure 2] A schematic cross-sectional view showing an exemplary plasma system according to several embodiments of this technology. [Figure 3] This figure shows the steps of an exemplary semiconductor processing method according to several embodiments of this technology. [Figure 4A] This is a cross-sectional view showing a substrate processed according to several embodiments of this technology. [Figure 4B] This is a cross-sectional view showing a substrate processed according to several embodiments of this technology. [Modes for carrying out the invention]

[0014]

[0017] Some of the figures are included as schematic diagrams. Please understand that the figures are for illustrative purposes only and should not be considered to scale unless the scale is specifically stated. Furthermore, as schematic diagrams, they are provided to aid understanding and may not include all aspects or information compared to realistic representations, and may contain exaggerated material for illustrative purposes.

[0015]

[0018] In the attached diagrams, similar components and / or features may be given the same reference label. Furthermore, various components of the same type may be distinguished by adding a letter after the reference label to distinguish similar components. If only the first reference label is used herein, its description is applicable to any one of the similar components having the same first reference label, regardless of the letter.

[0016]

[0019] In integrated circuit formation, numerous material layers are formed and then partially or completely removed. In some integrated circuits, spacer or liner materials need to be formed to at least partially isolate other materials formed on either side of the spacer. Conventional techniques may use purely thermal processes or deposition-etching loop processes to form spacer or liner materials with desired conformation. These conventional approaches cannot simultaneously achieve both low dielectric constant and high conformation. As integrated circuits become smaller, material layers that serve multiple purposes, such as low dielectric constant and high conformation, are increasingly desired. Furthermore, these conventional approaches may result in spacer or liner materials that do not meet leakage current or breakdown voltage requirements. Additionally, these conventional techniques are prone to shrinkage during post-formation processing such as annealing, potentially preventing the maintenance of desirable material properties.

[0017]

[0020] This technology can overcome these problems by performing fluorine treatment and / or plasma treatment after depositing a silicon-containing material. The fluorine treatment can introduce a fluorine-containing precursor to heat-treat the formed silicon-containing material, and fluorine can be doped into the silicon-containing material. When doped into the silicon-containing material, fluorine can replace the hydrogen bonds in the material with fluorine bonds. This replacement smoothens the surface of the silicon-containing material and improves its conformality. In plasma treatment, heavy inert precursors can be made to impinge on the film to densify the film and further enhance the conformality. Fluorine treatment and / or plasma treatment may also have a positive impact on the electrical properties of the silicon-containing material, such as dielectric constant, leakage current, and breakdown voltage. In the prior art, it was not possible to meet all these properties of the deposited film, and thereby one or more desirable properties were sacrificed.

[0018]

[0021] The remaining disclosure always identifies a specific deposition process using the disclosed technology, but it will be readily understood that the systems and methods are equally applicable to other deposition chambers and processes that can be performed in the described chambers. Therefore, the technology should not be considered limited to use only in these specific deposition processes or chambers. In this disclosure, before explaining additional details regarding embodiments of the technology, one possible system and chamber that can be used to execute the deposition process according to embodiments of the technology will be described.

[0019]

[0022] Figure 1 is a top view showing one embodiment of a deposition, etching, firing, and curing chamber processing system 100 according to an embodiment. In the figure, a pair of forward-opening unified pods 102 supply substrates of various sizes, which are received by a robotic arm 104 and placed in a low-pressure holding area 106 before being placed in one of the substrate processing chambers 108a-f positioned in tandem sections 109a-c. Substrate wafers can be transported from the holding area 106 to and from the substrate processing chambers 108a-f using a second robotic arm 110. Each substrate processing chamber 108a-f may be equipped to perform a number of substrate processing steps, including the formation of stacks of semiconductor materials as described herein, in addition to other substrate processes including plasma chemical vapor deposition, atomic layer deposition, physical vapor deposition, etching, pre-cleaning, degassing, orientation, and annealing, ashing, etc.

[0020]

[0023] The substrate processing chambers 108a-f may include one or more system components for depositing, annealing, curing, and / or etching dielectric films or other films on a substrate. In one configuration, two pairs of processing chambers, e.g., 108c-d and 108e-f, may be used to deposit dielectric material on a substrate, and a third pair of processing chambers, e.g., 108a-b, may be used to etch the deposited dielectric. In another configuration, all three pairs of chambers, e.g., 108a-f, may be configured to deposit alternating stacks of dielectric films on a substrate. One or more of the processes described may be carried out in chambers separate from the manufacturing system shown in different embodiments. It will be understood that additional configurations of deposition, etching, annealing, and curing chambers for dielectric films are assumed by system 100.

[0021]

[0024] FIG. 2 is a schematic cross-sectional view showing an exemplary plasma system 200 according to some embodiments of the present technology. The plasma system 200 may be equipped in one or more of the tandem sections 109 described above, and may exemplify a pair of processing chambers 108 that may include lid stack components according to embodiments of the present technology that may be further described below. The plasma system 200 generally may include a chamber body 202 having side walls 212, a bottom wall 216, and an internal side wall 201 that defines a pair of processing regions 220A and 220B. Each of the processing regions 220A-220B may be similarly configured and may include the same components.

[0022]

[0025] For example, the processing region 220B (the components of which may also be included in the processing region 220A) may include a pedestal 228 disposed within the processing region through a passage 222 formed in the bottom wall 216 within the plasma system 200. The pedestal 228 may provide a heater adapted to support a substrate 229 on the exposed surface of the pedestal, such as a body portion. The pedestal 228 may include a heating element 232, such as a resistive heating element, for example, and may heat and control the substrate temperature to a desired process temperature. The pedestal 228 may also be heated by a remote heating element, such as a lamp assembly, or any other heating device.

[0023]

[0026] The body of the pedestal 228 may be coupled to the stem 226 by a flange 233. The stem 226 can electrically couple the pedestal 228 to a power outlet or power box 203. The power box 203 may include a drive system that controls the raising and moving of the pedestal 228 within the processing area 220B. The stem 226 may also include a power interface for supplying power to the pedestal 228. The power box 203 may also include interfaces for power and temperature indicators, such as a thermocouple interface. The stem 226 may include a base assembly 238 adapted to be detachably coupled to the power box 203. A perimeter ring 235 is shown above the power box 203. In some embodiments, the perimeter ring 235 may be a shoulder adapted as a mechanical stop or land configured to provide a mechanical interface between the base assembly 238 and the top surface of the power box 203.

[0024]

[0027] The rod 230 may be included through a passage 224 formed in the bottom wall 216 of the processing area 220B and can be used to position substrate lift pins 261 which are positioned through the body of the pedestal 228. The substrate lift pins 261 can selectively space the substrate 229 away from the pedestal and facilitate the replacement of the substrate 229 by a robot used to transport the substrate 229 in and out of the processing area 220B through the substrate transfer port 260.

[0025]

[0028] A chamber lid 204 may be coupled to the top of the chamber body 202. The lid 204 can house one or more precursor distribution systems 208 coupled thereto. The precursor distribution system 208 may include a precursor inlet passage 240 that can deliver reaction and washing precursors into the processing area 220B through a dual-channel showerhead 218. The dual-channel showerhead 218 may include an annular base plate 248 having a blocker plate 244 positioned in the middle of a faceplate 246. A radio frequency ("RF") source 265 may be coupled to the dual-channel showerhead 218 to supply power to the dual-channel showerhead 218, facilitating the generation of a plasma region between the faceplate 246 of the dual-channel showerhead 218 and the pedestal 228. In some embodiments, the RF source may be coupled to other parts of the chamber body 202, such as the pedestal 228, to facilitate plasma generation. A dielectric isolator 258 can be placed between the lid 204 and the dual-channel showerhead 218 to prevent the conduction of RF power to the lid 204. A shadow ring 206 may be placed around the periphery of the pedestal 228 and engage with the pedestal 228.

[0026]

[0029] Optional cooling channels 247 may be formed in the annular base plate 248 of the precursor distribution system 208 for cooling the annular base plate 248 during the process. A heat transfer fluid such as water, ethylene glycol, or gas can be circulated through the cooling channels 247 so that the base plate 248 can be maintained at a predetermined temperature. The liner assembly 227 can be positioned in the processing area 220B close to the side walls 201, 212 of the chamber body 202 to prevent the side walls 201, 212 from being exposed to the processing environment in the processing area 220B. The liner assembly 227 may include an ambient pumping cavity 225 which may be coupled to a pumping system 264 configured to exhaust gases and by-products from the processing area 220B and to control the pressure within the processing area 220B. Multiple exhaust ports 231 may be formed on the liner assembly 227. The exhaust port 231 may be configured to allow gas flow from the processing area 220B to the surrounding pumping cavity 225 in a manner that facilitates processing within the system 200.

[0027]

[0030] Figure 3 shows the steps of an exemplary method 300 for semiconductor processing according to several embodiments of the present technology. The method can be performed in a variety of processing chambers, including the processing system 200 described above, and any other chambers in which plasma deposition may be performed. Method 400 may include one or more pre-initiation steps of the method, including front-end processing, polishing, cleaning, deposition, etching, or any other steps that may be performed before the described steps. Method 300 may include a number of optional steps that may or may not be particularly relevant to certain embodiments of the method relating to the present technology. For example, many of the steps are described to provide a broader range of structure formation but are not important to the present technology, or may be performed by alternative methodologies, as will be further described below. Method 300 shows the steps schematically shown in Figures 4A and 4B, and these illustrations will be explained in conjunction with the steps of Method 300. Figures 4A and 4B are only partial schematics, and it should be understood that the substrate may include any number of transistor sections having the configuration illustrated in the figures.

[0028]

[0031] As shown in Figure 4A, the structure 400 may include a substrate 405. The substrate 405 may be made of or contain silicon or other semiconductor substrate material. One or more material layers 410 may be formed on the substrate 405. One or more material layers 410 may include or define a recess 415. The aspect ratio of the recess 415, or the ratio of the length of the hole to the diameter of the hole, may be about 2:1 or greater, about 3:1 or greater, about 4:1 or greater, about 5:1 or greater, about 6:1 or greater, about 7:1 or greater, about 8:1 or greater, about 9:1 or greater, about 10:1 or greater, or greater.

[0029]

[0032] In step 305, method 300 may include supplying one or more deposition precursors into a processing chamber capable of delivering the precursors into a processing area of ​​the chamber in which the substrate 405 can be housed, for example, area 220. The deposition precursors may include, for example, silicon-containing precursors, boron-containing precursors, nitrogen-containing precursors, or any other deposition precursors used to form a silicon-containing material.

[0030]

[0033] In embodiments, one or more deposition precursors may include a silicon-containing precursor. The silicon-containing precursor may include organosilanes that may contain silane, disilane, and other materials. Additional silicon-containing precursors may include silicon, carbon, oxygen, or nitrogen, such as trisilylamine. In embodiments, one or more deposition precursors may include a boron-containing precursor. The boron-containing precursor may include boron, such as borane, diborane, or other multi-core boron materials, and any other boron-containing materials that may be used to produce silicon-boron-containing materials. In some embodiments, deposition may use a single deposition precursor, such as a silicon and boron-containing precursor. The precursor may or may not include the delivery of a carrier gas or additional precursors, such as one or more oxygen-containing precursors, for depositing the oxide layer.

[0031]

[0034] In step 310, method 300 may include contacting the substrate 405 with one or more deposition precursors. As shown in Figure 4B, in step 315, method 300 may include forming a silicon-containing material 420. The silicon-containing material may be formed on one or more material layers 410 formed on the substrate 405.

[0032]

[0035] The steps performed in Method 300 may depend on the process conditions. Each step of Method 300 may be performed at a constant temperature in some embodiments, but in some embodiments, the temperature may be adjusted during different steps. In some embodiments of the Art, Method 300 may be performed when the substrate, pedestal, and / or chamber temperature is below about 550°C due to thermal balance issues, and may be performed at temperatures below about 525°C, below about 500°C, below about 475°C, below about 450°C, below about 425°C, below about 400°C, below about 375°C, below about 350°C, below about 325°C, below about 300°C, or below. The temperature may also be maintained within these ranges, within a smaller range encompassed by these ranges, or at any temperature between any of these ranges. Forming the material at higher temperatures may reduce the deposition rate and thus improve conformability. Therefore, in some embodiments, the pressure may be maintained between about 400°C and about 500°C.

[0033]

[0036] The pressure within the semiconductor processing chamber can also affect the process being performed. In embodiments, the pressure may be maintained below about 40 Torr. Thus, the pressure may be maintained at about 35 Torr or less, about 30 Torr or less, about 25 Torr or less, about 20 Torr or less, about 18 Torr or less, about 16 Torr or less, about 14 Torr or less, about 12 Torr or less, about 10 Torr or less, about 8 Torr or less, about 6 Torr or less, about 4 Torr or less, about 2 Torr or less, about 1 Torr or less, or less. The pressure may also be maintained at any pressure within these ranges, a smaller range encompassed within these ranges, or any pressure between these ranges. Furthermore, the pressure may be adjusted during Method 300 as described below. Conformability may increase as the pressure increases, because the precursor scatters more before reaching the substrate, thereby reaching the substrate surface at a more random angle, resulting in greater conformability of film growth. Therefore, in some embodiments, the pressure can be maintained between approximately 10 Torr and approximately 20 Torr.

[0034]

[0037] In step 320, method 300 may include supplying a fluorine-containing precursor into a processing chamber capable of delivering the precursor into a processing area of ​​the chamber in which the substrate 405 can be housed. An exemplary fluorine-containing precursor may be nitrogen trifluoride (NF3). Other sources of fluorine may be used in combination with or as a substitute for nitrogen trifluoride. In some embodiments, the fluorine-containing precursor may be or may include atomic fluorine, diatomic fluorine, hydrogen fluoride, nitrogen trifluoride, carbon tetrafluoride, xenon difluoride, and various other fluorine-containing precursors used or available for semiconductor processing.

[0035]

[0038] In step 325, method 300 may include contacting the silicon-containing material 420 with a fluorine-containing precursor. The silicon-containing material 420 can be doped with the fluorine-containing precursor to form a silicon-doped fluorine-containing material. Specifically, the fluorine-containing precursor can rearrange the bonds in the silicon-containing material, replacing at least some Si-H and BH bonds with Si-F and BF bonds, respectively. The fluorine bonds, which have less polarization compared to the previous hydrogen bonds, may reduce the dielectric constant of the silicon-containing material 420. The fluorine bonds may reduce the leakage current of the silicon-containing material 420. Furthermore, contact between the silicon-containing material 420 and the fluorine-containing precursor may lead to the formation of Si-F bonds from dangling silicon bonds on the surface of the silicon-containing material 420. The formation of Si-F bonds from dangling silicon bonds and the increased polarization stability of fluorine may stabilize the surface of the silicon-containing material 420, thereby alleviating strained areas on the surface. By alleviating strained areas on the surface of the silicon-containing material 420, conformability may be improved. After contact with a fluorine-containing precursor, the silicon-containing material 420 may be characterized by a fluorine concentration of about 30 atomic percent or less, about 28 atomic percent or less, about 26 atomic percent or less, about 24 atomic percent or less, about 22 atomic percent or less, about 20 atomic percent or less, about 18 atomic percent or less, about 16 atomic percent or less, about 14 atomic percent or less, about 12 atomic percent or less, about 10 atomic percent or less, or less.

[0036]

[0039] In embodiments, method 300 may include reducing the pressure between steps 320 and 325. For example, the pressure can be reduced to about 15 Torr or less, about 14 Torr or less, about 13 Torr or less, about 12 Torr or less, about 11 Torr or less, about 10 Torr or less, about 9 Torr or less, about 8 Torr or less, about 7 Torr or less, about 6 Torr or less, about 5 Torr or less, about 4 Torr or less, about 3 Torr or less, about 2 Torr or less, about 1 Torr or less, or less. Lower pressures may result in shorter residence times for the fluorine-containing precursor compared to steps 305-315. Lower pressures may increase the mean free path and increase the interaction between the fluorine-containing precursor and the silicon-containing material 420.

[0037]

[0040] The fluorine treatment in steps 320 and 325 can be continued for a sufficient period of time for the fluorine-containing precursor to interact with the silicon-containing material 420. For example, the fluorine treatment in steps 320 and 325 can be continued for a period of approximately 2 seconds to approximately 60 seconds. However, it is assumed that steps 320 and 325 can be continued for periods of less than approximately 2 seconds and / or more than approximately 60 seconds, depending on various conditions such as temperature, pressure, flow rate of the fluorine-containing precursor, and the properties and characteristics of the silicon-containing material 420.

[0038]

[0041] In embodiments, method 300 may include stopping the flow of one or more deposition precursors before supplying the fluorine-containing precursors in step 320. By stopping the flow of one or more deposition precursors, the deposition of the material can be reduced or stopped, making it possible to dop the formed silicon-containing material 420 with the fluorine-containing precursors. However, it is assumed that the flow of one or more deposition precursors can, alternatively, be reduced and / or maintained during step 320.

[0039]

[0042] In step 330, method 300 may include contacting a fluorine-treated silicon-containing material with a plasma emitter. Note that prior to step 330, the semiconductor processing chamber may be kept plasma-free in any or all of steps 305 to 325, for example. Method 300 may include supplying one or more plasma processing precursors into a processing chamber capable of delivering the precursors into the processing area of ​​the chamber in which the substrate 405 can be housed. The plasma processing precursors may include nitrogen-containing precursors such as diatomic nitrogen, which can be added to the silicon-containing material 420. After treatment with the fluorine-containing precursor, the plasma treatment in step 330 may form a fluorine-doped silicon-nitrogen-containing material, such as a fluorine-doped silicon-boron-nitrogen-containing material. The plasma processing precursors may also include one or more inert species such as argon, neon, xenon, or hydrogen.

[0040]

[0043] Plasma emissions from one or more plasma-treated precursors can be generated at plasma power outputs of approximately 750 W or less. Plasma power outputs exceeding 750 W may increase the likelihood of arc discharges that could be detrimental to plasma treatment and the formation of fluorine-doped silicon-containing materials. Therefore, plasma emissions from one or more plasma-treated precursors can be generated at plasma power outputs of approximately 700 W or less, and can be generated at approximately 650 W or less, approximately 600 W or less, approximately 550 W or less, approximately 500 W or less, approximately 450 W or less, approximately 400 W or less, approximately 350 W or less, approximately 300 W or less, approximately 250 W or less, approximately 200 W or less, approximately 150 W or less, or less.

[0041]

[0044] In the plasma treatment in step 330, materials can be added to the silicon-containing material 420 through plasma emissions of a nitrogen-containing precursor. Furthermore, plasma emissions of an inert precursor collide with the film, causing the silicon-containing material 420 to densify. When the silicon-containing material 420 is densified, its conformability can be further improved. Using a heavy inert precursor such as argon can impact the film, causing the silicon-containing material 420 to densify. The plasma treatment in step 330 can be performed under reduced pressure in steps 320 and 325, which increases the plasma density and helps the film to densify more uniformly, which can also lead to improved conformability of the silicon-containing material 420.

[0042]

[0045] The plasma treatment in step 330 can be continued for a period of time sufficient for the plasma to interact with the silicon-containing material 420. For example, the plasma treatment in step 330 can be continued for a period of approximately 2 seconds to approximately 60 seconds. However, it is assumed that step 330 can be continued for a period of less than approximately 2 seconds and / or more than approximately 60 seconds, depending on various conditions such as temperature, pressure, flow rate of the plasma treatment precursor, and the properties and characteristics of the silicon-containing material 420.

[0043]

[0046] After the plasma treatment in step 330, the fluorine-doped silicon-containing material 420 may be characterized by a thickness of about 40 Å or less. If the silicon-containing material 420 is formed to a thickness greater than 40 Å, the fluorine treatment in steps 320 and 325 and the plasma treatment in step 330 may not be very effective. Therefore, the silicon-containing material 420 may be formed to a thickness of about 35 Å or less, about 30 Å or less, about 25 Å or less, about 20 Å or less, about 15 Å or less, about 10 Å or less, about 5 Å or less, or less.

[0044]

[0047] As shown in FIG. 3, method 300 may include repeating steps 300 to 330 a number of cycles in step 335. By repeating steps 300 to 330, a silicon-containing material 420 with an increased thickness may be formed. In an embodiment, the steps of method 300 may be repeated at least 2 cycles, at least 3 cycles, at least 4 cycles, at least 5 cycles, at least 10 cycles, at least 15 cycles, at least 20 cycles, at least 30 cycles, at least 40 cycles, at least 50 cycles, or more. Therefore, after repeating the steps a number of cycles, the silicon-containing material may be characterized by a thickness of up to about 750 Å or about 500 Å, for example, about 100 Å or more, about 125 Å or more, about 150 Å or more, about 175 Å or more, about 200 Å or more, about 250 Å or more, about 300 Å or more, about 350 Å or more, about 400 Å or more, about 450 Å or more, about 500 Å or more, about 550 Å or more, about 600 Å or more, about 650 Å or more, about 700 Å or more, or more.

[0045]

[0048] As described above, the present technology can form a silicon-containing material characterized by a low dielectric constant and improved electrical performance. For example, the silicon-containing material formed according to the present technology may be characterized by a conformality of about 90% or more, for example, about 91% or more, about 92% or more, about 93% or more, about 94% or more, about 95% or more, or more. Further, the silicon-containing material formed according to the present technology may be characterized by a dielectric constant of about 4.6 or less, for example, about 4.5 or less, about 4.4 or less, about 4.3 or less, about 4.2 or less, about 4.1 or less, about 4.0 or less, about 3.9 or less, or less. The silicon-containing material formed according to the present technology has a current density of about 5.0E-08 A / cm 2 or less, for example, about 4.8E-08 A / cm 2 or less, about 4.6E-08 A / cm 2 or less, about 4.4E-08 A / cm 2 or less, about 4.2E-08 A / cm 2 or less, about 4.​​​​​It may be characterized by leakage currents below or less than the following: Conventional techniques typically define conformity of about 90% or more, dielectric constant of about 4.6 or less, and / or about 5.0E-08A / cm². 2 It may not be possible to manufacture silicon-containing films characterized by the following leakage currents. The fluorine treatment and plasma treatment of this technology can sufficiently modify the formed silicon-containing material to adjust the film properties as described.

[0046]

[0049] In the embodiment, after forming the silicon-containing material 420 to a desired thickness, an optional step 340 may be performed to anneal or another rapid thermal process. The annealing or other process may not substantially alter the properties of the silicon-containing material, which demonstrates the thermal stability of the silicon-containing material 420.

[0047]

[0050] The foregoing description includes numerous details to provide an understanding of various embodiments of the Technology for illustrative purposes. However, it will be apparent to those skilled in the art that certain embodiments may be carried out without some of these details, or with additional details.

[0048]

[0051] While several embodiments have been disclosed, those skilled in the art will recognize that various modifications, alternative structures, and equivalents can be used without departing from the spirit of the embodiments. Furthermore, to avoid unnecessarily obscuring the Art, some well-known processes and elements have not been described. Therefore, the above description should not be considered as limiting the scope of the Art.

[0049]

[0052] Where a range of values ​​is provided, unless the context explicitly indicates otherwise, each intervening value between the upper and lower limits of that range, down to the smallest unit of the lower limit, is also specifically disclosed. This includes any narrower range between any unlisted intervening value of any listed value or range and any other listed value or intervening value of that range. The upper and lower limits of these smaller ranges may be independently included in or excluded from the range, and each range that includes one or both limits, or neither, is also included in this technique, according to any specifically excluded limits in the listed range. Where a listed range includes one or both limits, ranges that exclude one or both of those included limits are also included.

[0050]

[0053] As used herein and in the appended claims, the singular forms "a," "an," and "the" include plural references unless the context explicitly indicates otherwise. Thus, for example, a reference to "a silicon-containing precursor" includes multiple such silicon-containing precursors, and a reference to "the layer of material" includes one or more material layers and equivalents well known to those skilled in the art.

[0051]

[0054] Furthermore, as used herein and in the following claims, the terms “comprise,” “comprising,” “contain,” “containing,” “include,” and “including” specify the presence of the described feature, integer, component, or process, but do not preclude the presence or addition of one or more other features, integers, components, processes, operations, or groups.

Claims

1. A semiconductor processing method, Supplying one or more deposition precursors to the processing area of ​​a semiconductor processing chamber, The substrate housed in the processing area is brought into contact with the one or more deposition precursors, Forming a silicon-containing material on the aforementioned substrate, The process of supplying a fluorine-containing precursor to the processing region of the semiconductor processing chamber, To form a fluorine-treated silicon-containing material, the silicon-containing material on the substrate is brought into contact with the fluorine-containing precursor, The fluorine-treated silicon-containing material is brought into contact with argon or diatomic nitrogen plasma emissions. A method that includes this.

2. The semiconductor processing method according to claim 1, wherein the one or more deposition precursors include a silicon-containing precursor and a boron-containing precursor.

3. The semiconductor processing method according to claim 1, wherein the temperature inside the semiconductor processing chamber is maintained at approximately 550°C or lower during the semiconductor processing method.

4. The semiconductor processing method according to claim 1, wherein the substrate includes features characterized by an aspect ratio of approximately 3:1 or greater.

5. After the formation of the silicon-containing material on the substrate, the flow of the one or more deposition precursors is stopped. Before supplying the fluorine-containing precursor to the processing region of the semiconductor processing chamber, the pressure inside the semiconductor processing chamber is reduced. The semiconductor processing method according to claim 1, further comprising:

6. The semiconductor processing method according to claim 5, wherein the pressure in the semiconductor processing chamber is maintained at approximately 15 Torr or less while the silicon-containing material on the substrate is in contact with the fluorine-containing precursor.

7. The semiconductor processing method according to claim 1, further comprising forming the argon or diatomic nitrogen plasma emitter before contacting the fluorine-treated silicon-containing material with the argon or diatomic nitrogen plasma emitter, wherein the argon or diatomic nitrogen plasma emitter is formed with a plasma output of about 750 W or less.

8. By bringing the fluorine-treated silicon-containing material into contact with the argon or diatomic nitrogen plasma emitter, a fluorine-doped silicon-boron-nitrogen-containing material is formed. The aforementioned fluorine-doped silicon-boron-nitrogen-containing material exhibits conformality of approximately 90% or more. Characterized by, The semiconductor processing method according to claim 2.

9. The semiconductor processing method according to claim 8, wherein the fluorine-doped silicon-boron-nitrogen-containing material is characterized by a thickness of about 750 Å or less.

10. The semiconductor processing method according to claim 8, wherein the fluorine-doped silicon-boron-nitrogen-containing material is characterized by a dielectric constant of about 4.6 or less.

11. A semiconductor processing method, i) Forming a silicon-containing material on a substrate, ii) In order to form a fluorine-treated silicon-containing material, the silicon-containing material on the substrate is brought into contact with a fluorine-containing precursor, iii) To form a fluorine-doped silicon-nitrogen-containing material, the fluorine-treated silicon-containing material is brought into contact with diatomic nitrogen plasma emitters, iv) Repeat steps i) through iii) for at least 5 cycles. A method that includes this.

12. The semiconductor processing method according to claim 11, wherein steps i) and ii) are performed in a plasma-free manner.

13. The semiconductor processing method according to claim 11, wherein the substrate includes features characterized by an aspect ratio of approximately 3:1 or greater.

14. The semiconductor processing method according to claim 11, wherein the fluorine-doped silicon-nitrogen-containing material is characterized by conformation of about 90% or more.

15. During the semiconductor processing method described above, the temperature is maintained at approximately 550°C or below. During the semiconductor processing method, the pressure is maintained at approximately 40 Torr or less. The semiconductor processing method according to claim 11.

16. v) Annealing the substrate and the fluorine-doped silicon-nitrogen-containing material. The semiconductor processing method according to claim 11, further comprising:

17. A semiconductor processing method, Supplying one or more deposition precursors to the processing area of ​​a semiconductor processing chamber, wherein the one or more deposition precursors include a silicon-containing precursor, The substrate housed in the processing area is brought into contact with the one or more deposition precursors, A layer of silicon-containing material is thermally formed on the substrate, The process of supplying a fluorine-containing precursor to the processing region of the semiconductor processing chamber, In order to form a layer of fluorine-treated silicon-containing material, the layer of silicon-containing material on the substrate is brought into thermal contact with the fluorine-containing precursor, The process of supplying argon, diatomic nitrogen, or both to the processing area of ​​the semiconductor processing chamber, Forming plasma emitters of argon, diatomic nitrogen, or both, To form a layer of fluorine-doped silicon-containing material, the layer of fluorine-treated silicon-containing material is brought into contact with the plasma emitters of argon, diatomic nitrogen, or both. A method that includes this.

18. The semiconductor processing method according to claim 17, wherein the layer of fluorine-doped silicon-containing material is characterized by conformality of about 90% or more.

19. The semiconductor processing method according to claim 17, wherein the plasma emission of argon, diatomic nitrogen, or both is formed with a plasma output of approximately 750 W or less.

20. The layer of the fluorine-doped silicon-containing material is A dielectric constant of approximately 4.6 or less, Approximately 5.0E-08A / cm ２ The following leakage currents and The semiconductor processing method according to claim 17, characterized by the above.

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