Decoding circuit, decoding method, and computer program

Abstract

This decoding circuit is used in coherent digital signal processing, and comprises: a distributor for distributing respectively, to a plurality of lanes, a decoding metric obtained by demodulating transmission data transmitted from a transmission device, said decoding metric being distributed on the basis of a reception signal and information about noise generated in a communication channel; a first likelihood calculation circuit that is provided in one lane among the plurality of lanes, and that uses the decoding metric distributed by the distributor to calculate a first log-likelihood ratio; a decoding unit for using the first log-likelihood ratio to carry out error correction decoding, thereby obtaining an error-corrected code word; one or more second likelihood calculation circuits that are provided in a lane other than the lane in which the first likelihood calculation circuit is provided among the plurality of lanes, and that calculate a second log-likelihood ratio on the basis of the decoding metric distributed by the distributor and the obtained code word, thereby making a hard decision; a synthesis unit for combining the output from the decoding unit and the output from the one or more second log-likelihood calculation circuits; and an outer code decoding unit for decoding an outer code.　

Description

[Technical Field]

[0001] The present invention relates to a decoding circuit, a decoding method, and a computer program. [Background technology]

[0002] With the increase in internet traffic, there is a growing demand for higher capacity optical transmission systems. Therefore, research is underway to improve frequency utilization efficiency and reduce power consumption in forward error correction (FEC) used in coherent DSPs (Digital Signal Processors) in optical transmission networks. Conventionally, Bit-interleaved Coded Modulation (BICM), which can reduce the dependence on the modulation level during code application (see, for example, Non-Patent Document 1), and Multilevel coding (MLC), which efficiently reduces the computationally intensive but high-performance Soft-decision FEC (SD-FEC), have been proposed (see, for example, Non-Patent Document 2).

[0003] A technique similar to MLC, CP-MLC (Channel-polarized multilevel coding), has been proposed (see, for example, Non-Patent Documents 3 and 4). In CP-MLC, a phenomenon called channel polarization divides and heterogeneously disparates the channel into subchannels with high reliability (subchannels with high channel capacity) and subchannels with low reliability (subchannels with low channel capacity). By applying SD-FEC only to the subchannels with low channel capacity, the FEC computation amount can be reduced within the framework of binary coding, regardless of the modulation scheme. [Prior art documents] [Non-patent literature]

[0004] [Non-Patent Document 1] G. Caire et al., “Bit-Interleaved Coded Modulation”, IEEE Transactions on Information Theory, Vol.44, No 3, 927-946(1998) [Non-Patent Document 2] H. Imai and et al., “A New Multilevel Coding Method Using Error-Correcting Codes”, IEEE Transactions on Information Theory, vol IT-23, No.3, 371-377(1977) [Non-Patent Document 3] T. Kakizaki et al., “Low-complexity Channel Polarized Multilevel Coding for Modulation-format-independent Forward Error Correction”, ECOC2021, Th1G.3, (2021). [Non-Patent Document 4] T. Kakizaki et al., “Low-complexity Channel Polarized Multilevel Coding for Probabilistic Amplitude Shaping”, OFC2022, W3H.4, (2022) [Overview of the project] [Problems that the invention aims to solve]

[0005] In the CP-MLC decoding calculation circuit, there was a problem in that the computational complexity of the likelihood calculation circuits for the SD and HD calculation circuits increased exponentially with respect to the number of subchannel divisions d.

[0006] In view of the above circumstances, the present invention aims to provide a technology that can achieve high frequency utilization efficiency and reduce FEC calculation complexity regardless of the modulation level. [Means for solving the problem]

[0007] One aspect of the present invention is a decoding circuit used in coherent digital signal processing, comprising: a distributor that distributes a decoding metric obtained by demodulating transmitted data transmitted from a transmitting device based on noise information generated in the communication channel and a received signal to each of a plurality of lanes; a first likelihood calculation circuit provided in one of the plurality of lanes that calculates a first log-likelihood ratio using the decoding metric distributed by the distributor; a decoding unit that performs error correction decoding using the first log-likelihood ratio and obtains a codeword with the error corrected; one or more second likelihood calculation circuits provided in a lane different from the lane on which the first likelihood calculation circuit is provided that calculate a second log-likelihood ratio based on the decoding metric distributed by the distributor and the codeword obtained by the decoding unit and make a hard determination; a combining unit that combines the output of the decoding unit and the output of the one or more second likelihood calculation circuits; and an external code decoding unit that performs external code decoding.

[0008] One aspect of the present invention is a decoding method used in coherent digital signal processing, wherein a distributor distributes a decoding metric obtained by demodulating transmitted data transmitted from a transmitting device based on noise information generated in the communication channel and the received signal to each of a plurality of lanes; a first likelihood calculation circuit provided in one of the plurality of lanes calculates a first log-likelihood ratio using the distributed decoding metric; a decoding unit performs error correction decoding using the first log-likelihood ratio and obtains a codeword with the error corrected; one or more second likelihood calculation circuits provided in lanes different from the lane where the first likelihood calculation circuit is provided calculate one or more second log-likelihood ratios based on the decoding metric distributed by the distributor and the obtained codeword, and make a hard determination; a combining unit combines the output of the decoding unit and the output of the one or more second likelihood calculation circuits; and an external code decoding unit performs external code decoding.

[0009] One aspect of the present invention is a computer program that causes a computer to distribute a decoding metric obtained by demodulating transmitted data transmitted from a transmitting device based on noise information generated in the communication channel and the received signal to each of a plurality of lanes, calculate a first log-likelihood ratio using the distributed decoding metric, perform error correction decoding using the first log-likelihood ratio, obtain a codeword with the error corrected, calculate a second log-likelihood ratio of 1 or more based on the distributed decoding metric and the obtained codeword, perform a hard determination, synthesize the obtained results, and execute a process to decode the outer code. [Effects of the Invention]

[0010] This invention makes it possible to achieve high frequency utilization efficiency and reduce FEC calculation complexity regardless of the modulation level. [Brief explanation of the drawing]

[0011] [Figure 1] This is a block diagram showing an example configuration of a transmitting device in an embodiment. [Figure 2] This is a block diagram showing an example configuration of a receiving device in an embodiment. [Figure 3] This figure shows the numerical simulation results of the present invention and the conventional method. [Modes for carrying out the invention]

[0012] One embodiment of the present invention will be described below with reference to the drawings. Figure 1 is a block diagram showing an example configuration of the transmitting device 1 in an embodiment. The transmitting device 1 is part of a digital coherent communication system and is used to transmit data to be transmitted (hereinafter referred to as "transmitted data"). The transmitting device 1 transmits the transmitted data to a receiving device connected via a communication channel. The communication channel is, for example, an AWGN (Additive White Gaussian Noise) communication channel.

[0013] The transmission device 1 includes an encoding circuit 10, a symbol mapper 11, and a transmission unit 12. The encoding circuit 10 is composed of an outer encoder 110, a 1:d converter 120, an SD-FEC encoding unit 130, a bit conversion circuit 140, and a d:m converter 150.

[0014] The outer encoder 110 receives the data to be transmitted. The outer encoder 110 simultaneously corrects the errors that cannot be corrected by SD-FEC and all the remaining errors in the input data to be transmitted. The outer encoder 110 is one aspect of the outer encoding section.

[0015] The 1:d converter 120 divides the corrected data to be transmitted output from the outer encoder 110 into a predetermined number of divisions d (d is an integer of 2 or more). The 1:d converter 120 allocates a part of the corrected data to be transmitted (for example, d-1 data) to the first lane, and allocates the remaining corrected data to be transmitted to lanes 2 to d. Note that the 1:d converter 120 may perform interleaving as necessary to prevent burst errors caused by the inner code.

[0016] The SD-FEC encoding unit 130 is provided in the first lane and performs encoding on the corrected data to be transmitted allocated to the first lane using an error correction code.

[0017] The bit conversion circuit 140 is a conversion circuit that converts a bit sequence into another bit sequence using exclusive OR. For example, in the first lane, the bit conversion circuit 140 performs exclusive OR on a bit-by-bit basis for the data in lanes 2 to d. In lanes 2 to d, the bit conversion circuit 140 outputs the input data as it is. By combining with the receiver, errors are concentrated on the bits in the first lane, and the errors in the bits in lanes 2 to d are virtually reduced.

[0018] The d:m converter 150 converts the series data transmitted in each of the first to d lanes into series data in m lanes. m is the number of bits per symbol (bit / symbol).

[0019] The symbol mapper 11 generates the data to be transmitted by assigning the data in the m-lane sequence using gray labeling.

[0020] The transmitting unit 12 transmits the transmission data generated by the symbol mapper 11.

[0021] Figure 2 is a block diagram showing an example configuration of the receiving device 2 in an embodiment. The receiving device 2 is a transmitting device used in a digital coherent communication system. The receiving device 2 receives transmission data transmitted from the transmitting device 1, which is connected via a communication path.

[0022] The receiving device 2 comprises a receiving unit 20, a symbol demapper 21, and a decoding circuit 22.

[0023] The receiving unit 20 receives the transmission data sent from the transmitting device 1 via the communication channel.

[0024] The symbol demapper 21 demodulates the transmitted data received by the receiver 20 based on the channel information and the received signal using a demodulation method corresponding to the modulation scheme, and obtains a decoding metric. The decoding metric is, for example, the log-likelihood ratio (LLR). The channel information represents the noise distribution of the channel. The channel information can be measured using a spectrum analyzer or the like. It is assumed that the channel information has been measured in advance and is stored in the SD likelihood calculation unit 230, which will be described later.

[0025] The decoding circuit 22 consists of a distributor 220, an SD likelihood calculation unit 230, an SD-FEC decoding unit 240, a plurality of HD likelihood calculation units 250-1 to 250-(d-1), a d:1 converter 260, and an external code decoder 270.

[0026] The distributor 220 distributes the values ​​(decoded metrics) demapped by the symbol demapper 21 to all lanes from the first to the dth lane.

[0027] The SD likelihood calculation unit 230 is located in the first lane and calculates the likelihood based on the values ​​distributed by the distributor 220.

[0028] The processing of the SD likelihood calculation unit 230 in the present invention will be described in more detail. The SD likelihood calculation unit 230 calculates the log-likelihood ratio LLRλ1 based on the value obtained by demapping based on the received word y and the communication channel information P(y|x). Specifically, the SD likelihood calculation unit 230 calculates the log-likelihood ratio LLRλ1 based on the following equation 1. Calculating the log-likelihood ratio LLRλ1 using equation (1) requires only d operations.

[0029]

number

[0030] The right-hand side of equation (1) is calculated according to equation (2), based on the assumed known channel information P(y|x) and the received signal y.

[0031]

number

[0032] The operator 〇· (where · is at the center of 〇) in equation (1) is defined as in equation (3). The operator 〇· represents the operator of a function that outputs one real number from two real numbers.

[0033]

number

[0034] Equation (3) is a function that returns +1 if a > 0 and -1 if a ≤ 0.

[0035] The SD-FEC decoding unit 240 performs error correction decoding using the log-likelihood ratio LLRλ1 calculated by the SD likelihood calculation unit 230, and the error-corrected codeword z (1) Obtain it.

[0036] The plurality of HD likelihood calculation units 250-1 to 250-(d-1) directly calculate the log-likelihood ratio λ according to the following formula (4). j (i) for l j (1) , l j (2) , ···, l j (d) More specifically, the HD likelihood calculation units 250-1 to 250-(d-1) calculate the log-likelihood ratio λ for each j-th bit based on formula (4). Here, z j (i) represents the j-th bit of the corrected first-lane bit sequence in the SD-FEC decoder 240. j (1)

[0037]

Number

[0038] Subsequently, the HD likelihood calculation units 250-1 to 250-(d-1) perform hard decision based on the following formula (5).

[0039]

Number

[0040] d: The 1-to-1 converter 260 combines the information bit sequence corresponding to the codeword z transmitted in one lane and the information bit sequences corresponding to the respective codewords z output from the HD likelihood calculation units 250-1 to 250-(d-1). (1) (l)

[0041] The outer code decoder 270 performs decoding of the outer code after converting the bit sequence.

[0042] According to the receiving apparatus 2 configured as described above, by performing likelihood calculation in the log-likelihood domain in the likelihood calculation circuit of the decoding circuit, it is possible to suppress an increase in the amount of calculation with respect to the number of divisions of the calculation circuit in CP-MLC. ​​​

[0043] Figure 4 shows the numerical simulation results for the present invention and the conventional method. The numerical simulation was performed using the following parameters. (Numerical simulation parameters) Monte Carlo simulation (1000 codewords) Under AWGN (Additive white Gaussian noise) environment Encoded modulation: probabilistic amplitude shaping FEC frame length:21600 Modulation level: 16QAM Information rate: 3.29 FEC total OH: 14.82% FEC code: CP-MLC (d=4) SD-FEC redundancy 49.9%, [5400,3602]LDPC code HD-FEC: None

[0044] As shown in Figure 4, the numerical simulation results demonstrate that the present invention has performance equivalent to conventional SD and HD block calculation circuits. More specifically, the numerical simulation results show that the characteristics are almost the same whether it is a conventional circuit, the circuit of the present invention, or an approximate formula. On the other hand, while the number of calculations increases exponentially with respect to the number of divisions d in the conventional method, the present invention can perform calculations on a linear order. Therefore, the amount of computation can be reduced compared to the conventional method.

[0045] In the above-described embodiment, some of the functional components of the transmitting device 1 (e.g., the encoding circuit 10) and some of the functional components of the receiving device 2 (e.g., the decoding circuit 22) may be implemented using a computer. In that case, the program for implementing this function may be recorded on a computer-readable recording medium, and the program recorded on this recording medium may be loaded into a computer system and executed. The term "computer system" here includes hardware such as an operating system and peripheral devices.

[0046] Furthermore, "computer-readable recording media" refers to portable media such as flexible disks, magneto-optical disks, ROMs, and CD-ROMs, as well as storage devices such as hard disks built into computer systems. In addition, "computer-readable recording media" may also include those that dynamically hold programs for a short period of time, such as communication lines used when transmitting programs over networks such as the Internet or communication lines such as telephone lines, and those that hold programs for a certain period of time, such as volatile memory inside computer systems that act as servers or clients in such cases. Moreover, the above-mentioned programs may be for the purpose of realizing some of the functions described above, or they may be able to realize the above-mentioned functions in combination with programs already recorded in the computer system, or they may be realized using programmable logic devices such as FPGAs (Field Programmable Gate Arrays).

[0047] While embodiments of this invention have been described in detail above with reference to the drawings, the specific configuration is not limited to these embodiments and includes designs and the like that do not depart from the spirit of this invention. [Industrial applicability]

[0048] The present invention can be applied to communication systems using encoders and decoders. [Explanation of symbols]

[0049] 1…Transmitter, 2…Receiver, 10…Encoding circuit, 11…Symbol mapper, 12…Transmitting unit, 20…Receiver, 21…Symbol demapper, 22…Decoding circuit, 110…External encoder, 120…1:d converter, 130…SD-FEC encoding unit, 140…Bit conversion circuit, 150…d:m converter, 220…Distributor, 230…SD likelihood calculation unit, 240…SD-FEC decoding unit, 250…HD likelihood calculation unit, 260…d:1 converter, 270…External code decoder

Claims

1. A decoding circuit used in coherent digital signal processing, A distributor that distributes the decoding metric obtained by demodulating the transmitted data sent from the transmitting device based on noise information generated in the communication channel and the received signal to each of the multiple lanes, A first likelihood calculation circuit is provided in one of the multiple lanes and calculates a first log-likelihood ratio using the decoding metric distributed by the distributor. A decoding unit that performs error correction decoding using the first log-likelihood ratio and obtains a codeword with the error corrected, One or more second likelihood calculation circuits are provided in a lane different from the lane on which the first likelihood calculation circuit is provided among the plurality of lanes, and calculate a second log-likelihood ratio based on the decoding metric distributed by the distributor and the codeword obtained by the decoding unit, and make a hard determination. A combining unit that combines the output of the decoding unit and the output of the one or more second likelihood calculation circuits, An external code decoding unit that decodes the external code, Equipped with, The first log-likelihood ratio is λ ｊ （１） year, The first likelihood calculation circuit calculates the first log-likelihood ratio based on the following equation (1): The one or more second likelihood calculation circuits calculate the second log-likelihood ratio by multiplying the log-likelihood of the target lane by the result of calculating the log-likelihood of all lanes excluding the target lane, inverting the sign by the value based on the error-corrected and decoded bits, and adding it to the target lane's log-likelihood. Decoding circuit. [Math 1] Note that in equation (1), l on the right-hand side represents the log-likelihood, and the operator 〇・ (where ・ is located at the center of 〇) represents the operator of a function that outputs one real number from two real numbers.

2. Let the second log-likelihood ratio be λj(i) (where i is an integer of 1 or more), The one or more second likelihood calculation circuits calculate the second log-likelihood ratio based on the following equation (2): The decoding circuit according to claim 1. [Math 2] Note that in equation (2), l on the right-hand side represents the log-likelihood, and the operator 〇・ (where ・ is located at the center of 〇) represents the operator of a function that outputs one real number from two real numbers.

3. A decoding method used in coherent digital signal processing, The distributor distributes the decoding metric obtained by demodulating the transmitted data sent from the transmitting device, based on the noise information generated in the communication channel and the received signal, to each of the multiple lanes. A first likelihood calculation circuit provided in one of the multiple lanes calculates a first log-likelihood ratio using the allocated decoding metric. The decoding unit performs error correction decoding using the first log-likelihood ratio and obtains the error-corrected codeword. One or more second likelihood calculation circuits, provided in lanes different from the lane on which the first likelihood calculation circuit is provided, each calculate one or more second log-likelihood ratios based on the decoding metric distributed by the distributor and the acquired codeword, and make a hard determination. The combining unit combines the output of the decoding unit and the output of the one or more second likelihood calculation circuits. The external code decoding unit decodes the external code. The first log-likelihood ratio is λ ｊ （１） year, The first likelihood calculation circuit calculates the first log-likelihood ratio based on the following equation (1): The one or more second likelihood calculation circuits calculate the second log-likelihood ratio by adding the result of calculating the log-likelihood of all lanes excluding the target lane, multiplying it by a value based on the error-corrected and decoded bits, thereby inverting the sign. Decryption method. [Math 3] Note that in equation (1), l on the right-hand side represents the log-likelihood, and the operator 〇・ (where ・ is located at the center of 〇) represents the operator of a function that outputs one real number from two real numbers.

4. On the computer, Based on the noise information generated in the communication channel and the received signal, the decoding metric obtained by demodulating the transmitted data sent from the transmitting device is distributed to each of the multiple lanes. The first log-likelihood ratio is calculated using the distributed decoding metric. Error correction decoding is performed using the first log-likelihood ratio, and the error-corrected codeword is obtained. Based on the distributed decoding metric and the acquired codeword, calculate a second log-likelihood ratio of 1 or more, and perform a hard determination. The obtained results are combined, The process of decoding the outer code is executed. The first log-likelihood ratio is λ ｊ （１） year, The computer calculates the first log-likelihood ratio based on the following equation (1): A computer program for calculating the second log-likelihood ratio by multiplying the log-likelihood of the target lane by the result of calculating the log-likelihood of all lanes excluding the target lane, inverting the sign by the value based on the error-corrected and decoded bits, and adding it to the log-likelihood of the target lane. 【Number 4】 Note that in equation (1), l on the right-hand side represents the log-likelihood, and the operator 〇・ (where ・ is located at the center of 〇) represents the operator of a function that outputs one real number from two real numbers.

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