Chip system, virtual interrupt handling method, and corresponding device

Abstract

To provide a chip system, a method for processing virtual interrupt and a corresponding device.SOLUTION: A chip system includes a source physical processor, a control apparatus, an intermediate apparatus, a sending apparatus, and a target physical processor. A virtual environment is created on the system. A host machine or a virtual machine runs on the source physical processor. The host machine or virtual machine writes information used to trigger virtual interrupt to a register in the control apparatus, and the control apparatus receives it. The intermediate apparatus triggers the virtual interrupt based on the information when the control apparatus sends the information to the intermediate apparatus, and sends the virtual interrupt to the sending apparatus. The sending apparatus sends the virtual interrupt to the target physical processor. This solution is used to reduce overheads of switching from the virtual machine to the host machine or from a user mode of the host machine to a kernel mode of the host machine that are generated due to the virtual interrupt.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] This application relates to the field of virtualization technology, and more specifically to a chip system, a virtual interrupt processing method, and a corresponding device.

Background Art

[0002] Virtual interrupt is an essential part of virtualization technology. A virtual machine (VM) runs on a computer device. Notifications sent to the virtual machine by hardware devices such as disks or input / output (I / O) devices within the computer device, as well as various types of synchronization and coordination within the virtual machine, rely on virtual interrupts. A virtual interrupt is an event. Such events can have various sources, and the processing process for the event varies depending on the source. However, such events from each source are notified to the virtual machine in the form of interrupts received during the execution of the virtual machine.

[0003] Regardless of the source of the virtual interrupt, before the virtual interrupt finally reaches the virtual machine, the host machine needs to use various mechanisms of the host machine to complete the transmission of the virtual interrupt from the source to the target virtual machine. In a certain process of transmitting a virtual interrupt, the control flow of the processor needs to be switched from the running virtual machine to the host machine, or from the user mode of the host machine to the kernel mode of the host machine. This causes a relatively large switching overhead.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention provide a chip system, a virtual interrupt handling method, and a corresponding device for reducing switching overhead caused by virtual interrupts when switching from a virtual machine to a host machine, or from the user mode of a host machine to the kernel mode of a host machine. Embodiments of the present invention further provide corresponding computer devices, computer storage media, computer program products, and the like. [Means for solving the problem]

[0005] A first aspect of the present application provides a chip system. The chip system includes a source physical processor, a control unit, an intermediate unit, a transmitter, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The control unit includes a register. The register is configured to receive information used to trigger a virtual interrupt. The information used to trigger a virtual interrupt may come from a host machine or a virtual machine. The control unit is configured to receive the information used to trigger the virtual interrupt and send it to the intermediate unit. The intermediate unit is configured to trigger a virtual interrupt based on the information used to trigger the virtual interrupt and send the virtual interrupt to the transmitter. The transmitter is configured to receive the virtual interrupt from the intermediate unit and send the virtual interrupt to the target physical processor.

[0006] In this application, the chip system may be a system on a chip (SOC), and the source physical processor and target physical processor may each be a processing unit, such as a physical core. The control device, intermediate device, and transmitter may all be implemented using hardware circuits or using software. The source physical processor and target physical processor may be physical cores in a multicore processor. A multicore processor includes multiple physical cores. A physical core is a core integrated in a processor. A physical core is a processing unit. For example, a dual-core processor can be understood as a processor with two physical cores. The control device and transmitter may be deployed in a multicore processor and coupled to the source physical processor and target physical processor. The intermediate device may be deployed in a multicore processor or on peripheral devices / components coupled to the multicore processor. The system on a chip may include a multicore processor and peripheral devices / components coupled to the multicore processor. Any physical processor in the chip system may be used as a source physical processor or as a target physical processor.

[0007] In this application, a virtual interrupt is an interrupt sent to a virtual machine (VM) by a computer device, host machine, virtual machine clock, virtual processor of the virtual machine, etc. Hardware devices that generate virtual interrupts may include disks, network adapters, audio adapters, mice, hard disks, etc., within the computer device. A physical interrupt is an interrupt sent to a physical processor by a hardware device. Physical interrupts are processed by the host machine, while virtual interrupts are processed by the virtual machine.

[0008] It should be noted that the specific implementation of the virtual processor referred to in the embodiments of this application may be a virtual central processing unit (vCPU). The term "vCPU" below can be replaced with "virtual processor" for clarity.

[0009] In this application, virtual interrupts may include virtual local interrupts, virtual software interrupts, virtual device interrupts, and direct peripheral interrupts. A virtual local interrupt refers to an interrupt sent by a virtual local device simulated by a virtual machine, or by a local device of the virtual machine's vCPU, for example, a clock interrupt sent by a timer of the virtual machine's vCPU. A virtual software interrupt is a software-triggered interrupt that is generally sent by one vCPU of a virtual machine to another vCPU of the virtual machine. A virtual machine may have multiple vCPUs, which may be running on different physical processors at any given moment to perform different tasks of the virtual machine. A virtual software interrupt occurs when tasks performed by different vCPUs are interdependent or need to be scheduled. A virtual device interrupt refers to an interrupt triggered by a host machine simulating a hardware device, for example, an interrupt generated by a host machine simulating a virtual machine disk controller or another hardware device.

[0010] In this application, the control device may include at least one register, each of which may be configured to receive one type of information used to trigger a virtual interrupt. For example, it may include three registers, one of which may be configured to receive information used to trigger a virtual local interrupt, one of which may be configured to receive information used to trigger a virtual software interrupt, and one of which may be configured to receive information used to trigger a virtual device interrupt. Of course, the control device may have only one register configured for virtual interrupts, and the information used to trigger each type of virtual interrupt may differ. The type of virtual interrupt may be identified using the information received by the register.

[0011] There may be one or more intermediate devices. Each physical processor may have its own transmitter, or multiple physical processors may share a single transmitter.

[0012] From the first aspect, it can be seen that a register dedicated to handling virtual interrupts is located in the control unit. Thus, a host machine or virtual machine in user mode or kernel mode can directly write the information used to trigger a virtual interrupt to the register. The control unit may also send the information used to trigger a virtual interrupt to an intermediate unit, which then triggers the virtual interrupt. The intermediate unit may also send the virtual interrupt to a transmitter, which then sends the virtual interrupt to the target physical processor. In the solution provided herein, the host machine or virtual machine may directly access the register and write the information used to trigger a virtual interrupt to the register so that the virtual interrupt is sent. Therefore, compared to the prior art, the solution provided herein eliminates the need for the source physical processor to switch from the virtual machine to the host machine, and the need for the source physical processor to switch from the host machine's user mode to the host machine's kernel mode, thereby reducing the switching overhead that occurs during virtual interrupt processing and improving the performance of the chip system.

[0013] In one possible implementation of the first aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the registers are configured to receive information written by the virtual machine and used to trigger the virtual local interrupt. The transmitter is configured to send the virtual local interrupt to the first virtual processor vCPU of the virtual machine, where the first vCPU runs on the source physical processor.

[0014] In this possible implementation, since the virtual local interrupt is an in-core interrupt, the target physical processor and the source physical processor are the same physical processor. The intermediate device may be a timer, and the virtual local interrupt may be a clock interrupt. A single physical processor can run only one vCPU of a single virtual machine at any given moment, and the operation of sending a virtual local interrupt to the virtual machine can be completed by sending the virtual local interrupt to the vCPU. From this possible implementation, it can be seen that in the process of handling virtual local interrupts, the source physical processor does not need to switch from the virtual machine to the host machine, thus reducing the switching overhead that occurs during the handling of virtual local interrupts and improving the performance of the chip system.

[0015] In one possible implementation of the first aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of a second vCPU written to a register by the first vCPU of the virtual machine, where the second vCPU is the vCPU of the virtual machine running on the target physical processor. The control unit is configured to: read the identifier of the second vCPU from the register, obtain the identifier of the virtual machine; and send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate unit. The intermediate unit is configured to: determine the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from the first correspondence based on the identifier of the virtual machine and the identifier of the second vCPU, wherein the first correspondence is used to record the correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; and send the virtual software interrupt to the transmitter corresponding to the target physical processor. The transmitter is configured to send the virtual software interrupt to the second vCPU running on the target physical processor.

[0016] In this possible implementation, a virtual software interrupt is an interrupt sent by the first vCPU of a virtual machine to its second vCPU. Therefore, if the first vCPU of a virtual machine needs to trigger a virtual software interrupt, it must write the identifier of the second vCPU to a register. A single virtual machine can have multiple vCPUs, and vCPUs belonging to a single virtual machine can operate in a time-division multiplexing scheme on a single physical processor. For example, vCPU1 of virtual machine 1 may first operate on physical processor 1, and after physical processor 1 has finished operating vCPU 1, vCPU 2 of virtual machine 1 may start operating. Also, multiple vCPUs belonging to a single virtual machine may operate on different physical processors, and different vCPUs may operate on different physical processors simultaneously. For example, vCPU1 of virtual machine 1 may operate on physical processor 1, and vCPU2 of virtual machine 1 may operate on physical processor 2. In the virtual software interrupt scenario, the first vCPU operates on the source physical processor, and the second vCPU operates on the target physical processor. The control unit may obtain the virtual machine identifier from a dedicated register that stores the identifier of the virtual machine operating on the source physical processor. Each virtual machine can have multiple vCPUs, and the vCPU identifiers of different virtual machines may be the same. Therefore, the control unit needs to send the virtual machine identifier and the identifier of the second vCPU to the intermediate device. The intermediate device may store the first correspondence. The first correspondence may be located in the inposition vCPU identifier group. The inposition vCPU identifier group records the correspondence between each physical processor in the chip system, the vCPUs operating on each physical processor, and the virtual machine to which the operating vCPU belongs. In this application, the physical processor can be determined by looking up the inposition vCPU identifier group. From this possible implementation, it can be seen that the process of handling virtual software interrupts does not need to switch the source physical processor from the virtual machine to the host machine, thus reducing the switching overhead that occurs during the handling of virtual software interrupts and improving the performance of the chip system.

[0017] In a possible implementation of the first aspect, the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes a target interrupt number and a virtual machine identifier, which are written to a register by the host machine. Here, the target interrupt number is the identifier of the interrupt that is triggered when the host machine simulates a hardware device. The control unit is configured to read the target interrupt number and the virtual machine identifier from the register and send the virtual machine identifier and the target interrupt number to an intermediate unit. The intermediate unit is configured to perform the following steps: a step of searching for a second correspondence, which is used to record the correspondence between the virtual machine, the target interrupt number and the first vCPU, by determining from a third correspondence, which is used to record the correspondence between the virtual machine, the target interrupt number and the first vCPU, by which the virtual machine identifier and the first vCPU identifier are found; a step of determining the target physical processor, which is used to record the correspondence between the target physical processor and the first vCPU operating on the target processor and the virtual machine; and a step of sending the virtual device interrupt to a transmitter corresponding to the target physical processor. The transmitter is configured to send virtual device interrupts to the first vCPU running on the target physical processor.

[0018] In this possible implementation, a virtual device interrupt is an interrupt triggered by a hardware device simulated by the host machine in user mode when simulating a hardware device. There may be multiple types of hardware devices, and each type of hardware device has a different interrupt number. If the host machine simulates a disk, the target interrupt number is the disk's interrupt number. Since the host machine may manage multiple virtual machines, the host machine needs to write the virtual machine identifier and target interrupt number to a register. A second correspondence may reside in an interrupt affinity table. The interrupt affinity table may be composed of virtual machines. Therefore, there is an interrupt affinity table for each virtual machine. Thus, the interrupt affinity table of a virtual machine may be found based on the virtual machine identifier, and the corresponding vCPU is determined from the virtual machine's interrupt affinity table based on the target interrupt number. The target interrupt number is 10. If interrupt number 10 in the interrupt affinity table corresponds to vCPU ID 1, then it can be determined that the vCPU ID corresponding to that target interrupt number is 1. After determining that the vCPU ID is 1, the routing device may find the physical processor corresponding to vCPU ID 1 based on the imposition vCPU identifier group. For the meaning of the imposition vCPU identifier group, please refer to the explanation of virtual software interrupts. For the third correspondence, please refer to the first correspondence for understanding. From this possible implementation, it can be seen that in a process handling virtual device interrupts, the source physical processor does not need to switch from the host machine's user mode to the host machine's kernel mode, thereby reducing the switching overhead that occurs during the handling of virtual device interrupts and improving the performance of the chip system.

[0019] In a possible implementation of the first aspect, the intermediate device includes an address register, which is configured to store the address of the second correspondence in memory and the identifier of the virtual machine. The intermediate device is further configured to: look up the address register based on the identifier of the virtual machine and retrieve the second correspondence from memory based on the address in the address register.

[0020] In this possible implementation, the interrupt affinity table may be stored in an intermediate device or in memory. The intermediate device may provide an address register for each physical processor. The address register may be a base address register, which may store the address of the interrupt affinity table in memory and the identifier of the virtual machine. This avoids the intermediate device occupying excessive storage space.

[0021] In one possible implementation of the first aspect, the transmitter is configured to write a virtual interrupt to the pending register of the target physical processor, and the pending register is configured to receive commands for a procedure to be performed by the target physical processor.

[0022] In this possible implementation, the pending register is configured to receive commands to be subsequently executed by the target physical processor and write virtual interrupts to the pending register so that the target physical processor then executes virtual interrupts. In this way, the currently running process is interrupted, thereby blocking the host machine switch action in existing solutions. This reduces the overhead of switching the target physical processor from the virtual machine to the host machine.

[0023] A second aspect of the present application provides a chip system, which includes a source physical processor, a control unit, an intermediate unit, a transmitter, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The chip system further includes hardware devices for direct communication between the virtual machines. The intermediate device is configured to perform the following steps: receive a direct peripheral interrupt triggered by a hardware device; look up a virtual interrupt table for the corresponding virtual machine identifier and virtual interrupt number based on the physical interrupt number of the direct peripheral interrupt, wherein the virtual interrupt table records the correspondence between the physical interrupt number, the virtual machine identifier, and the virtual interrupt number; determine the corresponding interrupt affinity table based on the virtual machine identifier, and from the interrupt affinity table determine the virtual machine identifier and the identifier of the target virtual processor vCPU corresponding to the virtual interrupt number, wherein the interrupt affinity table records the correspondence between the virtual interrupt number and the virtual processor; determine the target physical processor corresponding to the target vCPU identifier from the imposition vCPU identifier group based on the target vCPU identifier; and transmit the direct peripheral interrupt to a transmitter corresponding to the target physical processor. The transmitter transmits the direct peripheral interrupt to a virtual machine running on the target physical processor.

[0024] In the second aspect, direct peripheral interrupts refer to interrupts triggered by peripheral devices directly connected to a virtual machine, such as interrupts generated by a graphics card directly connected to the virtual machine. The process for handling direct peripheral interrupts uses, in order, a virtual interrupt table, an interrupt affinity table, and an imposition vCPU identifier group. For an understanding of the interrupt affinity table and the imposition vCPU identifier group, see the explanation in the possible implementations of the first aspect. The virtual interrupt table is described below. The virtual interrupt table maintains a mapping relationship between physical interrupt numbers, virtual machine identifiers, and virtual interrupt numbers. When a physical interrupt number is input, the virtual machine identifier and virtual interrupt number can be output. In the process for handling direct peripheral interrupts, the intermediate device receives the physical interrupt number transmitted by the direct peripheral device and searches the virtual interrupt table for the corresponding virtual machine identifier and virtual interrupt number based on the physical interrupt number. For example, when physical interrupt number 100 is input, virtual machine identifier 1 and virtual interrupt number 10 may be output. Next, based on the virtual machine identifier 1 and virtual interrupt number 10, the interrupt affinity table is searched to find the corresponding vCPU ID. For example, it is found that the vCPU ID is 1. Furthermore, based on the vCPU ID, the imposition vCPU identifier group is searched to find the corresponding physical processor. For example, if physical processor 1 is found, the intermediate device may send a peripheral interrupt directly to the transmitter corresponding to physical processor 1, and the transmitter sends a peripheral interrupt directly to the vCPU corresponding to vCPU ID 1.

[0025] In the process for handling direct peripheral interrupts provided in the second aspect, the transmission process can be completed by searching for three correspondences, thereby improving the flexibility of handling direct peripheral interrupts.

[0026] A third aspect of the present application provides a control device. The control device is applied to a chip system. The chip system further includes a source physical processor, an intermediate device, and a transmission device. The source physical processor is configured to execute a host machine or a virtual machine. The control device includes a register. The register is configured to receive information used to trigger a virtual interrupt. The information used to trigger the virtual interrupt comes from a host machine or a virtual machine. The control device is configured to: read the information used to trigger the virtual interrupt from the register and transmit the information used to trigger the virtual interrupt to the intermediate device. The information used to trigger the virtual interrupt is used to enable the intermediate device to trigger the virtual interrupt, and the virtual interrupt is transmitted by the transmission device to a target physical processor.

[0027] In a possible implementation of the third aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, the register is written by the virtual machine, and is configured to receive information used to trigger the virtual local interrupt. The control device is configured to: transmit the information used to trigger the virtual local interrupt to the intermediate device. The information used to trigger the virtual local interrupt is used to enable the intermediate device to trigger the virtual local interrupt, and the virtual local interrupt is transmitted by the transmission device to the first virtual processor vCPU of the virtual machine, and the first vCPU operates on the source physical processor.

[0028] In a possible implementation of the third aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of the second vCPU written to the register by the first vCPU of the virtual machine, and the second vCPU is the vCPU of the virtual machine operating on the target physical processor. The control device is configured to read the identifier of the second vCPU from the register, obtain the identifier of the virtual machine; and transmit the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device. The identifier of the virtual machine and the identifier of the second vCPU are used by the intermediate device to determine the target physical processor and trigger a virtual software interrupt. The virtual software interrupt is transmitted by the transmitting device to the second vCPU of the target physical processor.

[0029] In a possible implementation of the third aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes the target interrupt number written to the register by the host machine and the identifier of the virtual machine, and the target interrupt number is the identifier of the interrupt triggered when the host machine simulates a hardware device. The control device is configured to read the target interrupt number and the identifier of the virtual machine from the register, and transmit the target interrupt number and the identifier of the virtual machine to the intermediate device. The identifier of the virtual machine and the target interrupt number are used by the intermediate device to determine the target physical processor and trigger a virtual device interrupt, and the virtual device interrupt is transmitted by the transmitting device to the first vCPU of the target physical processor.

[0030] A fourth aspect of the present application provides an intermediate device. The intermediate device is applied to a chip system. The chip system further includes a source physical processor, a control unit, a transmitter, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The control unit includes registers. The registers are configured to receive information used to trigger a virtual interrupt. The information used to trigger the virtual interrupt comes from the host machine or a virtual machine. The intermediate device is configured to receive the information used to trigger the virtual interrupt from the control unit, trigger the virtual interrupt based on the information used to trigger the virtual interrupt, and send the virtual interrupt to the transmitter. The virtual interrupt is sent by the transmitter to the target physical processor.

[0031] In a possible implementation of the fourth aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and source physical processor are the same physical processor, and the register is configured to receive information written by the virtual machine and used to trigger the virtual local interrupt. The intermediate device is configured to trigger the virtual local interrupt based on the information used to trigger the virtual local interrupt and to send the virtual local interrupt to the transmitter. The virtual local interrupt is sent by the transmitter to the first virtual processor vCPU of the virtual machine, the first vCPU operating on the source physical processor.

[0032] In a possible implementation of the fourth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of a second vCPU written to a register by the first vCPU of the virtual machine, where the second vCPU is the vCPU of the virtual machine running on the target physical processor. The intermediate device is configured to perform the following steps: receiving the identifier of the virtual machine and the identifier of the second vCPU from the control device; determining the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from the first correspondence, based on the identifier of the virtual machine and the identifier of the second vCPU, where the first correspondence is used to record the correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; triggering a virtual software interrupt; and sending the virtual software interrupt to a transmitter corresponding to the target physical processor. The virtual software interrupt is sent by the transmitter to the second vCPU of the target physical processor.

[0033] In a possible implementation of the fourth aspect, the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes a target interrupt number and a virtual machine identifier, which are written to registers by the host machine. The target interrupt number is the identifier of the interrupt that is triggered when the host machine simulates a hardware device. The intermediate device is configured to perform the following steps: receiving the virtual machine identifier and the target interrupt number from the control device; searching for a second correspondence by determining the identifier of the first vCPU of the virtual machine corresponding to the virtual machine identifier and the target interrupt number, based on the virtual machine identifier and the target interrupt number, the second correspondence being used to record the correspondence between the virtual machine, the target interrupt number and the first vCPU; determining the target physical processor corresponding to the virtual machine identifier and the first vCPU identifier from a third correspondence, based on the virtual machine identifier and the first vCPU identifier, the third correspondence being used to record the correspondence between the target physical processor, the first vCPU running on the target processor and the virtual machine; triggering a virtual device interrupt; and sending the virtual device interrupt to a transmitter corresponding to the target physical processor. The virtual device interrupt is sent by the transmitter to the first vCPU of the target physical processor.

[0034] In a possible implementation of the fourth aspect, the intermediate device includes an address register, which is configured to store the address of the second correspondence in memory and the identifier of the virtual machine. The intermediate device is further configured to: look up the address register based on the identifier of the virtual machine and retrieve the second correspondence from memory based on the address in the address register.

[0035] A fifth aspect of the present application provides a transmitter. The transmitter is applied to a chip system. The chip system further includes a source physical processor, an intermediate device, a target physical processor, and a control unit. The source physical processor is configured to run a host machine or a virtual machine. The control unit includes registers. The registers are configured to receive information used to trigger a virtual interrupt. The information used to trigger the virtual interrupt comes from the host machine or a virtual machine. The transmitter is configured to receive a virtual interrupt from the intermediate device and transmit the virtual interrupt to the target physical processor.

[0036] In a possible implementation of the fifth aspect, the virtual interrupt is a virtual local interrupt, and the target physical processor and source physical processor are the same physical processor. The transmitter is configured to receive the virtual local interrupt from the intermediate device and send the virtual local interrupt to the first virtual processor vCPU of the virtual machine. The first vCPU operates on the source physical processor.

[0037] In a possible implementation of the fifth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier for a second vCPU written to a register by the first vCPU of the virtual machine, where the second vCPU is the vCPU of the virtual machine running on the target physical processor. The transmitter is configured to receive the virtual software interrupt from the intermediate device and send the virtual software interrupt to the second vCPU running on the target physical processor.

[0038] In a possible implementation of the fifth aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes a target interrupt number, which is written to a register by the host machine, and a virtual machine identifier, where the target interrupt number is the identifier of the interrupt that is triggered when the host machine simulates a hardware device. The transmitter is configured to receive the virtual device interrupt from the intermediate device and send the virtual device interrupt to a first vCPU operating on the target physical processor.

[0039] In a possible implementation of the fifth aspect, the transmitter is configured to write a virtual interrupt to a pending register of the target physical processor, which is configured to receive commands for a procedure to be performed by the target physical processor.

[0040] For understanding the matters described in Aspects 3 through 5, and the possible implementations of any of Aspects 3 through 5, and their corresponding intended effects, please refer to the descriptions in Aspect 1 and the possible implementations of any of Aspects 1. Further details will not be explained again here.

[0041] A sixth aspect of the present application provides a virtual interrupt handling method. This method is applied to a control unit of a chip system. The chip system further includes a source physical processor, an intermediate unit, a transmitter, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The control unit includes registers. The registers are configured to receive information used to trigger a virtual interrupt. The information used to trigger a virtual interrupt comes from the host machine or a virtual machine. This method includes: reading the information used to trigger a virtual interrupt from the registers and sending the information used to trigger a virtual interrupt to the intermediate unit. The information used to trigger a virtual interrupt is used to enable the intermediate unit to trigger a virtual interrupt, which is then sent to the target physical processor by the transmitter.

[0042] In a possible implementation of the sixth aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is written by the virtual machine and configured to receive information used to trigger the virtual local interrupt. The information used to trigger the virtual local interrupt is used so that an intermediate device can trigger the virtual local interrupt, which is sent by a transmitter to the first virtual processor vCPU of the virtual machine, the first vCPU operating on the source physical processor.

[0043] In a possible implementation of the sixth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of a second vCPU written to a register by the first vCPU of the virtual machine, where the second vCPU is the vCPU of the virtual machine running on the target physical processor. This method further includes: the step of obtaining the identifier of the virtual machine; and the step of sending the identifier of the virtual machine and the identifier of the second vCPU to an intermediate device. The identifier of the virtual machine and the identifier of the second vCPU are used by the intermediate device to determine the target physical processor and trigger the virtual software interrupt. The virtual software interrupt is sent by the transmitter to the second vCPU of the target physical processor.

[0044] In a possible implementation of the sixth aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes a target interrupt number, which is written to a register by the host machine, and a virtual machine identifier, the target interrupt number being the identifier of the interrupt that is triggered when the host machine simulates a hardware device. The virtual machine identifier and target interrupt number are used by the intermediate device to determine the target physical processor and trigger the virtual device interrupt, which is then sent by the transmitter to the first vCPU of the target physical processor.

[0045] A seventh aspect of the present application provides a virtual interrupt handling method. This method is applied to an intermediate device of a chip system. The chip system further includes a source physical processor, a control unit, a transmitter, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The control unit includes registers. The registers are configured to receive information used to trigger a virtual interrupt. The information used to trigger a virtual interrupt comes from the host machine or a virtual machine. The method includes receiving the information used to trigger a virtual interrupt from the control unit; triggering a virtual interrupt based on the information used to trigger a virtual interrupt; and sending the virtual interrupt to the transmitter. The virtual interrupt is sent by the transmitter to the target physical processor.

[0046] In a possible implementation of the seventh aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the registers are configured to receive information written by the virtual machine and used to trigger the virtual local interrupt. The information used to trigger the virtual local interrupt is used to trigger the virtual local interrupt, which is sent by the transmitter to the first virtual processor vCPU of the virtual machine, the first vCPU operating on the source physical processor.

[0047] In a possible implementation of the seventh aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of a second vCPU written to a register by the first vCPU of the virtual machine, where the second vCPU is the vCPU of the virtual machine running on the target physical processor. The above steps for triggering the virtual interrupt based on the information used to trigger the virtual interrupt include: a step of determining the target physical processor corresponding to the virtual machine identifier and the second vCPU identifier from a first correspondence based on the virtual machine identifier and the identifier of the second vCPU, where the first correspondence is used to record the correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; and a step of triggering the virtual software interrupt. The virtual software interrupt is sent by a transmitter to the second vCPU of the target physical processor.

[0048] In a possible implementation of the seventh aspect, the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes a target interrupt number and a virtual machine identifier, which are written to registers by the host machine, the target interrupt number being the identifier of the interrupt that is triggered when the host machine simulates a hardware device. The steps above for triggering a virtual interrupt based on the information used to trigger the virtual interrupt include: a step of searching for a second correspondence, which is used to record the correspondence between the virtual machine, the target interrupt number, and the first vCPU, based on the virtual machine identifier and the target interrupt number; a step of determining the target physical processor, which is used to record the correspondence between the virtual machine identifier and the first vCPU identifier, from a third correspondence, based on the virtual machine identifier and the first vCPU identifier; and a step of triggering a virtual device interrupt. The virtual device interrupt is sent by a transmitter to the first vCPU of the target physical processor.

[0049] In a possible implementation of the seventh aspect, this method further comprises: locating an address register based on the virtual machine identifier, and retrieving the aforementioned second correspondence from memory based on the address in the address register, wherein the address register is configured to store the address of the aforementioned second correspondence in memory and the virtual machine identifier.

[0050] An eighth aspect of the present application provides a virtual interrupt handling method. This method is applied to a transmitter of a chip system. The chip system further includes a source physical processor, an intermediate device, a control device, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The control device includes registers. The registers are configured to receive information used to trigger a virtual interrupt. The information used to trigger a virtual interrupt comes from the host machine or a virtual machine. This method includes receiving a virtual interrupt from an intermediate device and transmitting the virtual interrupt to a target physical processor.

[0051] In one possible implementation of the eighth aspect, the virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor. The above steps for sending the virtual interrupt to the target physical processor include: sending the virtual local interrupt to the first virtual processor vCPU of the virtual machine, which operates on the source physical processor.

[0052] In a possible implementation of the eighth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier for a second vCPU written to a register by the first vCPU of the virtual machine, where the second vCPU is the vCPU of the virtual machine running on the target physical processor. The above steps for sending the virtual interrupt to the target physical processor include: sending the virtual software interrupt to the second vCPU running on the target physical processor.

[0053] In a possible implementation of the eighth aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes a target interrupt number, which is written to a register by the host machine, and a virtual machine identifier, where the target interrupt number is the identifier of the interrupt that is triggered when the host machine simulates a hardware device. The above step of sending the virtual interrupt to the target physical processor involves sending the virtual device interrupt to the first vCPU operating on the target physical processor.

[0054] In a possible implementation of the eighth aspect, this method further involves: writing a virtual interrupt to the target physical processor's pending register, which is configured to receive commands for the procedure to be performed by the target physical processor.

[0055] For understanding the matters described in Aspects 6 through 8, and the possible implementations of any of Aspects 6 through 8, and their corresponding intended effects, please refer to the descriptions in Aspect 1 and the possible implementations of any of Aspects 1. Further details will not be provided again here.

[0056] A ninth aspect of the present application provides a control device. The control device is applied to a chip system. The chip system further includes a source physical processor, an intermediate device, a transmitter, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The control device includes registers. The registers are configured to receive information used to trigger a virtual interrupt. The information used to trigger a virtual interrupt comes from the host machine or a virtual machine. The control device includes a read unit configured to read the information used to trigger a virtual interrupt from the registers; and a transmit unit configured to send the information used to trigger a virtual interrupt to an intermediate device. The information used to trigger a virtual interrupt is used by the intermediate device to trigger a virtual interrupt, and the virtual interrupt is sent by the transmitter to the target physical processor.

[0057] In one possible implementation of the ninth aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is written by the virtual machine and configured to receive information used to trigger the virtual local interrupt. The information used to trigger the virtual local interrupt is used so that an intermediate device can trigger the virtual local interrupt, which is sent by a transmitter to the first virtual processor vCPU of the virtual machine, the first vCPU operating on the source physical processor.

[0058] In a possible implementation of the ninth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of a second vCPU written to a register by the first vCPU of the virtual machine, where the second vCPU is the vCPU of the virtual machine running on the target physical processor. This control unit further includes: a processing unit configured to obtain the identifier of the virtual machine; and a transmitting unit configured to send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device. The identifier of the virtual machine and the identifier of the second vCPU are used by the intermediate device to determine the target physical processor and trigger the virtual software interrupt. The virtual software interrupt is sent by the transmitting device to the second vCPU of the target physical processor.

[0059] In a possible implementation of the ninth aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes a target interrupt number, which is written to a register by the host machine, and a virtual machine identifier, the target interrupt number being the identifier of the interrupt that is triggered when the host machine simulates a hardware device. The virtual machine identifier and target interrupt number are used by the intermediate device to determine the target physical processor and trigger the virtual device interrupt, which is then sent by the transmitter to the first vCPU of the target physical processor.

[0060] A tenth aspect of the present application provides an intermediate device, which is applied to a chip system. The chip system further includes a source physical processor, a control unit, a transmitter, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The control unit includes registers, which are configured to receive information used to trigger a virtual interrupt. The information used to trigger the virtual interrupt comes from the host machine or a virtual machine. The intermediate device includes a receiving unit configured to receive information used to trigger the virtual interrupt from the control unit; a processing unit configured to trigger the virtual interrupt based on the information used to trigger the virtual interrupt; and a transmitting unit configured to send the virtual interrupt to a transmitter. The virtual interrupt is sent to the target physical processor by the transmitter.

[0061] In a possible implementation of the tenth aspect, the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the registers are configured to receive information written by the virtual machine and used to trigger the virtual local interrupt. The information used to trigger the virtual local interrupt is used to trigger the virtual local interrupt, which is sent by the transmitter to the first virtual processor vCPU of the virtual machine, the first vCPU operating on the source physical processor.

[0062] In a possible implementation of the tenth aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes the identifier of a second vCPU written to a register by the first vCPU of the virtual machine, the second vCPU being the vCPU of the virtual machine running on the target physical processor. The processing unit is configured to perform the following steps: a step of determining the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU from a first correspondence based on the identifier of the virtual machine and the identifier of the second vCPU, the first correspondence being used to record the correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; and a step of triggering a virtual software interrupt. The virtual software interrupt is transmitted by a transmitter to the second vCPU of the target physical processor.

[0063] In a possible implementation of the tenth aspect, the virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes a target interrupt number and a virtual machine identifier, which are written to a register by the host machine, the target interrupt number being the identifier of the interrupt that is triggered when the host machine simulates a hardware device. The processing unit is configured to perform: a step of searching for a second correspondence, which is used to record the correspondence between the virtual machine, the target interrupt number, and the first vCPU, based on the virtual machine identifier and the target interrupt number; a step of determining the target physical processor, which is used to record the correspondence between the virtual machine identifier and the first vCPU identifier, from a third correspondence, based on the virtual machine identifier and the first vCPU identifier, the third correspondence being used to record the correspondence between the target physical processor, the first vCPU running on the target processor, and the virtual machine; and a step of triggering a virtual device interrupt. The virtual device interrupt is sent by a transmitter to the first vCPU of the target physical processor.

[0064] In a possible implementation of the tenth aspect, the processing unit is further configured to: locate an address register based on the identifier of a virtual machine, and retrieve the second correspondence from memory based on the address in the address register, the address register being configured to store the address of the second correspondence in memory and the identifier of a virtual machine.

[0065] An eleventh aspect of the present application provides a transmitter. The transmitter is applied to a chip system, which further includes a source physical processor, an intermediate device, a control unit, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The control unit includes registers, which are configured to receive information used to trigger virtual interrupts, which come from a host machine or a virtual machine. The transmitter includes a receiving unit configured to receive virtual interrupts from an intermediate device and a transmitting unit configured to transmit virtual interrupts to a target physical processor.

[0066] In one possible implementation of the eleventh aspect, the virtual interrupt is a virtual local interrupt, and the target physical processor and source physical processor are the same physical processor. The send unit is configured to send the virtual local interrupt to the first virtual processor vCPU of the virtual machine, which operates on the source physical processor.

[0067] In a possible implementation of the eleventh aspect, the virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier for a second vCPU written to a register by the first vCPU of the virtual machine, the second vCPU being the vCPU of the virtual machine running on the target physical processor. The transmit unit is configured to send the virtual software interrupt to the second vCPU running on the target physical processor.

[0068] In a possible implementation of the eleventh aspect, the virtual interrupt is a virtual device interrupt. The information used to trigger the virtual interrupt includes a target interrupt number, which is written to a register by the host machine, and a virtual machine identifier, where the target interrupt number is the identifier of the interrupt that is triggered when the host machine simulates a hardware device. The transmit unit is configured to send the virtual device interrupt to a first vCPU running on the target physical processor.

[0069] In a possible implementation of the eleventh aspect, the transmitting unit is further configured to write a virtual interrupt to a pending register of the target physical processor, which is configured to receive commands for a procedure to be performed by the target physical processor.

[0070] For understanding the matters described in Aspects 9 through 11, and the possible implementations of any of Aspects 9 through 11, and their corresponding intended effects, please refer to the descriptions in Aspect 1 and the possible implementations of any of Aspects 1. Further details will not be provided again here.

[0071] A twelfth aspect of the present application provides a computer-readable storage medium for storing one or more computer-executable instructions. When a computer-executable instruction is executed by a processor, the processor performs a method according to the sixth aspect or a possible implementation of the sixth aspect.

[0072] A thirteenth aspect of the present application provides a computer-readable storage medium for storing one or more computer-executable instructions. When a computer-executable instruction is executed by a processor, the processor performs a method according to the seventh aspect or a possible implementation of the seventh aspect.

[0073] A fourteenth aspect of the present application provides a computer-readable storage medium for storing one or more computer-executable instructions. When a computer-executable instruction is executed by a processor, the processor performs a method according to the eighth aspect or a possible implementation of the eighth aspect.

[0074] A fifteenth aspect of the present application provides a computer program product that stores one or more computer executable instructions. When the computer executable instructions are executed by a processor, the processor performs a method according to the sixth aspect or a possible implementation of the sixth aspect.

[0075] A sixteenth aspect of the present application provides a computer program product that stores one or more computer executable instructions. When the computer executable instructions are executed by a processor, the processor performs a method according to the seventh aspect or a possible implementation of the seventh aspect.

[0076] A 17th aspect of the present application provides a computer program product that stores one or more computer executable instructions. When the computer executable instructions are executed by a processor, the processor performs a method according to the 8th aspect or a possible implementation of the 8th aspect.

[0077] The eighteenth aspect of this application provides a computer device, which includes a chip system, either in accordance with the first aspect or a possible implementation of the first aspect.

[0078] A 19th aspect of the present application provides a chip system, the chip system comprising a source physical processor, a control unit, a transmitter, and a target physical processor. The control unit conforms to any of the third aspect, the ninth aspect, a possible implementation of the third aspect, or a possible implementation of the ninth aspect, and the transmitter conforms to any of the fifth aspect, the eleventh aspect, a possible implementation of the eleventh aspect, or a possible implementation of the fifth aspect.

[0079] In some implementations, the chip system may further include an intermediate device provided by any of the fourth side, the tenth side, a possible implementation of the tenth side, or a possible implementation of the fourth side.

[0080] In one implementation, the chip system according to the 19th aspect is a processor, the source physical processor and target physical processor are physical cores within the processor, the control unit is a component located within the processor and coupled to the source physical processor, and the transmitter is a component located within the processor and coupled to the target physical processor. It can be understood that any physical core of the processor can be used as a receiver of virtual interrupts. Thus, a physical core can be used as both a source physical processor and a target physical processor. Correspondingly, what is coupled to the physical core can include both a control unit and a transmitter.

[0081] According to the chip system provided in this embodiment of the present invention, a register dedicated to handling virtual interrupts is provided in the control unit. In this way, a host machine or virtual machine in user mode can directly write information used to trigger a virtual interrupt into the register. The control unit may also send the information to trigger the virtual interrupt to an intermediate device, which then triggers the virtual interrupt. The intermediate device then sends the virtual interrupt to a transmitter, which transmits the virtual interrupt to the target physical processor. In the solution provided in the present invention, the host machine or virtual machine can directly access the register, write the information used to trigger the virtual interrupt into the register, and send the virtual interrupt. Therefore, in the solution provided in the present invention, compared to the prior art, the source physical processor does not need to switch from the virtual machine to the host machine, or from the host machine's user mode to the host machine's kernel mode, thereby reducing the switching overhead that occurs during virtual interrupt processing and improving the performance of the chip system. [Brief explanation of the drawing]

[0082] [Figure 1] This is a schematic diagram of the structure of a computer device according to one embodiment of the present invention.

[0083] [Figure 2] This is a schematic diagram of a virtual interrupt type according to one embodiment of the present invention.

[0084] [Figure 3] This is a schematic diagram of the structure of a chip system according to one embodiment of the present invention.

[0085] [Figure 4] This is a schematic diagram of another structure of a chip system according to one embodiment of the present invention.

[0086] [Figure 5]This is a schematic diagram of a virtual clock interrupt according to one embodiment of the present invention.

[0087] [Figure 6] This is a schematic diagram of an example of an inposition virtual processor identifier group according to one embodiment of the present invention.

[0088] [Figure 7] This is a schematic diagram of an example of a virtual software interrupt according to one embodiment of the present invention.

[0089] [Figure 8] This is a schematic diagram of the structure of a routing device according to one embodiment of the present invention.

[0090] [Figure 9] This is a schematic diagram of an example of a direct peripheral interrupt according to one embodiment of the present invention.

[0091] [Figure 10] This is a schematic diagram of the structure of a chip system in a RISC-V microarchitecture according to one embodiment of the present invention.

[0092] [Figure 11] This is a schematic diagram of the process for handling virtual clock interrupts in a RISC-V microarchitecture according to one embodiment of the present invention.

[0093] [Figure 12] This is a schematic diagram of a process for handling virtual software interrupts in a RISC-V microarchitecture according to one embodiment of the present invention.

[0094] [Figure 13] This is a schematic diagram of a process for handling virtual device interrupts in a RISC-V microarchitecture according to one embodiment of the present invention.

[0095] [Figure 14]This is a schematic diagram of another process for handling virtual device interrupts in a RISC-V microarchitecture according to one embodiment of the present invention.

[0096] [Figure 15] This is a schematic diagram of a process for handling direct peripheral interrupts in a RISC-V microarchitecture according to one embodiment of the present invention.

[0097] [Figure 16] This is a schematic diagram of one embodiment of a virtual interrupt processing method according to one embodiment of the present invention.

[0098] [Figure 17] This is a schematic diagram of an embodiment of a control device according to one embodiment of the present invention.

[0099] [Figure 18] This is a schematic diagram of an embodiment of an intermediate device according to one embodiment of the present invention.

[0100] [Figure 19] This is a schematic diagram of one embodiment of a transmitting device according to one embodiment of the present invention.

[0101] [Figure 20] This is a schematic diagram of another structure of a computer device according to one embodiment of the present invention. [Modes for carrying out the invention]

[0102] The embodiments of the present application will be described below with reference to the accompanying drawings. Clearly, the embodiments described are merely some of the embodiments, rather than all of the embodiments of the present application. Those skilled in the art will know that, with the advancement of the art and the emergence of new scenarios, the technical solutions provided in the present application may also be applicable to similar technical problems.

[0103] In the specification, claims, and accompanying drawings of this application, terms such as “first,” “second,” etc., are intended to distinguish similar subjects but do not necessarily indicate a specific order or sequence. Data referred to in this manner are interchangeable in appropriate contexts, and it should be understood that the embodiments described herein may be implemented in an order other than that exemplified or described herein. Furthermore, the terms “include,” “contain,” and any other variations thereof mean to cover non-exclusive inclusion. For example, a process, method, system, product, or device that includes a set of steps or units is not necessarily limited to those steps or units explicitly listed, and may include other steps or units that are not explicitly listed or are specific to such process, method, system, product, or device.

[0104] Embodiments of the present invention provide a chip system, a virtual interrupt handling method, and a corresponding device for reducing switching overhead caused by virtual interrupts when switching from a virtual machine to a host machine, or from the user mode of a host machine to the kernel mode of a host machine. Embodiments of the present invention further provide corresponding computer devices, computer storage media, computer program products, etc. Further details will be described separately.

[0105] Virtualization is the process of virtualizing hardware resources (such as processors, memory storage space, and network resources) at the hardware layer of a computer device, and sharing these virtualized hardware resources among multiple virtual computers for use. A virtual computer is a general term for a software-virtualized execution environment in any type of virtualized device, and this concept includes virtual machines and containers.

[0106] As shown in Figure 1, the computer device 100 includes a hardware layer 112, a host layer 109, and a virtualization layer. The virtualization layer includes virtual machines 101 and 102. The number of virtual machines may be more or fewer; here, the case with two virtual machines is used as an example. The hardware layer 112 includes a processor system 114, memory 113, a communication interface 115, and an interrupt controller 116.

[0107] A virtual machine (VM) is simulated on a computer device using virtualization software. A guest operating system (guest OS) (Figures 105 and 106 in 1) may be installed on the virtual machine (Figures 101 and 102 in 1), and one or more applications (Figures 103 and 104 in 1) run on the guest operating system. The virtual machine may also have access to network resources. Applications running on a virtual machine behave as if they were running on a real computer.

[0108] A virtual processor (for example, 107 and 108 in Figure 1) represents a processing unit, such as a virtual central processing unit (vCPU), provided to a virtual computer for shared or sliced ​​use in virtualization technology. A single virtual computer may be serviced by one or more virtual processors. When there are multiple virtual processors, typically one virtual processor is the primary virtual processor and the others are secondary virtual processors. Other virtual hardware resources, such as virtual memory included in a virtual machine, are not shown in Figure 1. Virtual processors are obtained through virtualization using virtualization software. The execution of a virtual processor is actually implemented as follows: The host's processor or physical core reads and executes the software program. For example, a physical core reads the software program and executes it in a specific mode of hardware-assisted virtualization of the physical core (e.g., x86 non-root mode) to implement a virtual processor. Multiple virtual processors in a virtual machine may be located on different physical cores. It should be noted that the vCPU referred to in embodiments of this application is an optional specific implementation of a virtual processor. In each embodiment, the term "vCPU" may be replaced with "virtual processor" for the sake of understanding.

[0109] Trap-in and trap-out of virtual processors: A virtual system has two modes: host mode and guest mode. Host mode is sometimes called the host's privilege level, for example, the host's user mode or the host's kernel mode. Guest mode is sometimes called the VM's privilege level, for example, the VM's user mode or the VM's kernel mode. When a physical processor enters guest mode, it is called trap-in (virtual), and the trap-in process can be understood as the physical processor switching from host machine execution to virtual machine execution. When a physical processor exits guest mode, it is called trap-out (virtual), and the trap-out process can be understood as the physical processor switching from virtual machine execution to host machine execution. After trap-out, the physical processor temporarily stops executing the virtual processor's code. Therefore, in this case, the virtual processor can be understood as not running. When a virtual machine runs on a physical processor, the virtual processor of the virtual machine runs. A single virtual machine may have multiple virtual processors. A single physical processor can run only one virtual processor of a virtual machine at a time. Multiple virtual processors belonging to the same virtual machine may run on a physical processor using time-division multiplexing. For example, vCPU 1 of virtual machine 1 may run first on physical processor 1, and after physical processor 1 finishes running vCPU 1, vCPU 2 of virtual machine 1 may run. Multiple vCPUs belonging to the same virtual machine may run on different physical processors instead, and different vCPUs may run simultaneously on different physical processors. For example, vCPU 1 of virtual machine 1 may run on physical processor 1, and vCPU 2 of virtual machine 1 may run on physical processor 2.As the management layer, the host machine (host) layer 109 is configured to complete the management and allocation of hardware resources and provide various virtual hardware resources for virtual machines, such as virtual processors (107, 108), virtual memory, virtual disks, and virtual network adapters, and may further implement virtual machine scheduling and isolation. In some implementations, the host layer 109 includes a host operating system 111 and a virtual monitoring device, such as a virtual machine monitor 110 (VMM). The virtual machine monitor 110 may be deployed inside or outside the host operating system 111. In other virtualization architectures, the virtual monitoring device may be called a hypervisor or another type of virtual monitoring device. The host layer 109 is sometimes called a virtualization platform, and sometimes the host layer is abbreviated to simply "host". The privilege levels of the host machine include user mode and kernel mode.

[0110] The hardware layer 112 is the hardware platform on which the virtualized environment operates. The hardware layer may include multiple types of hardware. As shown in Figure 1, the hardware layer may include a processor system 114 and memory 113, and may further include a communication interface 115, such as a network interface card (NIC), and may also include an interrupt controller 116, input / output (I / O) devices, etc. The processor system 114 may include one or more processors, such as processor 1 and processor 2 shown in Figure 1. Each processor may include multiple physical cores, and a processor may further include multiple registers, such as general-purpose registers and floating-point registers.

[0111] The processor system 114 may include multiple processors, for example, processor 1 and processor 2 in Figure 1. Both processor 1 and processor 2 in Figure 1 are physical processors, such as a source physical processor and a target physical processor. Each physical processor may be understood as a physical core. Specifically, the processor system 114 may be a multi-core processor, which includes a source physical processor and a target physical processor. A virtual processor may be bound to a physical core. That is, a virtual processor always runs on a specific physical core and cannot be scheduled to run on another physical core. In this case, the virtual processor is a bound core. If a virtual processor is scheduled to run on different physical cores depending on the requirements, the virtual processor is not a bound core.

[0112] The interrupt controller 116 is positioned between the hardware that triggers the interrupt request and the processor, and is primarily configured to collect interrupt requests generated by the hardware and send those interrupt requests to the processor based on a specific priority or according to another rule. For example, the interrupt controller is an advanced programmable interrupt controller (APIC).

[0113] An interrupt interrupts the execution of an instruction in the current program and executes an interrupt service routine. Interrupts can include virtual interrupts and physical interrupts. A virtual interrupt is an interrupt notified to a virtual machine (VM) by a hardware device within the computer, the host machine, the virtual machine's clock, or the virtual central processing unit (vCPU) of the virtual machine. Hardware devices that generate virtual interrupts can include disks, network adapters, audio adapters, mice, and hard disks within the computer. A physical interrupt is an interrupt notified to a physical processor by a hardware device. Physical interrupts are handled by the host machine, while virtual interrupts are handled by the virtual machine.

[0114] An interrupt service routine (ISR), sometimes called an interrupt handling function, is a program used to handle interrupt requests. When an interrupt request is received, the processor interrupts the execution of the current program and executes the interrupt service routine that corresponds to the interrupt request.

[0115] The memory space (address space) provided by memory 113 is allocated to the virtual machine and the host for use. The host physical address (HPA) is the physical address space available to the local host (host). The host virtual address (HVA) is the virtual address space available to the local host (host). The guest physical address (GPA) is the physical address space available to the guest operating system of the virtual machine. The guest virtual address (GVA) is the virtual address space available to the guest operating system of the virtual machine.

[0116] Computer device 100 is a physical device such as a server or terminal device. A terminal device may be a handheld device with wireless connectivity or another processing device connected to a wireless modem. For example, a terminal device may be a mobile phone, a computer (personal computer, PC), a tablet computer, a personal digital assistant (PDA), a mobile internet device (MID), a wearable device, or an e-book reader, and may also be a portable mobile device, a pocket-sized mobile device, a handheld mobile device, a computer-integrated mobile device, or an in-vehicle mobile device.

[0117] A virtual machine or host machine within the computer device 100 may transmit information used to trigger a virtual interrupt, thereby enabling the chip system provided in this embodiment of the Application to complete the corresponding process for handling the virtual interrupt. The chip system provided in this embodiment of the Application may include the interrupt controller and processor system shown in Figure 1, or it may include the interrupt controller or processor system shown in Figure 1.

[0118] In this embodiment of the present application, as shown in Figure 2, virtual interrupts may include virtual local interrupts, virtual software interrupts, virtual device interrupts, and direct peripheral interrupts. A virtual local interrupt is an interrupt sent by a virtual local device, such as a virtual timer or virtual mouse, which is simulated by the virtual machine, or an interrupt sent by a local device of the virtual machine's vCPU, for example, an interrupt sent by a timer of the virtual machine's vCPU. Interrupts sent by timers are also called clock interrupts. A clock interrupt is an interrupt that is timed and sent by a timer when a point in time configured by the virtual machine is reached. A virtual software interrupt is an interrupt that is triggered by software and is generally sent by one vCPU of the virtual machine to another vCPU of the virtual machine. For example, Figure 2 shows an interrupt sent by a first vCPU to a second vCPU of the same virtual machine as the first vCPU. A single virtual machine may have multiple vCPUs, and these vCPUs may run simultaneously on different physical processors to perform different tasks of the virtual machine. Virtual software interrupts occur when tasks performed by different vCPUs are interdependent or need to be scheduled. Virtual device interrupts are interrupts triggered by a host machine simulating a hardware device. For example, interrupts generated by a host machine simulating a virtual machine's disk controller or another hardware device. Direct peripheral interrupts are triggered by peripheral devices directly connected to a virtual machine. For example, interrupts generated by a graphics card directly connected to a virtual machine.

[0119] In the four types of virtual interrupts described above, the processing of virtual local interrupts, virtual software interrupts, and virtual device interrupts requires the physical processor running the virtual machine to switch from the virtual machine to the host machine, or from the host machine's user mode to the host machine's kernel mode, which causes relatively high switching overhead. Therefore, embodiments of the present invention provide a chip system. In the process of processing virtual interrupts, the physical processor running the virtual machine does not need to switch from the virtual machine to the host machine, or from the host machine's user mode to the host machine's kernel mode, thus reducing switching overhead. A chip system provided in one embodiment of the present invention will be described below with reference to the accompanying drawings.

[0120] As shown in Figure 3, a chip system provided in one embodiment of the present application includes a source physical processor, a control unit, an intermediate unit, a transmitter, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The control unit includes registers. The registers are configured to receive information used to trigger a virtual interrupt. The information used to trigger the virtual interrupt may come from a host machine or a virtual machine. The control unit is configured to send the information in the registers, used to trigger the virtual interrupt, to the intermediate unit. The intermediate unit is configured to trigger a virtual interrupt based on the information used to trigger the virtual interrupt and to send the virtual interrupt to the transmitter. The transmitter is configured to receive the virtual interrupt from the intermediate unit and send the virtual interrupt to the target physical processor.

[0121] The chip system may be applied to the computer device shown in Figure 1, and the chip system may be an interrupt controller or processor system in Figure 1.

[0122] The chip system provided in this embodiment of the present application may be a system on a chip (SOC), and the source physical processor and target physical processor may each be a processing unit. The source physical processor or target physical processor may be a physical core and may be located on the same processor. Alternatively, the source physical processor and target physical processor may be different processors located within the same chip system. The control unit, intermediate unit, and transmitter may all be implemented using hardware circuitry. The control unit and transmitter may be deployed within a multicore processor and coupled to the source physical processor and target physical processor. The intermediate unit may be deployed within a multicore processor or on a peripheral / peripheral component coupled to the multicore processor. The system on a chip may include a multicore processor and peripheral / peripheral components coupled to the multicore processor. Any physical processor in the chip system may be used as the source physical processor or as the target physical processor.

[0123] In this application, a source physical processor and a target physical processor are used. It should be noted that the source physical processor and the target physical processor may be two physical cores within a single multi-core processor, or two physical cores located on different processors. In some implementations, the source physical processor and the target physical processor may be the same physical entity. For example, in a virtual local interrupt scenario, the source physical processor and the target physical processor may be the same physical processor.

[0124] In this application, the control device may include at least one register, each of which may be configured to receive one type of information used to trigger a virtual interrupt. For example, it may include three registers, one of which is configured to receive information used to trigger a virtual local interrupt, one of which is configured to receive information used to trigger a virtual software interrupt, and one of which is configured to receive information used to trigger a virtual device interrupt. Of course, the control device may have only one register configured for virtual interrupts, and the information used to trigger each type of virtual interrupt may differ. The type of virtual interrupt may be identified using the information received by the register.

[0125] There may be one or more intermediate devices. Each physical processor may have its own transmitter, or multiple physical processors may share a single transmitter.

[0126] In the chip system provided in this embodiment of the present invention, a register dedicated to virtual interrupt processing is set in the control unit. In this way, a host machine or virtual machine in user mode can directly write information used to trigger a virtual interrupt to the register. The control unit sends the information used to trigger the virtual interrupt to an intermediate unit, which then triggers the virtual interrupt. The intermediate unit also sends the virtual interrupt to a transmitter, which then sends the virtual interrupt to the target physical processor. The source physical processor does not need to switch from the virtual machine to the host machine, or from the host machine's user mode to the host machine's kernel mode, thereby reducing the switching overhead that occurs during virtual interrupt processing and improving the performance of the chip system.

[0127] In Figure 3, the intermediate device may be a virtual local interrupt generating device or a routing device. If the virtual interrupt is a virtual local interrupt, the intermediate device may be called a local interrupt generating device (e.g., a timer). If the virtual interrupt is a virtual software interrupt or a virtual device interrupt, the intermediate device may be called a routing device.

[0128] Four types of virtual interrupts are shown in Figure 2. The following describes the process of handling the four types of virtual interrupts using an example in which the control unit includes registers 1, 2, and 3, with reference to Figure 4. Register 1 is configured to receive information used to trigger a virtual device interrupt, register 2 is configured to receive information used to trigger a virtual software interrupt, and register 3 is configured to receive information used to trigger a virtual local interrupt.

[0129] In the chip system shown in Figure 4, the source physical processor is configured to run a host machine or a virtual machine, and the host machine or virtual machine may have permission levels 1 and 2. Permission level 1 may be user mode, and permission level 2 may be kernel mode. Different virtualization architectures may have different states corresponding to permission levels 1 and 2. This is not limited to this embodiment of the present application.

[0130] In Figure 4 of this application, four different lines are used to mark four types of virtual interrupts. The line marked with the number 1 represents the process that handles virtual local interrupts, the line marked with the number 2 represents the process that handles virtual software interrupts, the line marked with the number 3 represents the process that handles virtual device interrupts, and the line marked with the number 4 represents the process that handles direct peripheral interrupts.

[0131] 1. Virtual local interrupt

[0132] As shown in Figure 4, in the process handling the virtual local interrupt, the relevant register is register 3, and the intermediate device may be called the local interrupt generating device. Since the virtual local interrupt is an in-core interrupt, the target physical processor and the source physical processor are the same physical processor, and the transmitter corresponds to the source physical processor.

[0133] The register is configured to receive information written by the virtual machine and used to trigger virtual local interrupts.

[0134] The local interrupt generation device is configured to generate virtual local interrupts based on the information used to trigger virtual local interrupts.

[0135] The transmitter is configured to send virtual local interrupts to the first virtual processor vCPU of the virtual machine, which operates on the source physical processor.

[0136] According to the process for handling virtual local interrupts provided in this embodiment of the present application, a single physical processor can operate only one vCPU of a single virtual machine at a time, and the operation of sending a virtual local interrupt to the virtual machine can be completed by sending the virtual local interrupt to the vCPU. The local interrupt generating device in Figure 4 may be a timer, and the virtual local interrupt may be a clock interrupt. In the clock interrupt scenario, one implementation of the process can be understood by referring to Figure 5. As shown in Figure 5, the virtual machine writes an interrupt point to the control device (the process can be understood by referring to register 3 in Figure 4). The control device writes the interrupt point to a timer, and the timer is started accordingly. When the preset point is reached, the timer sends a clock interrupt. After receiving the clock interrupt, the transmitter determines that the first vCPU of the virtual machine is operating and sends a clock interrupt to the first vCPU.

[0137] From the processes shown in Figures 4 and 5, it can be seen that in the process of handling virtual local interrupts, the source physical processor does not need to switch from the virtual machine to the host machine, thereby reducing the switching overhead that occurs during the handling of virtual local interrupts and improving the performance of the chip system.

[0138] 2. Virtual software interrupts

[0139] As shown in Figure 4, in the process handling virtual software interrupts, the relevant register is register 2, and the intermediate device may be called the routing device. The first vCPU of the virtual machine runs on the source physical processor, and the second vCPU of the virtual machine runs on the target physical processor.

[0140] The register is configured to receive the identifier of the second vCPU, which is written by the first vCPU.

[0141] The control unit is configured to read the identifier of the second vCPU from a register, obtain the identifier of the virtual machine, and send the identifier of the virtual machine and the identifier of the second vCPU to the intermediate device.

[0142] The intermediate device is configured to perform the steps of: determining the target physical processor corresponding to the virtual machine identifier and the second vCPU identifier from a first correspondence based on the virtual machine identifier and the second vCPU identifier, wherein the first correspondence is used to record the correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; and sending a virtual software interrupt to a transmitter corresponding to the target physical processor.

[0143] The transmitter is configured to send virtual software interrupts to a second vCPU running on the target physical processor.

[0144] In the process for handling virtual software interrupts in this embodiment of the present invention, the control unit may obtain the identifier of a virtual machine from a dedicated register that stores the identifier of the virtual machine running on the source physical processor. Each virtual machine may have multiple vCPUs, and the vCPU identifiers of different virtual machines may be the same. Therefore, the control unit needs to send the virtual machine identifier and the identifier of the second vCPU to an intermediate device. The intermediate device may store the first correspondence. The first correspondence may be located in an inposition vCPU identifier group. The inposition vCPU identifier group records the correspondence between each physical processor in the chip system, the vCPU running on each physical processor, and the virtual machine to which the running vCPU belongs. In the present invention, the target physical processor can be determined by looking up the inposition vCPU identifier group. From the above description, it can be seen that in the process for handling virtual software interrupts, the source physical processor does not need to switch from the virtual machine to the host machine, thereby reducing the switching overhead that occurs during the processing of virtual software interrupts and improving the performance of the chip system.

[0145] The imposition vCPU identifier group can be understood by referring to Figure 6. The meaning shown in Figure 6 is as follows: VM1's vCPU 1 operates on physical processor 1, VM1's vCPU 2 operates on physical processor 2, VM2's vCPU 1 operates on physical processor 3, and VM2's vCPU 2 operates on physical processor 4. When the routing device receives the identifiers for VM1 and vCPU 2 from the control unit, it can determine that vCPU 2 is operating on physical processor 2 based on the imposition vCPU identifier group shown in Figure 6. In other words, a virtual software interrupt may be sent to the transmitter corresponding to physical processor 2, and the transmitter corresponding to physical processor 2 will send the virtual software interrupt to vCPU 2 which is operating on physical processor 2.

[0146] If the second vCPU cannot be found by using the imposition vCPU identifier group, this indicates that the second vCPU is not currently operational. In this case, the routing device may send a virtual software interrupt to the source physical processor's transmitter, which sends the virtual software interrupt to the host machine. After the second vCPU comes online and becomes operational, the host machine sends a virtual software interrupt to the second vCPU.

[0147] Since physical processors can execute different vCPUs at different times, the correspondence within the imposition vCPU identifier group may change. The imposition vCPU identifier group within the routing device may be managed by the host machine on the source physical processor.

[0148] The process for handling virtual software interrupts in this embodiment of the present application can be understood by referring to Figure 7. The virtual machine operates on the source physical processor, and the first vCPU of the virtual machine operates on the source physical processor. The second vCPU operates on another physical processor, and the first vCPU needs to send a virtual software interrupt to the second vCPU. In this case, the first vCPU of the virtual machine writes the identifier of the second vCPU to register 2 of the control unit. The control unit finds the identifier of the virtual machine and sends the identifier of the virtual machine and the identifier of the second vCPU to the routing unit. Based on the identifier of the virtual machine and the identifier of the second vCPU, the routing unit searches for the imposition vCPU identifier group shown, for example, in Figure 6, and determines that the physical processor corresponding to the identifier of the virtual machine and the identifier of the second vCPU is the target physical processor. The routing unit then sends a virtual software interrupt to the transmitter corresponding to the target physical processor, and the transmitter corresponding to the target physical processor sends a virtual software interrupt to the second vCPU, which is a virtual machine operating on the target physical processor.

[0149] From the processes shown in Figures 4, 6, and 7, it can be seen that in the process for handling virtual software interrupts provided in this embodiment of the present invention, the source physical processor does not need to switch from the virtual machine to the host machine, thereby reducing the switching overhead that occurs during the handling of virtual software interrupts and improving the performance of the chip system.

[0150] 3. Virtual device interrupts

[0151] As shown in Figure 4, in the process handling virtual device interrupts, the relevant register is register 1, and the intermediate device is the routing device. The host machine operates on the source physical processor, and the host machine is in user mode.

[0152] The register is configured to receive a target interrupt number and a virtual machine identifier written by the host machine. The target interrupt number is the identifier of the interrupt that is triggered when the host machine simulates a hardware device.

[0153] The control unit is configured to read the target interrupt number and virtual machine identifier from a register and send the virtual machine identifier and target interrupt number to the intermediate unit.

[0154] The intermediate device is configured to perform the following steps: a step of searching for a second correspondence based on the virtual machine identifier and target interrupt number to find the identifier of the first vCPU of the virtual machine corresponding to the virtual machine identifier and target interrupt number, wherein the second correspondence is used to record the correspondence between the virtual machine, the target interrupt number and the first vCPU; a step of determining the target physical processor corresponding to the virtual machine identifier and the first vCPU identifier from a third correspondence based on the virtual machine identifier and the first vCPU identifier, wherein the third correspondence is used to record the correspondence between the target physical processor, the first vCPU operating on the target processor and the virtual machine; and a step of sending a virtual device interrupt to a transmitter corresponding to the target physical processor.

[0155] The transmitter is configured to send virtual device interrupts to the first vCPU running on the target physical processor.

[0156] In this embodiment of the present application, a virtual device interrupt is an interrupt triggered when a host machine in user mode simulates a hardware device. There may be multiple types of hardware devices, and each type of hardware device has a different interrupt number. When the host machine simulates a disk, the target interrupt number is the disk's interrupt number. Since the host machine may manage multiple virtual machines, the host machine needs to write the virtual machine identifier and target interrupt number to a register. A second correspondence may be located in an interrupt affinity table. The interrupt affinity table may be composed of virtual machines. Therefore, there is an interrupt affinity table for each virtual machine. Thus, the interrupt affinity table of a virtual machine may be found based on the virtual machine identifier, and then the corresponding vCPU is determined from the virtual machine's interrupt affinity table based on the target interrupt number. The target interrupt number is 10. If interrupt number 10 in the interrupt affinity table corresponds to vCPU ID 1, then it may be determined that the vCPU ID corresponding to that target interrupt number is 1. After determining that the vCPU ID is 1, the routing device can find the physical processor corresponding to vCPU ID 1 based on the imposition vCPU identifier group. For an understanding of the meaning of the imposition vCPU identifier group, please refer to the explanation of virtual software interrupts. For an understanding of the third correspondence, please refer to the first correspondence.

[0157] The following describes the interrupt affinity table for virtual machines, referring to Table 1. [Table 1]

[0158] Table 1 is merely an example, and the correspondences are not limited to the types listed in Table 1. Alternatively, there may be other representations of the correspondences, and there may be a greater number of them. Further columns may be added to Table 1, which are used to store the virtual machine identifiers in Figure 4.

[0159] The interrupt affinity table may be stored in the routing device or in memory. The routing device may provide an address register for each physical processor. The address register may be a base address register. The base address register can store the address of the interrupt affinity table in memory and the identifier of the virtual machine. As shown in Figure 8, base address register 1 on the routing device corresponds to physical processor 1, base address register 2 corresponds to physical processor 2, base address register 3 corresponds to physical processor 3, and base address register 4 corresponds to physical processor 4. The address in each base address register points to one interrupt affinity table. For example, base address register 1 points to interrupt affinity table 1, base address register 2 points to interrupt affinity table 2, base address register 3 points to interrupt affinity table 3, and base address register 4 points to interrupt affinity table 4. If the same virtual machine is running on two physical processors, the addresses of the base address registers corresponding to the two physical processors may be the same, and the interrupt affinity tables they point to may be the same.

[0160] Thus, in the process of handling virtual device interrupts, the virtual machine writes the target interrupt number to register 1, the control unit reads the identifier of the currently running virtual machine from a dedicated register that stores virtual machines running on the source physical processor, and then the control unit sends the target interrupt number and the virtual machine identifier to the routing unit. The routing unit determines the corresponding interrupt affinity table based on the virtual machine identifier and then searches the interrupt affinity table using the target interrupt number to find the identifier of the corresponding vCPU. If the target interrupt number is 10, it may be determined that the corresponding vCPU identifier is 1. After determining that the vCPU identifier is 1, the routing unit may find that the processor corresponding to vCPU 1 is physical processor 1 based on the imposition vCPU identifier group shown in Figure 6. The routing unit sends a virtual device interrupt to the transmitter corresponding to physical processor 1, and the transmitter may send a virtual device interrupt to the first vCPU corresponding to vCPU 1.

[0161] If the first vCPU cannot be found using the imposition vCPU identifier group, this indicates that the first vCPU is not currently operational. In this case, the routing device sends a virtual software interrupt to the source physical processor's transmitter, the source physical processor's transmitter sends a virtual software interrupt to the host machine, and after the first vCPU comes online and starts running, the host machine sends a virtual software interrupt to the first vCPU.

[0162] From the processes shown in Figure 4, Table 1, Figure 8, and Figure 6, it can be seen that in the process for handling virtual device interrupts provided in this embodiment of the present application, the source physical processor does not need to switch from the host machine's user mode to the host machine's kernel mode, thereby reducing the switching overhead that occurs when handling virtual device interrupts and improving the performance of the chip system.

[0163] 4. Direct peripheral interrupts

[0164] As shown in Figure 4, a direct peripheral interrupt is an interrupt triggered by a hardware device directly connected to a virtual machine, such as a graphics card directly connected to the virtual machine. The intermediate device may also be called a routing device. For direct peripheral interrupts, this type of interrupt handling process can be implemented using a routing device and a transmitter. This process includes the following steps:

[0165] The intermediate device is configured to perform the following steps: receive a direct peripheral interrupt triggered by a hardware device; search a virtual interrupt table to find the corresponding virtual machine identifier and virtual interrupt number based on the physical interrupt number of the direct peripheral interrupt, wherein the virtual interrupt table records the correspondence between the physical interrupt number, the virtual machine identifier, and the virtual interrupt number; determine the corresponding interrupt affinity table based on the virtual machine identifier, and from the interrupt affinity table determine the identifier of the target virtual processor vCPU corresponding to the virtual machine identifier and virtual interrupt number, wherein the interrupt affinity table records the correspondence between the virtual processor and the virtual interrupt number; determine the target physical processor corresponding to the target vCPU identifier from the imposition vCPU identifier group based on the target vCPU identifier; and send the peripheral interrupt directly to the transmitter corresponding to the target physical processor.

[0166] The transmitter is configured to send peripheral interrupts directly to the virtual machine running on the target physical processor.

[0167] In this embodiment of the present application, the virtual interrupt table, the interrupt affinity table, and the imposition vCPU identifier group are used in order in the process of directly handling peripheral interrupts. See the previous description for details on the interrupt affinity table and the imposition vCPU identifier group. The virtual interrupt table is described below.

[0168] The virtual interrupt table maintains a mapping relationship between physical interrupt numbers, virtual machine identifiers, and virtual interrupt numbers. When a physical interrupt number is input, the virtual machine identifier and virtual interrupt number can be output. The virtual interrupt table can be understood by referring to Table 2. [Table 2]

[0169] As shown in Table 2, when physical interrupt number 100 is input, the virtual machine identifier 1 and virtual interrupt number 10 may be output. The virtual interrupt table in this application may be stored in a routing device or in memory, and the location of the virtual interrupt table in memory is indicated using another register similar to the base address register.

[0170] In the process of handling direct peripheral interrupts, as shown in Figure 9, the routing device receives the physical interrupt number transmitted by the direct peripheral device and uses the physical interrupt number to search the virtual interrupt table for the corresponding virtual machine identifier and virtual interrupt number. For example, if physical interrupt number 100 is input, the virtual machine identifier 1 and virtual interrupt number 10 may be output. Then, based on the virtual machine identifier 1 and virtual interrupt number 10, the interrupt affinity table in Table 1 is searched to find the corresponding vCPU identifier. For example, the vCPU identifier is found to be 1. Furthermore, based on vCPU 1, the imposition vCPU identifier group shown in Figure 6 is searched for the corresponding physical processor. For example, if physical processor 1 is found, the routing device sends a direct peripheral interrupt to the transmitter corresponding to physical processor 1, and the transmitter sends a direct peripheral interrupt to the first vCPU corresponding to vCPU 1.

[0171] If the first vCPU cannot be found by using the imposition vCPU identifier group, this indicates that the first vCPU is not currently operational. In this case, the routing device sends a virtual software interrupt to the source physical processor's transmitter, the source physical processor's transmitter sends a virtual software interrupt to the host machine, and after the first vCPU comes online and becomes operational, the host machine may send a virtual software interrupt to the first vCPU.

[0172] From the processes shown in Figure 4, Table 2, Table 1, Figure 6, and Figure 9, it can be seen that the process for handling direct peripheral interrupts provided in this embodiment of the present application can complete the transmission process by searching for three correspondences, thereby improving the flexibility of handling direct peripheral interrupts.

[0173] In the process for handling the four types of virtual interrupts described above, after receiving one of the four types of virtual interrupts from the intermediate device, the transmitter sends the virtual interrupt to the corresponding target physical processor. The transmitting process may also write some of the above types of virtual interrupts to a pending register, which is configured to receive commands to be subsequently executed by the target physical processor. After the virtual interrupt is written to the pending register, the target physical processor executes the virtual interrupt. In this way, the currently executing procedure may be interrupted. If the target vCPU is running, the target vCPU is interrupted and the interrupt is sent to the target vCPU. If the host machine is running, the host machine is interrupted and the interrupt is sent directly to the running host machine. When the corresponding target vCPU comes online, the host machine forwards the interrupt to the target vCPU. The target vCPU may be the first vCPU or the second vCPU described above. Thus, the solution provided in this embodiment of the present application can shield the host machine switching action in existing solutions, thereby reducing the overhead of switching the target physical processor from the virtual machine to the host machine.

[0174] The chip system provided in this embodiment of the present application may be applied to a RISC-V microarchitecture. RISC stands for reduced instruction set computing. Figure 10 is a schematic diagram of the structure of the chip system on RISC-V.

[0175] As shown in Figure 10, the chip system includes a control unit and a transmitter configured to interact with a physical processor, and an interrupt router. The interrupt router includes the routing device described in the embodiments described above.

[0176] In Figure 10, RISC-V-CPU represents the central processing unit in the RISC-V architecture, V=0 represents the host machine, V=1 represents the virtual machine, HU mode represents the host machine's user mode, HS mode represents the host machine's kernel mode, VU mode represents the virtual machine's user mode, and VS mode represents the virtual machine's kernel mode. Supervisor-generated inter-processor interrupt (sgenipi) logic is used to trigger virtual software interrupt information, and supervisor time compare (stimecmp) logic is used to trigger virtual local interrupt information registers. When V=1, i.e., when the virtual machine is running on a RISC-V-CPU, the information used to trigger a virtual software interrupt may be sent via sgenipi to the control unit's virtual supervisor generate inter-processor interrupt (vsgenipi) register, where the vsgenipi register is a register used to receive the information used to trigger a virtual software interrupt, as described in the above embodiment, for example, register 2. The information used to trigger a virtual local interrupt may be sent via stimecmp to the control unit's virtual supervisor time compare (vstimecmp) register, where the vstimecmp register is a register used to receive the information used to trigger a virtual local interrupt, as described in the above embodiment, for example, register 3.The user-generated virtual supervisor external interrupt (ugenvsei) register is a register configured to receive information used to trigger a virtual device interrupt, such as register 1 as described in the above embodiment. Information used to trigger a virtual device interrupt can be sent directly to the ugenvsei register through the host machine's user-mode virtual device simulation logic.

[0177] An implementation of the interrupt router includes a virtual heart shared interrupt mapping (vhsimap) register, a group of virtual table base (vtblbase) (1-n) registers, and a group of interrupt control interface mapping (ifmap) registers. The vhsimap (1-n) registers are used to point to a virtual interrupt table stored in memory. Each vtblbase register in the group of vtblbase (1-n) registers corresponds to a physical processor in a RISC-V system and is used to point to a virtual interrupt affinity table defined by the virtual machine to which the vCPU running on the physical processor belongs. A group of ifmap (1-n) registers is provided, each of which corresponds to a physical processor in the system and is used to record the identifier of the vCPU running on the physical processor and the identifier of the virtual machine to which the vCPU belongs.

[0178] In the RISC-V architecture shown in Figure 10, the process for handling virtual clock interrupts can be understood by referring to Figure 11.

[0179] As shown in Figure 11, the virtual machine writes the interrupt time to the vstimecmp register via stimecmp, and the control unit writes the time to trigger the next virtual clock interrupt to the virtual machine's dedicated clock device. When the interrupt time arrives, the virtual machine's dedicated clock device triggers a virtual clock interrupt. The virtual clock interrupt is sent to the transmitter.

[0180] The transmitter makes a decision based on the CPU's current virtualization state V. If V=1, the transmitter sends a local interrupt directly to the virtual machine in VS mode. If V=0, the transmitter sends a local interrupt to the host machine in HS mode, and the host machine processes it on behalf of the virtual machine. In other words, after the virtual machine comes online, the host machine forwards the virtual clock interrupt to the virtual machine.

[0181] In the RISC-V architecture shown in Figure 10, the process for handling virtual software interrupts can be understood by referring to Figure 12.

[0182] As shown in Figure 12, the virtual machine's vCPU (which may be referred to as the source vCPU in this scenario) runs on CPU 1. CPU 1 may also be the source physical processor in the previously described embodiment. The virtual machine's source vCPU writes the target vCPU identifier to sgenipi and uses sgenipi to write the target vCPU identifier to the vsgenipi register in the control unit. The control unit retrieves the virtual machine identifier and sends the virtual machine identifier and the target vCPU identifier (vhartid: the vCPU identifier in RISC-V) to the interrupt router. The interrupt router looks up ifmapx, and the sequence number x in the ifmapx register, which contains the VM ID and vhartid, is the identifier of the corresponding physical processor (mhartid: the physical processor identifier in RISC-V). In this scenario, the physical processor identifier is CPU 2 in Figure 12. CPU 2 may be understood by referring to the target physical processor in the previously described embodiment. The interrupt router sends a virtual software interrupt to the transmitter of the physical processor with mhartid. The transmitter determines the current virtualization state of the physical processor. If V=1, the transmitter sends the virtual software interrupt directly to the virtual machine. If V=0, the transmitter sends the virtual software interrupt to the host machine for processing. In other words, the host machine sends the virtual software interrupt to the virtual machine after the virtual machine comes online.

[0183] In the RISC-V architecture shown in Figure 10, the process for handling virtual device interrupts can be understood by referring to Figure 13.

[0184] As shown in Figure 13, the user-mode host machine writes the virtual machine identifier and virtual interrupt number to ugenvsei. The control unit sends the virtual machine identifier and virtual interrupt number to the interrupt router. The interrupt router searches the vtblbasex register to find the vtblbasex register containing the virtual machine identifier among the various vtblbasex registers. The interrupt affinity table stored in memory, which is pointed to by this register, is searched. The vhartid of the vCPU that will handle the interrupt is obtained from the interrupt affinity table. The interrupt router searches ifmapx to find the sequence number x of the physical processor corresponding to the register containing the VM ID and vhartid, where x is the mhartid of the target physical processor. The interrupt router sends a virtual device interrupt to the transmitter of the physical processor with mhartid. The transmitter determines the current virtualization state of the CPU. If V=1, the transmitter sends the device interrupt directly to the virtual machine. Alternatively, if V=0, the transmitter sends the device interrupt to the host machine for processing. In other words, after the virtual machine comes online, the host machine sends a virtual device interrupt to the virtual machine.

[0185] In the RISC-V architecture shown in Figure 10, a separate process that handles virtual device interrupts can be understood by referring to Figure 14.

[0186] As shown in Figure 14, the host machine writes the virtual machine identifier and virtual interrupt number to ugenvsei. The control unit sends the virtual machine identifier and virtual interrupt number to the interrupt router. The interrupt router does not implement vtblbasex and, by default, sends the virtual interrupt to any vCPU that has the virtual machine. The interrupt router then searches ifmapx and finds the sequence number x of the physical processor corresponding to the register with the virtual machine identifier, where x is the mhartid of the target physical processor. The interrupt router sends the virtual device interrupt to the transmitter of the physical processor with mhartid. The transmitter determines the current virtualization state of the physical processor. If V=1, the transmitter sends the virtual device interrupt directly to the virtual machine. Alternatively, if V=0, the transmitter sends the virtual device interrupt to the host machine for processing. In other words, the host machine sends the virtual device interrupt to the virtual machine after the virtual machine has come online.

[0187] In the RISC-V architecture shown in Figure 10, the process for directly handling peripheral interrupts can be understood by referring to Figure 15.

[0188] As shown in Figure 15, a hardware device that communicates directly with the virtual machine directly triggers a peripheral interrupt. The interrupt router searches the virtual interrupt table pointed to by vhlimap and finds the identifier of the virtual machine to which the interrupt is directly connected and the virtual interrupt number to be considered in the virtual machine after the interrupt is directly connected. The interrupt router searches the vtblbasex registers and finds the vtblbasex with the VM ID among them, and searches the virtual interrupt affinity table stored in memory that this register points to. The vhartid of the vCPU that handles the interrupt is obtained from the interrupt affinity table. The interrupt router searches ifmapx and finds the sequence number x of the physical processor corresponding to the register with the VM ID and vhartid, where x is the mhartid of the target physical processor. The interrupt router directly sends the peripheral interrupt to the transmitter of the physical processor with mhartid. The transmitter determines the current virtualization state of the CPU. If V=1, the transmitter directly sends the peripheral interrupt to the virtual machine. Alternatively, if V=0, the transmitter sends the peripheral interrupt directly to the host machine for processing. In other words, after the virtual machine comes online, the host machine sends the peripheral interrupt directly to the virtual machine.

[0189] According to the aforementioned solutions provided in this embodiment of the present application, virtual local interrupts are implemented using a control unit, intermediate unit, and transmitter, thereby preventing trap-out to the host machine from the local interrupt device to the vCPU throughout the entire process. By using a control unit, routing unit, and transmitter, virtual software interrupts are implemented without software coordination between the virtual machine and the host machine, preventing trap-out to the host machine from the transmitting vCPU to the receiving vCPU throughout the entire process. By using a control unit, routing unit, and transmitter, virtual device interrupts are implemented, preventing context switching / trap-out to the host machine from the host machine analog logic to the receiving host vCPU throughout the entire process. Therefore, the solutions provided in this embodiment of the present application can accelerate the performance of the virtual machine in terms of I / O, clock, scheduling, etc. Simulation data shows that when virtual local interrupts are handled using this solution, Redis is improved by 80% and the handling of virtual software interrupts is increased by 6%.

[0190] The above describes a process for handling virtual interrupts using hardware circuitry. The process for handling virtual interrupts provided in this embodiment of the present application may be implemented using software. The process implemented using software may be combined in the aforementioned chip system. The chip system includes a source physical processor, a control unit, an intermediate unit, and a transmitter. The control unit includes registers. The registers are configured to receive information used to trigger a virtual interrupt. The functions of the control unit, intermediate unit, and transmitter may be implemented in the form of software code. Further explanation is given below with reference to the accompanying drawings.

[0191] As shown in Figure 16, one embodiment of a virtual interrupt handling method according to one embodiment of the present invention includes the following steps:

[0192] 101: The control unit reads information from the registers that will be used to trigger a virtual interrupt.

[0193] The information used to trigger a virtual interrupt originates from a virtual machine or host machine running on the source physical processor.

[0194] 102: The control unit sends information to the intermediate unit to be used to trigger a virtual interrupt. In response, the intermediate unit receives information to be used to trigger a virtual interrupt.

[0195] 103: The intermediate device triggers a virtual interrupt based on the information used to trigger the virtual interrupt.

[0196] 104: The intermediate device sends a virtual interrupt to the transmitter. The transmitter receives the virtual interrupt in response.

[0197] 105: The transmitter sends a virtual device interrupt to the target physical processor.

[0198] According to the solution provided in this embodiment of the present application, a register dedicated to virtual interrupt processing is located in the control unit. Thus, a virtual machine or host machine in user mode can directly write the information used to trigger the virtual interrupt to the register. The control unit sends the information used to trigger the virtual interrupt to an intermediate device, which then triggers the virtual interrupt. The intermediate device then sends the virtual interrupt to a transmitter, which transmits the virtual interrupt to the target physical processor. In the solution provided in the present application, the host machine or virtual machine may directly access the register and write the information used to trigger the virtual interrupt to the register. This then sends the virtual interrupt. Therefore, compared to the prior art, the solution provided in the present application does not require the source physical processor to switch from the virtual machine to the host machine, or to switch from the host machine's user mode to the host machine's kernel mode, thereby reducing the switching overhead that occurs during virtual interrupt processing and improving the performance of the chip system.

[0199] If the virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor. The register receives information written by the virtual machine, which is used to trigger the virtual local interrupt.

[0200] The intermediate device generates a virtual local interrupt based on the information used to trigger the virtual local interrupt.

[0201] The transmitter sends a virtual local interrupt to the first virtual processor (vCPU) of the virtual machine, which operates on the source physical processor.

[0202] If the virtual interrupt is a virtual software interrupt, the information read from the register in step 101 and used to trigger the virtual interrupt includes the identifier of the second vCPU, which is written to the register by the first vCPU of the virtual machine, and the second vCPU is the vCPU of the virtual machine running on the target physical processor.

[0203] Prior to step 102, the control unit obtains the virtual machine identifier. In this case, step 103 specifically includes sending the virtual machine identifier and the identifier of the second vCPU to the intermediate unit.

[0204] Step 103 specifically includes: a step in which the intermediate device determines, from a first correspondence, the target physical processor corresponding to the virtual machine identifier and the second vCPU identifier, based on the virtual machine identifier and the second vCPU identifier, wherein the first correspondence is used to record the correspondence between the target physical processor, the second vCPU running on the target processor, and the virtual machine; and a step in which it triggers a virtual software interrupt.

[0205] Step 104 includes the following: The intermediate device sends a virtual software interrupt to the transmitter corresponding to the target physical processor.

[0206] Step 105 includes the following: The transmitter sends a virtual software interrupt to a second vCPU running on the target physical processor.

[0207] If the virtual interrupt is a virtual device interrupt, the information read from the register in step 101 and used to trigger the virtual interrupt includes the target interrupt number written to the register by the host machine and the virtual machine identifier. The target interrupt number is the identifier of the interrupt that is triggered when the host machine simulates a hardware device.

[0208] Step 102 includes the following: The control unit sends the virtual machine identifier and target interrupt number to the intermediate unit.

[0209] Step 103 includes: a step in which the intermediate device searches for a second correspondence based on the virtual machine identifier and target interrupt number to find the identifier of the first vCPU of the virtual machine corresponding to the virtual machine identifier and target interrupt number, the second correspondence being used to record the correspondence between the virtual machine, the target interrupt number and the first vCPU; a step in which, based on the virtual machine identifier and the first vCPU identifier, the device determines the target physical processor corresponding to the virtual machine identifier and the first vCPU identifier from a third correspondence, the third correspondence being used to record the correspondence between the target physical processor, the first vCPU running on the target processor and the virtual machine; and a step in which the device generates a virtual device interrupt.

[0210] Step 104 includes the following: The intermediate device sends a virtual device interrupt to the transmitter corresponding to the target physical processor.

[0211] Step 105 includes the following: The transmitter sends a virtual device interrupt to the first vCPU running on the target physical processor.

[0212] The functions of the control unit, intermediate unit, and transmitter unit, which are implemented using software, can be understood by referring to the corresponding contents in the embodiments shown in Figures 2 to 15, and further details will not be explained here.

[0213] The above describes a method for handling virtual interrupts implemented using software. The following describes a device that implements the above method for handling virtual interrupts, referring to the attached diagrams.

[0214] As shown in Figure 17, one embodiment of the control device 20 provided in this embodiment of the present application includes: The control device 20 is applied to a chip system, which further includes a source physical processor, an intermediate device, a transmitter, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The control device includes registers, which are configured to receive information used to trigger virtual interrupts, and this information used to trigger virtual interrupts originates from the host machine or a virtual machine. The control device 20 includes: A read unit 201 configured to read information from registers used to trigger a virtual interrupt; and A transmit unit 202 is configured to read information from a read unit 201 and send it to an intermediate device, the information used to trigger the virtual interrupt being used by the intermediate device to trigger the virtual interrupt, and the virtual interrupt being sent by the transmit unit to a target physical processor.

[0215] Optionally, the virtual interrupt is a virtual local interrupt, the target physical processor and source physical processor are the same physical processor, and the register is configured to receive information written by the virtual machine that is used to trigger the virtual local interrupt. The information used to trigger the virtual local interrupt is used so that the intermediate device can trigger the virtual local interrupt, and the virtual local interrupt is sent by the transmitter to the first virtual processor vCPU of the virtual machine, which runs on the source physical processor.

[0216] Optionally, a virtual interrupt is a virtual software interrupt. The information used to trigger a virtual interrupt includes an identifier for a second vCPU written by the first vCPU of the virtual machine, where the second vCPU is the vCPU of the virtual machine running on the target physical processor. The control unit 20 further includes a processing unit 203.

[0217] The processing unit 203 is configured to obtain the identifier of the virtual machine.

[0218] The transmitting unit 202 is configured to transmit the virtual machine identifier to the intermediate device, and the virtual machine identifier and the second vCPU identifier are used by the intermediate device to determine the target physical processor and trigger a virtual software interrupt, which is then sent by the transmitting device to the second vCPU of the target physical processor.

[0219] Optionally, a virtual interrupt is a virtual device interrupt. The information used to trigger a virtual interrupt includes a target interrupt number and a virtual machine identifier, which are written to a register by the host machine, and the target interrupt number is the identifier of the interrupt that is triggered when the host machine simulates a hardware device. The virtual machine identifier and target interrupt number are used by the intermediate device to determine the target physical processor and trigger the virtual device interrupt, which is then sent by the transmitter to the first vCPU of the target physical processor.

[0220] As shown in Figure 18, one embodiment of the intermediate device 30 according to one embodiment of the present application includes: The intermediate device 30 is applied to a chip system, which further includes a source physical processor, a control device, a transmitter, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The control device includes registers, which are configured to receive information used to trigger virtual interrupts, and this information used to trigger virtual interrupts originates from the host machine or a virtual machine. The intermediate device 30 includes: A receiving unit 301 configured to receive information from the control unit, which is used to trigger a virtual interrupt; Processing unit 302 configured to trigger a virtual interrupt based on information used to trigger a virtual interrupt; and A transmitting unit 303 configured to send virtual interrupts to a transmitting device, the virtual interrupts being transmitted by the transmitting device to a target physical processor.

[0221] Optionally, a virtual interrupt is a virtual local interrupt, the target physical processor and source physical processor are the same physical processor, and the registers are written by the virtual machine and configured to receive information used to trigger the virtual local interrupt. The information used to trigger the virtual local interrupt is used to trigger the virtual local interrupt, which is sent by the transmitter to the first virtual processor vCPU of the virtual machine, the first vCPU running on the source physical processor.

[0222] Optionally, a virtual interrupt is a virtual software interrupt. The information used to trigger a virtual interrupt includes an identifier for a second vCPU written by the first vCPU of the virtual machine, where the second vCPU is the vCPU of the virtual machine running on the target physical processor.

[0223] The processing unit 302 is configured to perform the following steps: a step of determining the target physical processor corresponding to the virtual machine identifier and the second vCPU identifier from a first correspondence based on the virtual machine identifier and the second vCPU identifier, wherein the first correspondence is used to record the correspondence between the target physical processor, the second vCPU running on the target physical processor, and the virtual machine; and a step of triggering a virtual software interrupt, wherein the virtual software interrupt is transmitted by a transmitter to the second vCPU of the target physical processor.

[0224] Optionally, a virtual interrupt is a virtual device interrupt, and the information used to trigger a virtual interrupt includes a target interrupt number and a virtual machine identifier, which are written to registers by the host machine. The target interrupt number is the identifier of the interrupt that is triggered when the host machine simulates a hardware device.

[0225] The processing unit 302 is configured to perform the following steps: a step of searching for a second correspondence by finding the identifier of the first vCPU of the virtual machine corresponding to the virtual machine identifier and target interrupt number, based on the virtual machine identifier and target interrupt number, wherein the second correspondence is used to record the correspondence between the virtual machine, the target interrupt number and the first vCPU; a step of determining the target physical processor corresponding to the virtual machine identifier and the first vCPU identifier from a third correspondence based on the virtual machine identifier and the first vCPU identifier, wherein the third correspondence is used to record the correspondence between the target physical processor, the first vCPU running on the target processor and the virtual machine; and a step of triggering a virtual device interrupt, which is transmitted by a transmitter to the first vCPU of the target physical processor.

[0226] Optionally, the processing unit 302 is further configured to locate an address register based on the virtual machine identifier and to retrieve a second correspondence from memory based on the address in the address register. Here, the address register is configured to store the address of the second correspondence in memory and the virtual machine identifier.

[0227] As shown in Figure 19, one embodiment of the transmitter 40 according to one embodiment of the present application includes: The transmitter 40 is applied to a chip system, which further includes a source physical processor, an intermediate device, a control device, and a target physical processor. The source physical processor is configured to run a host machine or a virtual machine. The control device includes registers, which are configured to receive information used to trigger virtual interrupts, and this information used to trigger virtual interrupts originates from the host machine or a virtual machine. The transmitter 40 includes: A receiver 401 configured to receive virtual interrupts from an intermediate device; and A transmit unit 402 configured to send virtual interrupts to the target physical processor.

[0228] Optionally, the virtual interrupt is a virtual local interrupt, and the target physical processor and source physical processor are the same physical processor. The transmit unit 402 is configured to send a virtual local interrupt to the first virtual processor vCPU of the virtual machine, which operates on the source physical processor.

[0229] Optionally, a virtual interrupt is a virtual software interrupt. The information used to trigger a virtual interrupt includes an identifier for a second vCPU written by the first vCPU of the virtual machine, where the second vCPU is the vCPU of the virtual machine running on the target physical processor.

[0230] The transmitting unit 402 is configured to send a virtual software interrupt to a second vCPU running on the target physical processor.

[0231] Optionally, a virtual interrupt is a virtual device interrupt, and the information used to trigger a virtual interrupt includes a target interrupt number and a virtual machine identifier, which are written to registers by the host machine. The target interrupt number is the identifier of the interrupt that is triggered when the host machine simulates a hardware device.

[0232] The transmitting unit 402 is configured to send a virtual device interrupt to a first vCPU running on the target physical processor.

[0233] Optionally, the transmit unit 402 is configured to write a virtual interrupt to the pending register of the target physical processor, which is configured to receive commands for procedures to be performed by the target physical processor.

[0234] For understanding the solutions described in Figures 17 to 19, please refer to the corresponding content in the embodiments shown in Figures 2 to 15. Further details will not be explained again here.

[0235] Figure 20 is a schematic diagram of a possible logical structure of a computer device 50 according to one embodiment of the present application. The computer device 50 may include a control unit, intermediate unit, or transmitter as shown in Figures 17 to 19. The computer device 50 includes a processor 501, a communication interface 502, a memory 503, and a bus 504. The processor 501, the communication interface 502, and the memory 503 are interconnected through the bus 504. In this embodiment of the present application, the processor 501 is configured to control and manage the actions of the computer device 50. For example, the processor 501 is configured to perform steps 101 or 103 in the method embodiment of Figure 16. The memory 503 is configured to store program code and data for the computer device 50. The communication interface 502 may be configured to perform steps 102, 104, or 105 in the method embodiment of Figure 16.

[0236] Furthermore, the processor 501 may be a central processing unit, a general-purpose processor, a digital signal processor, an application-specific integrated circuit, a field-programmable gate array, another programmable logic device, a transistor logic device, a hardware component, or any combination thereof. The processor may implement or run various exemplary logic blocks, modules, and circuits described by reference to what is disclosed herein. Alternatively, the processor 501 may be a combination of processors that implement computing functions, for example, a combination of one or more microprocessors, or a combination of a digital signal processor and a microprocessor. The bus 504 may be a Peripheral Component Interconnect (PCI) bus, an Extended Industry Standard Architecture (EISA) bus, etc. Buses may be classified into address buses, data buses, control buses, etc. For simplicity of representation, only one thick line represents the bus in Figure 20, but this does not mean that there is only one bus or only one type of bus.

[0237] In another embodiment of the present application, a computer-readable storage medium is further provided. The computer-readable storage medium stores computer-executable instructions. When the device's processor executes a computer-executable instruction, the device executes a virtual interrupt handling scheme performed by the control unit, intermediate unit, or transmitter shown in Figure 16.

[0238] In another embodiment of the present application, a computer program product is further provided. The computer program product includes computer-executable instructions, which are stored in a computer-readable storage medium. When the device's processor executes a computer-executable instruction, the device performs a virtual interrupt handling method, which is performed by a control unit, intermediate unit, or transmitter as shown in Figure 16.

[0239] Another embodiment of the present application further provides a chip system. The chip system includes a source physical processor, a control unit, a transmitter, and a target physical processor. The control unit is the control unit described in the embodiments of Figures 2 to 15, and the transmitter is the transmitter described in the embodiments of Figures 2 to 15.

[0240] In one possible embodiment, the chip system may further include the intermediate device described in the embodiments of Figures 2 to 15.

[0241] In one possible embodiment, the chip system is a processor, the source physical processor and the target physical processor are physical cores within the processor, the control unit is a component located within the processor and coupled to the source physical processor, and the transmitter is a component located within the processor and coupled to the target physical processor. It can be understood that any physical core of the processor may be used as a receiver of virtual interrupts. Thus, a physical core may be used as both a source physical processor and a target physical processor. Correspondingly, components coupled to a physical core may include both a control unit and a transmitter.

[0242] A person skilled in the art will recognize, in combination with the examples described in the embodiments disclosed in this specification, that units and algorithmic steps may be implemented by electronic hardware or a combination of computer software and electronic hardware. Whether the functions are performed by hardware or software depends on the specific application and design constraints of the technical solution. A person skilled in the art may use various methods to implement the described functions for each specific application, but should not consider that such implementations exceed the scope of the embodiments of this application.

[0243] For the sake of brevity, detailed operating processes of the above systems, apparatuses, and units can be found by referring to the corresponding processes in the above method embodiments, and it will be readily apparent to those skilled in the art that details are not described again here.

[0244] In some embodiments provided in the embodiments of this application, it should be understood that the disclosed systems, apparatus and methods may be implemented in other ways. For example, the described apparatus embodiments are merely examples. For example, the division into units is merely a logical functional division, and in actual implementation, other divisions may be used. For example, multiple units or components may be combined, integrated into other systems, or some functions may be ignored or not performed. Furthermore, the mutual coupling, direct coupling or communication connection shown or discussed may be implemented through some interfaces. Indirect coupling or communication connection between apparatus or units may be implemented electrically, mechanically or in other ways.

[0245] Units described as separate parts may or may not be physically separate. Parts presented as units may or may not be physical units. In other words, they may be in one location or distributed across multiple network units. Some or all of the units may be selected based on the actual requirements in order to achieve the objectives of the embodiment's solution.

[0246] Furthermore, the functional units in the embodiments of the present invention may be integrated into a single processing unit, or each unit may exist physically independently, or two or more units may be integrated into a single unit.

[0247] When functions are implemented in the form of software function units and sold or used as independent products, those functions may be stored on a computer-readable storage medium. Based on such understanding, the technical solutions of the embodiments of the present application, in essence, or in part with respect to the prior art, or a part of the technical solutions, may be implemented in the form of a software product. A computer software product is stored on a storage medium and includes several instructions for instructing a computer device (which may be a personal computer, server, or network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present application. The aforementioned storage medium includes any medium capable of storing program code, such as a USB flash drive, a removable hard disk drive, read-only memory (ROM), random access memory (RAM), a magnetic disk, or an optical disk.

[0248] The above description is merely an individual implementation of the embodiments of the present application and is not intended to limit the scope of protection of the embodiments of the present application. Modifications or substitutions readily identifiable by a person skilled in the art within the technical scope disclosed in the embodiments of the present application fall within the scope of protection of the embodiments of the present application. Therefore, the scope of protection of the embodiments of the present application should be subject to the scope of protection of the claims.

Claims

1. A source physical processor, wherein the source physical processor is configured to operate as a host machine or run a virtual machine; A control device having registers, the registers configured to receive information used to trigger a virtual interrupt, the information used to trigger the virtual interrupt originates from the host machine or the virtual machine, The control device is configured to transmit information in the register, which is used to trigger the virtual interrupt, to an intermediate device; The intermediate device is configured to send the virtual interrupt to the transmitter. It has, The transmitting device is configured to receive the virtual interrupt from the intermediate device and transmit the virtual interrupt to the target physical processor. Chip system.

2. The aforementioned virtual interrupt is a virtual local interrupt, and the target physical processor and the source physical processor are the same physical processor; The register is configured to receive information written to by the virtual machine and used to trigger the virtual local interrupt; The transmitting device is configured to transmit the virtual local interrupt to the first virtual processor of the virtual machine, and the first virtual processor operates on the source physical processor. The chip system according to claim 1.

3. The virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier for a second virtual processor written to the register by the first virtual processor of the virtual machine, the second virtual processor being a virtual processor of the virtual machine running on the target physical processor; The control device is configured to read the identifier of the second virtual processor from the register, obtain the identifier of the virtual machine, and transmit the identifier of the virtual machine and the identifier of the second virtual processor to the intermediate device; The aforementioned intermediate device is: A step of determining the target physical processor corresponding to the identifier of the virtual machine and the identifier of the second virtual processor from a first correspondence based on the identifier of the virtual machine and the identifier of the second virtual processor, wherein the first correspondence is used to record the correspondence between the target physical processor, the second virtual processor running on the target physical processor, and the virtual machine; The system is configured to perform the steps of: sending the virtual software interrupt to the transmitter corresponding to the target physical processor; The transmitting device is configured to transmit the virtual software interrupt to the second virtual processor running on the target physical processor. The chip system according to claim 1.

4. The virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes a target interrupt number and a virtual machine identifier, which are written to the register by the host machine, the target interrupt number being the identifier of the interrupt that is triggered when the host machine simulates a hardware device; The control device is configured to read the target interrupt number and the virtual machine identifier from the register and to transmit the virtual machine identifier and the target interrupt number to the intermediate device; The aforementioned intermediate device is: A step of searching for a second correspondence by determining the identifier of a first virtual processor of the virtual machine that corresponds to the identifier of the virtual machine and the target interrupt number, based on the identifier of the virtual machine and the target interrupt number, wherein the second correspondence is used to record the correspondence between the virtual machine, the target interrupt number and the first virtual processor; A step of determining the target physical processor corresponding to the virtual machine identifier and the first virtual processor identifier from a third correspondence based on the identifier of the virtual machine and the identifier of the first virtual processor, wherein the third correspondence is used to record the correspondence between the target physical processor, the first virtual processor operating on the target physical processor, and the virtual machine; The system is configured to perform the steps of sending the virtual device interrupt to the transmitter corresponding to the target physical processor, The transmitting device is configured to transmit the virtual device interrupt to the first virtual processor running on the target physical processor. The chip system according to claim 1.

5. The intermediate device has an address register, which is configured to store the second corresponding address in memory and the identifier of the virtual machine; The intermediate device is further configured to: locate the address register based on the identifier of the virtual machine, and obtain the second correspondence from the memory based on the address in the address register. The chip system according to claim 4.

6. A virtual interrupt handling method, the method being applied to a control unit in a chip system, the chip system further comprising a source physical processor, an intermediate unit, a transmitter, and a target physical processor, the source physical processor being configured to operate as a host machine or to run a virtual machine, the control unit having registers, the registers being configured to receive information used to trigger a virtual interrupt, the information used to trigger the virtual interrupt originating from the host machine or the virtual machine, and the method: The steps include: reading information from the register that is used to trigger the virtual interrupt; The steps include transmitting information used to trigger the virtual interrupt to the intermediate device, the information used to trigger the virtual interrupt being used to enable the intermediate device to trigger the virtual interrupt, and the virtual interrupt being transmitted by the transmitter to the target physical processor. method.

7. The virtual interrupt is a virtual local interrupt, the target physical processor and the source physical processor are the same physical processor, and the register is configured to receive information written by the virtual machine and used to trigger the virtual local interrupt; The information used to trigger the virtual local interrupt is used by the intermediate device to trigger the virtual local interrupt, the virtual local interrupt is transmitted by the transmitter to the first virtual processor of the virtual machine, and the first virtual processor operates on the source physical processor. The method according to claim 6.

8. The virtual interrupt is a virtual software interrupt, and the information used to trigger the virtual interrupt includes an identifier of a second virtual processor written to the register by the first virtual processor of the virtual machine, the second virtual processor being a virtual processor of the virtual machine operating on the target physical processor. The method further: The step of obtaining the identifier of the aforementioned virtual machine; The steps include transmitting the identifier of the virtual machine to the intermediate device, wherein the identifier of the virtual machine and the identifier of the second virtual processor are used by the intermediate device to determine the target physical processor and trigger the virtual software interrupt, and the virtual software interrupt is transmitted by the transmitting device to the second virtual processor of the target physical processor. The method according to claim 6.

9. The virtual interrupt is a virtual device interrupt, and the information used to trigger the virtual interrupt includes a target interrupt number and a virtual machine identifier, which are written to the register by the host machine, the target interrupt number being the identifier of the interrupt that is triggered when the host machine simulates a hardware device; The identifier of the virtual machine and the target interrupt number are used by the intermediate device to determine the target physical processor and trigger the virtual device interrupt, and the virtual device interrupt is transmitted by the transmitter to the first virtual processor of the target physical processor. The method according to claim 6.

10. The intermediate device includes an address register, which is configured to store a second corresponding address in memory and the identifier of the virtual machine; The method further: The intermediate device then performs the step of finding the address register based on the identifier of the virtual machine; The intermediate device includes the step of obtaining the second correspondence from the memory based on the address in the address register, The method according to claim 9.

11. A computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 6 to 10 is performed.

12. A computer device having a chip system as described in any one of claims 1 to 5.

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