Intercomponent materials in microelectronic assemblies with direct bonding

Abstract

To provide a microelectronic assembly having excellent thermal conductivity without hot spots.SOLUTION: A microelectronic assembly 100 includes an interposer 150, a first microelectronic component 102-1 with a first surface 151-1 coupled to the interposer 150 by a first direct coupling region and an opposing second surface 151-2, a second microelectronic component 102-2 with a first surface and an opposite second surface coupled to the interposer 150 by a second direct coupling region, a liner material 132 on the surface of the interposer and around the first microelectronic component and the second microelectronic component, an inorganic filler 126 on the liner material between the first microelectronic component and the second microelectronic component, and a third microelectronic component 102-3 bonded to the second surface of the first microelectronic component and the second microelectronic component.SELECTED DRAWING: Figure 1

Description

Background Art

[0001] An integrated circuit (IC) package typically includes a die wire bonded or soldered to an interposer, an underfill material between the die and the interposer, and a mold material disposed around the die. The mold material is usually temperature sensitive and limits the types of manufacturing processes that can be used during semiconductor assembly. In use, the mold material can negatively impact the performance of the processor by restricting heat conduction away from hot spots in the IC package.

Brief Description of the Drawings

[0002] Embodiments will be readily understood by the following detailed description in conjunction with the accompanying drawings. For ease of explanation, like reference numerals refer to like structural elements. In the figures of the accompanying drawings, embodiments are shown by way of example, not as a limitation.

[0003] [Figure 1] FIG. 1 is a side cross-sectional view of an exemplary microelectronic assembly including direct bonding and materials between components, according to various embodiments.

[0004] [Figure 2] FIG. 2 is a side cross-sectional exploded view of a portion of the microelectronic assembly of FIG. 1, according to various embodiments.

[0005] [Figure 3A] FIG. 3 is a side cross-sectional view of exemplary stages of manufacture of a portion of the microelectronic assemblies of FIGS. 1 and 2, according to various embodiments. [Figure 3B] FIG. 4 is a side cross-sectional view of exemplary stages of manufacture of a portion of the microelectronic assemblies of FIGS. 1 and 2, according to various embodiments. [Figure 3C] FIG. 5 is a side cross-sectional view of exemplary stages of manufacture of a portion of the microelectronic assemblies of FIGS. 1 and 2, according to various embodiments. [Figure 3D]These are side cross-sectional views of exemplary stages of the manufacturing of parts of the microelectronic assemblies shown in Figures 1 and 2, according to various embodiments. [Figure 3E] These are side cross-sectional views of exemplary stages of the manufacturing of parts of the microelectronic assemblies shown in Figures 1 and 2, according to various embodiments. [Figure 3F] These are side cross-sectional views of exemplary stages of the manufacturing of parts of the microelectronic assemblies shown in Figures 1 and 2, according to various embodiments. [Figure 3G] These are side cross-sectional views of exemplary stages of the manufacturing of parts of the microelectronic assemblies shown in Figures 1 and 2, according to various embodiments.

[0006] [Figure 4A] This is an enlarged side cross-sectional view of the dotted line portion of Figure 3G, which shows exemplary bonding interfaces according to various embodiments. [Figure 4B] This is an enlarged side cross-sectional view of the dotted line portion of Figure 3G, which shows exemplary bonding interfaces according to various embodiments. [Figure 4C] This is an enlarged side cross-sectional view of the dotted line portion of Figure 3G, which shows exemplary bonding interfaces according to various embodiments. [Figure 4D] This is an enlarged side cross-sectional view of the dotted line portion of Figure 3G, which shows exemplary bonding interfaces according to various embodiments.

[0007] [Figure 5] This is a side cross-sectional view of an exemplary microelectronic assembly, including direct bonding and inter-component materials, according to various embodiments.

[0008] [Figure 6A] Figure 3 shows an exemplary side cross-sectional view of the manufacturing steps of a microelectronic assembly according to various embodiments. [Figure 6B] Figure 3 shows an exemplary side cross-sectional view of the manufacturing steps of a microelectronic assembly according to various embodiments. [Figure 6C] Figure 3 shows an exemplary side cross-sectional view of the manufacturing steps of a microelectronic assembly according to various embodiments. [Figure 6D]A side cross-sectional view of exemplary stages of manufacturing the microelectronic assembly of FIG. 3, according to various embodiments. [Figure 6E] A side cross-sectional view of exemplary stages of manufacturing the microelectronic assembly of FIG. 3, according to various embodiments. [Figure 6F] A side cross-sectional view of exemplary stages of manufacturing the microelectronic assembly of FIG. 3, according to various embodiments.

[0009] [Figure 7] A side cross-sectional view of an exemplary microelectronic assembly including direct bonding and a thermal dissipation material between components, according to various embodiments.

[0010] [Figure 8] A top view of a wafer and die that may be included in a microelectronic component, according to some embodiments disclosed herein.

[0011] [Figure 9] A side cross-sectional view of an integrated circuit (IC) device that may be included in a microelectronic component, according to some embodiments disclosed herein.

[0012] [Figure 10] A side cross-sectional view of an IC device assembly including a microelectronic assembly, according to some embodiments disclosed herein.

[0013] [Figure 11] A block diagram of an exemplary electrical device including a microelectronic assembly, according to some embodiments disclosed herein.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Microelectronic assemblies, including microelectronic components bonded together by direct bonding regions using an inorganic dielectric filler material positioned around the microelectronic components, and related structures and techniques are disclosed herein. For example, in some embodiments, a microelectronic assembly may include an interposer having a first surface and an opposing second surface; a first microelectronic component bonded to the second surface of the interposer by a first direct bonding region; a second microelectronic component bonded to the second surface of the interposer by a second direct bonding region; a liner material on the second surface of the interposer and surrounding the first and second microelectronic components; and an inorganic dielectric material on the liner material and between the first and second microelectronic components. In some embodiments, the microelectronic assembly may include an interposer having a first surface and an opposing second surface; a first microelectronic component bonded to the second surface of the interposer by a first direct bonding region; a second microelectronic component bonded to the second surface of the interposer by a second direct bonding region; a liner material located on the second surface of the interposer and surrounding the first and second microelectronic components; and a thermally conductive filler material located on the liner material and between the first and second microelectronic components.

[0015] In the following detailed description, references are made to the accompanying drawings which form part of this specification. In the accompanying drawings, similar reference numerals throughout refer to similar parts, and possible embodiments are shown as examples. Other embodiments may be used, and structural or logical modifications may be made, which should not exceed the scope of this disclosure. Therefore, the following detailed description should not be construed as restrictive.

[0016] Various operations may be described sequentially as multiple separate actions or operations in the manner that is most helpful in understanding the subject matter described in the claims. However, the order of description should not be interpreted as suggesting that these operations are necessarily order-dependent. In particular, these operations do not have to be performed in the order presented. The described operations may be performed in a different order than in the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments.

[0017] For the purposes of this disclosure, the phrases "A and / or B" and "A or B" mean (A), (B) or (A and B). For the purposes of this disclosure, the phrases "A, B and / or C" and "A, B or C" mean (A), (B), (C), (A and B), (A and C), (B and C) or (A, B and C). The drawings are not necessarily to scale. Many of the drawings show straight structures with flat walls and right-angle corners, but this is simply for illustrative purposes, and actual devices made using these techniques will exhibit rounded corners, surface roughness and other features.

[0018] The descriptions use the phrases “in one embodiment” or “in an embodiment,” each of which may refer to one or more of the same or different embodiments. Furthermore, terms such as “comprising,” “including,” and “having” as used in reference to embodiments of this disclosure are synonymous. When used to describe a range of dimensions, the phrase “between X and Y” refers to a range including X and Y. Terms such as “top” and “bottom” may be used herein to describe various features of the drawings, but these terms are merely for the sake of clarity and do not suggest a desired or required direction. An element may be referred to singularly herein, but such an element may include multiple sub-elements. For example, “dielectric material” may include one or more dielectric materials. Where used herein, “conductive contact” may refer to a portion of conductive material (e.g., metal) that functions as an electrical interface between different components. The conductive contact may be located in a recess on the surface of a component, on the same plane as the surface, or extending away from the surface, and may take any suitable form (e.g., a conductive pad or socket, or a portion of a conductive wire or via). For ease of explanation, the drawings 3A to 3G may be referred to herein as "Figure 3".

[0019] Prior art for heterogeneous integration of dies from different semiconductor nodes to form composite dies generally involves thermal compression bonding or mass reflow of one or more dies to wafers from different nodes, and providing underfill and / or mold materials to enable subsequent processing such as through-substrate via (TSV) exposure and controlled collapse chip connection (C4) bumping. The use of low-temperature polymer dielectrics as underfill and / or mold materials severely limits the temperature that subsequent processing of the composite die may reach in order to avoid degassing, over-softening, or degradation of the dielectric, which could damage the individual dies and / or the interconnects between the dies and the wafer. The use of low-temperature polymer dielectrics is prone to leading to extreme wafer bending (e.g., bending greater than 800 microns), which makes handling the wafer during processing extremely difficult. Furthermore, the use of low-temperature polymer dielectrics is prone to performance degradation by hindering heat conduction away from the heat source. The microelectronic assemblies and methods disclosed herein enable composite dies to be made of inorganic materials that can be exposed to high temperatures to allow for better heat dissipation, and provide improved materials and structures that are easier to handle during processing to enable simpler manufacturing compared to conventional approaches.

[0020] Figure 1 is a side cross-sectional view of a microelectronic assembly 100 according to various embodiments. The microelectronic assembly 100 may include an interposer 150, a first microelectronic component 102-1, a second microelectronic component 102-2, a third microelectronic component 102-3, a liner material 132, an intercomponent filling material 126, a support component 182, and an underfill material 138. The interposer 150 includes a first surface 151-1 (i.e., bottom surface) and an opposing second surface 151-2 (i.e., top surface).

[0021] The microelectronic assembly 100 may include an interposer 150 which is coupled to the microelectronic component 102-1 by a direct bonding (DB) region 130-1 and to the microelectronic component 102-2 by a DB region 130-2. In particular, as shown in Figure 2, the DB region 130-1 may include a DB interface 180-1A on the upper surface 151-2 of the interposer 150, and the DB interface 180-1A may include a set of conductive DB contacts 110 and DB dielectrics 108 around the DB contacts 110 of the DB interface 180-1A. The DB region 130-1 also includes a DB interface 180-1B on the bottom surface of the microelectronic component 102-1, and the DB interface 180-1B may include a set of DB contacts 110 and DB dielectrics 108 around the DB contacts 110 of the DB interface 180-1B. The DB contact 110 of the DB interface 180-1A of the interposer 150 may be aligned with the DB contact 110 of the DB interface 180-1B of the microelectronic component 102-1 in the microelectronic assembly 100 such that the DB contact 110 of the microelectronic component 102-1 contacts the DB contact 110 of the interposer 150. In the microelectronic assembly 100 of Figure 1, the DB interface 180-1A of the interposer 150 may be joined (e.g., electrically and mechanically) with the DB interface 180-1B of the microelectronic component 102-1 so as to form a DB region 130-1 that connects the interposer 150 and the microelectronic component 102-1. As further shown in Figure 2, the microelectronic component 102-2 may be coupled to the interposer 150 by the DB region 130-2 (via DB interfaces 180-2A and 180-2B). More generally, the DB region 130 disclosed herein may include two complementary DB interfaces 180 that are joined together, but for the sake of ease of illustration, many of the subsequent figures may omit identification of the DB interfaces 180 to improve clarity of the drawings.Figures 1 and 2 show first and second microelectronic components that are single-sided (meaning that only individual microelectronic components 102 have conductive contacts (e.g., DB contacts 110) on a single surface of the individual microelectronic component 102), but the microelectronic component 102 may also be double-sided (meaning that individual microelectronic components 102 may have conductive contacts on multiple surfaces of the individual microelectronic component 102).

[0022] The microelectronic assembly 100 may also include a third microelectronic component 102-3 bonded to the first and second microelectronic components 102-1, 102-2 by fusion bonding regions and / or direct bonding regions, as described below with reference to Figures 4A to 4D. In some embodiments, the third microelectronic component 102-3 may not include a conductive structure on its bottom surface (e.g., it may be blank or passive), as shown in Figure 1, such that the dielectric on the bottom surface of the third microelectronic component 102-3 is bonded to the intercomponent filler material 126 and the single-sided first and second microelectronic components 102-1, 102-2 via fusion bonding. In such embodiments, the third microelectronic component 102-3 may further include passive heat dissipation features or structures to conduct and dissipate heat from the first and second microelectronic components 102-1, 102-2. In some embodiments, as shown in Figure 5, the third microelectronic component 102-3 may include a conductive structure on its bottom and / or top surface (for example, an active wafer or die) such that the conductive contact and / or dielectric material on the bottom surface of the third microelectronic component 102-3 is coupled via direct bonding to the conductive contact on the top surface of the double-sided first and second microelectronic components 102-1, 102-2.

[0023] As used herein, the term “direct bonding” is used to include metal-to-metal bonding techniques (e.g., copper-to-copper bonding, or other techniques in which contact is first brought to the DB contacts 110 at opposing DB interfaces 180, followed by heat and / or compression), and hybrid bonding techniques (e.g., techniques in which contact is first brought to the DB dielectrics 108 at opposing DB interfaces 180, followed by heat and optionally compression, or techniques in which contact is brought substantially simultaneously to the DB contacts 110 and DB dielectrics 108 at opposing DB interfaces 180, followed by heat and compression). In such techniques, contact is brought to the DB contacts 110 and DB dielectrics 108 at one DB interface 180, respectively, with contact being brought to the DB contacts 110 and DB dielectrics 108 at another DB interface 180, and high pressure and / or temperature may be applied to bond the contacting DB contacts 110 and / or the contacting DB dielectrics 108. In some embodiments, this joint can be achieved without the use of interfering solder or anisotropic conductive material, but in some other embodiments, a thin cap of solder may be used in the DB interconnect to adapt to planarity, and this solder may become an intermetallic compound (IMC) in the DB region 130 during processing. DB interconnects may be capable of reliably transmitting higher currents than other types of interconnects, for example, some conventional solder interconnects may form a large volume of brittle IMC when current flows, but the maximum current supplied through such interconnects may be constrained to mitigate mechanical failure. As used herein, the term “fusion bonding” means a dielectric-to-dielectric bonding technique (e.g., a technique that brings about contact with dielectrics at opposing interfaces, which are then subjected to heat and, optionally, compression).

[0024] The DB dielectric 108 may comprise one or more dielectric materials, such as one or more inorganic dielectric materials. For example, the DB dielectric 108 may comprise silicon and nitrogen (e.g., in the form of silicon nitride), silicon and oxygen (e.g., in the form of silicon oxide), silicon, carbon, and nitrogen (e.g., in the form of silicon carbonitride), carbon and oxygen (e.g., in the form of carbon-doped oxides), silicon, oxygen, and nitrogen (e.g., in the form of silicon oxynitride), aluminum and oxygen (e.g., in the form of aluminum oxide), titanium and oxygen (e.g., in the form of titanium oxide), hafnium and oxygen (e.g., in the form of hafnium oxide), silicon, oxygen, carbon, and hydrogen (e.g., in the form of tetraethyl orthosilicate (TEOS)), zirconium and oxygen (e.g., in the form of zirconium oxide), niobium and oxygen (e.g., in the form of niobium oxide), or tantalum and oxygen (e.g., in the form of tantalum oxide), and combinations thereof. In some embodiments, the DB dielectric 108 is the same material as the interposer 150 and the microelectronic component 102, and therefore the DB dielectric 108 becomes an integrated part of the respective interposer 150 or the respective microelectronic component 102 (for example, the DB dielectric 108 may or may not be deposited as a separate material layer). In some embodiments, then, the DB dielectric 108 is a different material from the interposer 150 and / or the microelectronic component 102, and therefore the DB dielectric 108 is deposited as a separate material layer on the respective interposer 150 and / or the respective microelectronic component 102.

[0025] The microelectronic assembly 100 in Figure 1 may also include an intercomponent filler material 126. The intercomponent filler material 126 may extend between (e.g., around) one or more microelectronic components 102 on the interposer 150. In some embodiments, the intercomponent filler material 126 may extend between multiple microelectronic components 102 on the interposer 150 and around the DB region 130. In some embodiments, the intercomponent filler material 126 may extend over one or more microelectronic components 102 on the interposer 150 (not shown). The intercomponent filler material 126 may be an inorganic dielectric material such as silicon and nitrogen (e.g., in the form of silicon nitride), or silicon and oxygen (e.g., in the form of silicon oxide), and combinations thereof. The intercomponent filler material 126 may be deposited using any suitable technique, such as chemical vapor deposition (CVD), atomic layer deposition (ALD), plasma-assisted chemical vapor deposition (PECVD), spin coating, or vacuum lamination. The intercomponent filler material 126 may have a thickness between 10 microns and 250 microns. The intercomponent filler material 126 may consist of a single layer or multiple layers. The deposition process may be adjusted to optimize the mechanical and electrical properties (e.g., porosity and shrinkage) of the intercomponent filler material 126. In some embodiments, the intercomponent filler material 126 may extend to the microelectronic component 102, surround the microelectronic component 102 laterally, and in some embodiments (not shown), the intercomponent filler material 126 may cover the top surface of the microelectronic component 102. As used herein, the terms “intercomponent filler material,” “intercomponent material,” “die material,” “gap material,” “filler material,” and “dielectric material” around the microelectronic component may be interchangeable. In some embodiments, the intercomponent filler material 126 used in the microelectronic assembly 100 may be selected at least partially with respect to thermal properties to facilitate heat conduction (for example, as described below with reference to Figure 7).

[0026] The microelectronic assembly 100 in Figure 1 may also include a liner material 132. The liner material 132 may be placed on the DB dielectric 108 of the interposer 150 and on and around the first and second microelectronic components 102-1, 102-2. The liner material 132 may function as an etching stop or sealing barrier for the active surface of the interposer 150 (e.g., the conductive contact (not shown) and dielectric on the second surface 151-2 of the interposer 150) and all facets (e.g., the side and top surfaces) of the microelectronic components 102-1, 102-2, to limit the diffusion of conductive contacts and adjacent dielectrics (e.g., copper diffusion that may occur when the DB contact 110 contains copper and the DB dielectric 108 contains silicon oxide). In some embodiments, the liner material 132 may include silicon, carbon, and nitrogen (e.g., in the form of silicon carbonitride), silicon and nitrogen (e.g., in the form of silicon nitride), silicon, oxygen, and nitrogen (e.g., in the form of silicon oxynitride), or silicon and carbon (e.g., in the form of silicon carbide), and combinations thereof. The liner material 132 may be deposited using any suitable technique, e.g., CVD, ALD, or PECVD. During deposition, the processing temperature, pressure, and power may be adjusted to regulate the stress of the film and the subsequent stresses of the interposer 150 and the first and second microelectronic components 102-1, 102-2. The liner material 132 may have a thickness between 10 nanometers and 2000 nanometers. In some embodiments, the thickness of the liner material 132 may vary (for example, the liner material 132 may be thicker on the top surface of the interposer 150 and the microelectronic component 102, and thinner on the side walls of the microelectronic component 102).

[0027] The interposer 150 may be referred to as the “bottom die” or “base wafer.” The interposer 150 may include an insulating material 106 (e.g., one or more dielectric materials formed in multiple layers, as known in the art) and one or more conductive paths 112 (e.g., including conductive wires 114 and / or conductive vias 116, as shown) through the insulating material 106. In some embodiments, the insulating material 106 of the interposer 150 includes inorganic dielectric materials such as silicon and nitrogen (e.g., in the form of silicon nitride), silicon and oxygen (e.g., in the form of silicon oxide), silicon and carbon (e.g., in the form of silicon carbide), silicon, carbon and oxygen (e.g., in the form of silicon oxycarbide), silicon, carbon and nitrogen (e.g., in the form of silicon carbonitride), carbon and oxygen (e.g., in the form of carbon-doped oxides), silicon, oxygen and nitrogen (e.g., in the form of silicon oxynitride), or silicon, oxygen, carbon and hydrogen (e.g., in the form of tetraethyl orthosilicate (TEOS)), and combinations thereof. In some embodiments, the insulating material 106 of the interposer 150 includes insulating metal oxides such as aluminum and oxygen (e.g., in the form of aluminum oxide), titanium and oxygen (e.g., in the form of titanium oxide), hafnium and oxygen (e.g., in the form of hafnium oxide), zirconium and oxygen (e.g., in the form of zirconium oxide), niobium and oxygen (e.g., in the form of niobium oxide), or tantalum and oxygen (e.g., in the form of tantalum oxide), and combinations thereof. In some embodiments, the interposer 150 may be semiconductor-based (e.g., silicon-based) or glass-based. In some embodiments, the interposer 150 is a silicon wafer or die. In some embodiments, the interposer 150 may be a silicon-on-insulator (SOI) and may further include layers such as silicon and germanium (e.g., in the form of silicon-germanium), gallium and nitrogen (e.g., in the form of gallium nitride), indium and phosphorus (e.g., in the form of indium phosphide).

[0028] In some embodiments, the insulating material 106 of the interposer 150 may be an organic material such as polyimide or polybenzoxasol, or it may include an organic polymer matrix (e.g., epoxide) containing a filler material (which may be inorganic, such as silicon nitride, silicon oxide, or aluminum oxide). In some such embodiments, the interposer 150 may be referred to as an “organic interposer”. In some embodiments, the insulating material 106 of the interposer 150 is provided in multiple layers consisting of an organic build-up film. The organic interposer 150 can be manufactured at a lower cost than semiconductor or glass-based interposers, and offers the advantages of electrical performance due to the low dielectric constant of the organic insulating material 106, and may have thicker wires that can be used, allowing for improved potential for power distribution, signaling, and thermal advantages. The organic interposer 150 may also have a larger footprint than that which can be achieved with semiconductor-based interposers, which is limited by the size of the reticle used for patterning. Furthermore, the organic interposer 150 is subject to fewer design rule limitations than semiconductor or glass-based interposers, allowing for the use of design features such as non-Manhattan routing (e.g., not restricted to using one layer for horizontal interconnects and another for vertical interconnects) and the avoidance of through-substrate vias (TSVs) such as through-silicon vias or through-glass vias (which limit the achievable pitch and result in reduced desired power distribution and signaling performance). Conventional integrated circuit packages, including organic interposers, are limited to solder-based mounting techniques, which can limit the achievable pitch to a lower level, excluding the use of conventional solder-based interconnects to achieve the finer pitches desired for next-generation devices.The use of an organic interposer 150 in a microelectronic assembly 100 by direct bonding, as disclosed herein, can leverage these advantages of organic interposers in combination with ultrafine pitches (e.g., pitch 128 described below) that are achievable by direct bonding (previously only achievable with semiconductor-based interposers), and thus can support the design and manufacture of large-scale, sophisticated die composites that can achieve package system competitive performance and capabilities not possible with conventional approaches.

[0029] In other embodiments, the insulating material 106 of the interposer 150 may include flame-retardant grade 4 material (FR-4), bismaleimidotriazine (BT) resin, or low-k or ultra-low-k dielectrics (e.g., carbon-doped dielectrics, fluorine-doped dielectrics, and porous dielectrics). When the interposer 150 is formed using standard printed circuit board (PCB) processing, the insulating material 106 may include FR-4, and the conductive paths 112 in the interposer 150 may be formed by patterned sheets of copper separated by a build-up layer of FR-4. In some such embodiments, the interposer 150 may be referred to as a “package substrate” or “circuit board”.

[0030] In some embodiments, one or more conductive paths 112 in the interposer 150 may extend between conductive contacts on the upper surface of the interposer 150 (e.g., one of the DB contacts 110) and conductive contacts 118 on the lower surface of the interposer 150. In some embodiments, one or more conductive paths 112 in the interposer 150 may extend between different conductive contacts on the upper surface of the interposer 150 (e.g., between different DB contacts 110 in potentially different DB regions 130, as further described below). In some embodiments, one or more conductive paths 112 in the interposer 150 may extend between different conductive contacts 118 on the lower surface of the interposer 150.

[0031] In some embodiments, the interposer 150 includes only the conductive path 112 and does not include any active or passive circuits. In other embodiments, the interposer 150 may include active or passive circuits (e.g., transistors, diodes, resistors, inductors, and capacitors). In some embodiments, the interposer 150 may include one or more device layers, including transistors.

[0032] In some embodiments, the microelectronic component 102 may include an IC die (packaged or unpackaged) or a stack of IC dies (e.g., a high-bandwidth memory die stack). In some such embodiments, the insulating material of the microelectronic component 102 may include silicon dioxide, silicon nitride, oxynitride, polyimide material, glass-reinforced epoxy matrix material, or low-k or ultra-low-k dielectric (e.g., carbon-doped dielectric, fluorine-doped dielectric, porous dielectric, organic polymer dielectric, photosensitive dielectric, and / or benzocyclobutene-based polymer). In some further embodiments, the insulating material of the microelectronic component 102 may include semiconductor materials such as silicon, germanium, or III-V material (e.g., gallium nitride), and one or more additional materials. For example, the insulating material of the microelectronic component 102 may include silicon dioxide or silicon nitride. Conductive paths in the microelectronic component 102 may include conductive wires and / or conductive vias and may be connected to several conductive contacts in the microelectronic component 102 in any preferred manner (e.g., connecting conductive contacts on the same or different surfaces of the microelectronic component 102). Examples of structures that may be included in the microelectronic component 102 disclosed herein are described later with reference to Figure 9. In particular, the microelectronic component 102 may include active and / or passive circuits (e.g., transistors, diodes, resistors, inductors, and capacitors). In some embodiments, the microelectronic component 102 may include one or more device layers including transistors. When the microelectronic component 102 includes active circuits, power and / or ground signals may be routed via the interposer 150 and to and from the microelectronic component 102 via the DB area 130 (and further via interfering the microelectronic component 102). In some embodiments, the microelectronic component 102 may take several forms of the embodiments of the interposer 150 described herein.Although the microelectronic component 102 of the microelectronic assembly 100 in Figure 1 is a single-sided component, in some embodiments the microelectronic component 102 may be a double-sided (or "multilevel" or "omnidirectional") component having conductive contacts on multiple faces of the component. Specific examples of double-sided microelectronic components 102 are described later with reference to Figure 5.

[0033] The DB contact 110 may include pillars, pads, or other structures. Although the DB contact 110 is shown in the same manner in the accompanying drawings at both DB interfaces 180 of the DB region 130, both DB interfaces 180 may have the same structure, or the DB contacts 110 at different DB interfaces 180 may have different structures. For example, in some embodiments, the DB contact 110 at one DB interface 180 may include a metal pillar (e.g., a copper pillar), and the complementary DB contact 110 at the complementary DB interface 180 may include a metal pad (e.g., a copper pad) in the dielectric recess. The DB contact 110 may include any one or more conductive materials such as copper, manganese, titanium, gold, silver, palladium, nickel, copper and aluminum (e.g., in the form of copper-aluminum alloys), tantalum (e.g., tantalum and nitrogen in the form of tantalum metal or tantalum nitride), cobalt, cobalt and iron (e.g., in the form of cobalt-iron alloys), or any alloy of any of the aforementioned materials (e.g., copper, manganese, and nickel in the form of manganin). Several specific arrangements of multiple materials for the DB contact 110 will be described later with reference to Figure 3. In some embodiments, the DB dielectric 108 of the DB interface 180 and the DB contact 110 may be manufactured using low-temperature deposition techniques such as low-temperature plasma-assisted chemical vapor deposition (PECVD) (e.g., techniques in which deposition occurs at temperatures below 250 degrees Celsius or below 200 degrees Celsius).

[0034] Figure 1 shows a specific number of microelectronic components 102 coupled to the interposer 150 by the DB region 130, but this number and arrangement is merely illustrative, and the microelectronic assembly 100 may include any desired number and arrangement of microelectronic components 102 coupled to the interposer 150 by the DB region 130. A single reference numeral "108" is used to refer to DB dielectrics of multiple different DB interfaces 180 (and different DB regions 130), but this is merely for illustrative purposes, and DB dielectrics 108 of different DB interfaces 180 (even within a single DB region 130) may have different materials and / or structures. Similarly, a single reference numeral "110" is used to refer to DB contacts of multiple different DB interfaces 180 (and different DB regions 130), but this is merely for illustrative purposes, and DB contacts 110 of different DB interfaces 180 (even within a single DB region 130) may have different materials and / or structures. In Figures 1 and 2, the DB contact 110 is shown as a pad in the underlying insulating material 106 that contacts the via 116. In other embodiments, the DB contact 110 is a via itself. For example, in one embodiment where the DB contact 110 is a via that contacts a pad in the insulating material 106, the DB contact 110 may be narrower than the pad they contact.

[0035] Different DB regions 130 in the microelectronic assembly 100 may contain different DB dielectrics 108. For example, a microelectronic assembly 100 in which DB region 130-1 contains DB dielectric 108-1 and DB region 130-2 contains a different DB dielectric 108-2. DB dielectrics 108-1 and 108-2 may differ in their material composition and / or structure. In some embodiments, DB dielectrics 108 in different DB regions 130 may be selected to have different thermal conductivity to facilitate and / or limit heat conduction between the interposer 150 and the microelectronic component 102. For example, DB dielectric 108-1 may have higher thermal conductivity than DB dielectric 108-2, resulting in greater heat conduction between microelectronic component 102-1 and the interposer 150 than between microelectronic component 102-2 and the interposer 150. In some such embodiments, DB dielectric 108-1 may contain silicon and nitrogen (e.g., in the form of silicon nitride), and DB dielectric 108-2 may contain silicon and oxygen (e.g., in the form of silicon oxide), where silicon nitride may have higher thermal conductivity than silicon oxide. Therefore, the use of silicon nitride as DB dielectric 108-1 may increase local heat conduction from microelectronic component 102-1 to the interposer 150, while the use of silicon oxide as DB dielectric 108-2 may reduce thermal crosstalk between microelectronic component 102-1 and microelectronic component 102-2 through the interposer 150. In embodiments of Figures 1 and 2, DB dielectric 108 extends outside the DB region 130 and covers the rest of the upper surface of the interposer 150. In other embodiments, different materials may be placed on the upper surface of the interposer 150 outside the DB region 130 (e.g., in contact with the intercomponent filler material 126).

[0036] In some embodiments, the density of the DB contacts 110 (i.e., the percentage of the bonding surface area of ​​the DB interface 180 occupied by the DB contacts 110) may differ among different DB regions 130. In some embodiments, this difference in density may result from one DB region 130 requiring fewer electrical paths than another DB region 130. In other embodiments, this difference in density may be used to increase or decrease thermal conductivity, with higher density DB contacts 110 (and therefore a larger percentage of thermally conductive metal) being used to increase thermal conductivity, and lower density DB contacts 110 (and therefore a smaller percentage of thermally conductive metal) being used to decrease thermal conductivity. For example, the density of the DB contacts 110 may be greater in DB region 130-1 than in DB region 130-2 to increase thermal conductivity between microelectronic component 102-1 and the interposer 150 and decrease thermal conductivity between microelectronic component 102-2 and the interposer 150. In some embodiments, the two DB regions 130 may have DB dielectrics 108 having the same material composition but DB contacts 110 of different densities.

[0037] Additional components (not shown), such as surface-mounted resistors, capacitors, and / or inductors, may be located on the top or bottom surface of the interposer 150, or embedded in the interposer 150. The microelectronic assembly 100 in Figure 1 also includes a support component 182 coupled to the interposer 150. In a particular embodiment of Figure 1, the support component 182 includes a conductive contact 118 electrically coupled to a complementary conductive contact 118 of the interposer 150 by interference solder 120 (e.g., solder balls in a ball grid array (BGA) arrangement), but any suitable interconnection structure (e.g., pins-in-a-pin grid array arrangement, lands-in-a-land grid array arrangement, pillars, pads and pillars, etc.) may be used. The solder 120 used in the microelectronic assembly 100 disclosed herein may include suitable materials such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, the coupling of the interposer 150 and the support component 182 may be referred to as a second-level interconnect (SLI) or multi-level interconnect (MLI).

[0038] In some embodiments, the support component 182 may be a package substrate (for example, it may be manufactured using PCB processing as described above). In some embodiments, the support component 182 may be a circuit board (for example, a motherboard) and may have other components (not shown) to which it is mounted. The support component 182 may include conductive paths and other conductive contacts (not shown) for routing power, ground, and signals through the support component 182, as is known in the Art. In some embodiments, the support component 182 may include another IC package, an interposer, or any other suitable component. The underfill material 138 may be disposed around the solder 120, the interposer 150, the intercomponent filler material 126, and at least portion of the microelectronic components 102-3 that bond the interposer 150, which includes the microelectronic components 102, to the support component 182. In some embodiments, the underfill material 138 may include an epoxy material.

[0039] In some embodiments, the support component 182 may be a lower-density component, while the interposer 150 and / or microelectronic component 102 may be a higher-density component. As used herein, the terms “lower density” and “higher density” are relative terms indicating that the conductive paths (e.g., including conductive wires and conductive vias) in the lower-density component are wider and / or have a larger pitch than the conductive paths in the higher-density component. In some embodiments, the microelectronic component 102 may be a higher-density component, and the interposer 150 may be a lower-density component. In some embodiments, the higher-density component may be manufactured using dual damascene or single damascene processing (e.g., when the higher-density component is a die), while the lower-density component may be manufactured using quasi-additive or modified quasi-additive processing (e.g., when the lower-density component is a package substrate or interposer) (by small vertical interconnect features formed by high-performance laser or lithography processing). In some other embodiments, higher-density components may be manufactured using quasi-additive or modified quasi-additive processes (e.g., when the higher-density component is a package substrate or interposer), while lower-density components may be manufactured using quasi-additive or subtractive processes (e.g., when the lower-density component is a PCB) (by using etching chemicals to remove unwanted metallic areas and by rough extended interconnect features formed by standard laser processing).

[0040] The microelectronic assembly 100 in Figure 1 may also include a thermal interface material (TIM) (not shown). The TIM may include a thermally conductive material (e.g., metal particles) in a polymer or other binder. The TIM may be a thermal interface material paste or a thermally conductive epoxy (which may be fluid-like or viscous when added and harden upon curing, as is known in the art). The TIM may also include a soldering material (e.g., indium). The TIM may provide a pathway for the heat generated by the microelectronic component 102 so that it flows readily into a thermal transition structure from which the heat spreads and / or dissipates.

[0041] The microelectronic assembly 100 in Figure 1 may also include a thermal transition structure (not shown). The thermal transition structure may be used to allow heat to be released from one or more microelectronic components 102 (for example, so that heat can be more easily dissipated). The thermal transition structure may include a suitable thermally conductive material (e.g., a metal, a suitable ceramic, etc.) and may include any suitable features (e.g., a heat spreader including fins, a cold plate, etc., a heat sink). In some embodiments, the thermal transition structure may be or include an integrated heat spreader (IHS).

[0042] The elements of the microelectronic assembly 100 may have appropriate dimensions. Only a subset of the accompanying drawings are labeled with reference numerals indicating dimensions, this is solely for illustrative purposes, and any of the microelectronic assemblies 100 disclosed herein may have components having the dimensions described herein. In some embodiments, the thickness 184 of the interposer 150 may be between 20 and 200 microns. In some embodiments, the thickness 188 of the DB region 130 may be between 50 nanometers and 5 microns. In some embodiments, the thickness 190 of the microelectronic component 102 may be between 5 and 800 microns. In some embodiments, the thickness 190 of the microelectronic component 102 may be between 5 and 250 microns. In some embodiments, the thickness 190 of the microelectronic component 102 may be less than 40 microns (e.g., between 5 and 40 microns). In some embodiments, the pitch 128 of the DB contact 110 in the DB region 130 may be less than 20 microns (e.g., between 0.1 and 20 microns).

[0043] Numerous elements are shown in Figure 1 as being included in the microelectronic assembly 100, but these numerous elements are not required to be shown in the microelectronic assembly 100. For example, in various embodiments, microelectronic components 102-3, underfill material 138, and / or support components 182 may not be included. Furthermore, Figure 1 shows numerous elements that may be included in any of the microelectronic assemblies 100 disclosed herein, although these are omitted from subsequent figures for ease of illustration. Examples of such elements include underfill material 138 and / or support components 182. Many of the elements of the microelectronic assembly 100 in Figure 1 are also included in other figures of the accompanying drawings, and the description of those elements is not repeated when describing those drawings, but any of those elements may take any form disclosed herein. In some embodiments, individual microelectronic assemblies 100 disclosed herein may function as a system-in-package (SiP) containing multiple microelectronic components 102 having different functions. In such embodiments, the microelectronic assembly 100 may be referred to as a SiP. Figures 1 and 2 (and others in the accompanying drawings) illustrate specific numbers and arrangements of conductive paths 112 in the interposer 150, but these are merely illustrative, and any suitable number and arrangement may be used. The conductive paths 112 disclosed herein (including, for example, lines 114 and / or vias 116) may be formed of any suitable conductive material, such as copper, silver, nickel, gold, aluminum, other metals or alloys, or combinations of materials.

[0044] The microelectronic assemblies 100 disclosed herein may be manufactured in any preferred manner. For example, Figures 3A to 3G are side cross-sectional views of exemplary steps in the manufacture of parts of the microelectronic assemblies 100 of Figures 1 and 2 according to various embodiments. The operations described with reference to Figures 3A to 3G may be shown with reference to specific embodiments of the microelectronic assemblies 100 disclosed herein, but the manufacturing methods described with reference to Figures 3A to 3G may be used to form any suitable microelectronic assembly 100. The operations are shown once each in a specific order in Figures 3A to 3G, but the operations may be reordered and / or repeated as desired (for example, by different operations performed in parallel when multiple microelectronic assemblies 100 are manufactured simultaneously). However, any suitable manufacturing process may be used to manufacture any of the microelectronic assemblies 100 disclosed herein.

[0045] Figure 3A shows an interposer 150 including two exposed DB interfaces 180-1 and 180-2. In some embodiments, the interposer 150 may be mounted on a carrier (not shown). The carrier may include any suitable material that provides mechanical support and stability, such as a glass panel. In some embodiments, the interposer may include a semiconductor wafer (e.g., a silicon wafer).

[0046] Figure 3B shows the assembly after the microelectronic components 102-1 and 102-2 have been directly bonded to the interposer 150 in Figure 3A. In particular, the DB interface 180 (unlabeled) of the microelectronic component 102 may come into contact with the DB interface 180 of the interposer 150, and heat and / or pressure may be applied to bond the contacting DB interfaces 180 to form DB regions 130 (DB regions 130-1 and 130-2, corresponding to DB interfaces 180-1 and 180-2, respectively).

[0047] Figure 3C shows the assembly after thinning the microelectronic component 102. The microelectronic component 102 can be thinned and planarized using any suitable technique, including, for example, mechanical polishing and chemical mechanical planarization (CMP). In some embodiments, the microelectronic component 102 is thinned to a thickness between 5 microns and 250 microns. In some embodiments, the microelectronic component 102 is thinned to a thickness of less than 40 microns. In some embodiments, a temporary, removable protective material may be deposited around the microelectronic component 102 before thinning to aid in the uniformity of the thinning process. In some embodiments, the thinning process may include dry plasma etching (e.g., SF6) or wet etching with time-based etching or an etching stop layer (e.g., silicon oxide) (e.g., using potassium hydroxide or tetramethylammonium hydroxide solution). In some embodiments, the thinning process may include hydrogen implantation or ion cutting techniques. In some embodiments, the thinning process further includes forming microcracks (e.g., similar to gettering polishing) to minimize metal migration to silicon.

[0048] Figure 3D shows the assembly of Figure 3C after the liner material 132 has been provided around the microelectronic components 102 and on the surfaces of the interposer 150. The liner material 132 may be deposited using any suitable technique, including, for example, CVD, ALD, or PECVD processing.

[0049] Figure 3E shows the assembly after the intercomponent filler material 126 has been provided on the liner material 132. The intercomponent filler material 126 may be deposited using any suitable technique, for example, including PECVD treatment or spin coating and subsequent thermal annealing treatment. In some embodiments, the intercomponent filler material 126 may extend over and remain above the microelectronic component 102, but in other embodiments, as shown, the intercomponent filler material 126 is polished back to expose the liner material 132 on the upper surface of the microelectronic component 102. In some embodiments, the intercomponent filler material 126 may be planarized using CMP, and subsequent semiconductor treatments may be performed, for example, damascene treatment or quasi-additive treatment, as described below with reference to Figure 5.

[0050] Figure 3F shows the assembly after bonding a third microelectronic component 102-3 onto the intercomponent filler material 126 and the first and second microelectronic components 102-1, 102-2. The third microelectronic component 102-3 may be bonded to the assembly by fusion bonding or direct bonding, as described below with reference to Figures 4A to 4D. The third microelectronic component 102-3 may be referred to as a “handle die”. The assembly in Figure 3F may be the microelectronic assembly 100 itself, as shown. Further manufacturing operations may be performed on the microelectronic assembly 100 of Figure 3F to form the microelectronic assembly 100, for example, as shown in Figure 3G. The assembly in Figure 3F may function mechanically as a monolithic wafer.

[0051] Figure 3G shows the assembly after solder 120 has been applied to the conductive contact 118 to bond the microelectronic assembly 100 of Figure 3F to the support component 182, and underfill material 138 has been applied around the solder 120 to extend to the third microelectronic component 102-3 to form the microelectronic assembly 100 of Figure 1. When carriers are used, they are removed before applying solder 120 to the conductive contact 118.

[0052] Figures 4A to 4D are enlarged side cross-sectional views of the dotted line portion of Figure 3G, showing exemplary bonding interfaces according to various embodiments. Figure 4A shows the portion of the interface between the first and second microelectronic components 102-1, 102-2 and the third microelectronic component 102-3, which has a single-material interface. As shown in Figure 4A, the intercomponent filler material 126 is present around the first and second microelectronic components 102-1, 102-2 and covers their upper surfaces, so that the third microelectronic component 102-3 forms an interface only with the intercomponent filler material 126, forming a single fusion bonding interface.

[0053] Figure 4B shows the interface between the first and second microelectronic components 102-1, 102-2 and the third microelectronic component 102-3, which has a mixed-material interface. As shown in Figure 4B, the intercomponent filler material 126 is around the first and second microelectronic components 102-1, 102-2 (for example, filling the space between the upper surfaces of the first and second microelectronic components 102-1, 102-2, but not covering it), and the liner material 132 covers the upper surfaces of the first and second microelectronic components 102-1, 102-2, so that the third microelectronic component 102-3 forms an interface with the intercomponent filler material 126 and the liner material 132 to form a mixed-material fusion interface.

[0054] Figure 4C shows the interface between the first and second microelectronic components 102-1, 102-2 and the third microelectronic component 102-3, which has a single-material interface. As shown in Figure 4C, the intercomponent filler material 126 is around the first and second microelectronic components 102-1, 102-2 (for example, it fills the space between the upper surfaces of the first and second microelectronic components 102-1, 102-2, but does not cover it), and the liner material 132 (for example, the second liner material 132-2) covers the upper surfaces of the first and second microelectronic components 102-1, 102-2, similar to the intercomponent filler material 126, so that the third microelectronic component 102-3 forms an interface only with the second liner material 132-2 to form a single fusion junction interface. At such an interface, a first liner material 132-1 is deposited, followed by an intercomponent filler material 126, and then a second liner material 132-2 is deposited. In some embodiments, the first and second liner materials 132-1 and 132-2 are the same material. In some embodiments, the first liner material 132-1 is a different material from the second liner material 132-2.

[0055] Figure 4D shows the portion of the interface between the first and second microelectronic components 102-1, 102-2 and the third microelectronic component 102-3, which has yet another single-material interface. As shown in Figure 4D, the material layer 134 is deposited on the intercomponent filler material 126 around the first and second microelectronic components 102-1, 102-2 and on the liner material 132 covering the upper surfaces of the first and second microelectronic components 102-1, 102-2, so that the third microelectronic component 102-3 forms an interface only with the material layer 134 to form a single fusion junction interface. In some embodiments, the material layer 134 may include silicon, carbon and nitrogen (e.g., in the form of silicon carbonitride), silicon and nitrogen (e.g., in the form of silicon nitride), silicon, oxygen and nitrogen (e.g., in the form of silicon oxynitride), silicon and carbon (e.g., in the form of silicon carbide), silicon, oxygen, carbon and hydrogen (e.g., in the form of tetraethyl orthosilicate (TEOS)), and the like.

[0056] The microelectronic assembly 100 may include multiple "tiers" of microelectronic components 102 joined by at least one direct bonding region. For example, Figure 5 shows a microelectronic assembly 100 in which microelectronic components 102-1 and 102-2 include conductive contacts (unlabeled) on their top and bottom surfaces, the conductive contact on the bottom surface being directly bonded to the interposer 150, and the conductive contact on the top surface being directly bonded to microelectronic component 102-3. In an embodiment in which microelectronic components 102-1 and 102-2 are directly bonded to the interposer 150 at their bottom surfaces and microelectronic component 102-3 is directly bonded at its top surface, the microelectronic assembly 100 in Figure 5 may be described as having two tiers that are directly bonded to the microelectronic components 102. In embodiments where the interposer 150 is an active interposer (e.g., an active wafer or active die), the microelectronic assembly 100 in Figure 5 may be described as a “three-layer active die composite,” where the upper die (e.g., microelectronic component 102-3) can be powered on and functional. In such embodiments, the interposer 150 may be referred to as the first or bottom tier, the first and second microelectronic components 102-1, 102-2 may be referred to as the second or middle tier, and the third microelectronic component 102-3 may be referred to as the top or third tier. For example, the third tier may include a high-power central processing unit (CPU) or graphics processing unit (GPU) (e.g., an active die including processing circuits), the second tier may include a memory die (e.g., an active die including memory circuits), and the first tier may include power distribution circuits and functions that supply power to the second and third tier components. In another example, the third tear die may include a thermoelectric Peltier cooling circuit active thermal management die that manages heat flow and throttling to maximize the performance of the three-layer active die composite. More generally, any microelectronic component 102 disclosed herein may include one or more dies and may have different types of pass-through conductive interconnects, such as copper pillars and TSVs (e.g., through-silicon vias).

[0057] In some embodiments, the microelectronic components 102-1 and 102-2 may further include a conductive structure 194 extending between their top and bottom surfaces, providing a conductive path for power, ground, and / or signals to the microelectronic component 102-3 in a third tier. In some embodiments, such a conductive structure 194 may include one or more TSVs, such as through-silicon vias when the microelectronic components 102-1 and 102-2 include a silicon substrate, or through-glass vias when the microelectronic components 102-1 and 102-2 include a glass substrate, including conductive material vias such as metal vias insulated by an oxide barrier from surrounding silicon or other semiconductor material. In some embodiments, the microelectronic components 102-1 and 102-2 may be passive (e.g., without transistors) or active (e.g., including transistors in the form of memory circuits and / or power distribution circuits).

[0058] As shown in Figure 5, the microelectronic assembly 100 may further include a conductive structure 193 that extends between the second surface 151-2 of the interposer 150 and the bottom surface of the third microelectronic components 102-3 (e.g., through the liner material 132 and the intercomponent filler material 126) and provides a conductive path for direct power, ground, and / or signals to the third microelectronic components 102-3 of the third tier.

[0059] Figure 6A shows the assembly after the microelectronic components 102-1 and 102-2 having a conductive structure 194 are directly bonded to the interposer 150. In particular, the DB interface 180 (unlabeled) of the microelectronic component 102 may come into contact with the DB interface 180 of the interposer 150, and heat and / or pressure may be applied to bond the contacting DB interfaces 180 to form DB regions 130 (DB regions 130-1 and 130-2 corresponding to DB interfaces 180-1 and 180-2, respectively).

[0060] Figure 6B shows the assembly after the microelectronic component 102 has been thinned to expose the conductive structure 194 on the upper surface of the microelectronic component 102. The microelectronic component 102 may be thinned and planarized using any suitable technique, including, for example, the technique described above with reference to Figure 3C.

[0061] Figure 6C shows the assembly of Figure 6B after the liner material 132 has been provided around the microelectronic components 102 and on the surfaces of the interposer 150. The liner material 132 may be deposited using any suitable technique, including, for example, those described.

[0062] Figure 6D shows the assembly after the intercomponent filler material 126 has been provided on the liner material 132. The intercomponent filler material 126 may be deposited using any suitable technique, including, for example, those described above with reference to Figure 3E. The intercomponent filler material 126 may be polished back to its original state or etched so that it is exposed on the upper surface of the microelectronic components 102. In some embodiments, the liner material 132 may be removed, for example, when the liner material 132 has conductive properties. In some embodiments, the liner material 132 may not be removed, for example, when the liner material 132 helps to insulate from copper or other metals or to prevent their diffusion. The intercomponent filler material 126 may be planarized using CMP and subsequent semiconductor processing may be performed.

[0063] Figure 6E shows the assembly after forming a conductive structure 193 via intercomponent filler material 126, and then depositing a dielectric material 199 by forming a conductive structure 197 on the upper surface of the intercomponent filler material 126 and microelectronic components 102-1, 102-2 using any suitable technique such as damascene processing.

[0064] Figure 6F shows the assembly after the third microelectronic component 102-3 has been directly bonded to the top surface of the assembly in Figure 6E. The assembly in Figure 6F may be the microelectronic assembly 100 itself, as shown. Further manufacturing operations may be performed on the microelectronic assembly 100 of Figure 6F to form the microelectronic assembly 100. For example, the assembly in Figure 6F may be further processed to form the microelectronic assembly of Figure 5 by providing solder 120 to conductive contacts 118 and using the solder 120 to bond the microelectronic assembly 100 of Figure 6F to the support component 182, and providing an underfill material 138 that is around the solder 120 and extends to the third microelectronic component 102-3.

[0065] Figure 7 is a side cross-sectional view of a microelectronic assembly 100 according to various embodiments. The microelectronic assembly 100 may include an interposer 150, a first microelectronic component 102-1, a second microelectronic component 102-2, a liner material 132, a thermally conductive intercomponent filler material 127 selected with respect to thermal properties that at least partially facilitate heat conduction, and a thermally conductive bulk material 103 selected with respect to thermal properties that at least partially facilitate heat conduction. In some embodiments, the thermally conductive intercomponent filler material 127 may include thermally conductive metals, ceramics, or composite particles, or materials including copper, aluminum, silver, diamond, graphene, silicon and carbon (e.g., in the form of silicon carbide), boron and nitrogen (e.g., in the form of boron nitride), or aluminum and nitrogen (e.g., in the form of aluminum nitride), and combinations thereof. The thermally conductive intercomponent filler material 127 may provide pathways for spreading and / or dissipating the heat generated by the first and / or second microelectronic components 102-1, 102-2. The thermally conductive intercomponent filler material 127 may further contain a solvent or polymer that may or may not dissipate during processing (e.g., after curing or sintering of the intercomponent filler material) to aid in the dispersibility of the material. The thermally conductive intercomponent filler material 127 may be deposited using any suitable technique, such as stencil / screen printing, additive manufacturing, electroplating, non-electroplating, or as described above with reference to Figure 3E. The thermally conductive intercomponent filler material 127 may have a thickness between 10 microns and 250 microns. The thermally conductive intercomponent filler material 127 may consist of a single layer or multiple layers. The deposition process can be adjusted to optimize mechanical and electrical properties (e.g., porosity and shrinkage) and to prevent voids in the thermally conductive intercomponent filler material 127. In some embodiments, the thicknesses of the first and second microelectronic components 102-1, 102-2 can be optimized to reduce the aspect ratio of the intercomponent space, which can aid in the deposition of void-free thermally conductive intercomponent filler material 127.In some embodiments, the thermally conductive intercomponent filler material 127 may extend to and surround the microelectronic component 102 laterally, and in some embodiments (not shown), the thermally conductive intercomponent filler material 127 may cover the upper surface of the microelectronic component 102. Any thermally conductive intercomponent filler material 127 as referred to herein may comprise one or more different materials having different material compositions.

[0066] The microelectronic assembly 100 in Figure 7 may also include a liner material 132, at least partially selected, whose thermal properties facilitate heat conduction. The liner material 132 may be placed on the DB dielectric 108 of the interposer 150, and on and around the first and second microelectronic components 102-1, 102-2. The liner material 132 can function as a diffusion barrier to limit the diffusion of metals (e.g., copper diffusion that may occur when the intercomponent filler material 127 contains copper) on all facets (e.g., side and top surfaces) of the second surface 151-2 of the interposer 150 and the microelectronic components 102-1, 102-2, and / or as an adhesion promoter to improve the strength of the mechanical interfaces (e.g., between the DB dielectric 108 and the thermally conductive intercomponent filler material 127, between the top and side surfaces of the first and second microelectronic components 102-1, 102-2 and the thermally conductive intercomponent filler material 127, and / or between the first and second microelectronic components 102-1, 102-2 and the top surface of the thermally conductive bulk material 103). In some embodiments, the liner material 132 may include conductive materials such as titanium, tantalum, vanadium, nickel, ruthenium, cobalt, and / or iridium. Other examples of thermally conductive materials that can be used for the liner material include, but are not limited to, titanium and nitrogen (e.g., in the form of titanium nitride), tantalum and nitrogen (e.g., in the form of tantalum nitride), vanadium and nickel (e.g., in the form of nickel vanadium), or iridium and oxygen (e.g., in the form of iridium oxide), and combinations thereof. In some embodiments, the liner material 132 may include nonconductive materials such as silicon, carbon and nitrogen (e.g., in the form of silicon carbonitride), silicon and nitrogen (e.g., in the form of silicon nitride), silicon and carbon (e.g., in the form of silicon carbide), or titanium and oxygen (e.g., in the form of titanium oxide), and combinations thereof. The liner material 132 can be deposited using any suitable technique, such as CVD, ALD, or PECVD.During deposition, the temperature, pressure, and power of the process can be adjusted to regulate the stress on the film and the subsequent stress on the interposer 150 and the first and second microelectronic components 102-1, 102-2. The liner material 132 may have a thickness between 10 nanometers and 2000 nanometers. In some embodiments, the thickness of the liner material 132 may vary (for example, the liner material 132 may be thicker on the top surface of the interposer 150 and microelectronic component 102, and thinner on the side walls of the microelectronic component 102). The microelectronic assembly 100 in Figure 7 may be manufactured using any suitable manufacturing process, which includes the processes described in Figures 3A to 3G.

[0067] The thermally conductive bulk material 103 may include conductive metals such as copper, aluminum, or silver, or highly conductive nonmetals such as silicon and / or carbon (e.g., silicon, silicon carbide, or diamond). In some embodiments, the thermally conductive bulk material 103 may be in the form of a paste, which can be produced additively by distributing it onto the intercomponent filler material and the upper surfaces of the first and second microelectronic components 102-1, 102-2, and then heat-treating it. In some embodiments, the thermally conductive bulk material 103 may be constructed of thermally conductive metal or nonmetallic particles (e.g., from the material examples described above) which are produced additively by cold-spraying the intercomponent filler material and the upper surfaces of the first and second microelectronic components 102-1, 102-2. In some embodiments, the thermally conductive bulk material 103 may be in the form of a wafer or die (e.g., made of silicon, or silicon and carbon) bonded to the upper surface of the intercomponent filler material and the first and second microelectronic components 102-1, 102-2 using die-to-wafer or wafer-to-wafer bonding. The thickness of the thermally conductive bulk material 103 may be between 10 microns and 650 microns.

[0068] The microelectronic components 102 and microelectronic assemblies 100 disclosed herein may include any suitable electronic components. Figures 8 to 11 show various examples of devices which may or may include some of the microelectronic components 102 and microelectronic assemblies 100 disclosed herein, as they are applicable.

[0069] Figure 8 is a top view of a wafer 1500 and a die 1502, which may be included in any of the microelectronic components 102 disclosed herein. For example, a die 1502 may function as a microelectronic component 102 or be included in a microelectronic component 102. The wafer 1500 may be composed of a semiconductor material and may include one or more dies 1502 having a plurality of IC structures formed on the surface of the wafer 1500. Each die 1502 may be a repeating unit of a semiconductor product containing any suitable IC. After the manufacturing of the semiconductor product is complete, the wafer 1500 may undergo a unitization process in which the dies 1502 are separated from each other to provide separate “chips” of the semiconductor product. The die 1502 may include one or more transistors (e.g., some of the transistors 1640 in Figure 9, described later) and / or support circuits for routing electrical signals to the transistors and any other IC components. In some embodiments, the wafer 1500 or die 1502 may include memory devices (e.g., random access memory (RAM) devices such as static RAM (SRAM) devices, magnetic RAM (MRAM) devices, resistive RAM (RRAM®) devices, conductive bridge RAM (CBRAM) devices, etc.), logic devices (e.g., AND, OR, NAND, or NOR gates), or any other suitable circuit elements. Multiple of these devices may be combined on a single die 1502. For example, a memory array formed by multiple memory devices may be formed on the same die 1502 as a processing device (e.g., processing device 1802 in Figure 11) or other logic configured to store information in the memory devices or execute instructions stored in the memory array.

[0070] Figure 9 is a side cross-sectional view of an IC device 1600 which may include any microelectronic component 102 disclosed herein. For example, an IC device 1600 (e.g., as part of a die 1502, as described above with reference to Figure 8) may function as a microelectronic component 102 or may be included in a microelectronic component 102. One or more IC devices 1600 may be included in one or more dies 1502 (Figure 8). An IC device 1600 may be formed on a substrate 1602 (e.g., a wafer 1500 in Figure 8) and may be included in a die (e.g., a die 1502 in Figure 8). The substrate 1602 may be a semiconductor substrate composed of a semiconductor material system including, for example, an n-type or p-type material system (or a combination thereof). The substrate 1602 may include, for example, a crystalline substrate formed using a bulk silicon or silicon-on-insulator (SOI) base structure. In some embodiments, the substrate 1602 may be formed using alternative materials that may or may not be bonded to silicon, and these alternative materials include, but are not limited to, germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. Furthermore, materials classified as Group II-VI, III-V, or IV may also be used to form the substrate 1602. A small number of examples of materials on which the substrate 1602 may be formed are described herein, but any material that can serve as the basis for the IC device 1600 may be used. The substrate 1602 may be a standalone die (e.g., die 1502 in Figure 8) or part of a wafer (e.g., wafer 1500 in Figure 8).

[0071] The IC device 1600 may include one or more device layers 1604 disposed on the substrate 1602. The device layer 1604 may include feature portions of one or more transistors 1640 (e.g., metal-oxide-semiconductor field-effect transistors (MOSFETs)) formed on the substrate 1602. The device layer 1604 may include, for example, one or more source and / or drain (S / D) regions 1620, a gate 1622 for controlling the flow of current in the transistor 1640 between the S / D regions 1620, and one or more S / D contacts 1624 for transferring electrical signals to and from the S / D regions 1620. The transistor 1640 may include additional feature portions, such as device isolation regions and gate contacts, which are not shown for clarity. The transistor 1640 is not limited to the types and configurations shown in Figure 9 and may include a variety of other types and configurations, such as planar transistors, non-planar transistors, or combinations of both. Planar transistors may include bipolar junction transistors (BJTs), heterojunction bipolar transistors (HBTs), or high electron mobility transistors (HEMTs). Non-planar transistors may include FinFET transistors such as double-gate or tri-gate transistors, as well as wrap-around gate or all-around gate transistors such as nanoribbon transistors and nanowire transistors.

[0072] Each transistor 1640 may include a gate 1622 formed of at least two layers, a gate dielectric, and a gate electrode. The gate dielectric may include one layer or a stack of layers. One or more layers may include silicon oxide, silicon dioxide, silicon carbide, and / or high-k dielectric materials. High-k dielectric materials may include elements such as hafnium, silicon, oxygen, titanium, tantalum, lanthanum, aluminum, zirconium, barium, strontium, yttrium, lead, scandium, niobium, and zinc. Examples of high-k materials that may be used for the gate dielectric include, but are not limited to, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate. In some embodiments, when a high dielectric constant material is used, an annealing treatment may be performed on the gate dielectric to improve the quality of the gate dielectric.

[0073] The gate electrode may be formed on the gate dielectric, and the gate electrode may include at least one p-type work function metal or n-type work function metal, depending on whether the transistor 1640 is to be a p-type metal-oxide-semiconductor (PMOS) or n-type metal-oxide-semiconductor (NMOS) transistor. In some implementations, the gate electrode may consist of a stack of two or more metal layers, one or more of which are work function metal layers and at least one of which is a filler metal layer. Furthermore, metal layers may be included for other purposes, such as barrier layers. In the case of a PMOS transistor, the metals that may be used for the gate electrode are not limited, but include ruthenium, palladium, platinum, cobalt, nickel, conductive metal oxides (e.g., ruthenium oxide), and any metals described later with reference to NMOS transistors (e.g., for work function tuning). In the case of NMOS transistors, the metals that can be used for the gate electrode are not limited to, but include hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, carbides of these metals (e.g., hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide, and aluminum carbide), and any of the metals mentioned above with reference to PMOS transistors (e.g., for work function adjustment).

[0074] In some embodiments, when viewed as a cross-section of transistor 1640 along the source-channel-drain direction, the gate electrode may consist of a U-shaped structure including a bottom portion substantially parallel to the substrate surface and two sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, at least one of the metal layers forming the gate electrode may simply be a planar layer substantially parallel to the top surface of the substrate and not including any sidewall portions substantially perpendicular to the top surface of the substrate. In other embodiments, the gate electrode may consist of a combination of a U-shaped structure and a planar non-U-shaped structure. For example, the gate electrode may consist of one or more U-shaped metal layers formed on one or more planar non-U-shaped layers.

[0075] In some embodiments, pairs of sidewall spacers may be formed on opposing faces of the gate stack so as to surround the gate stack. The sidewall spacers may be formed from materials such as silicon nitride, silicon oxide, silicon carbide, carbon-doped silicon nitride, and silicon oxynitride. The process for forming the sidewall spacers is known in the art and generally includes deposition and etching steps. In some embodiments, multiple pairs of spacers may be used. For example, two, three, or four pairs of sidewall spacers may be formed on opposing faces of the gate stack.

[0076] The S / D region 1620 can be formed within the substrate 1602 adjacent to the gate 1622 of each transistor 1640. The S / D region 1620 can be formed, for example, by an implantation / diffusion process or an etching / deposition process. In the former process, a dopant such as boron, aluminum, antimony, phosphorus, or arsenic is ion-implanted into the substrate 1602 to form the S / D region 1620. An annealing process may follow the ion implantation to activate the dopant and further diffuse it into the substrate 1602. In the latter process, the substrate 1602 can first be etched to form a recess at the location of the S / D region 1620. Then, an epitaxial deposition process can be performed to fill the recess with the material used to manufacture the S / D region 1620. In some implementations, the S / D region 1620 can be manufactured using a silicon alloy such as silicon germanium or silicon carbide. In some embodiments, the epitaxially deposited silicon alloy may be doped in situ with dopants such as boron, arsenic, or phosphorus. In some embodiments, the S / D region 1620 may be formed using one or more alternative semiconductor materials such as germanium or III-V material or alloy. In further embodiments, one or more layers of metal and / or metallic alloy may be used to form the S / D region 1620.

[0077] Electrical signals, such as power and / or input / output (I / O) signals, can be transferred to and / or from a device on the device layer 1604 (e.g., transistor 1640) through one or more interconnection layers (shown as interconnection layers 1606-1610 in Figure 9) located on the device layer 1604. For example, conductive features on the device layer 1604 (e.g., gate 1622 and S / D contact 1624) can be electrically coupled to an interconnection structure 1628 of interconnection layers 1606-1610. One or more interconnection layers 1606-1610 can form a metallization stack (also referred to as an "ILD" stack) 1619 of the IC device 1600.

[0078] The interconnect structure 1628 may be arranged within the interconnect layers 1606-1610 to transfer electrical signals according to a variety of designs (in particular, such arrangements are not limited to the specific configuration of the interconnect structure 1628 shown in Figure 9). Although Figure 9 shows a specific number of interconnect layers 1606-1610, embodiments of the present disclosure include IC devices having more or fewer interconnect layers than those shown.

[0079] In some embodiments, the interconnection structure 1628 may include wires 1628a and / or vias 1628b filled with a conductive material such as metal. The wires 1628a may be arranged to transfer electrical signals in a direction substantially parallel to the surface of the substrate 1602 on which the device layer 1604 is formed. For example, the wires 1628a may transfer electrical signals in the inward and outward directions of the page from the viewpoint of Figure 9. The vias 1628b may be arranged to transfer electrical signals in a direction substantially perpendicular to the surface of the substrate 1602 on which the device layer 1604 is formed. In some embodiments, the vias 1628b may electrically couple the wires 1628a of different interconnection layers 1606-1610 together.

[0080] As shown in Figure 9, the interconnection layers 1606-1610 may include a dielectric material 1626 disposed between interconnection structures 1628. In some embodiments, the dielectric material 1626 disposed between interconnection structures 1628 in each of the different interconnection layers 1606-1610 may have different compositions. In other embodiments, the composition of the dielectric material 1626 between different interconnection layers 1606-1610 may be the same.

[0081] The first interconnection layer 1606 may be formed on the device layer 1604. As shown, in some embodiments, the first interconnection layer 1606 may include lines 1628a and / or vias 1628b. Lines 1628a of the first interconnection layer 1606 may be coupled to contacts of the device layer 1604 (e.g., S / D contacts 1624).

[0082] A second interconnection layer 1608 may be formed on top of the first interconnection layer 1606. In some embodiments, the second interconnection layer 1608 may include vias 1628b for connecting lines 1628a of the second interconnection layer 1608 to lines 1628a of the first interconnection layer 1606. For clarity, lines 1628a and vias 1628b are structurally depicted by lines within each interconnection layer (e.g., within the second interconnection layer 1608), but in some embodiments, lines 1628a and vias 1628b may be structurally and / or materially continuous (e.g., filled simultaneously during dual damascene processing).

[0083] The third interconnection layer 1610 (and additional interconnection layers as desired) may be formed continuously on the second interconnection layer 1608 according to techniques and configurations similar to those described in relation to the second interconnection layer 1608 or the first interconnection layer 1606. In some embodiments, the "higher" (i.e., further away from the device layer 1604) interconnection layers in the metallization stack 1619 of the IC device 1600 may be thicker.

[0084] The IC device 1600 may include a solder resist material 1634 (e.g., polyimide or similar material) and one or more conductive contacts 1636 formed on interconnect layers 1606-1610. In Figure 9, the conductive contacts 1636 are illustrated as being in the form of bonding pads. The conductive contacts 1636 may be electrically coupled to an interconnect structure 1628 and may be configured to transfer electrical signals from transistor 1640 to other external devices. For example, solder joints may be formed on one or more conductive contacts 1636 to mechanically and / or electrically couple the chip containing the IC device 1600 to another component (e.g., a circuit board). The IC device 1600 may include additional or alternative structures for transferring electrical signals from the interconnect layers 1606-1610. For example, the conductive contacts 1636 may include other similar features (e.g., posts) for transferring electrical signals to external components.

[0085] Figure 10 is a side cross-sectional view of an IC device assembly 1700 which may include some of the microelectronic components 102 and / or microelectronic assemblies 100 disclosed herein. The IC device assembly 1700 includes a number of components arranged on a circuit board 1702 (which may be, for example, a motherboard). The IC device assembly 1700 includes a number of components arranged on a first surface 1740 of the circuit board 1702 and on an opposing second surface 1742 of the circuit board 1702, and generally the components may be arranged on one or both of surfaces 1740 and 1742. Some of the IC packages described later with reference to the IC device assembly 1700 may include embodiments of the microelectronic assembly 100 disclosed herein (for example, which may include a number of microelectronic components 102 that are bonded together by direct bonding).

[0086] In some embodiments, the circuit board 1702 may be a PCB comprising a plurality of metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. Any one or more of the metal layers may be formed (optionally, in conjunction with other metal layers) to transfer electrical signals between components coupled to the circuit board 1702 in a desired circuit pattern. In other embodiments, the circuit board 1702 may be a non-PCB substrate.

[0087] The IC device assembly 1700 shown in Figure 10 includes a package-on-interposer structure 1736 bonded to a first surface 1740 of a circuit board 1702 by a coupling component 1716. The coupling component 1716 may electrically and mechanically bond the package-on-interposer structure 1736 to the circuit board 1702 and may include solder balls (shown in Figure 10), male and female sockets, adhesive, underfill material, and / or any other suitable electrical and / or mechanical bonding structures.

[0088] The package-on-interposer structure 1736 may include an IC package 1720 coupled to a package interposer 1704 by a coupling component 1718. The coupling component 1718 may take any suitable form for the application, such as the form described above with reference to the coupling component 1716. Although a single IC package 1720 is shown in Figure 10, multiple IC packages may be coupled to the package interposer 1704, and in practice, additional interposers may be coupled to the package interposer 1704. The package interposer 1704 may provide an interference substrate used to bridge the circuit board 1702 and the IC package 1720. The IC package 1720 may be, for example, a die (die 1502 in Figure 8), an IC device (e.g., IC device 1600 in Figure 9), or any other suitable component, or may include them. Generally, the package interposer 1704 may spread connections to a wider pitch, and may re-transfer some connections to different connections. For example, the package interposer 1704 may couple an IC package 1720 (e.g., a die) to a set of BGA conductive contacts of a coupling component 1716 for coupling to a circuit board 1702. In the embodiment shown in Figure 10, the IC package 1720 and the circuit board 1702 are mounted on opposite sides of the package interposer 1704. In other embodiments, the IC package 1720 and the circuit board 1702 may be mounted on the same side of the package interposer 1704. In some embodiments, three or more components may be interconnected as the package interposer 1704.

[0089] In some embodiments, the package interposer 1704 may be formed as a PCB comprising multiple metal layers separated from each other by layers of dielectric material and interconnected by conductive vias. In some embodiments, the package interposer 1704 may be formed of polymer materials such as epoxy resin, glass fiber reinforced epoxy resin, epoxy resin containing inorganic fillers, ceramic material, or polyimide. In some embodiments, the package interposer 1704 may be formed of alternative rigid or flexible materials. These materials may include the same materials described above used for semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. The package interposer 1704 may include metal wires 1710 and vias 1708, including but not limited to TSV 1706. The package interposer 1704 may further include embedded devices 1714, which include both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and micro-electromechanical systems (MEMS) devices may also be formed on the package interposer 1704. The package-on-interposer structure 1736 may take any form of package-on-interposer structure known in the art.

[0090] The IC device assembly 1700 may include an IC package 1724 which is coupled to the first surface 1740 of the circuit board 1702 by a coupling component 1722. The coupling component 1722 may take the form of any embodiment described above with reference to the coupling component 1716, and the IC package 1724 may take the form of any embodiment described above with reference to the IC package 1720.

[0091] The IC device assembly 1700 shown in Figure 10 includes a package-on-package structure 1734 coupled to the second surface 1742 of the circuit board 1702 by a coupling component 1728. The package-on-package structure 1734 may include IC packages 1726 and 1732, which are coupled together by a coupling component 1730 such that IC package 1726 is positioned between the circuit board 1702 and IC package 1732. The coupling components 1728 and 1730 may take any form of the embodiment of the coupling component 1716 described above, and the IC packages 1726 and 1732 may take any form of the embodiment of the IC package 1720 described above. The package-on-package structure 1734 may be configured according to any package-on-package structure known in the art.

[0092] Figure 11 is a block diagram of an exemplary electrical device 1800, including the microelectronic components 102 and / or microelectronic assembly 100 disclosed herein. For example, any suitable components of the electrical device 1800 may include one or more of the IC device assembly 1700, IC device 1600, or die 1502 disclosed herein. Although numerous components are shown in Figure 11 as being included in the electrical device 1800, one or more of these components may be omitted or duplicated where appropriate for the application. In some embodiments, some or all of the components included in the electrical device 1800 may be mounted on one or more motherboards. In some embodiments, some or all of these components are manufactured on a single system-on-chip (SoC) die.

[0093] Additionally, in various embodiments, the electrical device 1800 does not have to include one or more of the components shown in Figure 11, but it may include interface circuits for coupling one or more components. For example, the electrical device 1800 does not have to include the display device 1806, but it may include a display device interface circuit (e.g., a connector and driver circuit) to which the display device 1806 can be coupled. In another set of examples, the electrical device 1800 does not have to include the audio input device 1824 or the audio output device 1808, but it may include an audio input or output device interface circuit (e.g., a connector and support circuit) to which the audio input device 1824 or the audio output device 1808 can be coupled.

[0094] The electrical device 1800 may include processing devices 1802 (e.g., one or more processing devices). As used herein, the terms “processing device” or “processor” may refer to any device or part of a device that processes electronic data from registers and / or memory and converts such electronic data into other electronic data that can be stored in registers and / or memory. The processing device 1802 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), CPUs, GPUs, cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The electrical device 1800 may include memory 1804. Memory 1804 may itself include one or more memory devices such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard drives. In some embodiments, memory 1804 may include memory that shares a die with processing device 1802. This memory may be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0095] In some embodiments, the electrical device 1800 may include a communication chip 1812 (e.g., one or more communication chips). For example, the communication chip 1812 may be configured to manage wireless communication for data transfer to and from the electrical device 1800. The term “wireless” and its derivatives may be used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can communicate data using modulated electromagnetic radiation through a non-solid medium. While the relevant devices may not include wiring in some embodiments, the term does not imply that the relevant devices are not wire-free.

[0096] The 1812 communication chip may implement any of a number of wireless standards or protocols, including, but is not limited to, Wi-Fi® (IEEE 802.11 family), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendment), and the Long-Term Evolution (LTE) project with any modifications, updates, and / or revisions (e.g., the Advanced LTE project, the Ultra Mobile Broadband (UMB) project (also known as "3GPP2")). IEEE 802.16-compatible broadband radio access (BWA) networks are commonly referred to as WiMAX® networks. This acronym stands for Worldwide Interoperability for Microwave Access, and is a certification mark for products that have passed compliance and interoperability testing of the IEEE 802.16 standard. The communication chip 1812 may operate in accordance with the Global System for Mobile Communications (GSM®), General-Purpose Packet Radio Service (GPRS), Universal Mobile Communications System (UMTS), High-Speed ​​Packet Access (HSPA), and Evolved HSPA (E-HSPA or LTE network). The communication chip 1812 may operate in accordance with GSM® Evolution Enhanced Data (EDGE), GSM® EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 1812 may operate in accordance with Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Cordless Telecommunications (DECT), Evolution Data Optimized (EV-DO) and their derivatives, as well as any other radio protocols designated as 3G, 4G, 5G, and later. In other embodiments, the communication chip 1812 may operate in accordance with other radio protocols. The electrical device 1800 may include an antenna 1822 for facilitating wireless communication and / or for receiving other wireless communications (such as AM or FM radio transmissions).

[0097] In some embodiments, the communication chip 1812 may manage wired communications such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet®). As described above, the communication chip 1812 may comprise multiple communication chips. For example, the first communication chip 1812 may be dedicated to shorter-range wireless communications such as Wi-Fi® or Bluetooth®, and the second communication chip 1812 may be dedicated to longer-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX®, LTE, EV-DO, or others. In some embodiments, the first communication chip 1812 may be dedicated to wireless communications, and the second communication chip 1812 may be dedicated to wired communications.

[0098] The electrical device 1800 may include a battery / power supply circuit 1814. The battery / power supply circuit 1814 may include a circuit for coupling components of the electrical device 1800 to one or more energy storage devices (e.g., batteries or capacitors) and / or an energy source separate from the electrical device 1800 (e.g., AC line power).

[0099] The electrical device 1800 may include a display device 1806 (or the corresponding interface circuit described above). The display device 1806 may include any visual indicator such as a head-up display, computer monitor, projector, touchscreen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0100] The electrical device 1800 may include an audio output device 1808 (or the corresponding interface circuit described above). The audio output device 1808 may include any device that generates an audible indicator, such as a speaker, headset, or earbuds.

[0101] The electrical device 1800 may include an audio input device 1824 (or the corresponding interface circuit described above). The audio input device 1824 may include any device that generates a signal representing sound, such as a microphone, a microphone array, or a digital device (e.g., a device with a musical instrument digital interface (MIDI) output).

[0102] The electrical device 1800 may include a GPS device 1818 (or the corresponding interface circuit described above). The GPS device 1818 may communicate with a satellite system and may receive the position of the electrical device 1800 in a manner known in the art.

[0103] The electrical device 1800 may include other output devices 1810 (or the corresponding interface circuits described above). Examples of other output devices 1810 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0104] The electrical device 1800 may include other input devices 1820 (or the corresponding interface circuits described above). Examples of other input devices 1820 may include accelerometers, gyroscopes, compasses, imaging devices, cursor control devices such as keyboards and mice, styluses, touchpads, barcode readers, quick response (QR) code readers, any sensors, or radio frequency identification (RFID) readers.

[0105] The electrical device 1800 may have any desired form of factor, such as a handheld or mobile electrical device (e.g., a mobile phone, smartphone, mobile internet device, music player, tablet computer, laptop computer, netbook computer, ultrabook computer, personal digital assistant (PDA), ultramobile personal computer, etc.), a desktop electrical device, a server device or other networked computing component, a printer, scanner, monitor, set-top box, entertainment control unit, vehicle control unit, digital camera, digital video recorder, or wearable electrical device. In some embodiments, the electrical device 1800 may be any other electronic device that processes data.

[0106] The following paragraphs provide various examples of embodiments disclosed herein.

[0107] Example 1A is a microelectronic assembly comprising an interposer having a first surface and an opposing second surface; a first microelectronic component bonded to the second surface of the interposer by a first direct bonding region; a second microelectronic component bonded to the second surface of the interposer by a second direct bonding region; a liner material located on the second surface of the interposer and surrounding the first and second microelectronic components; and a thermally conductive filler material located on the liner material and between the first and second microelectronic components.

[0108] Example 2A may include the subject matter of Example 1A and may further specify that the thermally conductive filler material includes ceramic, copper, aluminum, silver, diamond, graphene, silicon, and carbon, boron and nitrogen, or aluminum and nitrogen, and combinations thereof.

[0109] Example 3A may include the subject matter of Example 1A and may further specify that the thickness of the thermally conductive filler material is between 10 microns and 250 microns.

[0110] Example 4A may include the subject matter of Example 1A and may further specify that the liner material includes titanium, tantalum, vanadium, nickel, ruthenium, cobalt, iridium, titanium and nitrogen, tantalum and nitrogen, vanadium and nickel, iridium and oxygen, silicon and carbon and nitrogen, silicon and nitrogen, silicon and carbon, or titanium and oxygen, and combinations thereof.

[0111] Example 5A may include the subject matter of Example 1A and may further specify that the thickness of the liner material is between 10 nanometers and 2000 nanometers.

[0112] Example 6A may include the subject matter of Example 1A and may further specify that the thicknesses of the first and second microelectronic components are less than or equal to 40 microns.

[0113] Example 7A may include the subject matter of Example 1A, further specifying that the first and second microelectronic components include a first surface bonded to an interposer and an opposing second surface, and further including a thermally conductive bulk material bonded to the second surface of the first and second microelectronic components.

[0114] Example 8A may include the subject matter of Example 7A and may further specify that the thickness of the thermally conductive bulk material is between 10 microns and 650 microns.

[0115] Example 9A may include the subject matter of Example 1A, and the thermally conductive bulk materials include copper, aluminum, silver, silicon, silicon and carbon, or diamond, and combinations thereof.

[0116] Example 10A may include the subject matter of Example 7A and may further include a package substrate bonded to a first surface of the interposer and an underfill material extending between the package substrate and a thermally conductive bulk material.

[0117] Example 11A is a microelectronic assembly comprising: an interposer having a first surface and an opposing second surface; a first microelectronic component having a first surface and an opposing second surface and bonded to the second surface of the interposer at the first surface by a first direct bonding region; a second microelectronic component having a first surface and an opposing second surface and bonded to the second surface of the interposer at the first surface by a second direct bonding region; a liner material located on the second surface of the interposer and surrounding the first and second microelectronic components; a thermally conductive filler material located on the liner material and between the first and second microelectronic components; and a thermally conductive bulk material bonded to the second surfaces of the first and second microelectronic components.

[0118] Example 12A may include the subject matter of Example 11A and may further specify that the interposer includes an organic dielectric material.

[0119] Example 13A may include the subject matter of Example 11A and may further specify that the interposer includes an inorganic dielectric material.

[0120] Example 14A may include the subject matter of Example 11A and may further include a package substrate bonded to a first surface of the interposer, and an underfill material extending between the package substrate and a thermally conductive bulk material.

[0121] Example 15A may include the subject matter of Example 11A and may further specify that the first and second microelectronic components include semiconductor dies.

[0122] Example 16A is a microelectronic assembly comprising an interposer, a first microelectronic component having a first surface and an opposing second surface, the first surface of the first microelectronic component being bonded to the interposer by a first direct bonding region, a second microelectronic component having a first surface and an opposing second surface, the first surface of the second microelectronic component being bonded to the interposer by a second direct bonding region, a thermally conductive filler material located on the surface of the interposer and between the first and second microelectronic components, and a thermally conductive bulk material bonded to the second surfaces of the first and second microelectronic components.

[0123] Example 17A may include the subject matter of Example 16A and may further specify that the thermally conductive filler material includes ceramic, copper, aluminum, silver, diamond, graphene, silicon, and carbon, boron and nitrogen, or aluminum and nitrogen, and combinations thereof.

[0124] Example 18A may include the subject matter of Example 16A and may further specify that the thermally conductive bulk material includes copper, aluminum, silver, silicon, silicon and carbon, or diamond, and combinations thereof.

[0125] Example 19A may include the subject matter of Example 16A and may further include a liner material between the interposer and the thermally conductive filler material, and between the first and second microelectronic components and the thermally conductive filler material.

[0126] Example 20A may include the subject matter of Example 19A and may further specify that the liner material includes titanium, tantalum, vanadium, nickel, ruthenium, cobalt, iridium, titanium and nitrogen, tantalum and nitrogen, vanadium and nickel, iridium and oxygen, silicon and carbon and nitrogen, silicon and nitrogen, silicon and carbon, or titanium and oxygen, and combinations thereof.

[0127] Example 1B is a microelectronic assembly comprising an interposer having a first surface and an opposing second surface; a first microelectronic component bonded to the second surface of the interposer by a first direct bonding region; a second microelectronic component bonded to the second surface of the interposer by a second direct bonding region; a liner material located on the second surface of the interposer and surrounding the first and second microelectronic components; and an inorganic dielectric material located on the liner material and between the first and second microelectronic components.

[0128] Example 2B may include the subject matter of Example 1B and may further specify that the inorganic dielectric material includes silicon and oxygen, or silicon and nitrogen, or a combination thereof.

[0129] Example 3B may include the subject matter of Example 1B and may further specify that the thickness of the inorganic dielectric material is between 10 microns and 250 microns.

[0130] Example 4B may include the subject matter of Example 1B and may further specify that the liner material comprises silicon and carbon and nitrogen, silicon and nitrogen, silicon and oxygen and nitrogen, or silicon and carbon.

[0131] Example 5B may include the subject matter of Example 1B and may further specify that the thickness of the liner material is between 10 nanometers and 2000 nanometers.

[0132] Example 6B may include the subject matter of Example 1B and may further specify that the thicknesses of the first and second microelectronic components are less than or equal to 40 microns.

[0133] Example 7B may include the subject matter of Example 1B, further specifying that the first and second microelectronic components include a first surface bonded to an interposer and an opposing second surface, and may further include a third microelectronic component bonded to the second surface of the first and second microelectronic components.

[0134] Example 8B includes the subject matter of Example 7B, and may further specify that the inorganic dielectric material is a first inorganic dielectric material, and may further include a second inorganic dielectric material on the first inorganic dielectric material and on the second surfaces of the first and second microelectronic components, and the third microelectronic component is bonded to the second inorganic dielectric material by a fusion bonding region.

[0135] Example 9B may include the subject matter of Example 7B, and may further specify that the first and second microelectronic components are single-sided dies, the third microelectronic component is a passive die, and the third microelectronic component is fusion-bonded to the second surface of the first and second microelectronic components by a bonding region.

[0136] Example 10B may include the subject matter of Example 9B and may further specify that the third microelectronic component further includes a thermal dissipation structure.

[0137] Example 11B is a microelectronic assembly comprising: an interposer having a first surface and an opposing second surface; a first microelectronic component having a first surface and an opposing second surface and bonded to the second surface of the interposer at the first surface by a first direct bonding region; a second microelectronic component having a first surface and an opposing second surface and bonded to the second surface of the interposer at the first surface by a second direct bonding region; a liner material located on the second surface of the interposer and surrounding the first and second microelectronic components; an inorganic filler material located on the liner material and between the first and second microelectronic components; and a third microelectronic component bonded to the second surfaces of the first and second microelectronic components.

[0138] Example 12B may include the subject matter of Example 11B, further specifying that the first and second microelectronic components are double-sided dies, the third microelectronic component is an active die, and the third microelectronic component is bonded to the second surface of the first and second microelectronic components by a third direct bonding region.

[0139] Example 13B may include the subject matter of Example 12B and may further include through-substrate vias (TSVs) through an inorganic filler material that electrically connect a third microelectronic component to the interposer.

[0140] Example 14B may include the subject matter of Example 13B and may further specify that the interposer includes a power distribution circuit, the first and second microelectronic components include a memory circuit, and the third microelectronic component includes a processing circuit.

[0141] Example 15B may include the subject matter of Example 11B and further include a package substrate bonded to a first surface of the interposer, and an underfill material extending between the package substrate and a third microelectronic component.

[0142] Example 16B is a microelectronic assembly comprising an interposer, a first microelectronic component having a first surface and an opposing second surface, the first surface of which is bonded to the interposer by a first direct bonding region, a second microelectronic component having a first surface and an opposing second surface, the first surface of which is bonded to the interposer by a second direct bonding region, a liner material on the surface of the interposer and surrounding the first and second microelectronic components, an inorganic filler material of the liner material between the first and second microelectronic components, and a third microelectronic component bonded to the second surfaces of the first and second microelectronic components.

[0143] Example 17B may include the subject matter of Example 16B and may further specify that the inorganic dielectric material includes silicon and oxygen, or silicon and nitrogen, or a combination thereof.

[0144] Example 18B may include the subject matter of Example 16B and may further specify that the liner material includes silicon and carbon and nitrogen, silicon and nitrogen, silicon and oxygen and nitrogen, or silicon and carbon, and combinations thereof.

[0145] Example 19B may include the subject matter of Example 16B and may further specify that the thickness of the inorganic dielectric material is between 10 microns and 250 microns.

[0146] Example 20B may include the subject matter of Example 16B and may further specify that the thickness of the liner material is between 10 nanometers and 2000 nanometers. Other possible claims. 1. An interposer having a first surface and an opposing second surface, A first microelectronic component bonded to the second surface of the interposer by a first direct bonding region, A second microelectronic component bonded to the second surface of the interposer by a second direct bonding region, A liner material located on the second surface of the interposer and surrounding the first and second microelectronic components, A thermally conductive filler material located on the liner material and between the first and second microelectronic components, Microelectronic assemblies, including 2. The thermally conductive filler material includes ceramic, copper, aluminum, silver, diamond, graphene, silicon and carbon, boron and nitrogen, or aluminum and nitrogen, and combinations thereof. The microelectronic assembly described in item 1. 3. A microelectronic assembly as described in item 1, wherein the thickness of the thermally conductive filler material is between 10 microns and 250 microns. 4. A microelectronic assembly as described in Item 1, wherein the liner material includes titanium, tantalum, vanadium, nickel, ruthenium, cobalt, iridium, titanium and nitrogen, tantalum and nitrogen, vanadium and nickel, iridium and oxygen, silicon and carbon and nitrogen, silicon and nitrogen, silicon and carbon, or titanium and oxygen, and combinations thereof. 5. A microelectronic assembly as described in item 1, wherein the thickness of the liner material is between 10 nanometers and 2000 nanometers. 6. A microelectronic assembly as described in item 1, wherein the thickness of the first and second microelectronic components is less than or equal to 40 microns. 7. The first and second microelectronic components include a first surface bonded to the interposer and an opposing second surface, The microelectronic assembly according to item 1, further comprising a thermally conductive bulk material bonded to the second surface of the first and second microelectronic components. 8. A microelectronic assembly as described in item 7, wherein the thickness of the thermally conductive bulk material is between 10 microns and 650 microns. 9. The thermally conductive bulk materials include copper, aluminum, silver, silicon, silicon and carbon, or diamond, and combinations thereof, as described in Item 1, for the microelectronic assemblies. 10. A package substrate bonded to the first surface of the interposer, The package substrate and the thermally conductive bulk material are further included as underfill material extending between them. The microelectronic assembly described in item 7. 11. An interposer having a first surface and an opposing second surface, A first microelectronic component having a first surface and an opposing second surface, and bonded to the second surface of the interposer at the first surface by a first direct bonding region, A second microelectronic component having a first surface and an opposing second surface, and coupled to the second surface of the interposer at the first surface by a second direct bonding region, A liner material located on the second surface of the interposer and surrounding the first and second microelectronic components, A thermally conductive filler material located on the liner material and between the first and second microelectronic components, A thermally conductive bulk material bonded to the second surface of the first and second microelectronic components, Microelectronic assemblies, including 12. A microelectronic assembly as described in item 11, wherein the interposer contains an organic dielectric material. 13. A microelectronic assembly as described in item 11, wherein the interposer includes an inorganic dielectric material. 14. A package substrate bonded to the first surface of the interposer, The following further includes an underfill material extending between the package substrate and the thermally conductive bulk material. The microelectronic assembly described in item 11. 15. The microelectronic assembly according to item 11, wherein the first and second microelectronic components include a semiconductor die. 16. Interposer and, A first microelectronic component having a first surface and an opposing second surface, wherein the first surface of the first microelectronic component is coupled to an interposer by a first direct bonding region, A second microelectronic component having a first surface and an opposing second surface, wherein the first surface of the second microelectronic component is coupled to an interposer by a second direct bonding region, A thermally conductive filler material located on the surface of the interposer and between the first and second microelectronic components, A thermally conductive bulk material bonded to the second surface of the first and second microelectronic components, Microelectronic assemblies, including 17. A microelectronic assembly as described in item 16, wherein the thermally conductive filler material includes ceramic, copper, aluminum, silver, diamond, graphene, silicon, and carbon, boron and nitrogen, or aluminum and nitrogen, and combinations thereof. 18. A microelectronic assembly as described in item 16, wherein the thermally conductive bulk material includes copper, aluminum, silver, silicon, silicon and carbon, or diamond, and combinations thereof. 19. The interposer and the thermally conductive filler material, and the first and second microelectronic components and the thermally conductive filler material, further include a liner material. The microelectronic assembly described in item 16. 20. A microelectronic assembly as described in item 19, wherein the liner material includes titanium, tantalum, vanadium, nickel, ruthenium, cobalt, iridium, titanium and nitrogen, tantalum and nitrogen, vanadium and nickel, iridium and oxygen, silicon and carbon and nitrogen, silicon and nitrogen, silicon and carbon, or titanium and oxygen, and combinations thereof.

Claims

1. An interposer having a first surface and an opposing second surface, A first microelectronic component bonded to the second surface of the interposer by a first direct bonding region, A second microelectronic component bonded to the second surface of the interposer by a second direct bonding region, A liner material located on the second surface of the interposer and surrounding the first microelectronic component and the second microelectronic component, A thermally conductive filler material located on the liner material and between the first microelectronic component and the second microelectronic component, Includes, A microelectronic assembly comprising an interposer containing an organic dielectric material.

2. The thermally conductive filler material includes ceramic, copper, aluminum, silver, diamond, graphene, silicon and carbon, boron and nitrogen, or aluminum and nitrogen, and combinations thereof. The microelectronic assembly according to claim 1.

3. The microelectronic assembly according to claim 1 or 2, wherein the thickness of the thermally conductive filler material is between 10 microns and 250 microns.

4. The microelectronic assembly according to any one of claims 1 to 3, wherein the liner material includes titanium, tantalum, vanadium, nickel, ruthenium, cobalt, iridium, titanium and nitrogen, tantalum and nitrogen, vanadium and nickel, iridium and oxygen, silicon and carbon and nitrogen, silicon and nitrogen, silicon and carbon, or titanium and oxygen, and combinations thereof.

5. The microelectronic assembly according to any one of claims 1 to 4, wherein the thickness of the liner material is between 10 nanometers and 2000 nanometers.

6. The microelectronic assembly according to any one of claims 1 to 5, wherein the thickness of the first microelectronic component and the second microelectronic component is less than or equal to 40 microns.

7. The first microelectronic component and the second microelectronic component each include a first surface coupled to the interposer and an opposing second surface, The present invention further includes a thermally conductive bulk material bonded to the second surface of the first microelectronic component and the second microelectronic component. The microelectronic assembly according to any one of claims 1 to 6.

8. The microelectronic assembly according to claim 7, wherein the thickness of the thermally conductive bulk material is between 10 microns and 650 microns.

9. The microelectronic assembly according to claim 7 or 8, wherein the thermally conductive bulk material includes copper, aluminum, silver, silicon, silicon and carbon, or diamond, and combinations thereof.

10. A package substrate bonded to the first surface of the interposer, The package substrate and the thermally conductive bulk material are further included as underfill material extending between them. The microelectronic assembly according to any one of claims 7 to 9.

11. An interposer having a first surface and an opposing second surface, A first microelectronic component having a first surface and an opposing second surface, the first surface being bonded to the second surface of the interposer by a first direct bonding region, A second microelectronic component having a first surface and an opposing second surface, and bonded at the first surface to the second surface of the interposer by a second direct bonding region, A liner material located on the second surface of the interposer and surrounding the first microelectronic component and the second microelectronic component, A thermally conductive filler material located on the liner material and between the first microelectronic component and the second microelectronic component, A thermally conductive bulk material bonded to the second surface of the first microelectronic component and the second microelectronic component, Includes, A microelectronic assembly comprising an interposer containing an organic dielectric material.

12. The microelectronic assembly according to claim 11, wherein the interposer includes an inorganic dielectric material.

13. A package substrate bonded to the first surface of the interposer, The package substrate and the thermally conductive bulk material are further included as underfill material extending between them. The microelectronic assembly according to claim 11 or 12.

14. The microelectronic assembly according to any one of claims 11 to 13, wherein the first microelectronic component and the second microelectronic component include a semiconductor die.

15. Interposer and, A first microelectronic component having a first surface and an opposing second surface, wherein the first surface of the first microelectronic component is coupled to the interposer by a first direct bonding region, A second microelectronic component having a first surface and an opposing second surface, wherein the first surface of the second microelectronic component is coupled to the interposer by a second direct bonding region, A thermally conductive filler material located on the surface of the interposer and between the first microelectronic component and the second microelectronic component, A thermally conductive bulk material bonded to the second surface of the first microelectronic component and the second microelectronic component, Includes, A microelectronic assembly comprising an interposer containing an organic dielectric material.

16. The microelectronic assembly according to claim 15, wherein the thermally conductive filler material includes ceramic, copper, aluminum, silver, diamond, graphene, silicon, and carbon, boron and nitrogen, or aluminum and nitrogen, and combinations thereof.

17. The microelectronic assembly according to claim 15 or 16, wherein the thermally conductive bulk material includes copper, aluminum, silver, silicon, silicon and carbon, or diamond, and combinations thereof.

18. The liner material further includes between the interposer and the thermally conductive filler material, and between the first microelectronic component and the second microelectronic component and the thermally conductive filler material. The microelectronic assembly according to claim 17.

19. The microelectronic assembly according to claim 18, wherein the liner material includes titanium, tantalum, vanadium, nickel, ruthenium, cobalt, iridium, titanium and nitrogen, tantalum and nitrogen, vanadium and nickel, iridium and oxygen, silicon and carbon and nitrogen, silicon and nitrogen, silicon and carbon, or titanium and oxygen, and combinations thereof.

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