Method and apparatus relating to memory chip raw hammer threat back pressure signal and host-side response

Abstract

To provide a memory chip, a memory controller, and a computing system relating to a memory chip row hammer thread back pressure signal and a host-side response.SOLUTION: A memory chip 301 includes a row hammer (RH) threat detection circuit 302, an output part, and a back pressure signal generation circuit 303 coupled between the row hammer threat detection circuit and the output part. The back pressure signal generation circuit generates a back pressure signal to be transmitted from the output part in response to the detection of a row hammer threat by the row hammer threat detection circuit.SELECTED DRAWING: Figure 3

Description

Technical Field

[0001] Cross - Reference to Related Applications This application claims the benefit of U.S. Provisional Application No. 63 / 183,509, filed on May 3, 2021, entitled "Method and Apparatus For Row Hammer Recovery", the entire content of which is incorporated herein by reference.

[0002] The field of the present invention generally relates to computer science, and more specifically, to methods and apparatuses related to memory chip row hammer threat back - pressure signals and host - side responses.

Background Art

[0003] Dynamic Random Access Memory (DRAM) cells store charge in capacitive cells. During standby mode (when there is no access to the cell), the charge leaks from the cell Continuous leakage such that its stored value may change condition (e.g., from 1 to 0) To reach with a certain probability.

Summary of the Invention

[0004] To prevent such data loss, DRAM memory chips are designed to refresh their storage cells. The refresh activity typically involves reading from the cell to detect its stored value and then writing the same value The back to the cell. The write operation the adds a new amount of charge The to the cell for a particular stored value.

[0005] To ensure the integrity of its data over an extended runtime, the memory chip will periodically refresh its storage cells. Specifically, each cell within the cell array of the memory chip is refreshed at a frequency sufficient to prevent loss of its stored data, even if the cell is not frequently accessed.

[0006] The recently published Joint Electron Device Engineering Council (JEDEC) standard, Dual Data Rate 5 ("DDR5"), defines coordinated refresh operations between the memory chip and the host (memory controller). Specifically, memory chip manufacturers define specific timing requirements related to cell refresh in the memory chip's cell array (in the memory chip's mode register (MR) space).

[0007] The memory controller reads the timing requirements and schedules REFRESH commands according to a schedule that matches the timing requirements. The memory controller then issues REFRESH commands to the memory chip that match the schedule. In response to each REFRESH command, the memory chip refreshes cells at a granularity specified by the type of REFRESH command received (all banks in a particular bank group, or the same bank in all bank groups).

[0008] DRAM memory cells can also suffer from a data corruption mechanism called "row hammer." In the case of a row hammer, data can be corrupted in cells coupled to rows (e.g., the next row) that are frequently activated. Therefore, the memory system should ideally include counters to monitor row activation. certain Over the time window Exceeding the threshold If a large number of activations are deemed to have been received, The row in question Cells merged into neighboring rows are, cell To protect it from the low hammer effect, prevention It will be refreshed.

[0009] The JEDEC DDR5 standard includes a low hammer mitigation technique called "refresh management." In refresh management, the memory controller counts row activations for each bank. If the bank count exceeds a threshold specified by the memory chip manufacturer, the memory controller issues a refresh management (RFM) command to the memory chip.

[0010] In response to each RFM command, the memory chip refreshes its cells at a granularity specified by the type of RFM command received (all banks in a particular bank group, or the same bank in all bank groups). In particular, the refresh performed in response to an RFM command is an additional refresh beyond the normal scheduled refresh performed by the REFRESH command, as described above.

[0011] The DDR5 standard also provides a mechanism for the memory chip to send back the presence of a problem to the memory controller. A typical DDR5 implementation includes a pair of subchannels 101_1, 101_2 coupled between the memory controller 102 and the memory module 103, as shown in Figure 1. For simplification, only the memory module components of one of the subchannels are shown. As seen in Figure 1, the subchannel components include first-rank memory chips 104_1 and second-rank memory chips 104_2 that send / receive data to and from the memory controller 102, and a register clock driver (RCD) chip 105 that receives command and address (C / A) signals from the memory controller.

[0012] Each memory chip 106 includes an Alert_n output 107 used to signal any write cyclic redundancy check (CRC) errors ("DQ CRC" write errors) that occur. Here, DDR5 data transfers are performed in bursts that consume multiple cycles. The actual data is transferred during the initial cycles, and the CRC information is transferred during the later cycles. For each write burst, the target It is said Each memory chip in the rank internally calculates its own CRC information from the received data. Internally calculated CRC information The received CRC information is then compared with this information. If there is a mismatch, the memory chip asserts a flag in its Alert_n output 107 (for clarity, Figure 1 shows only one memory chip 106 and one Alert_n output 107 labeled).

[0013] The Alert_n outputs from each memory chip within the same rank are combined and forwarded to the RCD chip 105. D Q: If any memory chip detects that a CRC write error has occurred, According to the DDR5 standard, within 3 to 13 ns of events The memory chip operates for 12 to 20 clock cycles (nCK). range It generates a pulse with a width within the specified range. The RCD chip 105 receives the pulse and re-drives the pulse on the subchannel ALERT_N wire 108 to the memory controller. this Notify about the event.

[0014] Furthermore, the RCD chip 105 receives subchannels. did It is designed to detect parity errors in the C / A signal. If the RCD chip 105 detects a parity error in the C / A signal, the RCD chip 105 will sa On the ALERT_N wire 108 of the channel It has a range of 60 to 120 ns. Generate a pulse and send it to the memory controller. this Notify about the event.

[0015] Figure 2 shows the time windows for both the DQ CRC write error pulse and the CA parity error pulse. As seen in Figure 2, both pulses are logically low assertions in that they both begin on a falling edge and end on a rising edge. Note that the minimum pulse width of the CA parity error is longer than the maximum pulse width of the DQ CRC write error, so the memory controller can distinguish which type of error has occurred. [Brief explanation of the drawing]

[0016] A good understanding of the present invention can be obtained from the following detailed description in conjunction with the following drawings.

[0017] [Figure 1] (Prior art) A diagram showing a memory controller coupled to a memory module. [Figure 2] (Prior art) A diagram showing CRC write errors and C / A parity error signals. [Figure 3] A diagram showing an improved memory chip. [Figure 4] A diagram showing a backpressure signal. [Figure 5] A diagram showing an improved memory controller. [Figure 6] A diagram showing a system. [Figure 7] A diagram showing a data center. [Figure 8] A diagram showing an environment.

Mode for Carrying Out the Invention

[0018] Future generations of memory chips are expected to be designed to include their own row hammer threat detection circuits. For example, at least some future generations of memory chips are expected to include additional DRAM cells per row that are used to hold the activation count for that row. If the activation count for a row for any particular row reaches a threshold, the memory chip recognizes the presence of a "nominal" row hammer threat.

[0019] If the activation counts for a number of different rows within the same memory chip all reach their respective thresholds approximately simultaneously ("row hammer overload"), an extended row hammer threat can occur. In this case, the memory chip refreshes the set of rows that are threatened (rows in the vicinity of one set per row that reached the threshold). but This is expected to consume a significant amount of time.

[0020] Regardless of the type of Lowhammer threat (collectively referred to below as "Lowhammer (RH) threat" or "Lowhammer (RH) event," such as a "nominal" Lowhammer threat or a "Lowhammer overload" threat) detected by the memory chip, the memory chip should notify the memory controller that it has detected a Lowhammer threat.

[0021] Furthermore, especially when a large number of refreshes are not expected to mitigate the low hammer threat (e.g., a low hammer overload), the memory chip should send some kind of low hammer-related backpressure signal to the memory controller, which informs the memory controller that it is temporarily not advisable to send further read, write, or activate commands to the memory chip.

[0022] Therefore, a first circuit 301 for internally detecting an RH threat and, in response to the internal detection of an RH threat, constructs an RH back pressure signal. From the Alert_n output 304 An improved memory chip 301, including a second circuit 302 for transmission, is shown in Figure 3. According to various memory module implementation configurations consistent with the description in Figure 1 above, the RH back pressure signal is received by the RCD chip and re-driven on the subchannel ALERT_N wire.

[0023] In various embodiments, the structure of the RH back pressure signal is determined by the memory controller for DQ CRC write errors and C / A parity errors. DQ CRC write error and C / A parity error can be distinguished from both. It is different.

[0024] Specifically, as shown in Figure 4, the minimum pulse width of the RH back pressure signal is greater than the maximum pulse width of the CA parity error signal. Here, if a pulse is asserted on the ALERT_N wire with a high-to-low transition, and a subsequent low-to-high transition indicating the end of the pulse occurs within the following 60 ns, the memory controller understands that a DQ CRC write error signal has been transmitted. In contrast, if the subsequent low-to-high transition occurs 60 ns later, within 120 ns, the memory controller understands that a CA parity error signal has been transmitted. Finally, if the subsequent low-to-high transition 401 occurs 120 ns later instead, the memory controller understands that an RH back pressure signal has been transmitted.

[0025] In various embodiments, as shown in Figure 4, the minimum pulse width of the back pressure signal is defined as 150 ns, such that there is a pulse width difference of 30 ns between the CA parity error signal and the back pressure signal. This allows the memory controller to easily distinguish whether or not the CA parity error signal is being transmitted or whether or not the RH back pressure signal is being transmitted (if the low-to-high transition occurs 60 ns later and within 120 ns, the memory controller understands that the CA parity error signal is being transmitted, or if the low-to-high transition 401 occurs 150 ns or later, the memory controller understands that the back pressure signal is being transmitted).

[0026] In various embodiments, the minimum and / or maximum pulse width definitions for the back pressure signal are defined in the MR space 305 of the memory chip (e.g., together with the pulse width definitions for DQ CRC write and / or CA parity bit error).

[0027] In a further embodiment, the MR space 305 further includes a “Partial_CMD_Block” parameter that defines a time window 402 in which the memory controller refrains from sending commands (read, write, and activate) that could exacerbate at least a low hammer threat. Here, the partial command block time window 402 begins on the rising / falling edge of the ALERT_N pulse and ends within a specified time range in the MR space of the memory chip. Within the time window 402, the memory controller refrains from sending at least certain types of commands, such as read commands, write commands, and activate commands.

[0028] In various embodiments, both minimum and maximum times are specified in the MR space 305 of the partial command block window 402. The memory controller refrains from sending at least a specific command from the moment the memory controller first samples the rising / falling edge of the ALERT_N pulse until the period 402 that falls within the minimum and maximum settings of the partial block window has elapsed. Expected It will be done.

[0029] Designing the memory controller to stop sending commands as soon as it observes the rising / falling edge of the ALERT_N pulse will not distinguish between other ALERT_N signals (DQ CRC write error and CA parity error). Therefore, if the ALERT_N signal is a DQ CRC write error or a CA parity error... too , partial block time window teeth This would cause the command to stop. Therefore, a time window of 402 can be advantageously used to correct, for example, DQ CRC write errors or CA parity errors. The memory chip is Before the memory controller stops sending commands in response to sampling the ALERT_N falling edge, all commands received from the memory controller must be executed. Expected It will be done.

[0030] In various configurations, the settings of the partial command block window 402 are such that the memory controller can determine whether the ALERT_N signal is a DQ CRC write error or a CA parity error within the window 402 or immediately after the window 402 expires. For example, the partial block window 402 is configured to extend beyond the minimum pulse width of a CA parity error (a high-to-low transition of 60 ns).

[0031] By doing so, while the memory controller is blocking the issuance of a specific command within window 402, the memory controller actually observes a low-to-high transition corresponding to a DQ CRC write error or CA parity error. There is a possibility that .So of In this case, after window 402 has expired (the block has been released), the memory controller is free to send any desired command.

[0032] In contrast, if the pulse width of the ALERT_N signal extends beyond window 402 and reaches the minimum pulse width 401 of the RH back pressure signal, the memory controller will not emit the RH back pressure signal. Sera Upon recognizing the threat, the system initiates sending an RFM command 403 to the memory chip. Sending the RFM command 403 authorizes the memory chip to apply a refresh to mitigate the lowhammer threat.

[0033] In various embodiments, the memory controller stops transmitting the RFM command 403 when the memory chip terminates the pulse (a transition from low to high is observed) or when the pulse width reaches the maximum pulse 404 of the RH back pressure signal specified in the memory chip's MR space (whichever comes first). Here, in various embodiments, the memory chip's back pressure signal circuit 303 is designed to terminate the Alert_N pulse by a rising edge (which the RCD chip re-drives) in response to a signal from the memory chip's low hammer threat detection circuit 302 that the low hammer threat that caused the back pressure signal has been mitigated by sufficient refresh.

[0034] Alternatively, if the memory controller stops sending RFM commands because it has reached the maximum specified pulse width 404, ideally the memory chip will not need any more time to mitigate the low hammer threat. Thus, in various embodiments, the difference between the minimum pulse width setting 401 and the maximum pulse width setting 404 is defined considering the worst-case low hammer threat (e.g., low hammer overload) that is expected to be well mitigated.

[0035] A refresh performed in response to an RFM command 403 transmitted by the memory controller in response to a back pressure signal is considered an additional refresh transmitted beyond the nominal refresh operation achieved using the REFRESH command and any refresh operation achieved by an RFM command triggered from tracking the bank activation of the memory controller (both types of refresh operations continue in addition to the refresh performed in response to a low hammer overload signal).

[0036] In various embodiments, when a memory chip detects a low hammer threat event, the memory chip updates its MR space 305 to determine the type of error (e.g., a low hammer overload) and / or additional information about the error (e.g., which specific rows reached their respective thresholds). The memory controller can then freely read the MR space 305 to check and / or better understand the situation on the memory chip 301.

[0037] For example, if the MR space 305 indicates which row has reached its threshold, the memory controller is transmitted in response to the back pressure signal. of RFM command 403 is Rera Specify the bank address where the corresponding sacrifice row for the given row resides. target RFM command and It is possible. In an alternative or combined method, the MR space 305 indicates the number of RFM commands required to alleviate the low hammer overload condition. In this case, after a specified number of RFM commands have been sent (rather than waiting for the pulse to end or reach the maximum pulse width 404), the memory controller responds to the back pressure signal by of The transmission of RFM command 403 can be stopped. In yet another or combined embodiment, the MR space 305 indicates the time required for the memory chip to spend refreshing before the RH threat is mitigated. In this case, the memory controller transmits RFM command 403 in response to the back pressure signal for a specified time. Afterwards, This will stop the transmission of RFM command 403.

[0038] Furthermore, in the case of a multi-rank memory module, the MR register space can be read. UnlessThe memory controller cannot know which ranks are under a low hammer threat (because the Alert_n pins of memory chips from more than one rank are linked to the same RCD input). In this case, the memory controller can be designed to apply low hammer mitigation to all ranks (stopping the transmission of read / write / activate commands within window 402 and starting the transmission of RFM command 403). If the memory controller reads the MR register space, it can understand which ranks of memory chips are under a low hammer threat and apply low hammer mitigation only to the memory chips of the affected ranks.

[0039] In various embodiments, when the memory chip observes that the low hammer threat has been mitigated, the memory chip Waxhammer Set to indicate the presence of a threat attitude Clear any of the MR spaces 305. Alternatively, when the memory chip terminates the pulse or the memory controller sends all permitted RFM commands 403 in response to the assertion of the back pressure signal, the memory controller may clear the MR space (by writing to the MR space 305 of the memory chip).

[0040] According to the embodiments described above, the memory chip is (If not in self-refresh mode) , REFRESH sent by the memory controller command and only in response to RFM commands, Ri It was intended to issue a fresh copy. In alternative or combined implementations, the memory chip 301 is The memory chip itselfThe circuit includes a mechanism for scheduling / issuing refreshes to be initiated. In such embodiments, as long as the memory controller stops sending new read, write, or activate commands (for example, the memory can internally mitigate a threat within window 402), the memory chip can internally initiate enough refreshes to mitigate the problem, thus reducing the number of RFM commands 403 required by the memory chip (for example, to 0).

[0041] Furthermore, following another method, the memory chip but Back pressure signal of Assert to do In response, the memory controller automatically puts the memory chip into self-refresh mode (instead of sending RFM command 403).

[0042] Furthermore, according to another method, the read burst includes metadata bits used to indicate whether or not a low hammer threat is present. For example, per read transaction. Each memory chip to , 1 bit (for example, 0 = no low hammer threat, 1 = low hammer threat exists) is reserved. If any metadata bit indicates the presence of a low hammer threat, the memory controller will, at the same address of The read command issues a series of spaced-out RFM commands. The memory controller continues to operate in this state until the metadata indicates that no lowhammer threat is present.

[0043] The above embodiments are for each subchannel. of Single ALERT_N wire , and All memory chips of the same rank or the same subchannel are connected to the same alert wire on the memory module. We have been emphasizing this point.However, it is appropriate to recognize that other embodiments that deviate from these particular designs may nevertheless incorporate the teachings provided herein. For example, there may be multiple ALERT_N wires for each subchannel (e.g., one such wire per rank).

[0044] Figure 5 shows a memory controller 501 designed to handle a raw hammer back pressure signal (or other types of back pressure signals) consistent with the teachings provided above. In particular, the memory controller 501 includes an input for receiving signals from an ALERT_N wire, which communicates errors / problems from the memory module and / or memory chip according to various pulse widths generated on the ALERT_N wire. One of these signals is a back pressure signal, such as a raw hammer back pressure signal. Thus, the memory controller 501 includes a circuit 502 that can distinguish between various signals and detect back pressure signals.

[0045] The memory controller 501 includes a command scheduler circuit 503 that determines which commands are to be sent to the memory module / chip to which the memory controller 501 is coupled. The command scheduler logic circuit 503 is designed to stop sending at least certain types of commands (e.g., read, write, activate) and / or send additional refresh commands (e.g., RFM commands) in response to detection by the memory controller of a back pressure signal received at the ALERT_N input.

[0046] In yet another embodiment, instead of using the ALERT_N wire, the back pressure signal is transmitted via digital communication through some kind of packetized communication link between the memory module and the memory controller. For example, a packet may be sent back from the memory chip to the memory controller using a specific wire of the command / address bus or data bus (DQ bus). Such a packet may include a header and / or payload corresponding to the back pressure signal as described above. The packetized communication link may be formed by a single wire or multiple wires, depending on the implementation. In the case of a multiple-wire implementation, the terms “output” and “input” related to the transmission and reception of the back pressure signal can be interpreted to include such multiple wires as well.

[0047] The teachings provided above can be applied to various memory implementations, including JEDEC DDR5 implementations, JEDEC DDR6 implementations, JEDEC graphics DDR (GDDR) implementations, and JEDEC high-bandwidth memory (HBM) implementations.

[0048] The various types of circuits described above can be implemented in logic circuits, at least partially. Logic circuits can include logic gates and / or larger logic macros formed by such logic gates, and logic gates are specialized and hardwired versions of programmable or configurable logic circuits, such as field-programmable gate array (FPGA) circuits and / or circuit designs for executing some form of program code (e.g., microcontrollers).

[0049] Figure 6 shows an exemplary system. The system can use the teachings provided herein. System 600 includes a processor 610 that provides instruction processing, operation management, and execution for System 600. The processor 610 may include any type of microprocessor, central processing unit (CPU), graphics processing unit (GPU), processing core, or other processing hardware or combination of processing units to provide processing to System 600. The processor 610 controls the overall operation of System 600 and may be or include one or more programmable general-purpose or dedicated microprocessors, digital signal processing units (DSPs), programmable controllers, application-specific integrated circuits (ASICs), programmable logic devices (PLDs), or combinations of such devices.

[0050] In one example, system 600 includes an interface 612 coupled to processor 610, where interface 612 can represent a high-speed or high-throughput interface for system components requiring high-bandwidth connectivity, such as a memory subsystem 620, a graphics interface component 640, or an accelerator 642. Interface 612 represents an interface circuit, which may be a standalone component or integrated on the processor die. If present, graphics interface 640 interfaces to a graphics component for providing a visual display to the user of system 600. In one example, graphics interface 640 can drive a high-definition (HD) display that provides output to the user. High-definition can refer to a display with a pixel density of approximately 100 PPI (pixels per inch) or higher, and can include formats such as Full HD (e.g., 1080p), Retina display, 4K (Ultra High Definition or UHD). In one example, the display may include a touchscreen display. In one example, the graphics interface 640 generates a display based on data stored in memory 630, or based on operations performed by the processor 610, or both.

[0051] Accelerator 642 can be a fixed-function offload engine that can be accessed or used by processor 610. For example, one of the accelerators of accelerator 642 can provide cryptographic services, such as compression (DC) functions, public-key cryptography (PKE), cryptography, hashing / authentication functions, and decryption, or other functions or services. In some embodiments, additionally or alternatively, one of the accelerators of accelerator 642 provides field selection controller functions as described herein. In some cases, accelerator 642 can be integrated into a CPU socket (e.g., a connector to a motherboard or circuit board that includes a CPU and provides an electrical interface with the CPU). For example, accelerator 642 may include programmable processing elements such as single or multi-core processors, graphics processing units, single or multi-level caches for logic execution units, function units that can be used to independently execute programs or threads, application-specific integrated circuits (ASICs), neural network processors (NNPs), "X" processing units (XPUs), programmable control logic, and field-programmable gate arrays (FPGAs). Accelerator 642 can provide multiple neural networks, processing cores, or graphics processing units, which can be made available for use with artificial intelligence (AI) or machine learning (ML) models. For example, an AI model may use or include any of the following: reinforcement learning methods, Q-learning methods, deep Q-learning, or asynchronous Advantage Actor-Critic (A3C), combinatorial neural networks, recurrent combinatorial neural networks, or other AI or ML models, or a combination thereof. Multiple neural networks, processing cores, or graphics processing units can be made available for use with AI or ML models.

[0052] The memory subsystem 620 represents the main memory of the system 600 and provides storage for data values ​​used when executing code or routines run by the processor 610. The memory subsystem 620 may include one or more memory devices 630, such as read-only memory (ROM), flash memory, volatile memory, or a combination of such devices. Memory 630, among other things, stores and hosts the operating system (OS) 632 to provide a software platform for executing instructions within the system 600. Furthermore, applications 634 can run from memory 630 on the software platform of OS 632. An application 634 represents a program with its own operational logic for performing one or more functions. A process 636 represents an agent or routine that provides auxiliary functions to OS 632 or one or more applications 634 or a combination thereof. OS 632, applications 634, and processes 636 provide the software logic that provides functionality to the system 600. In one example, the memory subsystem 620 includes a memory controller 622, which is a memory controller for generating and issuing commands to memory 630. It will be understood that the memory controller 622 may be a physical part of the processor 610 or a physical part of the interface 612. For example, the memory controller 622 may be an integrated memory controller integrated on the circuit having the processor 610. In some examples, a system-on-a-chip (SOC or SoC) combines one or more of the processing unit, graphics, memory, memory controller, and input / output (I / O) control logic into a single SoC package.

[0053] Volatile memory is memory whose state (and therefore the data stored in it) is undefined when power to the device is cut off. Dynamic volatile memory requires the data stored in the device to be refreshed in order to maintain its state. Examples of dynamic volatile memory include DRAM (Dynamic Random Access Memory) or any variation thereof such as synchronous DRAM (SDRAM). The memory subsystems described herein include DDR3 (Double Data Rate version 3, original release by JEDEC (Joint Electronic Device Engineering Council) on June 27, 2007), DDR4 (initial specification of DDR version 4 published by JEDEC in September 2012), DDR4E (DDR version 4), LPDDR3 (Low Power DDR version 3 by JEDEC, JESD209-3B in August 2013), LPDDR4 (LPDDR version 4, originally published by JEDEC in August 2014, JESD 209-4), WIO2 (Wide Input / Output version 2, originally published by JEDEC in August 2014, JESD229-2), and HBM (High Bandwidth). Memory (originally JESD325, published by JEDEC in October 2013), LPDDR5 (currently under discussion by JEDEC), HBM2 (HBM version 2, currently under discussion by JEDEC), or others, or combinations of memory technologies, and technologies based on derivatives or extensions of such specifications may be compatible. JEDEC standards are available at www.jedec.org.

[0054] The memory 630 may include one or more memory chips designed to transmit a back pressure signal, and the memory controller 622 may respond to the back pressure signal in accordance with the teachings described in detail with respect to Figures 3 to 5.

[0055] Although not specifically indicated, it will be understood that System 600 may include one or more buses or bus systems between devices, such as a memory bus, graphics bus, interface bus, or others. Buses or other signal lines can communicate or electrically couple components with each other, or both can communicate and electrically couple components. A bus may include physical communication lines, point-to-point connections, bridges, adapters, controllers, or other circuits, or combinations thereof. A bus may include, for example, one or more of the following: system bus, Peripheral Component Interconnection Express (PCIe) bus, Hypertransport or Industry Standard Architecture (ISA) bus, Small Computer System Interface (SCSI) bus, Remote Direct Memory Access (RDMA), Internet Small Computer System Interface (iSCSI), NVM Express (NVMe), Coherent Accelerator Interface (CXL), Coherent Accelerator Processing Unit Interface (CAPI), Universal Serial Bus (USB), or Institute of Electrical and Electronics Engineers (IEEE) Standard 1394 bus.

[0056] In one example, system 600 includes interface 614 which may be coupled to interface 612. In one example, interface 614 represents an interface circuit which may include standalone components and integrated circuits. In one example, multiple user interface components or peripheral components, or both, are coupled to interface 614. Network interface 650 provides system 600 with the ability to communicate with remote devices (e.g., servers or other computing devices) over one or more networks. Network interface 650 may include an Ethernet® adapter, a wireless interconnect component, a cellular network interconnect component, USB (Universal Serial Bus), or other wired or wireless standard-based or dedicated interface. Network interface 650 may transmit data to a remote device which may include transmitting data stored in memory. Network interface 650 may receive data from a remote device which may include storing received data in memory. Various embodiments can be used in relation to network interface 650, processor 610, and memory subsystem 620.

[0057] For example, system 600 includes one or more input / output (I / O) interfaces 660. The I / O interfaces 660 may include one or more interface components through which the user interacts with system 600 (e.g., voice, alphanumeric, haptic / touch, or other interfaces). Peripheral interfaces 670 may include any hardware interfaces not specifically mentioned above. Peripherals generally refer to devices that connect dependently to system 600. Dependent connections are those through which system 600 provides a software platform, a hardware platform, or both, on which operations are performed and user interaction occurs.

[0058] In one example, system 600 includes a storage subsystem 680 for non-volatile storage of data. In one example, in a particular system implementation, at least certain components of storage 680 may overlap with components of memory subsystem 620. The storage subsystem 680 includes a storage device 684, which may be any conventional medium for non-volatile storage of large amounts of data, e.g., one or more magnetic, solid-state, or optical-based disks, or a combination thereof, or may include these. Storage 684 holds code or instructions and data 686 in a persistent state (e.g., values ​​are retained despite power interruption to system 600). While storage 684 can generally be considered “memory”, memory 630 is typically execution or operational memory for providing instructions to processor 610. Although storage 684 is non-volatile, memory 630 may include volatile memory (e.g., the values ​​or state of data are indeterminate if power to system 600 is cut off). In one example, the storage subsystem 680 includes a controller 682 for interface with the storage 684. In one example, the controller 682 may be a physical part of the interface 614 or the processor 610, or it may include circuitry or logic in both the processor 610 and the interface 614.

[0059] Non-volatile memory (NVM) devices are memories whose state remains fixed even when power to the device is cut off. In one embodiment, an NVM device may comprise a block-addressable memory device, such as NAND technology, or more specifically, multi-threshold level NAND flash memory (e.g., single-level cell ("SLC"), multi-level cell ("MLC"), quad-level cell ("QLC"), tri-level cell ("TLC"), or any other NAND). NVM devices may also include byte-addressable write-in-place three-dimensional cross-point memory devices, or other byte-addressable write-in-place NVM devices (also known as persistent memory), such as single or multi-level phase-change memory (PCM) or switched phase-change memory (PCMS), NVM devices using chalcogenide phase-change materials (e.g., chalcogenide glass), resistive memory including metal oxide-based, oxygen-vacancy-based and conductive bridge random-access memory (CB-RAM), nanowire memory, ferroelectric random-access memory (FeRAM, FRAM®), magnetoresistive random-access memory (MRAM) incorporating memristor technology, spin-transfer torque (STT)-MRAM, spintronic magnetic junction memory-based devices, magnetic tunnel junction (MTJ)-based devices, DW (Domain Wall) and SOT (Spin Orbit Transfer)-based devices, thyristor-based memory devices, or any combination of the above, or other memories.

[0060] A power supply (not shown) provides power to the components of System 600. More specifically, the power supply typically interfaces with one or more power devices within System 700 to provide power to the components of System 600. In one example, the power device includes an AC-DC (alternating current-to-direct current) adapter that plugs into a wall outlet. Such AC power can be a renewable energy source (e.g., solar power). In one example, the power supply includes a DC power source, such as an external AC / DC converter. In one example, the power supply or power device includes wireless charging hardware for charging in proximity to a charging field. In one example, the power supply may include an internal battery, an AC device, a motion-based power device, a solar power device, or a fuel cell source.

[0061] For example, System 600 can be implemented as a disaggregated computing system. For instance, System 700 can be implemented with interconnected computing threads of processing units, memory, storage, network interfaces, and other components. High-speed interconnects such as PCIe, Ethernet®, or optical interconnects (or a combination thereof) can be used. For example, threads can be designed according to any specifications published by the Open Compute Project (OCP) or other disaggregated computing efforts that aim to modularize the computer components of the main architecture into rack-pluggable components (e.g., rack-pluggable processing components, rack-pluggable memory components, rack-pluggable storage components, rack-pluggable accelerator components, etc.).

[0062] Figure 7 shows an example of a data center. Various embodiments can be used in or with the data center in Figure 7. As shown in Figure 7, the data center 700 may include an optical fabric 712. The optical fabric 712 may generally include a combination of an optical signaling medium (such as optical cables) and an optical switching infrastructure from which any particular thread in the data center 700 can transmit (and receive signals from) other threads in the data center 700. However, optical, radio, and / or electrical signals can be transmitted using the fabric 712. The signaling connections that the optical fabric 712 provides to any given thread may include connections to other threads in the same rack and to threads in other racks. The data center 700 includes four racks 702A-702D, each housing a pair of threads 704A-1 and 704A-2, 704B-1 and 704B-2, 704C-1 and 704C-2, and 704D-1 and 704D-2. Thus, in this example, the data center 700 contains a total of eight threads. The optical fabric 712 can provide thread signaling connections to one or more of the other seven threads. For example, via the optical fabric 712, thread 704A-1 in rack 702A may have signaling connections with thread 704A-2 in rack 702A, as well as with six other threads 704B-1, 704B-2, 704C-1, 704C-2, 704D-1, and 704D-2 distributed among other racks 702B, 702C, and 702D in the data center 700. Embodiments are not limited to this example. For example, the fabric 712 can provide optical and / or electrical signaling.

[0063] Figure 8 shows that environment 800 includes multiple computing racks 802, each containing a top-of-rack (ToR) switch 804, a pod management unit 806, and multiple pooled system drawers. Generally, pooled system drawers may include, for example, pooled compute drawers and pooled storage drawers to run isolated computing systems. Optionally, pooled system drawers may also include pooled memory drawers and pooled input / output (I / O) drawers. In the illustrated embodiment, the pooled system drawers include an INTEL® XEON® pooled computer drawer 808, and an INTEL® ATOM® pooled compute drawer 810, a pooled storage drawer 812, a pooled memory drawer 814, and a pooled I / O drawer 816. Each of the pooled system drawers is connected to the ToR switch 804 via a high-speed link 818, such as a 40 gigabits per second (Gb / s) or 100 Gb / s Ethernet® link, or a 100+ Gb / s silicon photonics (SiPh) optical link. In one embodiment, the high-speed link 818 comprises an 800 Gb / s SiPh optical link.

[0064] Here too, Drawer can be designed according to any specifications published by the Open Compute Project (OCP) or other isolated computing initiatives, and it attempts to modularize the main architectural computer components into rack-pluggable components (e.g., rack-pluggable processing components, rack-pluggable memory components, rack-pluggable storage components, rack-pluggable accelerator components, etc.).

[0065] Multiple computing racks 800 may be interconnected via their ToR switches 804 (e.g., pod-level switches or data center switches), as indicated by their connection to the network 820. In some embodiments, a group of computing racks 802 is managed as a separate pod via a pod management unit 806. In one embodiment, a single pod management unit is used to manage all racks within a pod. Alternatively, distributed pod management units may be used for pod management operations.

[0066] The RSD environment 800 further includes a management interface 822 used to manage various aspects of the RSD environment. This includes managing the rack configuration using corresponding parameters stored as rack configuration data 824.

[0067] Embodiments of this specification may be implemented in various types of computing, smartphones, tablets, personal computers, and network equipment, such as switches, routers, racks, and blade servers, including those used in data center and / or server farm environments. Servers used in data centers and server farms have an arrayed server configuration, such as rack-based servers or blade servers. These servers are interconnected by communication over various network facilities, such as dividing the set of servers into LANs with appropriate switching and routing capabilities between local area networks (LANs) to form a private intranet. For example, cloud hosting facilities may use large data centers with a large number of servers. A blade comprises a separate computing platform configured to perform server-type functionality, i.e., "server on a card." Thus, each blade includes components common to conventional servers, including a main printed circuit board (main board) that provides internal wiring (e.g., buses) for coupling appropriate integrated circuits (ICs), and other components mounted on that board.

[0068] Various examples may be implemented using hardware elements, software elements, or a combination of both. In some examples, hardware elements may include devices, components, processing units, microprocessors, circuits, circuit elements (e.g., transistors, resistors, capacitors, inductors, etc.), integrated circuits, ASICs, PLDs, DSPs, FPGAs, memory units, logic gates, registers, semiconductor devices, chips, microchips, chipsets, etc. In some examples, software elements may include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof. For example, the determination of whether or not an implementation is carried out using hardware and / or software elements may vary according to any number of factors, such as desired computation speed, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus rate, and other design or performance constraints, as desired for a given implementation. Note that hardware elements, firmware elements, and / or software elements may be referred to collectively or individually as “modules,” “logic,” “circuits,” or “circuit wiring” in this specification.

[0069] Some examples may be implemented using or as a product or at least one computer-readable medium. The computer-readable medium may include non-temporary storage medium for storing logic. In some examples, the non-temporary storage medium may include one or more types of computer-readable storage medium capable of storing electronic data, including volatile or non-volatile memory, removable or non-removable memory, erasable or non-erasable memory, writable or overwriteable memory, etc. In some examples, the logic may include a variety of software elements, such as software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs, instruction sets, computing code, computer code, code segments, computer code segments, words, values, symbols, or any combination thereof.

[0070] According to some examples, computer-readable media may include non-temporary storage media for storing or maintaining instructions that, when executed by a machine, computing device, or system, cause the machine, computing device, or system to perform methods and / or actions in accordance with the examples described. Instructions may include any appropriate type of code, such as source code, compiled code, interpreted code, executable code, static code, or dynamic code. Instructions may be executed according to a predefined computer language, method, or syntax to instruct a machine, computing device, or system to perform a particular function. Instructions may be executed using any appropriate high-level, low-level, object-oriented, visual, compiled, and / or interpreted programming language.

[0071] One or more embodiments of at least one example can be executed by representative instructions stored in at least one machine-readable medium representing various logics within a processing unit, which, when read by a machine, computing device, or system, assemble the logic for performing the techniques described herein. Such representations, known as "IP cores," may be stored in tangible machine-readable medium and supplied to various customers or manufacturing facilities for loading into assembly machines that actually produce the logic or processing unit.

[0072] The occurrence of the phrase "example" or "example" does not necessarily mean that all instances refer to the same example or embodiment. Any embodiment described herein can be combined with any other embodiment or similar embodiment described herein, whether or not the embodiment is described with respect to the same drawing or element. The division, omission, or inclusion of block functions shown in the accompanying drawings does not necessarily mean that hardware components, circuits, software, and / or elements for implementing those functions are necessarily divided, omitted, or included in the embodiment.

[0073] Some examples can be explained using the expressions “joined” and “connected” along with their derivatives. These terms are not necessarily intended to be synonymous with each other. For example, explanations using the terms “connected” and / or “joined” may indicate that two or more elements are in direct physical or electrical contact with each other. However, the term “joined” can also mean that two or more elements are not in direct contact with each other, but still work together or interact with each other.

[0074] In this specification, terms such as “first,” “second,” etc., are not used to indicate order, quantity, or importance, but are used to distinguish any element from another. In this specification, terms such as “one (a)” and “one (an)” are not used to indicate a limitation of quantity, but rather to indicate the presence of at least one of the items being referenced. As used herein with respect to signals, the term “asserted” indicates a state of the signal in which the signal is active and which can be achieved by applying any logic level, either logic 0 or logic 1, to the signal. The terms “following” or “after” can refer to immediately after or following one or more other events. Other sets of steps may also be performed according to alternative embodiments. Furthermore, additional steps may be added or removed depending on the particular application. Any combination of modifications may be used, and those skilled in the art who benefit from this disclosure will understand its many variations, modifications, and alternative embodiments.

[0075] Disjunctive language, such as the phrase "at least one of X, Y, or Z," is generally understood, unless otherwise specified, to indicate in the context of its common use, that an item, term, etc., can be any of X, Y, or Z, or any combination thereof (e.g., X, Y, and / or Z). Therefore, such disjunctive language should not be intended or implied, in general, that a particular embodiment requires at least one of X, at least one of Y, or at least one of Z to exist, respectively. Furthermore, conjunctions such as the phrase "at least one of X, Y, and Z" should also be understood, unless otherwise specified, to mean X, Y, Z, or any combination thereof, including "X, Y, and / or Z." [Other adjacent items] (Item 1) Lowhammer threat detection circuit, Output section, A back pressure signal generation circuit is coupled between the low hammer detection circuit and the output unit, and generates a back pressure signal to be transmitted from the output unit in response to the detection of a low hammer threat by the low hammer threat detection circuit. A memory chip equipped with this feature. (Item 2) The memory chip described in item 1, wherein the output unit outputs alert_n. (Item 3) The memory chip according to item 1, comprising multiple rows of memory cell arrays within the memory chip where the row hammer threat simultaneously reaches a row activation threshold. (Item 4) The memory chip according to item 1, wherein the back pressure signal includes pulses having a width within a specific minimum and maximum pulse width. (Item 5) The memory chip according to item 1, wherein the memory chip comprises a mode register (MR) mode space for recording the minimum pulse width. (Item 6) The memory chip according to item 1, wherein the memory chip comprises an MR space for providing information about the Lowhammer threat. (Item 7) The memory chip described in item 1, wherein the information describes a time window during which the memory controller stops sending read commands, write commands, and activate commands to the memory chip as a result of the memory controller receiving the back pressure signal. (Item 8) The memory chip according to item 1, wherein the information described above affects the number of refresh commands that the memory controller transmits to the memory chip in response to the back pressure signal. (Item 9) The memory chip described in item 8, wherein the refresh command is a refresh management (RFM) command. (Item 10) The memory chip described in item 1, wherein the back pressure signal is transmitted in a packet via the output unit. (Item 11) Input section, A back pressure signal detection circuit coupled to the input unit for detecting the back pressure signal received in the input unit, A command circuit coupled to the back pressure signal detection circuit, wherein, as a result of the memory controller receiving the back pressure signal, the command circuit stops transmitting read commands, write commands, and activate commands to the memory chip, and the memory chip generates the back pressure signal in response to a low hammer threat. A memory controller equipped with the following features. (Item 12) The memory controller described in item 11, wherein the input unit is an alert_n output. (Item 13) The memory controller according to item 11, wherein the back pressure signal includes pulses having a width within a specific minimum and maximum pulse width. (Item 14) The memory controller described in item 11, wherein the memory controller reads the MR space within the memory chip to obtain information about a low hammer threat. (Item 15) The memory controller according to item 11, wherein the memory controller refrains from sending the read command, the write command, and the activation command for a predetermined period of time. (Item 16) The memory controller according to item 11, wherein the memory controller transmits a refresh command to the memory chip in response to the back pressure signal. (Item 17) The memory controller according to item 11, wherein the memory controller also receives a cyclic redundancy check write error signal and a command / address parity error signal at the input section. (Item 18) a) Multiple processing cores, b) Network interface and, c) A memory chip, i) Lowhammer threat detection circuit, ii) Output section and, iii) A back pressure signal generation circuit coupled between the raw hammer detection circuit and the output unit, which generates a back pressure signal to be transmitted from the output unit in response to the detection of a raw hammer threat by the raw hammer threat detection circuit. A memory chip equipped with, d) A memory controller coupled to the memory chip, i) Input section, ii) A back pressure signal detection circuit coupled to the input unit and detecting the back pressure signal received at the input unit, iii) A command circuit coupled to the back pressure signal detection circuit, wherein, as a result of the memory controller receiving the back pressure signal, the command circuit stops transmitting read commands, write commands, and activate commands to the memory chip. A memory controller having A computing system equipped with [the following features]. (Item 19) The computing system described in item 18, wherein the output unit outputs alert_n. (Item 20) The computing system according to item 18, comprising multiple rows of memory cell arrays in the memory chip where the row hammer threat simultaneously reaches a row activation threshold. (Item 21) The computing system according to item 18, wherein the memory controller transmits a refresh command to the memory chip in response to the back pressure signal.

Claims

1. A low hammer threat detection circuit for detecting a low hammer event in which the row activation counts of multiple rows of memory simultaneously reach a threshold, wherein the threshold indicates when the row activation count of a particular row becomes a low hammer threat, The output section is coupled to the signal line, A memory chip comprising a back pressure signal generation circuit coupled between the low hammer threat detection circuit and the output unit, which transmits a back pressure signal on the signal line in response to the detection of the low hammer event, wherein the back pressure signal indicates to the memory controller that the memory chip requires additional refresh time to internally mitigate the low hammer event.

2. Lowhammer threat detection circuit, Output section, A back pressure signal generation circuit is coupled between the low hammer threat detection circuit and the output unit, and generates a back pressure signal to be transmitted from the output unit in response to the detection of a low hammer threat by the low hammer threat detection circuit. A mode register (MR) space for providing information regarding the aforementioned lowhammer threat, Equipped with, The information describes a time window during which, as a result of the memory controller receiving the back pressure signal, the memory controller stops sending read, write, and activate commands to the memory chip.

3. The memory chip according to claim 1 or 2, wherein the output unit is an alert_n output.

4. The memory chip according to claim 2, comprising a plurality of rows of memory cell arrays within the memory chip, wherein the low hammer threat simultaneously reaches the row activation threshold.

5. The memory chip according to any one of claims 1 to 4, wherein the back pressure signal includes pulses having a width within a range of a specific minimum pulse width and a specific maximum pulse width.

6. The MR space is a memory chip according to claim 5, which is dependent on claim 2, for recording the minimum pulse width.

7. The memory chip according to claim 1, wherein the memory chip comprises an MR space for providing information regarding the low hammer threat.

8. The memory chip according to claim 7, wherein the information is for describing a time window in which the memory controller stops transmitting read commands, write commands, and activate commands to the memory chip as a result of the memory controller receiving the back pressure signal.

9. The memory chip according to claim 7 or 8, wherein the information affects the number of refresh commands that the memory controller transmits to the memory chip in response to the back pressure signal.

10. The memory chip according to claim 9, wherein the refresh command is a refresh management (RFM) command.

11. The memory chip according to any one of claims 1 to 10, wherein the back pressure signal is transmitted in a packet via the output unit.

12. It is a memory controller, An input unit coupled to a signal line that receives a back pressure signal, wherein the back pressure signal indicates that the memory chip has detected a low hammer event in which the row activation counts of multiple rows of memory simultaneously reach a threshold, the threshold indicates when the row activation count of a particular row becomes a low hammer threat, and the memory chip requires additional refresh time to internally mitigate the low hammer event; A command circuit that, in response to receiving the back pressure signal, stops transmitting read commands, write commands, and activation commands to the memory chip. A memory controller equipped with the following features.

13. It is a memory controller, Input section, A back pressure signal detection circuit coupled to the input unit for detecting the back pressure signal received in the input unit, A command circuit coupled to the back pressure signal detection circuit, wherein, as a result of the memory controller receiving the back pressure signal, the command circuit stops transmitting read commands, write commands, and activate commands to the memory chip, and the memory chip generates the back pressure signal in response to a low hammer threat. Equipped with, A memory controller that reads the MR space within the memory chip in order to obtain information about a low hammer threat.

14. The memory controller according to claim 12 or 13, wherein the input unit is an alert_n output.

15. The memory controller according to any one of claims 12 to 14, wherein the back pressure signal includes pulses having a width within a range of a specific minimum pulse width and a specific maximum pulse width.

16. The memory controller according to claim 12, wherein the memory controller reads the MR space within the memory chip to obtain information regarding a low hammer threat.

17. The memory controller according to any one of claims 12 to 16, wherein the memory controller refrains from transmitting the read command, the write command, and the activation command for a predetermined period of time.

18. The memory controller according to any one of claims 12 to 17, wherein the memory controller transmits a refresh command to the memory chip in response to the back pressure signal.

19. The memory controller according to any one of claims 12 to 18, wherein the memory controller also receives a cyclic redundancy check write error signal and a command / address parity error signal at the input unit.

20. a) Multiple processing cores, b) Network interface and, c) A memory chip, wherein the memory chip is i) A low hammer threat detection circuit that detects a low hammer event in which the row activation counts of multiple rows in memory simultaneously reach a threshold, wherein the threshold indicates when the row activation count of a particular row becomes a low hammer threat, ii) Output section coupled to the signal line, iii) A back pressure signal generation circuit coupled between the low hammer threat detection circuit and the output unit, which transmits a back pressure signal on the signal line in response to the detection of the low hammer event, wherein the back pressure signal indicates that the memory chip requires additional refresh time to internally mitigate the low hammer event. A memory chip having, d) A memory controller coupled to the memory chip, wherein the memory controller is i) An input unit coupled to the signal line, ii) A command circuit that stops transmitting read commands, write commands, and activation commands to the memory chip in response to receiving the back pressure signal. A memory controller having A computing system equipped with [the following features].

21. a) Multiple processing cores, b) Network interface and, c) A memory chip, i) Low hammer threat detection circuit, ii) Output section and, iii) A back pressure signal generation circuit coupled between the low hammer threat detection circuit and the output unit, which generates a back pressure signal to be transmitted from the output unit in response to the detection of a low hammer threat by the low hammer threat detection circuit, iv) A mode register (MR) space for providing information about the low hammer threat, wherein the information describes a time window in which the memory controller stops sending read, write, and activate commands to the memory chip as a result of the memory controller receiving the back pressure signal. A memory chip having, d) The memory controller coupled to the memory chip, i) Input section and, ii) A back pressure signal detection circuit coupled to the input unit and detecting the back pressure signal received in the input unit, iii) A command circuit coupled to the back pressure signal detection circuit, wherein, as a result of the memory controller receiving the back pressure signal, the command circuit stops transmitting the read command, the write command, and the activate command to the memory chip. A memory controller having A computing system equipped with [the following features].

22. a) Multiple processing cores, b) Network interface and, c) A memory chip, i) Low hammer threat detection circuit, ii) Output section and, iii) A back pressure signal generation circuit coupled between the low hammer threat detection circuit and the output unit, which generates a back pressure signal to be transmitted from the output unit in response to the detection of a low hammer threat by the low hammer threat detection circuit. A memory chip having, d) A memory controller coupled to the memory chip, i) Input section and, ii) A back pressure signal detection circuit coupled to the input unit and detecting the back pressure signal received in the input unit, iii) A command circuit coupled to the back pressure signal detection circuit, wherein, as a result of the memory controller receiving the back pressure signal, the command circuit stops transmitting read commands, write commands, and activate commands to the memory chip. A memory controller having Equipped with, The memory controller is a computing system that reads the MR space within the memory chip to obtain information about the Lowhammer threat.

23. The computing system according to any one of claims 20 to 22, wherein the output unit is an alert_n output.

24. The computing system according to claim 21 or 22, comprising multiple rows of memory cell arrays in the memory chip where the row hammer threat simultaneously reaches a row activation threshold.

25. The computing system according to any one of claims 20 to 24, wherein the memory controller transmits a refresh command to the memory chip in response to the back pressure signal.

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