Memory chip testing apparatus
By setting power-on indicator lights and test status indicator lights on the memory chip test fixture, the problems of the test system not being powered on and the information not being intuitive are solved, enabling rapid handling of anomalies and improving test efficiency and accuracy.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- KINGTIGER TESTING TECH (SZ) LTD
- Filing Date
- 2025-07-16
- Publication Date
- 2026-07-07
AI Technical Summary
During memory chip testing, the test system fails to power on, preventing normal testing. Operators cannot immediately confirm the system status, and the test results are scattered and not intuitive, affecting operational efficiency.
A power-on indicator and a test status indicator are set on the memory chip test fixture to display the test status and results, respectively. The status of the indicator lights can alert the operator to abnormal situations, thereby improving the operator's judgment and handling efficiency.
With intuitive indicator lights, operators can promptly address issues such as power failure and malfunctions, saving time and improving testing efficiency and accuracy.
Smart Images
Figure CN224471727U_ABST
Abstract
Description
Technical Field
[0001] This utility model belongs to the technical field of memory chip testing, and specifically relates to a memory chip testing fixture. Background Technology
[0002] In the memory chip testing industry, chip testing fixtures are widely used for incoming quality inspection of memory chips, product development, chip testing, etc. They are suitable for various BGA, LGA, QFP, QFN, SOP and other packages, and come in many styles, including flip-top type, sliding type and aging type.
[0003] During the testing of these chip products, situations frequently arise where the testing system fails to power on, preventing normal testing. However, operators cannot immediately confirm the system's power-on status. Furthermore, testing operators typically operate multiple testing devices simultaneously, needing to load materials while observing the testing status, and then unload and categorize the tested products based on the results. The testing equipment is connected to a computer monitor, and operators must rely on the displayed results or prompts for further instructions. These scattered and unintuitive prompts significantly hinder compliant operations.
[0004] Therefore, a new type of memory chip testing fixture is needed to solve all or part of the above problems. Utility Model Content
[0005] To address at least one of the aforementioned problems and deficiencies in the existing technology, embodiments of this utility model provide a memory chip testing fixture. By setting indicator lights with different functions on the testing fixture, the testing status and results of the chip are displayed intuitively, facilitating operation and judgment by testing personnel. Simultaneously, it distinguishes between abnormalities such as the chip not being powered on and those in poor condition, enabling timely handling of these two types of anomalies, saving time and improving testing efficiency. The technical solution is as follows:
[0006] According to one aspect of the present invention, a memory chip testing fixture is provided. The memory chip testing fixture includes:
[0007] Test substrate;
[0008] A test socket is disposed on a test substrate and electrically connected to the test substrate;
[0009] A power-on indicator light is located on the test board.
[0010] Test status indicator lights are located on the test substrate;
[0011] The power-on indicator and the test status indicator are located on both sides of the test socket.
[0012] In some embodiments, the test stand specifically includes a first light guide post and a second light guide post, which are respectively disposed on both sides of the test stand. The first light guide post is disposed in correspondence with the power-on indicator light, and the second light guide post is disposed in correspondence with the test status indicator light.
[0013] In some embodiments, the test substrate includes test positions disposed on the test substrate, and a power-on indicator and a test status indicator are located on both sides of the test positions.
[0014] In some embodiments, the test socket further includes a mounting base, on which a limiting frame for accommodating the chip under test is provided, and conductive adhesive is provided at the bottom of the limiting frame, the conductive adhesive being electrically connected to the test position.
[0015] In some embodiments, the test fixture further includes a cover-lifting block, one side of which is rotatably connected to the mounting base. A chip pressure head is provided on the side of the cover-lifting block opposite to the mounting base, and the chip pressure head cooperates with the limiting frame.
[0016] In some embodiments, specifically, a cover-closing buckle is provided on the side of the cover-lifting block away from its connection with the mounting base, and a cover-closing slot is provided on the mounting base, with the cover-closing buckle and the cover-closing slot cooperating with each other.
[0017] In some embodiments, the test substrate is further provided with mounting holes and positioning holes.
[0018] In some embodiments, the memory chip test fixture further includes a detection control module disposed inside the test substrate. The detection control module includes an integrated control circuit and a data comparison unit. The power-on indicator and the test status indicator are electrically connected to the detection control module through the control circuit.
[0019] In some embodiments, the control circuit specifically includes a chip testing circuit and an LED circuit. The chip testing circuit is electrically connected to the data comparison unit, and the LED circuit includes a first indicator circuit and a second indicator circuit.
[0020] In some embodiments, specifically, the power-on indicator light is electrically connected to the first indicator circuit. When the memory chip test fixture is powered on, the detection control module outputs a level to the power-on indicator light via the first indicator circuit to drive the power-on indicator light to illuminate. The test status indicator light is electrically connected to the second indicator circuit. When the memory chip test fixture is powered on and enters the chip testing stage, the detection control module outputs different level values to the test status indicator light via the second indicator circuit to drive the test status indicator light to display different colors.
[0021] The memory chip testing fixture provided by the embodiments of this utility model has at least one or a portion of the following advantages:
[0022] (1) By setting different function indicator lights on the test fixture, the test status and test results of the test chip can be displayed intuitively, which is convenient for testers to operate and judge. At the same time, the abnormalities of the test chip not being powered on and the poor status can be distinguished, and these two types of abnormalities can be dealt with in a timely manner, saving time and improving test efficiency.
[0023] (2) By improving the test fixture for memory chips, power-on indicator and test status indicator are set on its test substrate respectively. When the test chip is closed, the power-on indicator can be used to confirm whether the test fixture is powered on. The test status indicator can be used to determine the progress of the memory chip test and the test results.
[0024] (3) By setting power-on indicator and test status indicator on the test board, operators can be provided with clear and intuitive information prompts for the entire test process, thereby improving the work efficiency and test accuracy of operators;
[0025] (4) The test status indicator flashes during the test to help remind the operator that the chip is under test. When the flashing stops and the corresponding color is displayed, the test result of the chip is reminded to the operator. The structure is simple and the prompts are intuitive.
[0026] (5) By using the power-on indicator and the test status indicator to distinguish between the abnormalities of the chip not being powered on and the abnormality of the status, the two types of abnormalities can be dealt with in a timely manner, saving time and improving test efficiency. Attached Figure Description
[0027] These and / or other aspects and advantages of this invention will become apparent and readily understood from the following description of preferred embodiments taken in conjunction with the accompanying drawings, in which:
[0028] Figure 1 This is a schematic diagram of the structure of a memory chip testing fixture according to an embodiment of the present invention;
[0029] Figure 2 for Figure 1 The diagram shows the structure of the test substrate of the memory chip test fixture.
[0030] Figure 3 For use Figure 1 The diagram shows a chip testing station consisting of a test fixture array, which is a memory chip testing fixture.
[0031] Figure 4 for Figure 1 The diagram shows the circuit connection of the detection control module in the memory chip testing fixture. Detailed Implementation
[0032] The technical concept and technical solution of this utility model will be further described in detail below through embodiments and in conjunction with the accompanying drawings. In this specification, the same or similar reference numerals indicate the same or similar components. The following description of the embodiments of this utility model with reference to the accompanying drawings is intended to explain the overall concept of this utility model and should not be construed as a limitation thereof.
[0033] It should also be understood that although the terms "first," "second," "third," etc., may be used in the following embodiments of this utility model to describe a component comprising two or more of the same component, these components should not be limited to these terms, which are only used to distinguish each component from one another. Furthermore, descriptions indicating orientation such as "upper," "lower," "left," "right," "front," and "rear" are merely illustrative of the relative positions of components and should not be construed as a limitation of this utility model.
[0034] Furthermore, unless otherwise expressly specified and limited, the terms "installation," "connection," "joining," and "fixing," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.
[0035] According to one aspect of an embodiment of the present invention, a memory chip testing fixture is provided.
[0036] See Figure 1 The diagram illustrates the structure of a memory chip test fixture 100 according to one embodiment.
[0037] See Figure 2 , showed Figure 1 The structure of the test substrate 10 of the memory chip test fixture 100 shown.
[0038] Combination Figure 1 and Figure 2 As shown, the memory chip testing fixture 100 provided in this embodiment is mainly composed of five main parts: a test substrate 10, a test socket 20, a cover pressing block 30, a power-on indicator light 40, and a test status indicator light 50. The test socket 20 is disposed on and electrically connected to the test substrate 10, while the power-on indicator light 40 and the test status indicator light 50 are disposed on the test substrate 10 and located on opposite sides of the test socket 20.
[0039] In one example, specifically, a first light guide post 21a and a second light guide post 21b are respectively provided on both sides of the test base 20. The first light guide post 21a and the second light guide post 21b located on both sides of the test base 20 correspond to the power-on indicator light 40 and the test status indicator light 50 located on the test substrate 10, respectively. A test position 11 is provided on the test substrate 10, and the power-on indicator light 40 and the test status indicator light 50 are respectively located on both sides of the test position 11. The test base 20 includes a mounting base ( Figure 1 The test base 20 is located below the test substrate 10 (the side that is in contact with the test base 10). A limiting frame 22 is provided on the mounting base. The chip under test is placed in the limiting frame 22. Conductive adhesive is provided at the bottom of the limiting frame 22. The conductive adhesive is electrically connected to the test position 11. The test substrate 10 is also provided with positioning holes 12 for positioning the limiting frame 22 on the test substrate 10 when the test base 20 is installed, and mounting holes 13 for fixing the test base 20 after positioning.
[0040] like Figure 1 The image shows the state of the memory chip testing fixture 100 when the cover is lifted. Figure 2 As shown, the test substrate 10 is provided with test positions 11 and control circuits (including test circuits and LED circuits) are provided inside it. They are installed at the center of the test substrate 10, and positioning holes 12 and mounting holes 13 for mounting test seats 20 are provided around it.
[0041] In one example, preferably, such as Figure 2 As shown, a power-on indicator light 40 and a test status indicator light 50 are respectively provided in front of and behind the test position 11. Positioning holes 12 are provided around or near the test position 11. Alternatively, two positioning holes 12 are provided and located next to the power-on indicator light 40 and the test status indicator light 50, respectively, that is, the two positioning holes 12 are respectively located in front of and behind the test position 11. Alternatively, four mounting holes 13 are symmetrically provided on the surface of the test substrate 10 according to the size of the test holder to be mounted on its upper surface. The test holder 20 is mounted on the test substrate 10. It includes a mounting base (the part of the test holder 20 that abuts against the test substrate 10). The mounting base determines its position in the test position 11 through the positioning holes 12 and is aligned and fixedly mounted through the mounting holes 13. Alternatively, pins, screws, bolts, etc., are used to fix the test holder 20 to the test substrate 10 through the positioning holes 12 and the mounting holes 13.
[0042] In one example, specifically, a limiting frame 22 is provided at the center of the mounting base of the test socket 20, and conductive adhesive is provided at the bottom of the limiting frame 22 for cooperation with the test position 11 on the test substrate 10 and the control circuit to achieve electrical conduction.
[0043] In one example, preferably, combined Figure 1and Figure 2 As shown, through holes (not shown) are provided in front of and behind the mounting base of the test base 20. The first light guide post 21a and the second light guide post 21b are installed in the through holes, respectively corresponding to the power-on indicator light 40 and the test status indicator light 50 of the test substrate 10.
[0044] In one example, specifically, a cover-lifting block 30 is connected to the left side of the test base 20 via a pivot. The size of the cover-lifting block 30 is slightly smaller than the size of the mounting base of the test base 20. During the closed-cover test, it will not block the front and rear edges of the mounting base, so that the status of the power-on indicator light 40 and the test status indicator light 50 can be observed through the first light guide post 21a and the second light guide post 21b on the test base 20.
[0045] In one example, alternatively, one side of the lifting block 30 is rotatably connected to the test base 20 (specifically, its mounting base). A chip pressing head 31 is provided on the side of the lifting block 30 opposite to the mounting base, and the chip pressing head 31 cooperates with the limiting frame 22 of the test base 20. A closing buckle 32 is provided on the opposite side of the lifting block 30 where it is rotatably connected to the mounting base. A closing slot 23 is provided on the mounting base, and the closing buckle 32 and the closing slot 23 cooperate with each other. The lifting block 30 is rotatably connected to the mounting base of the test base 20, and the lifting and lowering of the cover are achieved by rotation. Preferably, the lifting block 30 has a flexible chip pressing head 31 in the middle, used to press the chip under test within the limiting frame 22 of the test base 20 and meet the thickness requirements. Preferably, the pressing surface of the chip pressing head 31 has a cross-shaped groove, into which air enters, creating air pressure during pressing, facilitating the rapid detachment of the chip under test after pressing. When pressing the chip under test, the cover-closing buckle 32 of the cover-opening block 30 engages with the cover-closing slot 23 of the mounting base of the test socket 20, ensuring the pressing force on the chip under test.
[0046] See Figure 3 This shows the use of Figure 1 The illustrated chip testing fixture 100 comprises a chip testing station 1000 with an array of memory chip testing fixtures 100. Several memory chip testing fixtures 100 are arranged in an array on the surface of the chip testing station 1000. Since each memory chip testing fixture 100 has its own independent control circuit for chip testing, each fixture can perform testing independently and can be independently inspected and repaired when malfunctions occur. A power supply is installed inside the chip testing station 1000 to power the memory chip testing fixtures 100.
[0047] See Figure 4The diagram illustrates the LED circuit connection structure for the power-on indicator 40 and the test status indicator 50. This LED circuit is integrated into, for example, a control circuit module or control circuit board of the test substrate 10.
[0048] Combination Figure 1 , Figure 2 and Figure 4 As shown, specifically, the memory chip test fixture 100 also includes a detection control module 14 disposed inside the test substrate 10. The detection control module 14 includes an integrated control circuit and a data comparison unit. The power-on indicator light 40 and the test status indicator light 50 are electrically connected to the detection control module 14 through the control circuit.
[0049] In one example, specifically, the control circuit includes a chip test circuit and an LED circuit. The chip test circuit is electrically connected to the data comparison unit, and the LED circuit includes a first indicator circuit L1 and a second indicator circuit L2.
[0050] In one example, specifically, the power-on indicator light 40 is electrically connected to the first indicator circuit L1. When the memory chip test fixture 100 is powered on, the detection control module 14 outputs a level to the power-on indicator light 40 via the first indicator circuit L1 to drive the power-on indicator light 40 to light up. The test status indicator light 50 is electrically connected to the second indicator circuit L2. When the memory chip test fixture 100 is powered on and enters the chip testing stage, the detection control module 14 outputs different level values to the test status indicator light 50 via the second indicator circuit L2 to drive the test status indicator light 50 to display different colors.
[0051] In one example, during actual chip testing, the chip under test (DUT) is placed within the limiting frame 22 of the test socket 20. Then, conductive adhesive is used to connect the pins of the DUT to the test position 11 of the test substrate 10. The test position 11 is connected to a detection control module 14 built into the test substrate 10. The detection control module 14 includes a voltage detection circuit, a current detection circuit, and a data comparison unit.
[0052] Furthermore, in the detection control module 14, the basic electrical parameters of the chip are tested by voltage detection circuit and current detection circuit. The basic electrical parameter tests typically include whether the chip supply voltage is within the standard range (e.g., the supply voltage is preset to 1.2V±0.1V) and whether the operating current exceeds the threshold (e.g., the operating current threshold is ≤50mA).
[0053] Furthermore, the core read and write functions of the chip are tested in the detection and control module 14 through the data comparison unit, including whether the chip can respond normally to read and write commands and whether the data read and write is accurate.
[0054] In one example, specifically, the power-on indicator 40 and the test status indicator 50 are connected via, as shown in the example... Figure 4 The LED circuit shown is electrically connected to the detection and control module 14 in the test substrate 10. The detection and control module 14 receives the chip test signal transmitted by the test socket 20 through the conductive adhesive in real time and judges the above-mentioned basic electrical parameters and core read and write functions.
[0055] If all parameters meet the standards and the read / write function is normal, the chip under test is determined to be "qualified". At this time, the detection control module 14 drives the test status indicator 50 to light up green by outputting a continuous high level with the first level value through the LED circuit.
[0056] If any parameter exceeds the standard or the read / write function is abnormal, the chip under test is determined to be "unqualified". At this time, the detection control module 14 drives the test status indicator 50 to light up red by outputting a continuous high level with a second level value through the LED circuit.
[0057] To begin testing, open the memory chip test fixture 100. First, pick up the chip under test and place it into the limiting frame 22 of the test socket 20. Then, close the flip cover clamping block 30. The tester operates the test button on the test system. At this time, the power-on indicator light 40 and the test status indicator light 50 can be observed. They will display different states. The power-on indicator light 40 will be lit or unlit. When lit, it indicates that the memory chip test fixture 100 is powered on and the next chip test can be performed. If unlit, it indicates that there is no power and the test state cannot be entered. The memory chip test fixture 100 needs to be restarted or checked until the power-on indicator light 40 lights up again after power is restored.
[0058] During testing, the power-on indicator light 40 remains constantly on, while the test status indicator light 50 flashes continuously. Upon completion of the test, the power-on indicator light 40 automatically turns off, and the test status indicator light 50 stops flashing and displays either red or green. Green indicates that the chip test is successful, while red indicates that the chip test is unsuccessful. At this point, the chip testing is complete, and the tester can open the memory chip testing fixture 100 and, based on the indication of the test status indicator light 50, perform operations such as classification of the tested chips.
[0059] The memory chip testing fixture provided by the embodiments of this utility model has at least one or a portion of the following advantages:
[0060] (1) By setting different function indicator lights on the test fixture, the test status and test results of the test chip can be displayed intuitively, which is convenient for testers to operate and judge. At the same time, the abnormalities of the test chip not being powered on and the poor status can be distinguished, and these two types of abnormalities can be dealt with in a timely manner, saving time and improving test efficiency.
[0061] (2) By improving the test fixture for memory chips, power-on indicator and test status indicator are set on its test substrate respectively. When the test chip is closed, the power-on indicator can be used to confirm whether the test fixture is powered on. The test status indicator can be used to determine the progress of the memory chip test and the test results.
[0062] (3) By setting power-on indicator and test status indicator on the test board, operators can be provided with clear and intuitive information prompts for the entire test process, thereby improving the work efficiency and test accuracy of operators;
[0063] (4) The test status indicator flashes during the test to help remind the operator that the chip is under test. When the flashing stops and the corresponding color is displayed, the test result of the chip is reminded to the operator. The structure is simple and the prompts are intuitive.
[0064] (5) By using the power-on indicator and the test status indicator to distinguish between the abnormalities of the chip not being powered on and the abnormality of the status, the two types of abnormalities can be dealt with in a timely manner, saving time and improving test efficiency.
[0065] While some embodiments of the general concept of this utility model have been shown and described, those skilled in the art will understand that changes may be made to these embodiments without departing from the principles and spirit of the general concept of this utility model, the scope of which is defined by the claims and their equivalents.
Claims
1. A memory chip testing fixture, characterized in that, The memory chip testing fixture includes: Test substrate, A test socket is disposed on and electrically connected to the test substrate. The power-on indicator light is located on the test substrate. A test status indicator light is provided on the test substrate. The power-on indicator and the test status indicator are located on both sides of the test socket.
2. The memory chip testing fixture according to claim 1, characterized in that, The test stand includes a first light guide post and a second light guide post, which are respectively disposed on both sides of the test stand. The first light guide post is configured to correspond to the power-on indicator light. The second light guide column is set to correspond to the test status indicator light.
3. The memory chip testing fixture according to claim 2, characterized in that, The test substrate includes test positions, which are disposed on the test substrate. The power-on indicator and the test status indicator are located on both sides of the test position, respectively.
4. The memory chip testing fixture according to claim 3, characterized in that, The test socket also includes a mounting base, on which a limiting frame for accommodating the chip under test is provided. The bottom of the limiting frame is provided with conductive adhesive, which is electrically connected to the test position.
5. The memory chip testing fixture according to claim 4, characterized in that, The test fixture also includes a cover-lifting block, one side of which is rotatably connected to the mounting base. The flip-top pressing block has a chip pressing head on one side opposite to the mounting base, and the chip pressing head cooperates with the limiting frame.
6. The memory chip testing fixture according to claim 5, characterized in that, A closing latch is provided on the side of the cover-lifting block away from its connection with the mounting base. A cover slot is provided on the mounting base. The lid-closing buckle and the lid-closing slot cooperate with each other.
7. The memory chip testing fixture according to claim 6, characterized in that, The test substrate is also provided with mounting holes and positioning holes.
8. The memory chip testing fixture according to any one of claims 1-7, characterized in that, The memory chip testing fixture also includes a detection and control module disposed inside the testing substrate. The detection and control module includes an integrated control circuit and a data comparison unit. The power-on indicator and the test status indicator are electrically connected to the detection control module through the control circuit.
9. The memory chip testing fixture according to claim 8, characterized in that, The control circuit includes a chip testing circuit and an LED circuit. The chip testing circuit is electrically connected to the data comparison unit. The LED circuit includes a first indicator circuit and a second indicator circuit.
10. The memory chip testing fixture according to claim 9, characterized in that, The power-on indicator light is electrically connected to the first indicator circuit. When the memory chip test fixture is powered on, the detection control module outputs a level to the power-on indicator light through the first indicator circuit to drive the power-on indicator light to light up. The test status indicator is electrically connected to the second indicator circuit. When the memory chip test fixture is powered on and enters the chip test stage, the detection control module outputs different level values to the test status indicator via the second indicator circuit to drive the test status indicator to display different colors.