Image sensor equipped with thin-film transistors and method for manufacturing the same

Abstract

To provide a vertical color separation type imaging device in which an appropriately sized storage capacity is provided in each layer without changing a pixel aperture ratio between layers and without decreasing a pixel aperture ratio.SOLUTION: An imaging device 1 has a vertical color separation-type three-layer structure, Each layer includes a photoelectric conversion layer 10, a signal readout circuit 11, and an interlayer insulating layer 12 (a substrate 13 for a third layer). The photoelectric conversion layer 10 comprises a pixel electrode 20, a counter electrode 21, and an organic film 22 having upper and lower faces sandwiched with these electrodes. The signal readout circuit 11 comprises a TFT 30, wiring 31 and a storage capacitor electrode 32. The TFT 30 is constituted by laminating a gate electrode 40, a gate insulating film 41, a semiconductor 42, source and drain electrodes 43 and 44, and a protective film 45, in the order. The storage capacitor electrode 32 is provided at the bottom of the pixel electrode 20 such that the entire surface of the storage capacitor electrode is covered with the pixel electrode 20, and is made of the same material as the wiring 31 or the gate electrode 40 and has the same film thickness as the wiring 31 or the gate electrode 40, the storage capacitor electrode 32 being formed simultaneously with the wiring 31 or the gate electrode 40.SELECTED DRAWING: Figure 2

Description

[Technical Field]

[0001] The present invention relates to a vertical color separation type image sensor equipped with thin-film transistors (TFTs) and a method for manufacturing the same. [Background technology]

[0002] Current cameras employ two methods: a three-chip system that uses three image sensors to acquire color images, and a single-chip system that uses one image sensor to acquire color images.

[0003] In a three-chip system, incident light is separated into three primary colors—red (R), green (G), and blue (B)—by a color-separation prism, and images are acquired by three image sensors. This allows for efficient use of incident light and enables high-quality imaging, but on the other hand, the use of color-separation prisms makes miniaturization difficult.

[0004] On the other hand, in a single-chip system, RGB color filters are arranged in-plane on a single image sensor to separate colors. While this allows for miniaturization, it uses color filters that absorb light outside of a specific wavelength range from the incident light, resulting in lower light utilization efficiency and reduced image quality compared to a three-chip system.

[0005] Thus, both three-chip and single-chip image sensors have their advantages and disadvantages, and there is a need to develop image sensors that can achieve both high image quality and miniaturization in cameras.

[0006] In this context, a vertical color separation type image sensor has been proposed that uses a single image sensor to acquire all RGB information, with the aim of achieving both high image quality and miniaturization of the image sensor.

[0007] This image sensor comprises an organic photoelectric conversion film (organic film) that is sensitive only to R light, G light, and B light, respectively, and a signal readout circuit using a light-transmitting TFT, with these components stacked alternately. This allows for color separation in the direction of light propagation, enabling the acquisition of all RGB information using a single image sensor.

[0008] For example, an image sensor is disclosed in which three layers of organic films and signal readout circuits using TFTs are alternately directly stacked on a single glass substrate (see, for example, Patent Document 1). An image sensor is also disclosed in which three elements, each consisting of a signal readout circuit using TFTs and an organic film, are stacked on a glass substrate (see, for example, Patent Document 2). Furthermore, an image sensor is disclosed in which the bottom organic film and signal readout circuit are replaced with a CMOS image sensor (see, for example, Patent Document 3). [Prior art documents] [Patent Documents]

[0009] [Patent Document 1] Japanese Patent Publication No. 2002-217474 [Patent Document 2] Japanese Patent Publication No. 2005-51115 [Patent Document 3] Japanese Patent Publication No. 2019-102623 [Overview of the project] [Problems that the invention aims to solve]

[0010] In the stacked image sensors described in the aforementioned Patent Documents 1, 2, and 3, the value of the capacitance (pixel capacitance) for accumulating the signal charge generated in the organic film (pixel capacitance value) is determined from the capacitance of the organic film (organic film capacitance), the parasitic capacitance of the signal readout circuit, etc.

[0011] Since the sensitivity of the image sensor is determined by this pixel capacitance value, it is desirable to separately provide an appropriate design value for storage capacitance that takes into account the organic film capacitance. This is because by providing storage capacitance in each of the RGB layers, it is possible to obtain an image sensor with uniform sensitivity characteristics for each layer. In this case, the pixel capacitance value will be determined from the organic film capacitance, storage capacitance, parasitic capacitance, etc.

[0012] However, since each layer of organic film needs to be used with a film thickness corresponding to the differences in its respective properties (light absorption rate, quantum efficiency, etc.), differences in the capacity of each layer of organic film will occur.

[0013] Therefore, in order to obtain an appropriate design value for the storage capacitance, it is necessary to separately provide a storage capacitance (different storage capacitances for each layer) for compensating for the differences in the organic film capacitances of each layer in each layer.

[0014] However, if storage capacitances of sizes corresponding to each layer are provided within the pixel layout, the pixel aperture ratio for transmitting light to the lower layer may decrease. Also, if there are differences in the pixel aperture ratios of each layer, differences will occur in the characteristics as a signal readout circuit according to those differences. For this reason, there is a problem that inconveniences occur when driving the image sensor. Here, the pixel aperture ratio refers to the ratio occupied by the pixel electrodes (pixel electrodes 20-1, 20-2, 20-3 in the plane when viewed from the incident direction in FIG. 2 described later) in a pixel.

[0015] Therefore, the present invention has been made to solve the above problems, and an object thereof is to provide an image sensor and a method for manufacturing the same in a vertical color separation type image sensor, in which storage capacitances of appropriate sizes are provided in each layer without changing the pixel aperture ratio between layers and without decreasing the pixel aperture ratio.

Means for Solving the Problems

[0016] In order to solve the above problems, the image sensor according to claim 1 is configured by laminating a plurality of layers from the Nth to the 1st in order from top to bottom, which is the incident direction when light in at least N (N is an integer of 2 or more) wavelength regions is incident. Each of the layers other than the 1st layer (the nth layer where n is an integer of 2 or more and n is less than or equal to N) of the plurality of layers absorbs light in the nth wavelength region and performs photoelectric conversion, and transmits light other than the light in the nth wavelength region among the light incident on the nth layer. An nth photoelectric conversion layer, and an nth signal readout circuit that reads out the signal charges generated in the nth photoelectric conversion layer. The 1st layer includes a 1st photoelectric conversion layer that absorbs light in the 1st wavelength region and performs photoelectric conversion, and a 1st signal readout circuit that reads out the signal charges generated in the 1st photoelectric conversion layer. In the vertical color separation type image sensor, each of the signal readout circuits from the Nth to the 1st but, comprising at least one TFT, and provided with wiring and a storage capacitance electrode, each of the photoelectric conversion layers from the Nth to the 1st being provided with a pixel electrode, an organic film, and a counter electrode, wherein the TFT is configured by laminating a gate electrode, a gate insulating film, a semiconductor, source / drain electrodes, and a protective film in this order from bottom to top, which is the reverse direction of the incidence, and the storage capacitance electrode is entirely covered by the pixel electrode in a plan view from the incidence direction. Along with, the protective film is sandwiched between the pixel electrode, below the pixel electrode The source and drain electrodes are provided directly above the gate insulating film and directly below the protective film. It is characterized in that it is an electrode made of the same material and film thickness and formed simultaneously.

[0020] Furthermore, in the method for manufacturing an image pickup device according to claim 2 , in the order from top to bottom, which is the incidence direction when light in at least N (N is an integer of 2 or more) wavelength bands is incident, a plurality of layers from the Nth to the 1st are laminated and configured, and each of the layers other than the 1st layer (the nth (n is an integer of N or less and 2 or more) layer) among the plurality of layers absorbs light in the nth wavelength band and performs photoelectric conversion, and transmits light other than the light in the nth wavelength band among the light incident on the nth layer, and a photoelectric conversion layer of the nth layer, and a nth signal readout circuit for reading out the signal charges generated in the nth photoelectric conversion layer, and the 1st layer includes a 1st photoelectric conversion layer that absorbs light in the 1st wavelength band and performs photoelectric conversion, and a 1st signal readout circuit for reading out the signal charges generated in the 1st photoelectric conversion layer. In the method for manufacturing a vertical color separation type image pickup device, for the 1st layer, on a substrate, at least one TFT, which is configured by laminating a gate electrode, a gate insulating film, a semiconductor, source / drain electrodes, and a protective film in this order from bottom to top, which is the reverse direction of the incidence. and wiring are formed on the gate insulating film storage capacitance electrode Forms a protective film onThe process involves a first step of forming a pixel electrode, a second step of laminating an organic film on the protective film and the pixel electrode, a third step of forming a counter electrode on the organic film, a fourth step of providing an interlayer insulating film or interlayer substrate on the counter electrode formed in the (n-1)th layer for each of the n layers, and at least one TFT on the interlayer insulating film or interlayer substrate, wherein the TFT is constructed by laminating a gate electrode, gate insulating film, semiconductor, source / drain electrodes and protective film in the order of bottom to top, which is the reverse direction of incidence. and wiring are formed on the gate insulating film Storage capacitor electrode Forms a protective film on A fifth step is to form a pixel electrode; a sixth step is to laminate an organic film on the protective film of the TFT and the pixel electrode formed in the fifth step; and a seventh step is to form a counter electrode on the organic film laminated in the sixth step, thereby ensuring that the entire surface of the storage capacitance electrode is covered by the pixel electrode in the first and fifth steps. Along with, the protective film is sandwiched between the pixel electrode, Lower part of the pixel electrode and provided so as to be located directly above the gate insulating film and directly below the protective film, The aforementioned electrode for storage capacity is The source and drain electrodes It is characterized by being formed simultaneously using the same material and film thickness. [Effects of the Invention]

[0021] As described above, according to the present invention, in a vertical color separation type image sensor, it is possible to provide an appropriate size of storage capacity in each layer without changing the pixel aperture ratio between layers and without reducing the pixel aperture ratio. [Brief explanation of the drawing]

[0022] [Figure 1] This is a schematic cross-sectional view showing an example of the configuration of an image sensor according to an embodiment of the present invention. [Figure 2] This figure shows specific examples of components in a cross-sectional view of an image sensor according to an embodiment of the present invention. [Figure 3] This figure shows an example of the manufacturing process for an image sensor according to an embodiment of the present invention. [Figure 4] This diagram illustrates an example of the process for forming the third layer. [Figure 5]This figure shows specific examples of components in a cross-sectional view of an image sensor according to the first modified example. [Figure 6] This figure shows specific examples of components in a cross-sectional view of an image sensor according to a second modification. [Figure 7] This figure shows an example of a single-layer circuit with a 1-pixel-1-transistor configuration. [Figure 8] This figure shows an example of a single-layer layout in a 1-pixel-1-transistor configuration. [Figure 9] This figure shows an example of a single-layer circuit with a 1-pixel, 3-transistor configuration. [Figure 10] This figure shows an example of a single-layer layout in a 1-pixel, 3-transistor configuration. [Figure 11] This figure shows an example of a single-layer layout in the case of a 1-pixel-1-transistor configuration in the first modified example. [Figure 12] This figure shows an example of a single-layer layout in the case of a 1-pixel, 3-transistor configuration in the first modified example. [Modes for carrying out the invention]

[0023] The embodiments for carrying out the present invention will be described in detail below with reference to the drawings. [Image sensor configuration] First, the configuration of the image sensor according to an embodiment of the present invention will be described. Figure 1 is a schematic cross-sectional view showing an example of the configuration of an image sensor according to an embodiment of the present invention, and shows the cross-section of one pixel.

[0024] This image sensor 1 is a vertical color separation type organic image sensor, and is equipped with a first photoelectric conversion layer 10-1, a second photoelectric conversion layer 10-2, and a third photoelectric conversion layer 10-3 in the order of incidence from top to bottom, which is the direction of incidence when a predetermined light is incident. Furthermore, the image sensor 1 is equipped with a first signal readout circuit 11-1 below the first photoelectric conversion layer 10-1 and above the second photoelectric conversion layer 10-2, a second signal readout circuit 11-2 below the second photoelectric conversion layer 10-2 and above the third photoelectric conversion layer 10-3, and a third signal readout circuit 11-3 below the third photoelectric conversion layer. Furthermore, the image sensor 1 includes a first interlayer insulating layer 12-1 below the first signal readout circuit 11-1 and on the second photoelectric conversion layer 10-2, a second interlayer insulating layer 12-2 below the second signal readout circuit 11-2 and on the third photoelectric conversion layer 10-3, and a substrate 13 below the third signal readout circuit 11-3.

[0025] As shown in Figure 1, the image sensor 1 has a three-layer structure, consisting of a first layer comprising a first photoelectric conversion layer 10-1, a first signal readout circuit 11-1, and a first interlayer insulating layer 12-1, a second layer comprising a second photoelectric conversion layer 10-2, a second signal readout circuit 11-2, and a second interlayer insulating layer 12-2, and a third layer comprising a third photoelectric conversion layer 10-3, a third signal readout circuit 11-3, and a substrate 13, in the direction of incidence from top to bottom.

[0026] This image sensor 1 is designed to receive light including at least a first wavelength range, a second wavelength range, and a third wavelength range from the incident direction shown in Figure 1.

[0027] The first photoelectric conversion layer 10-1 absorbs light in a first wavelength range from the incident light of the image sensor 1 and performs photoelectric conversion, while transmitting light in a second wavelength range and light in a third wavelength range. The first signal readout circuit 11-1 reads out the signal charge generated by the photoelectric conversion of the first photoelectric conversion layer 10-1.

[0028] The second photoelectric conversion layer 10-2 absorbs the light in the second wavelength range and the light in the third wavelength range that was transmitted through the first photoelectric conversion layer 10-1, performs photoelectric conversion, and transmits the light in the third wavelength range. The second signal readout circuit 11-2 reads out the signal charge generated by the photoelectric conversion of the second photoelectric conversion layer 10-2.

[0029] The third photoelectric conversion layer 10-3 absorbs light in the third wavelength range transmitted through the second photoelectric conversion layer 10-2 and performs photoelectric conversion. The third signal readout circuit 11-3 reads out the signal charge generated by the photoelectric conversion of the third photoelectric conversion layer 10-3.

[0030] Figure 2 shows specific examples of components in a cross-sectional view of the image sensor 1 according to the embodiment of the present invention shown in Figure 1.

[0031] The first photoelectric conversion layer 10-1 in the first layer of the image sensor 1 is composed of a transparent pixel electrode (hereinafter referred to as "pixel electrode") 20-1, a transparent counter electrode (hereinafter referred to as "counter electrode") 21-1, and an organic film 22-1 sandwiched between these electrodes on its upper and lower surfaces.

[0032] The first signal readout circuit 11-1 in the first layer comprises a TFT 30-1, wiring 31-1, and a transparent storage capacitance electrode (hereinafter referred to as "storage capacitance electrode") 32-1. The TFT 30-1 is constructed by stacking a gate electrode 40, gate insulating film 41, semiconductor 42, source and drain electrodes 43, 44 (source electrode 43 and drain electrode 44), and protective film 45 in the order of bottom to top, in the opposite direction of incidence, on an interlayer insulating film 50-1 which is an interlayer insulating layer 12-1. The source electrode 43 and wiring 31-1 of the TFT 30-1 are connected by via holes 51.

[0033] The storage capacitance electrode 32-1 is provided such that its entire surface is covered by the pixel electrode 20-1 when viewed from the incident direction, and the gate insulating film 41 is sandwiched below the pixel electrode 20-1. It is made of the same material and film thickness as the wiring 31-1 or gate electrode 40, and is formed at the same time (formed integrally with the wiring 31-1 or gate electrode 40 (by the same process)). The interlayer insulating layer 12-1 is composed of the interlayer insulating film 50-1.

[0034] The second photoelectric conversion layer 10-2 in the second layer has the same components as the first photoelectric conversion layer 10-1 in the first layer, and consists of a pixel electrode 20-2, a counter electrode 21-2, and an organic film 22-2. The second signal readout circuit 11-2 has the same components as the first signal readout circuit 11-1, and includes a TFT 30-2, wiring 31-2, and a storage capacitance electrode 32-2. The storage capacitance electrode 32-2 is the same electrode as the storage capacitance electrode 32-1 in the first layer. The interlayer insulating layer 12-2 is composed of an interlayer insulating film 50-2.

[0035] The third photoelectric conversion layer 10-3 in the third layer has the same components as the first photoelectric conversion layer 10-1 in the first layer, and consists of a pixel electrode 20-3, a counter electrode 21-3, and an organic film 22-3. The third signal readout circuit 11-3 has the same components as the first signal readout circuit 11-1, and includes a TFT 30-3, wiring 31-3, and a storage capacitance electrode 32-3. The storage capacitance electrode 32-3 is the same electrode as the storage capacitance electrode 32-1 in the first layer.

[0036] [Method for manufacturing an image sensor] Next, a method for manufacturing the image sensor 1 according to an embodiment of the present invention will be described. Figure 3 is a diagram showing an example of the manufacturing process of the image sensor 1 according to the embodiment of the present invention shown in Figures 1 and 2, and Figure 4 is a diagram illustrating an example of the process for forming the third layer in the image sensor 1.

[0037] As shown in Figure 3, the manufacturing of the image sensor 1 is carried out in the following order: formation of the third layer (processes P301-P303), formation of the second layer (processes P304-P306), and formation of the first layer (processes P307-P309).

[0038] (Formation of the third layer) First, in order to form the third layer, the wiring 31-3 and the storage capacitance electrode 32-3 are simultaneously formed on the substrate 13 using the same material and film thickness, referring to Figures 3 and 4 (step P301).

[0039] In step P301, the wiring 31-3 and the capacitance electrode 32-3 are formed simultaneously on the substrate 13 using the same material and film thickness. However, the gate electrode 40 and the capacitance electrode 32-3 may also be formed simultaneously on the substrate 13 using the same material and film thickness. In this case, the wiring 31-3 is formed on the substrate 13 in a subsequent step, and it is not necessary to form the gate electrode 40 on the substrate 13 in the subsequent step P302-1. The same applies to steps P305 and P308, which will be described later.

[0040] Next, after step P301, the TFT 30-3 is formed on the substrate 13, and the pixel electrode 20-3 is formed on the gate insulating film 41 of the TFT 30-3 (step P302).

[0041] Specifically, referring to Figure 4, after step P301, a gate electrode 40 is formed on the substrate 13, a gate insulating film 41 is laminated on the substrate 13, wiring 31-3, gate electrode 40 and storage capacitance electrode 32-3, and a pixel electrode 20-3 is formed on the gate insulating film 41 (step P302-1).

[0042] Then, via holes 51 for connecting the wiring 31-3 and the source electrode 43 (described later) are formed at predetermined locations in the gate insulating film 41, a semiconductor 42 is formed on the gate insulating film 41, a source electrode 43 is formed on the gate insulating film 41 and the semiconductor 42, and a drain electrode 44 is formed on the gate insulating film 41, the semiconductor 42 and the pixel electrode 20-3 (step P302-2).

[0043] Then, a protective film 45 is laminated on the gate insulating film 41, semiconductor 42, source electrode 43, drain electrode 44, and pixel electrode 20-3 (step P302-3).

[0044] As a result, in steps P302-1 to P302-3, the TFT 30-3 is constructed by stacking the gate electrode 40, gate insulating film 41, semiconductor 42, source / drain electrodes 43, 44 and protective film 45 on the substrate 13 in that order.

[0045] Referring to Figures 3 and 4, after step P302 (after step P302-3), the organic film 22-3 is laminated on the pixel electrode 20-3 and the protective film 45, and the counter electrode 21-3 is formed on the organic film 22-3 (step P303).

[0046] As a result, the third layer of the image sensor 1 is formed in steps P301 to P303. The image sensor 1 is then formed by stacking three layers of this single-layer third layer in steps P304 to P309, such as by providing interlayer insulating films 50-2 and 50-1 in steps P304 and P307, which will be described later.

[0047] (Formation of the second layer) Next, after the third layer is formed, an interlayer insulating film 50-2 is laminated on the counter electrode 21-3 of the third layer in order to form the second layer (step P304), referring to Figure 3.

[0048] Next, wiring 31-2 and storage capacitance electrodes 32-2 are simultaneously formed on the interlayer insulating film 50-2 using the same material and film thickness (step P305).

[0049] Next, similar to step P302 described above, a TFT 30-2 is formed on the interlayer insulating film 50-2, and a pixel electrode 20-2 is formed on the gate insulating film 41 of the TFT 30-2. Then, similar to step P303 described above, an organic film 22-2 is laminated on the pixel electrode 20-2 and the protective film 45, and a counter electrode 21-2 is formed on the organic film 22-2 (step P306).

[0050] As a result, the second layer of the image sensor 1 is formed in steps P304 to P306.

[0051] (Formation of the first layer) Next, after the second layer is formed, an interlayer insulating film 50-1 is laminated on the counter electrode 21-2 of the second layer in order to form the first layer (step P307).

[0052] Next, wiring 31-1 and storage capacitance electrodes 32-1 are simultaneously formed on the interlayer insulating film 50-1 using the same material and film thickness (step P308).

[0053] Next, similar to step P302 described above, a TFT 30-1 is formed on the interlayer insulating film 50-1, and a pixel electrode 20-1 is formed on the gate insulating film 41 of the TFT 30-1. Then, similar to step P303 described above, an organic film 22-1 is laminated on the pixel electrode 20-1 and the protective film 45, and a counter electrode 21-1 is formed on the organic film 22-1 (step P309).

[0054] As a result, the first layer of the image sensor 1 is formed in steps P307 to P309, and the image sensor 1 is manufactured.

[0055] Furthermore, Figures 1 to 4 described above illustrate the case where the pixel electrodes 20-1, 20-2, and 20-3 are directly above the gate insulating film 41.

[0056] Alternatively, a protective film 45 may be formed over the entire image sensor 1, and an opening may be provided directly above the protective film 45, allowing the pixel electrodes 20-1, 20-2, and 20-3 to be placed in the opening. In either case, the storage capacitance electrodes 32-1, 32-2, and 32-3 are made of the same material and film thickness as the wiring 31-1, 31-2, and 31-3 or the gate electrode 40, and are formed at the same time.

[0057] [Variation] Next, a modified example of the image sensor 1 according to the embodiment of the present invention shown in Figures 1 to 4 will be described. (First variation) Figure 5 shows a specific example of the components in a cross-sectional view of the image sensor according to the first modified example, and shows the structure corresponding to the third layer in the cross-sectional view of the image sensor 1 shown in Figure 2.

[0058] The image sensor 2 according to this first modification has a three-layer structure similar to that in Figure 1, and is composed of a first layer, a second layer, and a third layer, from top to bottom in the incident direction. In Figure 5, only the third layer is shown, and the first and second layers are provided with an interlayer insulating film 50-1, which is an interlayer insulating layer 12-1, and an interlayer insulating film 50-2, which is an interlayer insulating layer 12-2, respectively, instead of the substrate 13 of the third layer.

[0059] In the image sensor 2, pixel electrodes 20-1, 20-2, and 20-3 are formed directly above the protective film 45, while storage capacitance electrodes 32-1, 32-2, and 32-3 are formed directly above the gate insulating film 41 and directly below the protective film 45.

[0060] Specifically, the third signal readout circuit 11-3 in the third layer comprises a TFT 30-3, wiring 31-3, and a storage capacitance electrode 32-3. The TFT 30-3 is constructed by stacking a gate electrode 40, gate insulating film 41, etc., and a protective film 45 on a substrate 13 in the same order as the TFT 30-3 shown in Figure 2. The source electrode 43 and wiring 31-3 of the TFT 30-3 are connected by via holes 51, and the pixel electrode 20-3 and drain electrode 44 are connected by via holes 52.

[0061] The storage capacitance electrode 32-3 is positioned such that, in a plan view from the incident direction, its entire surface is covered by the pixel electrode 20-3, with a protective film 45 sandwiched below the pixel electrode 20-3, and above the gate insulating film 41. It is made of the same material and film thickness as the source and drain electrodes 43 and 44, and is formed at the same time. In other words, the storage capacitance electrode 32-3 is entirely covered by the pixel electrode 20-3, and is positioned directly below the protective film 45 and directly above the gate insulating film 41. The same applies to the second and first layers.

[0062] Next, a method for manufacturing the image sensor 2 according to the first modified example will be described. The manufacturing of the image sensor 2 is carried out in the same order as for the image sensor 1 shown in Figure 3, with the formation of the third layer, the second layer, and the first layer.

[0063] First, in order to form the third layer, wiring 31-3 is formed on the substrate 13, and then TFT 30-3 is formed on the substrate 13, and at the same time, a storage capacitance electrode 32-3 is formed directly above the gate insulating film 41 and directly below the protective film 45.

[0064] Specifically, a gate electrode 40 is formed on the substrate 13, a gate insulating film 41 is laminated on the substrate 13, the wiring 31-3 and the gate electrode 40, and a storage capacitance electrode 32-3 is formed on the gate insulating film 41.

[0065] Next, via holes 51 for connecting the wiring 31-3 and the source electrode 43 (described later) are formed at predetermined locations in the gate insulating film 41, a semiconductor 42 is formed on the gate insulating film 41, the source electrode 43 is formed on the gate insulating film 41 and the semiconductor 42, and a drain electrode 44 is formed on the gate insulating film 41 and the semiconductor 42.

[0066] Next, a protective film 45 is laminated onto the storage capacitance electrode 32-3, gate insulating film 41, semiconductor 42, source electrode 43, and drain electrode 44. Then, via holes 52 for connecting the drain electrode 44 and the pixel electrode 20-3 (described later) are formed at predetermined locations in the protective film 45, and the pixel electrode 20-3 is formed on the protective film 45.

[0067] Next, an organic film 22-3 is stacked on the pixel electrode 20-3 and the protective film 45, and a counter electrode 21-3 is formed on the organic film 22-3.

[0068] This forms the third layer of the image sensor 2. By stacking the second and first layers on the single-layer element of the third layer thus fabricated, such as by providing interlayer insulating films 50-2 and 50-1, a three-layer image sensor 2 is formed.

[0069] (Second variation) Figure 6 shows a specific example of the components in a cross-sectional view of the image sensor according to the second modified example, and shows the structure corresponding to the third layer in the cross-sectional view of the image sensor 1 shown in Figure 2.

[0070] The image sensor 3 according to this second modification has a three-layer structure similar to that in Figure 1, and is composed of a first layer, a second layer, and a third layer, from top to bottom in the direction of incidence. In Figure 6, only the third layer is shown, and the first and second layers are provided with an interlayer insulating film 50-1, which is an interlayer insulating layer 12-1, and an interlayer insulating film 50-2, which is an interlayer insulating layer 12-2, respectively, instead of the substrate 13 of the third layer.

[0071] In the image sensor 3, pixel electrodes 20-1, 20-2, and 20-3 are formed directly above the protective film 45, while storage capacitance electrodes 32-1, 32-2, and 32-3 are formed directly below the gate insulating film 41.

[0072] Specifically, the third signal readout circuit 11-3 in the third layer comprises a TFT 30-3, wiring 31-3, and a storage capacitance electrode 32-3. The TFT 30-3 is constructed by stacking a gate electrode 40, gate insulating film 41, etc., and a protective film 45 on a substrate 13 in the same order as the TFT 30-3 shown in Figure 2. The source electrode 43 and wiring 31-3 of the TFT 30-3 are connected by via holes 51, and the pixel electrode 20-3 and drain electrode 44 are connected by via holes 52.

[0073] The storage capacitance electrode 32-3 is positioned such that its entire surface is covered by the pixel electrode 20-3 when viewed from the incident direction, with a protective film 45 and a gate insulating film 41 sandwiched below the pixel electrode 20-3, and located below the gate insulating film 41. It is made of the same material and film thickness as the wiring 31-3 or gate electrode 40, and is formed at the same time. In other words, the storage capacitance electrode 32-3 is fully covered by the pixel electrode 20-3, located below the pixel electrode 20-3, and directly beneath the gate insulating film 41. The same applies to the second and first layers.

[0074] Next, a method for manufacturing the image sensor 3 using a second modified example will be described. The manufacturing of the image sensor 3 is carried out in the same order as for the image sensor 1 shown in Figure 3: formation of the third layer, formation of the second layer, and formation of the first layer.

[0075] First, in order to form the third layer, wiring 31-3 and storage capacitance electrodes 32-3 are simultaneously formed on the substrate 13 using the same material and film thickness. Then, TFT 30-3 is formed on the substrate 13. Note that the storage capacitance electrodes 32-3 may be formed simultaneously with the gate electrode 40, which will be described later, using the same material and film thickness.

[0076] Next, via holes 51 for connecting the wiring 31-3 and the source electrode 43 (described later) are formed at predetermined locations in the gate insulating film 41, a semiconductor 42 is formed on the gate insulating film 41, the source electrode 43 is formed on the gate insulating film 41 and the semiconductor 42, and a drain electrode 44 is formed on the gate insulating film 41 and the semiconductor 42.

[0077] Next, a protective film 45 is laminated on the gate insulating film 41, semiconductor 42, source electrode 43, and drain electrode 44. Then, via holes 52 for connecting the drain electrode 44 and the pixel electrode 20-3 (described later) are formed at predetermined locations in the protective film 45, and the pixel electrode 20-3 is formed on the protective film 45.

[0078] Next, an organic film 22-3 is stacked on the pixel electrode 20-3 and the protective film 45, and a counter electrode 21-3 is formed on the organic film 22-3.

[0079] This forms the third layer of the image sensor 3. By stacking the second and first layers on the single-layer element of the third layer thus fabricated, such as by providing interlayer insulating films 50-2 and 50-1, a three-layer image sensor 3 is formed.

[0080] [Circuit example and plan view layout example] In Figures 1 to 4 above, the image sensor 1 was described as having a one-pixel, one-transistor configuration (one-layer, one-transistor configuration) in which one TFT 30 is provided to which the pixel electrode 20 and drain electrode 44 (or source electrode 43) are connected. In contrast, the image sensor 1 may also have a one-pixel, multiple-transistor configuration (one-layer, multiple-transistor configuration) in which multiple transistors are provided in one pixel. The same applies to the first modified image sensor 2 shown in Figure 5 and the second modified image sensor 3 shown in Figure 6.

[0081] The following describes single-layer circuits in a 1-pixel, 1-transistor configuration and a 1-pixel, 3-transistor configuration. Pixel electrodes 20-1, 20-2, and 20-3 are collectively referred to as pixel electrode 20, counter electrodes 21-1, 21-2, and 21-3 are collectively referred to as counter electrode 21, and storage capacitance electrodes 32-1, 32-2, and 32-3 are collectively referred to as storage capacitance electrode 32. Wiring 31-1, 31-2, and 31-3 are collectively referred to as wiring 31, and TFTs 30-1, 30-2, and 30-3 are collectively referred to as TFT 30.

[0082] (One pixel, one transistor configuration in image sensor 1) First, we will describe an example of the circuit and a plan view layout of the image sensor 1 in the embodiment of the present invention shown in Figure 2.

[0083] Figure 7 shows an example of a single-layer circuit in a 1-pixel, 1-transistor configuration. The circuit of this image sensor 1 is a selectable TFT 30A (M) to which the pixel electrode 20 and the source electrode 43 or drain electrode 44 are connected. S ), a capacitor element made of an organic film 22 sandwiched between the counter electrode 21 and the pixel electrode 20, and a capacitor element made of a gate insulating film 41 sandwiched between the pixel electrode 20 and the storage capacitance electrode 32 (C S ) is composed of and corresponds to the structure of each layer shown in Figure 2. In this case, the organic film capacitance of the capacitor element by the organic film 22 is the same as that of the capacitor element (C S The total capacity, obtained by adding the storage capacity of each layer, will be the same for each layer.

[0084] Figure 8 shows an example of a single-layer layout in a 1-pixel-1-transistor configuration, and corresponds to the circuit example shown in Figure 7.

[0085] As shown in Figure 8, the single layer of the image sensor 1 has one selection TFT 30A, and a pixel electrode 20 is formed above the storage capacitance electrode 32. An organic film 22 (not shown) and a counter electrode 21 are formed over the entire surface above these layers (see Figure 2).

[0086] The pixel electrode 20 is located inside the protective film opening 60 where the protective film 45 is not present.

[0087] (Image sensor 1 has a 3-transistor configuration per pixel) Figure 9 shows an example of a single-layer circuit in a 1-pixel, 3-transistor configuration. The circuit of this image sensor 1 is connected to an amplification TFT 30B (described later) and a selectable TFT 30A (M) to which the source electrode 43 or drain electrode 44 is connected. S ), the amplification TFT 30B (M) to which the pixel electrode 20 and gate electrode 40 are connected. A ), reset TFT30C(M) for resetting the storage capacity electrode 32 R ), a capacitor element made of an organic film 22 sandwiched between the counter electrode 21 and the pixel electrode 20, and a capacitor element made of a gate insulating film 41 sandwiched between the pixel electrode 20 and the storage capacitance electrode 32 (C S This structure is composed of ) and corresponds to a structure in which each layer shown in Figure 2 has three TFT30s.

[0088] Figure 10 shows an example of a single-layer layout in a 1-pixel, 3-transistor configuration, and corresponds to the circuit example shown in Figure 9.

[0089] As shown in Figure 10, the single layer of the image sensor 1 has three TFTs: a selection TFT 30A, an amplification TFT 30B, and a reset TFT 30C, as well as a pixel electrode 20 formed above the storage capacitance electrode 32. An organic film 22 (not shown) and a counter electrode 21 are formed over the entire surface above these layers (see Figure 2).

[0090] The pixel electrode 20 is located inside the protective film opening 60 where the protective film 45 is not present. The via hole 51' is formed within the gate insulating film 41 (not shown).

[0091] Furthermore, the layout examples shown in Figures 8 and 10 show the case where the capacitance storage electrode 32 is made of the same material and film thickness as the wiring 31 or gate electrode 40, and is formed at the same time, as shown in Figures 1 to 4 and 6. The wiring connecting the capacitance storage electrode 32 to the outside of the pixel is formed without intersecting with other lateral wiring.

[0092] (One pixel, one transistor configuration in image sensor 2) Next, an example of the circuit and a plan view layout of the first modified image sensor 2 shown in Figure 5 will be described. As mentioned above, the first modified image sensor 2 shown in Figure 5 shows a case where the storage capacitance electrode 32 is made of the same material and film thickness as the source and drain electrodes 43 and 44, and is formed at the same time.

[0093] Figure 11 shows an example of a single-layer layout in the case of a one-pixel, one-transistor configuration in the first modified example, and corresponds to the circuit example shown in Figure 7.

[0094] As shown in Figure 11, the single layer of the image sensor 2 has one selection TFT 30A, and a pixel electrode 20 is formed above the storage capacitance electrode 32. An organic film 22 (not shown) and a counter electrode 21 are formed over the entire surface above these layers (see Figure 5).

[0095] The pixel electrode 20 is located inside the protective film opening 60. The via hole 51' is formed within the gate insulating film 41 (not shown).

[0096] The wiring connecting the storage capacitance electrode 32 to the outside of the pixel is formed in advance at the intersection with the vertical wiring (at the location of the via hole 51' formed in the gate insulating film 41, which is not shown) when forming the lateral wiring. Then, after opening the gate insulating film 41, the storage capacitance electrode 32 is formed simultaneously with the vertical wiring, and the storage capacitance electrode 32 is connected to the lateral wiring that was formed in advance (the wiring connecting the storage capacitance electrode 32 to the outside of the pixel). Furthermore, the wiring 31 connecting the storage capacitance electrode 32 to the outside of the pixel is formed without intersecting with other lateral wiring. The same applies to Figure 12, which will be described later.

[0097] (Image sensor 2 has a 3-transistor configuration per pixel) Figure 12 shows an example of a single-layer layout in the case of a 1-pixel, 3-transistor configuration in the first modified example, and corresponds to the circuit example shown in Figure 9.

[0098] As shown in Figure 12, the single layer of the image sensor 2 has three TFTs: a selection TFT 30A, an amplification TFT 30B, and a reset TFT 30C, as well as a pixel electrode 20 formed above the storage capacitance electrode 32. An organic film 22 (not shown) and a counter electrode 21 are formed over the entire surface above these layers (see Figure 5).

[0099] The pixel electrode 20 is located inside the protective film opening 60. The via hole 51' is formed within the gate insulating film 41 (not shown). The wiring connecting the storage capacitance electrode 32 to the outside of the pixel is the same as in Figure 11.

[0100] Note that the examples shown in Figures 1 to 12 show only one pixel of image sensors 1, 2, and 3, but in reality, image sensors 1, 2, and 3 have a number of pixels arranged vertically and horizontally in an array. Also, the examples shown in Figures 1 to 12 show the case where the storage capacitance electrode 32 is connected to ground outside the pixel (see Figures 7 and 9), but the storage capacitance electrode 32 may be connected to a power supply that is below the reset potential and at a fixed potential.

[0101] [Materials, etc., of the components of the image sensor 1] Next, we will explain the materials and other components of the image sensor 1 shown in Figure 2. The same applies to the image sensor 2, which is the first modified example shown in Figure 5, and the image sensor 3, which is the second modified example shown in Figure 6.

[0102] Hereinafter, the first photoelectric conversion layer 10-1, the second photoelectric conversion layer 10-2, and the third photoelectric conversion layer 10-3 will be collectively referred to as the photoelectric conversion layer 10, and the first signal readout circuit 11-1, the second signal readout circuit 11-2, and the third signal readout circuit 11-3 will be collectively referred to as the signal readout circuit 11. Furthermore, the first interlayer insulating layer 12-1 and the second interlayer insulating layer 12-2 will be collectively referred to as the interlayer insulating layer 12, and the interlayer insulating films 50-1 and 50-2 will be collectively referred to as the interlayer insulating film 50.

[0103] Materials used for the substrate 13 include glass, silicon, silicon oxide, magnesium oxide, nickel oxide, aluminum oxide, plastic film, polyimide, polyethylene terephthalate (PET), etc.

[0104] The photoelectric conversion layer 10 has a rectangular shape when viewed from the direction of incident light, and the organic film 22 of the photoelectric conversion layer 10 is made of a single organic material that has the property of absorbing light in a specific wavelength range and transmitting light in other wavelength ranges. The organic film 22 may also be constructed by mixing or laminating two or more types of organic materials.

[0105] Organic materials that are sensitive only to blue light (absorbing light in the blue wavelength range and transmitting other light) include, for example, coumarin derivatives and porphyrin derivatives. Organic materials that are sensitive only to green light (absorbing light in the green wavelength range and transmitting other light) include, for example, quinacridone derivatives and perylene derivatives. Organic materials that are sensitive only to red light (absorbing light in the red wavelength range and transmitting other light) include, for example, phthalocyanine derivatives and naphthalocyanine derivatives.

[0106] The thickness of the organic film 22 is preferably about 10 nm to 1 μm. In addition, an electron blocking layer or hole blocking layer with a thickness of about 5 nm to 50 nm may be appropriately inserted into the photoelectric conversion layer 10 to prevent charge injection from the electrodes.

[0107] A transparent conductive material with light transmission properties is desirable for the pixel electrode 20. For example, indium tin oxide (ITO), fluorine-doped tin oxide (FTO), indium zinc oxide (IZO), zinc oxide (ZnO), tin oxide (SnO2), etc., can be used. The film thickness of the pixel electrode 20 is preferably about 5 nm to 100 nm.

[0108] A transparent conductive material with light transmission properties is desirable for the material of the counter electrode 21. For example, indium tin oxide (ITO), fluorine-doped tin oxide (FTO), indium zinc oxide (IZO), zinc oxide (ZnO), tin oxide (SnO2), etc., can be used.

[0109] The material of the storage capacitance electrode 32 is formed collectively using the same material as the wiring 31, gate electrode 40, and one of the source / drain electrodes 43, 44. The film thickness of the storage capacitance electrode 32 is preferably about 5 nm to 100 nm.

[0110] For the signal readout circuit 11, it is preferable to use a TFT 30 made of a light-transmitting semiconductor material. For example, zinc oxide (ZnO) and amorphous oxide semiconductors such as indium gallium zinc oxide (InGaZnO) can be used as semiconductor materials. The film thickness of the TFT 30 is preferably 5 nm to 100 nm.

[0111] As the material of the protective film 45, it is desirable to use a material formed of an insulating material. For example, inorganic insulating materials such as silicon, silicon oxide, magnesium oxide, nickel oxide, aluminum oxide, or organic insulating materials such as olefin resins, acrylic resins, polyimide, etc. are used. Also, materials obtained by laminating two or more of these are used. The film thickness of the protective film 45 is preferably about 50 nm to several μm.

[0112] As the material of the gate insulating film 41 of the TFT 30, for example, inorganic insulating materials such as silicon, silicon oxide, magnesium oxide, nickel oxide, aluminum oxide, or organic insulating materials such as olefin resins, acrylic resins, polyimide, etc. are used. Also, materials obtained by laminating two or more of these are used. The film thickness of the gate insulating film 41 is preferably about 50 nm to several hundred nm.

[0113] As the material of the substrate 13 and the interlayer insulating layer 12 (interlayer insulating film 50), it is desirable to use a material formed of a light-transmissive insulating material. For example, silicon, silicon oxide, magnesium oxide, nickel oxide, aluminum oxide, plastic film, polyimide, polyethylene terephthalate (PET), etc. are used.

[0114] 〔Example of color imaging device〕 Next, the case where the imaging device 1 is applied to a three-layer stacked color imaging device will be described. The same applies to the imaging devices 2 and 3.

[0115] The pixel pitch is set to 50 μm, the pixel aperture ratio, that is, the ratio occupied by the pixel electrodes 20-1, 20-2, 20-3 in the pixel is set to 37%, and the area of the pixel electrodes 20-1, 20-2, 20-3 is 9.25×10 -10 m 2 . Also, the light in the first wavelength range is blue light (peak wavelength 450 nm), the light in the second wavelength range is green light (peak wavelength 500 - 540 nm), and the light in the third wavelength range is red light (peak wavelength 650 nm).

[0116] A 400 nm layer of coumarin derivative (dielectric constant 4.0) is stacked as the organic film 22-1 of the first photoelectric conversion layer 10-1, a 200 nm layer of quinacridone derivative (dielectric constant 4.0) is stacked as the organic film 22-2 of the second photoelectric conversion layer 10-2, and a 100 nm layer of naphthalocyanine derivative (dielectric constant 4.0) is stacked as the organic film 22-3 of the third photoelectric conversion layer 10-3. In addition, an electron blocking layer and a hole blocking layer (both with a dielectric constant 4.0) are inserted at a depth of 30 nm each in the first to third photoelectric conversion layers 10-1, 10-2, and 10-3.

[0117] In this case, the capacitances of the first to third photoelectric conversion layers 10-1, 10-2, and 10-3 (capacitances between the counter electrodes 21-1, 21-2, and 21-3 sandwiching the organic films 22-1, 22-2, and 22-3 and the pixel electrodes 20-1, 20-2, and 20-3) are 71.2 fF, 126 fF, and 205 fF, respectively.

[0118] Now, let's consider a case where the storage capacitance electrodes 32-1, 32-2, and 32-3 are formed simultaneously with the wiring 31-1, 31-2, and 31-3, respectively, with the gate insulating film 41 sandwiched between them and the pixel electrodes 20-1, 20-2, and 20-3, and the pixel capacitance value is set to 40 fF.

[0119] In this case, if silicon oxide with a thickness of 200 nm (relative permittivity of 3.9) is used as the gate insulating film 41, the capacitances of the storage capacitance electrodes 32-1, 32-2, and 32-3 (the capacitance between the storage capacitance electrodes 32-1, 32-2, and 32-3 sandwiching the gate insulating film 41 and the pixel electrodes 20-1, 20-2, and 20-3) should be 91.3 fF, 58.6 fF, and 49.7 fF, respectively.

[0120] Therefore, the area of ​​the storage capacity electrodes 32-1, 32-2, and 32-3 is 5.29 × 10⁻⁶ each. -10 m 2 ,3.39×10 -10 m 2 ,2.88×10 -10 m 2 That's all you need to do.

[0121] In this way, by providing the storage capacitance electrodes 32-1, 32-2, and 32-3 having the aforementioned area, it is possible to absorb the differences in organic film capacitance due to the differences in the thickness of the organic films 22-1, 22-2, and 22-3 in each layer, and to achieve a pixel capacitance value of 40 fF, which is the same for each layer.

[0122] Furthermore, the area of ​​the pixel electrodes 20-1, 20-2, and 20-3 is 9.25 × 10⁻⁶. -10 m 2 The areas of the storage capacity electrodes 32-1, 32-2, and 32-3 are 5.29 × 10⁻⁶ each. -10 m 2 ,3.39×10 -10 m 2 ,2.88×10 -10 m 2 Therefore, the area of ​​the storage capacitance electrodes 32-1, 32-2, and 32-3 can be made smaller than the area of ​​the pixel electrodes 20-1, 20-2, and 20-3, and no inconsistencies arise in the layout design.

[0123] In other words, the storage capacitance electrodes 32-1, 32-2, and 32-3 can be placed below the pixel electrodes 20-1, 20-2, and 20-3, respectively, so that their entire surfaces are covered by the pixel electrodes 20-1, 20-2, and 20-3 when viewed in a plan view in the direction of incidence.

[0124] Furthermore, when the image sensor 1 is applied to a three-layer stacked color image sensor, even if organic films 22-1, 22-2, and 22-3 of different materials and thicknesses are used in each layer, the pixel aperture ratio can be kept the same without changing between layers. Also, since the TFT 30 can be placed as is and no other metal materials are required, appropriate-sized storage capacitance electrodes 32-1, 32-2, and 32-3 can be provided in each layer without reducing the pixel aperture ratio, that is, without sacrificing the pixel aperture ratio. And the pixel capacitance value can be made the same in each layer.

[0125] As described above, the image sensor 1 according to the embodiment of the present invention has a vertical color separation type three-layer structure, and each layer is composed of a photoelectric conversion layer 10, a signal readout circuit 11, and an interlayer insulating layer 12 (or a substrate 13 in the case of the third layer).

[0126] The photoelectric conversion layer 10 consists of a pixel electrode 20, a counter electrode 21, and an organic film 22 sandwiched between these electrodes on its upper and lower surfaces, while the signal readout circuit 11 consists of a TFT 30, wiring 31, and a storage capacitance electrode 32.

[0127] The TFT 30 is constructed by stacking a gate electrode 40, gate insulating film 41, semiconductor 42, source / drain electrodes 43, 44, and protective film 45 in that order on an interlayer insulating film 50 (substrate 13 in the case of the third layer), which is an interlayer insulating layer 12.

[0128] The storage capacitance electrode 32 is provided below the pixel electrode 20 so that its entire surface is covered by the pixel electrode 20, and is made of the same material and film thickness as the wiring 31 or gate electrode 40, and is formed at the same time.

[0129] This makes it possible to provide an appropriate size of storage capacitance while matching the circuit characteristics of each layer, without changing or reducing the pixel aperture ratio, and by forming the storage capacitance electrode 32 in the same process as other layers, without increasing the number of steps.

[0130] In other words, in a vertical color separation type image sensor 1, it is possible to provide an appropriate size of storage capacity in each layer without changing the pixel aperture ratio between layers, without reducing the pixel aperture ratio, that is, without making the pixel aperture ratio the same for each layer and without sacrificing the pixel aperture ratio.

[0131] Although the present invention has been described above with reference to embodiments, a first modification, and a second modification, the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the technical concept.

[0132] For example, in the image sensor 1 shown in Figures 1 to 4, the image sensor 2 shown in Figure 5, and the image sensor 3 shown in Figure 6, interlayer insulating films 50-1 and 50-2 are provided between the layers, but a substrate 13 (interlayer substrate) may also be provided between the layers. In this case, by stacking three single-layer elements as the third layer, an image sensor 1 is fabricated using the substrate 13 as the interlayer insulating layers 12-1 and 12-2.

[0133] Furthermore, while the image sensor 1 shown in Figures 1 to 4, the image sensor 2 shown in Figure 5, and the image sensor 3 shown in Figure 6 are examples composed of a total of three layers, the number of layers in the present invention does not necessarily have to be three; it may be two or four layers, or any number of layers, up to N (where N is an integer of 2 or more). In other words, the present invention is applicable to vertical color separation type organic image sensors composed of multiple layers stacked in order from top to bottom, which is the incident direction when light in a wavelength range of at least N or more is incident.

[0134] Furthermore, in the image sensor 1 shown in Figures 1 to 4, the image sensor 2 shown in Figure 5, and the image sensor 3 shown in Figure 6, a filter that absorbs infrared light may be provided on the first photoelectric conversion layer 10-1 in the first layer.

[0135] Furthermore, in the image sensor 1 shown in Figures 1 to 4, the image sensor 2 shown in Figure 5, and the image sensor 3 shown in Figure 6, one TFT30 is provided in each layer, and in the examples in Figures 9, 10, and 12, three TFT30s are provided in each layer, but other numbers of TFT30s may also be provided. In short, the present invention only requires that at least one TFT30 be provided in each layer. [Explanation of Symbols]

[0136] 1,2,3 Image sensors 10 Photoelectric conversion layer 11 Signal readout circuit 12 interlayer insulating layer 13 circuit boards 20 Pixel electrodes 21 Counter electrode 22 Organic film 30 TFT 30A Selectable TFT 30B Amplifier TFT 30C Reset TFT 31 Wiring 32 Electrode for storage capacitor 40 Gateway 41 Gate insulating film 42 Semiconductors 43 Source electrode 44 Drain electrodes 45 Protective film 50 Interlayer insulating film 51, 51', 52 Beer Hall 60 Protective membrane opening

Claims

1. The device is constructed by stacking multiple layers, from the Nth to the 1st, in the order of incidence from top to bottom, which is the direction of incidence when light with a wavelength range of at least N (where N is an integer greater than or equal to 2) or more is incident on it. Each of the plurality of layers other than the first layer (the nth layer (where n is less than or equal to N and an integer of 2 or more)) is a photoelectric conversion layer that absorbs light in the nth wavelength range and performs photoelectric conversion, and transmits light other than the nth wavelength range from the light incident on the nth layer, and an nth signal readout circuit that reads out the signal charge generated in the nth photoelectric conversion layer, In a vertical color separation type image sensor, the first layer comprises a first photoelectric conversion layer that absorbs light in a first wavelength range and performs photoelectric conversion, and a first signal readout circuit that reads out the signal charge generated in the first photoelectric conversion layer, Each of the Nth to the First signal readout circuits includes at least one TFT, as well as wiring and electrodes for storage capacitance. Each of the Nth to the first photoelectric conversion layers comprises a pixel electrode, an organic film, and a counter electrode. The TFT is constructed by stacking the gate electrode, gate insulating film, semiconductor, source / drain electrodes, and protective film in the order of bottom to top, which is the reverse direction of incidence. The image sensor is characterized in that the storage capacitance electrode is entirely covered by the pixel electrode in a plan view from the incident direction, and is located below the pixel electrode, directly above the gate insulating film and directly below the protective film, sandwiching the protective film between itself and the pixel electrode, and is made of the same material and film thickness as the source and drain electrodes, and is formed at the same time.

2. The device is constructed by stacking multiple layers, from the Nth to the 1st, in the order of incidence from top to bottom, which is the direction of incidence when light with a wavelength range of at least N (where N is an integer greater than or equal to 2) or more is incident on it. Each of the plurality of layers other than the first layer (the nth layer (where n is less than or equal to N and an integer of 2 or more)) is a photoelectric conversion layer that absorbs light in the nth wavelength range and performs photoelectric conversion, and transmits light other than the nth wavelength range from the light incident on the nth layer, and an nth signal readout circuit that reads out the signal charge generated in the nth photoelectric conversion layer, A method for manufacturing a vertical color separation type image sensor, comprising a first layer which is a first photoelectric conversion layer that absorbs light in a first wavelength range and performs photoelectric conversion, and a first signal readout circuit that reads out the signal charge generated in the first photoelectric conversion layer, Regarding the first layer, The first step involves forming at least one TFT on a substrate, wherein the TFT and wiring are constructed by stacking a gate electrode, a gate insulating film, a semiconductor, source / drain electrodes, and a protective film in the reverse direction of incidence from bottom to top, and forming a storage capacitance electrode on the gate insulating film and a pixel electrode on the protective film. A second step involves laminating an organic film on the protective film and the pixel electrode, A third step is performed to form a counter electrode on the organic film, For each of the n layers mentioned above, A fourth step involves providing an interlayer insulating film or interlayer substrate on the counter electrode formed in the (n-1)th layer, A fifth step involves forming at least one TFT on the interlayer insulating film or the interlayer substrate, wherein the TFT and wiring are constructed by stacking a gate electrode, a gate insulating film, a semiconductor, source / drain electrodes, and a protective film in the reverse direction of incidence from bottom to top, and forming a storage capacitance electrode on the gate insulating film and a pixel electrode on the protective film. A sixth step involves laminating an organic film onto the protective film of the TFT and the pixel electrode formed in the fifth step, A seventh step is performed in which a counter electrode is formed on the organic film laminated by the sixth step described above, A manufacturing method characterized in that, by the first and fifth steps, the entire surface of the storage capacity electrode is covered by the pixel electrode, and the storage capacity electrode is simultaneously formed with the same material and film thickness as the source and drain electrodes, so as to be located below the pixel electrode, directly above the gate insulating film and directly below the protective film, with the protective film sandwiched between the pixel electrode and the storage capacity electrode.

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