Solid-state image sensor and method for manufacturing the same

Abstract

[Problem] To suppress deterioration in quantum efficiency and suppress increase in parasitic capacitance and dark current. [Solution] A solid-state imaging element comprising: a photoelectric conversion layer that includes a compound semiconductor material; two laminated semiconductor layers that are disposed on the opposite side to the light-incidence surface of the photoelectric conversion layer and each including impurities having mutually different conductivity types; and a diffusion layer that is disposed on a side wall of the photoelectric conversion layer and the two semiconductor layers and includes impurities having a higher impurities concentration than the two semiconductor layers. The width of the two semiconductor layers in the planar direction, excluding the diffusion layer on the side wall, is less than the width of the photoelectric conversion layer in the planar direction, excluding the diffusion layer on the side wall.

Description

[Technical Field]

[0001] The embodiments described herein relate to a solid-state image sensor and a method for manufacturing the same. [Background technology]

[0002] Compound semiconductors are used in image sensors for short-infrared cameras. Furthermore, it is desirable that solid-state image sensors used in image sensors suppress the movement of signal charge between adjacent pixels and reduce dark current. Therefore, a structure has been proposed in which grooves are provided to separate pixels, and an impurity diffusion layer is provided on the side of the grooves (see, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] International Publication No. 2018 / 212175 [Overview of the project] [Problems that the invention aims to solve]

[0004] However, as the impurity diffusion layer thickens, for example, the photoelectric conversion layer becomes narrower, potentially leading to a decrease in quantum efficiency. On the other hand, as the impurity diffusion layer thins, for example, the depletion layer caused by the pn junction in the semiconductor layer on the photoelectric conversion layer becomes wider, potentially increasing parasitic capacitance and dark current. In other words, the thickness of the impurity diffusion layer is in a trade-off relationship, making it difficult to achieve both high quantum efficiency and low parasitic capacitance and dark current.

[0005] Therefore, this disclosure provides a solid-state image sensor and a method for manufacturing the same that can suppress a decrease in quantum efficiency and suppress an increase in parasitic capacitance and dark current. [Means for solving the problem]

[0006] To solve the above problems, according to this disclosure, A photoelectric conversion layer containing a compound semiconductor material, Two stacked semiconductor layers are arranged on the opposite side of the photoelectric conversion layer from the light incident surface, each containing impurities of different conductivity types. The photoelectric conversion layer and the two semiconductor layers are disposed on the side walls of the two semiconductor layers, and the diffusion layer contains impurities with a higher impurity concentration than the two semiconductor layers, A solid-state image sensor is provided in which the planar width of the two semiconductor layers, excluding the diffusion layer on the sidewall, is narrower than the planar width of the photoelectric conversion layer, excluding the diffusion layer on the sidewall.

[0007] The two semiconductor layers mentioned above are A first semiconductor layer containing a first-conductivity type impurity, The first semiconductor layer and the photoelectric conversion layer are disposed between the first semiconductor layer and the second semiconductor layer which contains an impurity of a second conductivity type, The diffusion layer is arranged on the side walls of the first semiconductor layer and the second semiconductor layer, and may contain impurities of a second conductivity type with a higher impurity concentration than that of the second semiconductor layer.

[0008] The diffusion layer on the sidewall of the two semiconductor layers may be thicker than the diffusion layer on the sidewall of the photoelectric conversion layer.

[0009] The planar width of the two semiconductor layers, including the diffusion layer on the sidewall, is substantially the same as the planar width of the photoelectric conversion layer, including the diffusion layer on the sidewall, or the planar width may continuously narrow from the light incident surface side of the photoelectric conversion layer, including the diffusion layer on the sidewall, towards the two semiconductor layers.

[0010] The photoelectric conversion layer is disposed on the light incident surface side and further comprises a third semiconductor layer of the same conductivity type as the photoelectric conversion layer, The diffusion layer disposed on the side wall of the third semiconductor layer may be thicker than the diffusion layer on the side wall of the photoelectric conversion layer, and thinner than the diffusion layer on the side walls of the two semiconductor layers.

[0011] The two semiconductor layers mentioned above are A first semiconductor layer containing impurities of a first conductivity type, A second semiconductor layer disposed between the first semiconductor layer and the photoelectric conversion layer and containing impurities of a second conductivity type. Further comprising a first insulating film disposed on the first semiconductor layer and disposed inside the first semiconductor layer when viewed in plan from the opposite side of the light incident surface. The diffusion layer on the sidewall of the first semiconductor layer may be thicker than the diffusion layer on the sidewall of the second semiconductor layer.

[0012] The two semiconductor layers including the diffusion layer on the sidewall may gradually decrease in width in the plane direction from the photoelectric conversion layer including the diffusion layer on the sidewall.

[0013] The diffusion layer on the sidewalls of the two semiconductor layers may have substantially the same thickness as the diffusion layer on the sidewalls of the photoelectric conversion layer.

[0014] The diffusion layer on the sidewalls of the two semiconductor layers may be thicker than the diffusion layer on the sidewalls of the photoelectric conversion layer.

[0015] A first insulating film disposed to cover the diffusion layer on the sidewalls of the two semiconductor layers, Further comprising a second insulating film disposed to cover the diffusion layer on the sidewalls of the photoelectric conversion layer and different from the first insulating film.

[0016] Further comprising an electrode disposed to sandwich the two semiconductor layers between the electrode and the photoelectric conversion layer and reading out charges photoelectrically converted by the photoelectric conversion layer. The diffusion layer on the sidewalls of the two semiconductor layers may be disposed close to the electrode while leaving a gap from the electrode.

[0017] An electrode disposed to sandwich the two semiconductor layers between the electrode and the photoelectric conversion layer and reading out charges photoelectrically converted by the photoelectric conversion layer, Further comprising a fourth semiconductor layer disposed between the two semiconductor layers and the electrode and having a conductivity type different from that of the photoelectric conversion layer. The diffusion layers on the side walls of the two semiconductor layers may be arranged so as to be close to the fourth semiconductor layer while maintaining a distance from it.

[0018] The two semiconductor layers may have band gap energies greater than the band gap energy of the photoelectric conversion layer.

[0019] According to this disclosure, a laminate is formed comprising a photoelectric conversion layer containing a compound semiconductor material and two stacked semiconductor layers, each containing impurities of different conductivity types. A diffusion layer containing impurities with a higher impurity concentration than that of the two semiconductor layers is formed on the two semiconductor layers. A first groove is formed that exposes the diffusion layer on the sidewalls of the two semiconductor layers and the sidewall of the photoelectric conversion layer. A method for manufacturing a solid-state image sensor is provided, comprising forming the diffusion layer on the side wall of the photoelectric conversion layer, and making the diffusion layer on the side wall of the two semiconductor layers thicker than the diffusion layer on the side wall of the photoelectric conversion layer.

[0020] After forming the aforementioned laminate, A first insulating film is formed on the laminate, with each pixel having its own insulating film. Using the first insulating film as a mask, the diffusion layer is formed on the two semiconductor layers. After forming the first groove, When viewed from a plan view from the opposite side of the light incident surface of the photoelectric conversion layer, the outer periphery of the first insulating film is removed so that the first insulating film is positioned inside the two semiconductor layers. The first insulating film may be used as a mask to form the diffusion layer on the sidewall of the photoelectric conversion layer, and the diffusion layer on the sidewalls of the two semiconductor layers may be made thicker than the diffusion layer on the sidewall of the photoelectric conversion layer.

[0021] According to this disclosure, a laminate is formed comprising a photoelectric conversion layer containing a compound semiconductor material and two stacked semiconductor layers, each containing impurities of different conductivity types. A first groove is formed that exposes the sidewalls of the two semiconductor layers and the sidewall of the photoelectric conversion layer. By removing a portion of the two semiconductor layers from the side wall, A method for manufacturing a solid-state image sensor is provided, comprising forming a diffusion layer containing impurities with a higher impurity concentration than that of the two semiconductor layers on the side walls of the photoelectric conversion layer and the two semiconductor layers.

[0022] According to this disclosure, a laminate is formed comprising a photoelectric conversion layer containing a compound semiconductor material and two stacked semiconductor layers, each containing impurities of different conductivity types. A second groove is formed to expose the side walls of the two semiconductor layers. A diffusion layer containing impurities with a higher impurity concentration than that of the two semiconductor layers is formed on the side walls of the two semiconductor layers. A third groove, narrower than the second groove, is formed to expose the side wall of the photoelectric conversion layer. A method for manufacturing a solid-state image sensor is provided, comprising forming the diffusion layer on the side wall of the photoelectric conversion layer, and making the diffusion layer on the side wall of the two semiconductor layers thicker than the diffusion layer on the side wall of the photoelectric conversion layer.

[0023] After forming the diffusion layer on the sidewalls of the two semiconductor layers, A first insulating film is formed to cover the diffusion layer on the side walls of the two semiconductor layers. The diffusion layer is formed on the side wall of the photoelectric conversion layer, and the diffusion layer on the side walls of the two semiconductor layers is thickened, The present invention may further include forming a second insulating film, different from the first insulating film, that covers the diffusion layer on the side wall of the photoelectric conversion layer. [Brief explanation of the drawing]

[0024] [Figure 1] This is a schematic cross-sectional view showing the general configuration of a solid-state image sensor according to the first embodiment of this disclosure. [Figure 2] Figure 1 is a schematic diagram representing the planar configuration of the solid-state image sensor. [Figure 3A]Figure 1 is a schematic cross-sectional diagram showing one step in the manufacturing process of a solid-state image sensor. [Figure 3B] This is a schematic cross-sectional view showing the process following Figure 3A. [Figure 3C] This is a schematic cross-sectional view showing the process following Figure 3B. [Figure 3D] This is a schematic cross-sectional view showing the process following Figure 3C. [Figure 3E] This is a schematic cross-sectional view showing the process following Figure 3D. [Figure 3F] This is a schematic cross-sectional view showing the process following Figure 3E. [Figure 3G] This is a schematic cross-sectional view showing the process that follows Figure 3F. [Figure 4] This is a schematic cross-sectional view showing the general configuration of a solid-state image sensor according to a first modified example of the first embodiment. [Figure 5A] Figure 4 is a schematic cross-sectional diagram showing one step in the manufacturing process of a solid-state image sensor. [Figure 5B] This is a schematic cross-sectional view showing the process following Figure 5A. [Figure 5C] This is a schematic cross-sectional view showing the process following Figure 5B. [Figure 6] This is a schematic cross-sectional view showing the general configuration of a solid-state image sensor according to a second modified example of the first embodiment. [Figure 7] This is a schematic cross-sectional view showing the general configuration of a solid-state image sensor according to a third modified example of the first embodiment. [Figure 8] This is a schematic cross-sectional view showing the general configuration of a solid-state image sensor according to a fourth modified example of the first embodiment. [Figure 9] This is a schematic cross-sectional view showing the general configuration of a solid-state image sensor according to a fifth modified example of the first embodiment. [Figure 10] This is a schematic cross-sectional view showing the general configuration of a solid-state image sensor according to a sixth modified example of the first embodiment. [Figure 11] This is a schematic cross-sectional view showing the general configuration of a solid-state image sensor according to a second embodiment of the present disclosure. [Figure 12] Figure 11 is a schematic diagram representing the planar configuration of the solid-state image sensor. [Figure 13A]Figure 11 is a schematic cross-sectional diagram showing one step in the manufacturing process of a solid-state image sensor. [Figure 13B] This is a schematic cross-sectional view showing the process following Figure 13A. [Figure 13C] This is a schematic cross-sectional view showing the process following Figure 13B. [Figure 13D] This is a schematic cross-sectional view showing the process following Figure 13C. [Figure 13E] This is a schematic cross-sectional view showing the process following Figure 13D. [Figure 14] This is a schematic cross-sectional view showing the general configuration of a solid-state image sensor according to the first modified example of the second embodiment. [Figure 15] Figure 14 is a schematic diagram representing the planar configuration of the solid-state image sensor. [Figure 16A] Figure 14 is a schematic cross-sectional diagram showing one step in the manufacturing process of a solid-state image sensor. [Figure 16B] This is a schematic cross-sectional view showing the process following Figure 16A. [Figure 16C] This is a schematic cross-sectional view showing the process following Figure 16B. [Figure 16D] This is a schematic cross-sectional view showing the process following Figure 16C. [Figure 16E] This is a schematic cross-sectional view showing the process following Figure 16D. [Figure 17] This is a schematic cross-sectional view showing the general configuration of a solid-state image sensor according to a second modified example of the second embodiment. [Figure 18] This is a schematic cross-sectional view showing the general configuration of a solid-state image sensor according to a third modified example of the second embodiment. [Figure 19] This block diagram shows an example of a schematic configuration of a vehicle control system. [Figure 20] This is an explanatory diagram showing an example of the installation location of the external information detection unit and the imaging unit. [Modes for carrying out the invention]

[0025] The following description will focus on the main components of the solid-state image sensor and its manufacturing method, with reference to the drawings. However, the solid-state image sensor and its manufacturing method may contain components and functions not shown or described. The following description does not exclude any components or functions not shown or described.

[0026] <First Embodiment> [composition] Figures 1 and 2 show a schematic configuration of a solid-state image sensor (solid-state image sensor 1) according to the first embodiment of this disclosure. Figure 1 shows a cross-sectional configuration of the solid-state image sensor 1, and Figure 2 shows a planar configuration of the solid-state image sensor 1. The solid-state image sensor 1 is applied to infrared sensors and the like using compound semiconductor materials such as III-V semiconductors, and has a photoelectric conversion function for light with wavelengths from the visible region (e.g., 380 nm to less than 780 nm) to the short infrared region (e.g., 780 nm to less than 2400 nm). This solid-state image sensor 1 is provided with a plurality of light-receiving unit regions P (pixels P) arranged in a matrix in two dimensions, for example. Here, the solid-state image sensor 1 is given as a specific example of the photoelectric conversion element of this technology and will be explained.

[0027] The pixels P of the solid-state image sensor 1 are provided with a first electrode 11, a first semiconductor layer 12, a second semiconductor layer 13, a light absorption layer 14 (photoelectric conversion layer), a contact layer 15, and a second electrode 16 in this order. The light absorption layer 14 has a first surface S1 (surface opposite to the light incident surface) and a second surface S2 (light incident surface) that face each other, with the second semiconductor layer 13 provided on the first surface S1 and the contact layer 15 on the second surface S2. In this solid-state image sensor 1, light incident from the second electrode 16 side is incident on the second surface S2 of the light absorption layer 14 via the contact layer 15. An insulating film 17 is provided around the first electrode 11. The solid-state image sensor 1 has a diffusion region D (diffusion layer) between adjacent pixels P. This diffusion region D is provided across the first semiconductor layer 12, the second semiconductor layer 13, the light absorption layer 14, and the contact layer 15.

[0028] The first electrode 11 is a readout electrode to which a voltage is supplied for reading out the signal charge (holes or electrons; for convenience, the signal charge will be described as electrons) generated in the light absorption layer 14. It is provided for each pixel P facing the first surface S1 of the light absorption layer 14. The first electrode 11 is electrically connected to the pixel circuit and the silicon semiconductor substrate for signal readout, for example, via bumps or vias. The silicon semiconductor substrate is provided with various wirings, for example. This first electrode 11 is provided in contact with the first semiconductor layer 12, for example. The planar shape of the first electrode 11 is, for example, a rectangle, and multiple first electrodes 11 are arranged spaced apart from each other. The first electrode 11 is embedded in an opening in the insulating film 17, and the insulating film 17, a coating film 18, and a protective film 19 are provided between adjacent first electrodes 11.

[0029] The first electrode 11 is composed of, for example, one of the elements listed below: titanium (Ti), tungsten (W), titanium nitride (TiN), platinum (Pt), gold (Au), copper (Cu), germanium (Ge), palladium (Pd), zinc (Zn), nickel (Ni), indium (In), and aluminum (Al), or an alloy containing at least one of these elements. The first electrode 11 may be a single film of such constituent material, or it may be a multilayer film combining two or more of these elements.

[0030] The first semiconductor layer 12 and the second semiconductor layer 13 are provided in common to, for example, all pixels P. As will be described later, these first and second semiconductor layers 12 and 13 are for forming a pn junction and are made of a compound semiconductor material having a bandgap energy greater than the bandgap energy of the compound semiconductor material constituting the light absorption layer 14. When the light absorption layer 14 is made of, for example, InGaAs (indium gallium arsenide, bandgap energy 0.75 eV), the first and second semiconductor layers 12 and 13 can be made of, for example, InP (indium phosphide, bandgap energy 1.35 eV). The first and second semiconductor layers 12 and 13 can be made of, for example, a III-V semiconductor containing at least one of In (indium), Ga (gallium), Al (aluminum), As (arsenic), P (phosphorus), Sb (antimony), and N (nitrogen). Specifically, in addition to InP, examples include InGaAsP (indium gallium arsenide phosphide), InAsSb (indium arsenide antimony), InGaP (indium gallium phosphide), GaAsSb (gallium arsenide antimony), and InAlAs (indium aluminum arsenide). The sum of the thickness of the first semiconductor layer 12 and the thickness of the second semiconductor layer 13 is, for example, 100 nm to 3000 nm.

[0031] If the combined thickness of the first semiconductor layer 12 and the second semiconductor layer 13 is less than 100 nm, for example, the pn junction formed between the first semiconductor layer 12 and the second semiconductor layer 13 may come into contact with, for example, the first electrode 11 or the light absorption layer 14. Also, if the combined thickness of the first semiconductor layer 12 and the second semiconductor layer 13 is less than 100 nm, etching damage when forming the first groove G1 (described later) or damage when forming the coating film 18 (described later) may reach the light absorption layer 14. These can cause an increase in dark current. If the combined thickness of the first semiconductor layer 12 and the second semiconductor layer 13 is thicker than 3000 nm, it becomes difficult to extend and form the diffusion region D to the light absorption layer 14, making it difficult to electrically isolate adjacent pixels P.

[0032] The first semiconductor layer 12, positioned between the first electrode 11 and the second semiconductor layer 13, has, for example, n-type (first conductivity type) carriers. The second semiconductor layer 13 is positioned between the first semiconductor layer 12 and the light absorption layer 14 (first surface S1), and has carriers of the opposite conductivity type to the first semiconductor layer 12, for example, p-type (second conductivity type). As a result, a pn junction is formed between the first semiconductor layer 12 and the second semiconductor layer 13 (at the interface between the first semiconductor layer 12 and the second semiconductor layer 13). As will be described in detail later, dark current can be reduced by forming a pn junction at the interface between the first semiconductor layer 12 and the second semiconductor layer 13, which have a larger band gap than the light absorption layer 14. Alternatively, an i-type semiconductor layer (intrinsic semiconductor layer) may be provided between the first semiconductor layer 12 and the second semiconductor layer 13 to form a pin junction.

[0033] The light-absorbing layer 14 between the second semiconductor layer 13 and the contact layer 15 is, for example, provided in common to all pixels P. This light-absorbing layer 14 absorbs light of a predetermined wavelength to generate a signal charge, and is composed of, for example, a p-type compound semiconductor material. The compound semiconductor material constituting the light-absorbing layer 14 is, for example, a III-V group semiconductor containing at least one of In (indium), Ga (gallium), Al (aluminum), As (arsenic), P (phosphorus), Sb (antimony), and N (nitrogen). Specifically, examples include InGaAs (indium gallium arsenide), InGaAsP (indium gallium arsenide phosphide), InAsSb (indium arsenide antimony), InGaP (indium gallium phosphide), GaAsSb (gallium arsenide antimony), and InAlAs (indium aluminum arsenide). The doping density of the light-absorbing layer 14 is, for example, 1 × 10⁻⁶. 14 cm -3 ~1 × 10 17 cm -3 The doping density of the light-absorbing layer 14 is 1 × 10⁻⁶. 17 cm -3 When the value exceeds a certain level, the probability of loss due to the recombination of signal charges generated by photoelectric conversion increases, and the quantum efficiency decreases.

[0034] The thickness of the light absorption layer 14 is, for example, 100 nm to 10,000 nm. If the thickness of the light absorption layer 14 is less than 100 nm, the amount of light transmitted through the light absorption layer 14 increases, and there is a risk that the quantum efficiency will be significantly reduced. If the thickness of the light absorption layer 14 is made thicker than 5000 nm, it is difficult to form the diffusion region D with a depth of 5000 nm or more, and it becomes difficult to sufficiently suppress the occurrence of crosstalk between adjacent pixels P. In the light absorption layer 14, for example, photoelectric conversion of light with wavelengths from the visible region to the short infrared region is performed.

[0035] The diffusion region D is, for example, a region where p+-type impurities are diffused. This diffusion region D is for electrically separating adjacent pixels P. The diffusion region D is provided on the sidewalls of the first semiconductor layer 12, the second semiconductor layer 13, and the light absorption layer 14. In the plane direction of the first semiconductor layer 12 (the XY plane in FIGS. 1 and 2), it spreads around the first electrode 11 with the first electrode 11 as the center. In the thickness direction of the first semiconductor layer 12 (the Z direction in FIGS. 1 and 2), it spreads from the first semiconductor layer 12 through the second semiconductor layer 13 and the light absorption layer 14 to the contact layer 15. Since the diffusion region D is provided so as to straddle the second semiconductor layer 13 and the light absorption layer 14 in this way, the interface between the second semiconductor layer 13 and the light absorption layer 14 in each pixel P is surrounded by the diffusion region D. Although details will be described later, a temporary retention portion of signal charges is formed thereby.

[0036] In the diffusion region D, for example, zinc (Zn) is diffused as p+-type impurities. The p+-type impurities may be, for example, magnesium (Mg), cadmium (Cd), beryllium (Be), silicon (Si), germanium (Ge), carbon (C), tin (Sn), lead (Pb), sulfur (S), or tellurium (Te), etc. The doping density of the diffusion region D is higher than that of the first semiconductor layer 12, the second semiconductor layer, and the light absorption layer 14. The doping density of the diffusion region D is, for example, 1×10 17 cm -3 ~5×10 19 cm -3 is. If the doping density of the diffusion region D is 1×10 17 cm -3This suppresses the generation of dark current at the interface. The upper limit of the doping density is 5 × 10⁻⁶. 19 cm -3 This is the upper limit obtained by the diffusion process, and is 5 × 10 19 cm -3 Doping densities exceeding a certain level approach the solid solubility limit, causing dopants to aggregate in the crystal, leading to defect formation and deteriorating the dark current properties.

[0037] Furthermore, the width in the planar direction (XY plane direction) of the two semiconductor layers (first semiconductor layer 12 and second semiconductor layer 13), excluding the sidewall diffusion region D, is narrower than the width in the planar direction of the light-absorbing layer 14, excluding the sidewall diffusion region D. Also, the sidewall diffusion region D of the first semiconductor layer 12 and the second semiconductor layer 13 is thicker than the sidewall diffusion region D of the light-absorbing layer 14. As a result, as will be explained later, a decrease in quantum efficiency can be suppressed, and an increase in parasitic capacitance and dark current can be suppressed.

[0038] The contact layer 15 is provided in common to all pixels P, for example. This contact layer 15 is provided between the light absorption layer 14 (second surface S2) and the second electrode 16 and is in contact with them. The contact layer 15 is a region to which the charge discharged from the second electrode 16 moves, and is composed of a compound semiconductor containing, for example, p+ type impurities. For example, p+ type InP (indium phosphide) can be used for the contact layer 15. The contact layer 20 has the same conductivity type as the light absorption layer 14. The doping density of the contact layer 15 is higher than that of the first semiconductor layer 12, the second semiconductor layer 13, and the light absorption layer 14.

[0039] The second electrode 16 is provided on the second surface S2 (light incident surface) of the light absorption layer 14 via the contact layer 15, for example, as a common electrode for each pixel P. The second electrode 16 is for discharging charges generated in the light absorption layer 14 that are not used as signal charges. For example, when electrons are read out from the first electrode 11 as signal charges, holes can be discharged through this second electrode 16. The second electrode 16 is made of a transparent conductive film that can transmit incident light such as infrared light, and has a transmittance of 50% or more for light with a wavelength of 1.6 μm (1600 nm), for example. For the second electrode 16, ITO (Indium Tin Oxide) or ITiO (In2O3-TiO2) can be used.

[0040] An insulating film 17 (first insulating film) is provided on the surface of the first semiconductor layer 12 for each pixel P. This insulating film 17 is for defining the diffusion region D and, as will be described later, functions as a mask in the diffusion process when forming the diffusion region D (see Figure 3C below). In other words, the diffusion region D is formed between adjacent insulating films 17. The thickness of the insulating film 17 is, for example, less than the thickness of the first electrode 11, and the first electrode 11 protrudes from the insulating film 17. The thickness of the insulating film 17 is preferably 10 nm to 5000 nm. By using an insulating film 17 of 10 nm or more, it is possible to suppress the transmission of diffusing elements (impurities) in the diffusion process. If the thickness of the insulating film 17 is greater than 5000 nm, there is a risk that etching of the insulating film 17 during the formation of the first electrode 11 will become difficult.

[0041] The insulating film 17 can be an insulating material containing at least one of the following: silicon (Si), nitrogen (N), aluminum (Al), hafnium (Hf), tantalum (Ta), titanium (Ti), magnesium (Mg), oxygen (O), lanthanum (La), gadolinium (Gd), and yttrium (Y). Specifically, for example, a silicon nitride (SiN) film can be used for the insulating film 17. The insulating film 17 may also be a silicon oxide (SiO2) film, a silicon oxynitride (SiON) film, an aluminum oxynitride (AlON) film, an aluminum silicon nitride (SiAlN) film, a magnesium oxide (MgO), an aluminum oxide (Al2O3) film, an aluminum silicon oxide (AlSiO) film, a hafnium oxide (HfO2) film, or an aluminum hafnium oxide (HfAlO) film. The insulating film 17 may also be composed of an organic material. This organic material is one that can suppress the permeation of diffusing elements.

[0042] The coating film 18 (second insulating film) covers the insulating film 17 and the sidewall surfaces of the first semiconductor layer 12, the second semiconductor layer 13, the light absorption layer 14, and the contact layer 15. This coating film 18 is for protecting the sidewall surfaces of the first semiconductor layer 12, the second semiconductor layer 13, the light absorption layer 14, and the contact layer 15. The coating film 18 is composed of, for example, an insulating material or a semiconductor material. Examples of insulating materials that constitute the coating film 18 include insulating materials containing at least one of silicon (Si), nitrogen (N), aluminum (Al), hafnium (Hf), tantalum (Ta), titanium (Ti), magnesium (Mg), scandium (Sc), zirconium (Zr), oxygen (O), lanthanum (La), gadolinium (Gd), and yttrium (Y). Specifically, the coating film 18 is composed of, for example, an aluminum oxide (Al2O3) film. The coating film 18 may be composed of silicon nitride (SiN) film, silicon oxide (SiO2) film, silicon oxynitride (SiON) film, aluminum oxynitride (AlON) film, aluminum silicon nitride (SiAlN) film, magnesium oxide (MgO), aluminum silicon oxide (AlSiO) film, hafnium oxide (HfO2) film, aluminum hafnium oxide (HfAlO) film, tantalum oxide (Ta2O3) film, titanium oxide (TiO2) film, scandium oxide (Sc2O3) film, zirconium oxide (ZrO2) film, gadolinium oxide (Gd2O3) film, lanthanum oxide (La2O3) film, or yttrium oxide (Y2O3) film, etc. Examples of semiconductor materials constituting the coating film 18 include group IV semiconductor materials such as silicon (Si) and germanium (Ge). The thickness of the coating film 18 is, for example, 1 nm to 500 nm. There is no particular lower limit to the thickness of the coating film 18, but from the viewpoint of the film formation process, it is preferable to have a thickness of 1 nm or more in order to completely cover the exposed compound semiconductor. There is no particular upper limit to the thickness of the coating film 18, but from the viewpoint of the subsequent formation of the first electrode 11 and the planarization process, it is preferable to have a thickness of 500 nm or less. Note that the coating film 18 is not necessarily required and may be omitted as appropriate.

[0043] The protective film 19 is provided so as to be laminated on the coating film 18. The protective film 19 can be made of an insulating material containing at least one of the following: silicon (Si), nitrogen (N), aluminum (Al), hafnium (Hf), tantalum (Ta), titanium (Ti), magnesium (Mg), oxygen (O), lanthanum (La), gadolinium (Gd), and yttrium (Y). Specifically, the protective film 19 is made of, for example, a silicon oxide (SiO2) film. The protective film 19 may also be made of a silicon nitride (SiN) film, an aluminum oxide (Al2O3) film, a silicon oxynitride (SiON) film, an aluminum oxynitride (AlON) film, a silicon aluminum nitride (SiAlN) film, a magnesium oxide (MgO), an aluminum silicon oxide (AlSiO) film, a hafnium oxide (HfO2) film, or a hafnium aluminum oxide (HfAlO) film, etc.

[0044] The first groove G1 is used to separate pixels P. The first groove G1 is positioned between adjacent pixels P and is arranged, for example, in a grid pattern in a plan view.

[0045] [Manufacturing method for solid-state image sensor 1] The solid-state image sensor 1 can be manufactured, for example, as follows. Figures 3A to 3G show the manufacturing process of the solid-state image sensor 1 in chronological order.

[0046] First, as shown in Figure 3A, a laminated structure having a contact layer 15, a light absorption layer 14, a second semiconductor layer 13, and a first semiconductor layer 12 in this order is formed, for example, by epitaxial growth. At this time, a pn junction is formed between the second semiconductor layer 13 and the first semiconductor layer 12.

[0047] Next, as shown in Figure 3B, an insulating film 17 with a thickness of, for example, 10 nm or more is deposited on the entire surface of the first semiconductor layer 12. Subsequently, as shown in Figure 3C, photoresist and etching are performed, for example, using a mask. Etching is performed using either dry etching or wet etching. This removes a portion of the insulating film 17, exposing the surface of the first semiconductor layer 12 in a grid pattern. That is, the insulating film 17 is arranged for each pixel P.

[0048] After exposing the surface of the first semiconductor layer 12 in a grid pattern from the insulating film 17, a diffusion region D is formed using the insulating film 17 as a mask, as shown in Figure 3C. The diffusion region D is formed by diffusing p+-type impurities, such as zinc (Zn), from the exposed surface of the first semiconductor layer 12. The diffusion of impurities is carried out, for example, by gas-phase diffusion or solid-phase diffusion. The diffusion conditions for impurities are set so that the diffusion region D is formed from the first semiconductor layer 12 through the second semiconductor layer 13 into the light-absorbing layer 14. For example, the annealing temperature is adjusted to 300°C to 800°C.

[0049] Furthermore, the diffusion region D may be formed only up to a certain point in the second semiconductor layer 13, without reaching the light absorption layer 14. If the diffusion region D is formed deep into the light absorption layer 14, the quantum efficiency may decrease. Therefore, it is preferable that the diffusion region D is formed up to approximately the interface between the second semiconductor layer 13 and the light absorption layer 14.

[0050] After forming the diffusion region D, a first groove G1 is formed as shown in Figure 3D. The first groove G1 exposes the diffusion region D on the sidewalls of the first semiconductor layer 12 and the second semiconductor layer 13, and the light absorption layer 14. The first groove G1 is formed, for example, up to the contact layer 15. The first groove G1 is formed, for example, by dry etching or wet etching.

[0051] After forming the first groove G1, a second impurity diffusion process is performed as shown in Figure 3E. The diffusion region D formed in the first diffusion process extends even deeper into the first semiconductor layer 12 and the second semiconductor layer 13. In the second diffusion process, diffusion regions D are formed almost simultaneously on the sidewalls of the light absorption layer 14 and the contact layer 15. That is, a diffusion region D is formed on the sidewall of the light absorption layer 14, and the diffusion regions D on the sidewalls of the first semiconductor layer 12 and the second semiconductor layer 13 are made thicker than the diffusion region D on the sidewall of the light absorption layer 14. Therefore, the thickness of the diffusion region D changes from the light absorption layer 14 to the second semiconductor layer 13.

[0052] Furthermore, the diffusion region D is formed slightly deeper in the contact layer 15 than in the light-absorbing layer 14. That is, the diffusion region D located on the sidewall of the contact layer 15 is thicker than the diffusion region D on the sidewall of the light-absorbing layer 14, but thinner than the diffusion region D on the sidewalls of the first semiconductor layer 12 and the second semiconductor layer 13. This is because, for example, the diffusion rate of impurities may differ depending on the compound semiconductor material. Also, if the contact layer 15 is much thinner than the first semiconductor layer 12 and the second semiconductor layer 13, the diffusion region D on the sidewall of the contact layer 15 does not significantly affect the deterioration of quantum efficiency.

[0053] After the second diffusion step, as shown in Figure 3F, a coating film 18 is formed on the entire sidewalls of the first semiconductor layer 12, the second semiconductor layer 13, the light absorption layer 14, and the contact layer 15. The coating film 18 is formed so as to cover the insulating film 17 together with the diffusion region D. The coating film 18 is formed by depositing an insulating material using, for example, a thermal oxidation method, a CVD (Chemical Vapor Deposition) method, or an ALD (Atomic Layer Deposition) method. Alternatively, the coating film 18 may be formed by depositing a semiconductor material using a sputter deposition method, an electron beam (E-beam gun) deposition method, a resistance heating deposition method, a CVD method, or an ALD method.

[0054] After forming the coating film 18, a protective film 19 is formed to cover the coating film 18, as shown in Figure 3G.

[0055] After forming the protective film 19, photoresist and etching are performed, for example, using a mask. Dry etching or wet etching is used for the etching. This creates holes in the protective film 19, the coating film 18, and the insulating film 17 that reach the first semiconductor layer 12. These holes are for forming the first electrode 11 and are formed in positions that do not overlap with the diffusion region D in a plan view.

[0056] After forming holes in the protective film 19, the coating film 18, and the insulating film 17, the first electrode 11 is formed in these holes. Finally, the second electrode 16 is formed on the lower surface of the contact layer 15 and the coating film 18. This completes the solid-state image sensor 1 shown in Figure 1.

[0057] [Operation of Solid State Image Sensor 1] In the solid-state image sensor 1, when light L (for example, light with wavelengths in the visible and infrared regions) is incident on the light absorption layer 14 via the second electrode 16 and the contact layer 15, this light L is absorbed by the light absorption layer 14. As a result, holes and electrons are generated in the light absorption layer 14 (photoelectric conversion occurs). At this time, for example, when a predetermined voltage is applied to the first electrode 11, a potential gradient is generated in the light absorption layer 14, and one of the generated charges (for example, an electron) moves as a signal charge to a temporary dwelling area near the interface between the light absorption layer 14 and the second semiconductor layer 13.

[0058] Since the bandgap energy of the second semiconductor layer 13 is greater than that of the light-absorbing layer 14, a band offset barrier is provided at the interface between the light-absorbing layer 14 and the second semiconductor layer 13. Therefore, the movement of signal charge from the light-absorbing layer 14 to the second semiconductor layer 13 is temporarily hindered. Furthermore, since a diffusion region D is provided between adjacent pixels P, movement between adjacent pixels P is also inhibited. Consequently, signal charge temporarily accumulates in a pocket-like region near the interface between the light-absorbing layer 14 and the second semiconductor layer 13, and surrounded by the diffusion region D. From this temporary accumulation, the signal charge overcomes the band offset barrier and is collected at the first electrode 11 via the second semiconductor layer 13 and the first semiconductor layer 12. This signal charge is then read out for each pixel P by the ROIC.

[0059] As described above, according to the first embodiment, the diffusion region D can be controlled for each compound semiconductor layer by performing the diffusion process in two stages. This makes the diffusion region D of the side walls of the first semiconductor layer 12 and the second semiconductor layer 13 thicker than the diffusion region D of the side wall of the light absorption layer 14.

[0060] If the thickness of the diffusion region D is approximately the same regardless of its position, the thinner the diffusion region D becomes, the wider the width of the first semiconductor layer 12 and the second semiconductor layer 13 excluding the diffusion region D becomes. The depletion layer formed by the pn junction of the first semiconductor layer 12 and the second semiconductor layer 13 can be one of the causes of parasitic capacitance and dark current. Therefore, the thinner the diffusion region D becomes, the more likely parasitic capacitance and dark current are to increase. On the other hand, the thicker the diffusion region D becomes, the narrower the width of the light absorption layer 14 excluding the diffusion region D becomes, which tends to decrease quantum efficiency. In other words, there is a trade-off relationship between parasitic capacitance and dark current and quantum efficiency. For example, if the diffusion region D on the side walls of the first semiconductor layer 12 and the second semiconductor layer 13 is widened to reduce parasitic capacitance, the diffusion region D on the side walls of the light absorption layer 14 also widens. Therefore, quantum efficiency decreases.

[0061] In contrast, in the first embodiment, by making the diffusion regions D of the side walls of the first semiconductor layer 12 and the second semiconductor layer 13 relatively thick, an increase in parasitic capacitance and dark current can be suppressed, and by making the diffusion region D of the side wall of the light absorption layer 14 relatively thin, a decrease in quantum efficiency can be suppressed. In other words, by controlling the thickness of the diffusion region D for each compound semiconductor layer, it is possible to achieve both low parasitic capacitance and dark current and high quantum efficiency.

[0062] Furthermore, the thickness of the diffusion region D is determined by the damage depth during the formation of the first groove G1. If the damage during the formation of the first groove G1 reaches the light absorption layer 14, the dark current will increase. Therefore, for example, if the damaged layer is confirmed to be 200 nm thick, a diffusion region D with a thickness of 200 nm or more will be formed. The thickness of the diffusion region D is, for example, 100 nm or more.

[0063] Furthermore, from the viewpoint of reducing dark current, it is preferable that the thickness of the diffusion region D on the side wall of the first semiconductor layer 12 is just enough so that the diffusion region D does not come into contact with the first electrode 11. That is, the diffusion regions D on the side walls of the first semiconductor layer 12 and the second semiconductor layer 13 are arranged to be close to the first electrode 11 while maintaining a distance from it. The thickness of the diffusion region D is controlled, for example, by adjusting the annealing temperature and time.

[0064] Furthermore, as shown in Figure 1, the width in the planar direction of the light-absorbing layer 14, including the diffusion region D of the sidewall, narrows continuously from the light incident surface (second surface S2) to the first semiconductor layer 12 and the second semiconductor layer 13. For example, depending on the dry etching conditions, the sidewall may be tapered. Note that the width in the planar direction of the first semiconductor layer 12 and the second semiconductor layer 13, including the diffusion region D of the sidewall, may be approximately the same as the width in the planar direction of the light-absorbing layer 14, including the diffusion region D of the sidewall.

[0065] Furthermore, the first semiconductor layer 12 and the second semiconductor layer 13 have bandgap energies greater than the bandgap energy of the light absorption layer 14. As a result, a depletion layer is formed in the vicinity between the first semiconductor layer 12 and the second semiconductor layer 13. This makes it possible to suppress the generation of dark current.

[0066] <First modified example of the first embodiment> [composition] Figure 4 shows a schematic cross-sectional configuration of the solid-state image sensor 1 according to the first modified example of the first embodiment described above. The first modified example of the first embodiment differs from the first embodiment in that the diffusion region D of the side wall of the first semiconductor layer 12 is further thickened.

[0067] Compared to the first embodiment, a portion of the outer periphery of the insulating film 17 has been removed. That is, when viewed from the opposite side of the light incident surface (second surface S2), the insulating film 17 is located inside the first semiconductor layer 12, including the diffusion region D of the side wall.

[0068] The diffusion region D of the sidewall of the first semiconductor layer 12 is thicker than the diffusion region D of the sidewall of the second semiconductor layer 13. Therefore, in the second embodiment, the increase in parasitic capacitance and dark flow can be suppressed more effectively compared to the first embodiment. As in the first embodiment, the diffusion region D of the sidewall of the second semiconductor layer 13 is thicker than the diffusion region D of the sidewall of the light absorption layer 14.

[0069] The other configurations of the solid-state image sensor 1 according to the first modified example of the first embodiment are the same as the corresponding configurations of the solid-state image sensor 1 according to the first embodiment, so a detailed description thereof will be omitted.

[0070] [Manufacturing method for solid-state image sensor 1] Figures 5A to 5C show the manufacturing process of the solid-state image sensor 1 in chronological order. Note that the steps prior to the step in Figure 5A are the same as the steps in Figures 3A to 3D described in the first embodiment.

[0071] First, a laminated structure is formed (see Figure 3A). Next, an insulating film 17 is formed (see Figure 3B). Then, a portion of the insulating film 17 is removed to form a diffusion region D (see Figure 3C).

[0072] After forming the first groove G1 in the process shown in Figure 3D, the outer periphery of the insulating film 17 is removed as shown in Figure 5A. More specifically, the outer periphery of the insulating film 17 is removed so that, when viewed from a plan view from the opposite side of the light incident surface (second surface S2) of the light absorption layer 14, the insulating film 17 is positioned inside the first semiconductor layer 12 and the second semiconductor layer 13. The outer periphery of the insulating film 17 is removed, for example, by dry etching.

[0073] After removing a portion of the first insulating film, a second diffusion process is performed using the insulating film 17 as a mask. The second diffusion process is almost the same as in Figure 3E. In Figure 5A, compared to Figure 3E, the insulating film 17, which functions as a mask, has a smaller area in plan view. Therefore, a portion of the upper surface of the first semiconductor layer 12 is exposed from the insulating film 17. This makes it easier for impurities to diffuse from the upper surface of the first semiconductor layer 12. As a result, the diffusion region D of the sidewall of the first semiconductor layer 12 can be made thicker than the diffusion region D of the sidewall of the second semiconductor layer 13.

[0074] After the second diffusion step, a coating film 18 is formed to cover the first semiconductor layer 12, the second semiconductor layer 13, the light absorption layer 14, the contact layer 15, and the insulating film 17, as shown in Figure 5B. The coating film 18 is formed in the same manner as shown in Figure 3F, which was described in the first embodiment.

[0075] After forming the coating film 18, a protective film 19 is formed to cover the coating film 18, as shown in Figure 5C. The protective film 19 is formed in the same manner as shown in Figure 3G, which was described in the first embodiment.

[0076] After forming the protective film 19, the first electrode 11 and the second electrode 16 are formed as described in the first embodiment. This completes the solid-state image sensor 1 shown in Figure 4. In the second embodiment, compared to the first embodiment, the diffusion region D extends more deeply into the first semiconductor layer 12. The first electrode 11 needs to be narrowed in a plan view so that it does not come into contact with the diffusion region D.

[0077] As shown in this modified example, a portion of the outer periphery of the insulating film 17 may be etched to thicken the diffusion region D of the sidewall of the first semiconductor layer 12. In this case as well, the same effects as those of the first embodiment can be obtained.

[0078] <Second modified example of the first embodiment> Figure 6 shows a schematic cross-sectional configuration of the solid-state image sensor 1 according to a second modification of the first embodiment described above. The second modification of the first embodiment differs from the first embodiment in that the conductivity type is reversed.

[0079] The solid-state image sensor 1 shown in Figure 1, described in the first embodiment, has p-type pixels, i.e., an electronic readout structure. On the other hand, the solid-state image sensor 1 shown in Figure 6 has n-type pixels, i.e., a Hole readout structure. Furthermore, since the diffusion region D in Figure 6 is n-type, the dopant of the diffusion region D is, for example, silicon (Si) or germanium (Ge).

[0080] As shown in this modified example, holes may be read out as signal charges. In this case as well, the same effects as in the first embodiment can be obtained. The second modified example may be combined with the first modified example of the first embodiment.

[0081] <Third modified example of the first embodiment> Figure 7 shows a schematic cross-sectional configuration of the solid-state image sensor 1 according to the third modification of the first embodiment described above. The third modification of the first embodiment differs from the first modification of the first embodiment in that a light-shielding member is provided.

[0082] The solid-state image sensor 1 further includes a light-shielding member (light-shielding member 25).

[0083] The light-shielding member 25 is, for example, arranged in a grid pattern in a plan view and embedded in the first groove G1 from the surface of the protective film 19. This light-shielding member 25 is for optically separating adjacent pixels P, and for example, the light-shielding member 25 can prevent light incident at an oblique angle from entering adjacent pixels P. In addition, for example, the light-shielding member 25 can suppress color mixing between pixels P.

[0084] The light-shielding member 25 can be made of a material with low transmittance to light of wavelengths in the infrared and visible regions, for example. For example, the light-shielding member 25 is made of a metallic material having a transmittance of 10% or less for light with a wavelength of 1 μm. Specifically, the light-shielding member 25 can be made of any element from among titanium (Ti), tungsten (W), titanium nitride (TiN), platinum (Pt), gold (Au), copper (Cu), germanium (Ge), palladium (Pd), zinc (Zn), nickel (Ni), indium (In), and aluminum (Al), or an alloy containing at least one of these.

[0085] In the example shown in Figure 7, the upper end of the light-shielding member 25 is exposed from the protective film 19. The lower end of the light-shielding member 25 reaches the second electrode 16. Therefore, the light-shielding member 25 penetrates the coating film 18.

[0086] As shown in this modified example, a light-shielding member 25 may be provided in the first groove G1. In this case as well, the same effects as the first modified example of the first embodiment can be obtained. Furthermore, the diffusion region D electrically separates adjacent pixels P, and the light-shielding member 25 optically separates adjacent pixels P. Therefore, the occurrence of crosstalk between pixels P can be suppressed more effectively. Note that the light-shielding member 25 may be provided not only in the first embodiment and its modified examples, but also in the second embodiment and its modified examples.

[0087] <Fourth modified example of the first embodiment> Figure 8 shows a schematic cross-sectional configuration of the solid-state image sensor 1 according to the fourth modification of the first embodiment described above. The fourth modification of the first embodiment differs from the third modification of the first embodiment in the arrangement of the light-shielding members 25.

[0088] In the example shown in Figure 8, the upper end of the light-shielding member 25 is exposed from the protective film 19, similar to Figure 7. The lower end of the light-shielding member 25 is located inside the protective film 19 without reaching the coating film 18. Therefore, the light-shielding member 25 does not need to penetrate the coating film 18.

[0089] As shown in this modified example, the position of the light-shielding member 25 may be changed. In this case as well, the same effect as the third modified example of the first embodiment can be obtained.

[0090] <Fifth modified example of the first embodiment> Figure 9 shows a schematic cross-sectional configuration of the solid-state image sensor 1 according to the fifth modification of the first embodiment described above. The fifth modification of the first embodiment differs from the third modification of the first embodiment in the arrangement of the light-shielding members 25.

[0091] In the example shown in Figure 9, the upper end of the light-shielding member 25 is located inside the protective film 19 and is not exposed from the surface of the protective film 19. The lower end of the light-shielding member 25 reaches the second electrode 16, as in Figure 7.

[0092] As shown in this modified example, the position of the light-shielding member 25 may be changed. In this case as well, the same effect as the third modified example of the first embodiment can be obtained.

[0093] <Sixth variation of the first embodiment> Figure 10 shows a schematic cross-sectional configuration of the solid-state image sensor 1 according to the sixth modification of the first embodiment described above. The sixth modification of the first embodiment differs from the third modification of the first embodiment in the arrangement of the light-shielding members 25.

[0094] In the example shown in Figure 10, both the upper and lower ends of the light-shielding member 25 are located inside the protective film 19.

[0095] As shown in this modified example, the position of the light-shielding member 25 may be changed. In this case as well, the same effect as the third modified example of the first embodiment can be obtained.

[0096] <Second Embodiment> [composition] Figures 11 and 12 show a schematic configuration of a solid-state image sensor 1 according to a second embodiment of this disclosure. Figure 11 shows a cross-sectional configuration of the solid-state image sensor 1, and Figure 12 shows a planar configuration of the solid-state image sensor 1. The second embodiment differs from the first embodiment in that the side walls of the first semiconductor layer 12 and the second semiconductor layer 13 are partially removed, narrowing their width. In addition, the thickness of the diffusion region D is approximately the same depending on the location.

[0097] The first semiconductor layer 12 and the second semiconductor layer 13, including the diffusion region D of the sidewall, have a planar width that is progressively (stepwise) narrower than the light absorption layer 14, which also includes the diffusion region D of the sidewall.

[0098] Furthermore, as shown in Figures 11 and 12, a step is provided at the bottom of the first groove G1, and a step is provided on the first surface S1.

[0099] The thickness of the diffusion region D is approximately the same for the first semiconductor layer 12, the second semiconductor layer 13, and the light-absorbing layer 14. That is, the diffusion region D on the side walls of the first semiconductor layer 12 and the second semiconductor layer 13 has approximately the same thickness as the diffusion region D on the side wall of the light-absorbing layer 14. However, the thickness of the diffusion region D does not necessarily have to be the same; for example, the thickness of the diffusion region D may differ due to differences in the diffusion rate of impurities in each compound semiconductor material.

[0100] Furthermore, the solid-state image sensor 1 according to the second embodiment further comprises a contact layer 20. The contact layer 20 is provided in common to all pixels P, for example. This contact layer 20 is provided between the first electrode 11 and the first semiconductor layer 12 and is in contact with them. The contact layer 20 is a region through which the charge collected on the first electrode 11 moves, and is composed of a compound semiconductor containing, for example, n+-type impurities. For example, n+-type InP (indium phosphide) can be used for the contact layer 20. By providing the contact layer 20, contact resistance can be reduced. Note that the contact layer 20 is not necessarily required.

[0101] The other configurations of the solid-state image sensor 1 according to the second embodiment are the same as the corresponding configurations of the solid-state image sensor 1 according to the first embodiment, so a detailed explanation thereof will be omitted.

[0102] [Manufacturing method for solid-state image sensor 1] Figures 13A to 13E show the manufacturing process of the solid-state image sensor 1 in chronological order.

[0103] First, as shown in Figure 13A, a stacked structure having a contact layer 15, a light absorption layer 14, a second semiconductor layer 13, a first semiconductor layer 12, and a contact layer 20 in this order is formed, for example, by epitaxial growth. At this time, a pn junction is formed between the second semiconductor layer 13 and the first semiconductor layer 12. Next, photoresist and etching are performed, for example, using a mask. Etching is performed using dry etching or wet etching. This removes a portion of the contact layer 20, exposing the surface of the first semiconductor layer 12 in a grid pattern. This results in the structure shown in Figure 13A. That is, the contact layer 20 is arranged for each pixel P.

[0104] Next, as shown in Figure 13B, an insulating film 17 is formed to cover the surface of the first semiconductor layer 12 and the contact layer 20.

[0105] The insulating film 17 is more preferably an insulating film such as an oxide film suitable for the first semiconductor layer 12 (e.g., InP).

[0106] After forming the insulating film 17, a first groove G1 is formed to separate the pixels P, as shown in Figure 13C. For example, photoresist and etching are performed using a mask. For etching, dry etching is used. As a result, the first groove G1 is formed in the insulating film 17, the first semiconductor layer 12, the second semiconductor layer 13, and the light absorption layer 14. The first groove G1 may be formed only partway through the light absorption layer 14, or it may penetrate all the way to the contact layer 15.

[0107] After forming the first groove G1, as shown in Figure 13D, a portion of the exposed sidewalls of the first semiconductor layer 12 and the second semiconductor layer 13 is etched. That is, the first semiconductor layer 12 and the second semiconductor layer 13 are removed from their sidewalls at a predetermined distance. This results in a two-stage shape in which the width changes in a step-like manner between the first semiconductor layer 12 and the second semiconductor layer 13 and the light-absorbing layer 14. For example, the etching is performed using wet etching with an InP etching solution that allows for a selectivity ratio between InP in the first semiconductor layer 12 and the second semiconductor layer 13 and InGaAs in the light-absorbing layer 14. During this wet etching, the damaged layer (defect layer) on the sidewall generated by dry etching for forming the first groove G1 can be removed. Furthermore, it is necessary to control the amount of etching so that the width of the first semiconductor layer 12 and the second semiconductor layer 13 becomes wider than that of the contact layer 20. This is to suppress contact between the diffusion region D, which will be formed later, and the contact layer 20.

[0108] Furthermore, by wet etching the sidewalls of the light-absorbing layer 14, the damaged layer on the sidewalls of the light-absorbing layer 14 caused by dry etching can be removed. However, due to the two-stage shape described above, the etching width of the light-absorbing layer 14 must be less than the etching width of the first semiconductor layer 12 and the second semiconductor layer 13.

[0109] After forming the two-stage shape, a diffusion region D is formed as shown in Figure 13E. The diffusion region D is formed on the sidewalls of the first semiconductor layer 12, the second semiconductor layer 13, and the light absorption layer 14. The diffusion region D is formed by diffusing p+-type impurities, such as zinc (Zn), from the exposed surface of the first semiconductor layer 12. The diffusion of impurities is carried out by gas-phase diffusion or solid-phase diffusion, for example. If the diffusion region D is made too thick, the quantum efficiency may decrease. Also, if a damaged layer remains from the sidewall processing, it is necessary to diffuse the impurities so that they reach the entire damaged layer in order to suppress the increase in dark current. Therefore, the thickness of the diffusion region D is set considering the quantum efficiency and dark current. Furthermore, if the diffusion region D on the sidewall of the first semiconductor layer 12 connects to the contact layer 20, the dark current may increase. Therefore, it is necessary to control the etching amount of the first semiconductor layer 12 and the thickness of the diffusion region D so that the diffusion region D on the sidewall of the first semiconductor layer 12 does not come into contact with the contact layer 20.

[0110] After forming the diffusion region D, a protective film 19 is formed to cover the insulating film 17 and the diffusion region D. Next, photoresist and etching are performed, for example, using a mask. Etching is performed using either dry etching or wet etching. This creates holes in the protective film 19 and the insulating film 17 that reach the contact layer 20. After the holes are formed, the first electrode 11 is formed in these holes. Finally, the second electrode 16 is formed over the entire surface of the contact layer 15. This completes the solid-state image sensor 1 shown in Figure 11.

[0111] As described above, according to the second embodiment, the widths of the first semiconductor layer 12 and the second semiconductor layer 13, including the diffusion region D of the sidewall, are made narrower than the width of the light absorption layer 14, thereby separating the sidewall into two stages. Furthermore, the diffusion region D is formed on the sidewall of both of these stages. As a result, the diffusion region D can be formed deeper in the first semiconductor layer 12 and the second semiconductor layer 13 compared to the light absorption layer 14.

[0112] If the width of the first semiconductor layer 12, the second semiconductor layer 13, and the light-absorbing layer 14, including the diffusion region D of the sidewall, are approximately the same, then as the diffusion region D becomes thinner, the width of the first semiconductor layer 12 and the second semiconductor layer 13 excluding the diffusion region D increases. The depletion layer formed by the pn junction of the first semiconductor layer 12 and the second semiconductor layer 13 can be one of the causes of parasitic capacitance and dark current. Therefore, as the diffusion region D becomes thinner, parasitic capacitance and dark current tend to increase. On the other hand, as the diffusion region D becomes thicker, the width of the light-absorbing layer 14 excluding the diffusion region D becomes narrower, which tends to decrease the quantum efficiency.

[0113] In contrast, in the second embodiment, parasitic capacitance and dark current can be reduced by narrowing the widths of the first semiconductor layer 12 and the second semiconductor layer 13 through etching or the like. Therefore, it is not necessary to thicken the diffusion region D in order to reduce parasitic capacitance and dark current. Furthermore, selective etching can reduce the amount of etching of the light absorption layer 14, allowing the light absorption layer 14 to be kept wide. In other words, by controlling the width in the planar direction for each compound semiconductor layer, it is possible to achieve both low parasitic capacitance and dark current and high quantum efficiency.

[0114] Furthermore, as explained in the process shown in Figure 13D, the damaged layer on the grooved surface can be removed by wet etching. From the standpoint of removing the damaged layer, dark current can be further suppressed.

[0115] Furthermore, from the viewpoint of reducing dark current, it is preferable that the thickness of the diffusion region D on the side wall of the first semiconductor layer 12 is just enough so that the diffusion region D does not come into contact with the contact layer 20. That is, the diffusion regions D on the side walls of the first semiconductor layer 12 and the second semiconductor layer 13 are arranged to be close to the contact layer 20 while maintaining a gap between them. The thickness of the diffusion region D is controlled, for example, by the annealing temperature and time.

[0116] <First modified example of the second embodiment> [composition] Figures 14 and 15 show a schematic configuration of the solid-state image sensor 1 according to the first modified example of the second embodiment described above. Figure 14 shows the cross-sectional configuration of the solid-state image sensor 1, and Figure 15 shows the planar configuration of the solid-state image sensor 1. The first modified example of the second embodiment differs from the second embodiment in that the thickness of the diffusion region D is not the same depending on the position.

[0117] Furthermore, as shown in Figures 14 and 15, a step is provided at the bottom of the third groove G3, and a step is provided in the second semiconductor layer 13 that is parallel to the XY plane.

[0118] The diffusion regions D of the sidewalls of the first semiconductor layer 12 and the second semiconductor layer 13 are thicker than the diffusion regions D of the sidewalls of the light-absorbing layer 14. Therefore, in the second embodiment, parasitic capacitance and dark flow can be further reduced compared to the first embodiment.

[0119] Compared to the second embodiment, the insulating film 17 is provided so as to cover the diffusion region D of the sidewalls of the first semiconductor layer 12 and the second semiconductor layer 13. More specifically, the insulating film 17a is provided in addition to the insulating film 17 so as to cover the sidewalls of the first semiconductor layer 12 and the second semiconductor layer 13. The material of the insulating film 17a is, for example, the same material as the insulating film 17.

[0120] The coating film 18 is provided so as to cover the diffusion region D of the side wall of the light absorption layer 14. Therefore, the first semiconductor layer 12 and the second semiconductor layer 13 are covered by the insulating film 17a and are not covered by the coating film 18.

[0121] The other configurations of the solid-state image sensor 1 according to the first modified example of the second embodiment are the same as the corresponding configurations of the solid-state image sensor 1 according to the second embodiment, so a detailed explanation thereof is omitted.

[0122] [Manufacturing method for solid-state image sensor 1] Figures 16A to 16E show the manufacturing process of the solid-state image sensor 1 in chronological order. Note that the steps prior to the steps in Figure 16A are the same as the steps in Figures 13A and 13B described in the second embodiment.

[0123] First, a laminated structure is formed, and a portion of the contact layer 20 is removed (see Figure 13A).

[0124] After forming the insulating film 17 in the process shown in Figure 13B, a second groove G2 is formed as shown in Figure 16A. The second groove G2 exposes the side walls of the first semiconductor layer 12 and the second semiconductor layer 13. For example, photoresist and etching are performed using a mask. For etching, dry etching is used. As a result, the second groove G2 is formed in the insulating film 17, the first semiconductor layer 12, and the second semiconductor layer 13. The second groove G2 is formed, for example, up to partway through the second semiconductor layer 13.

[0125] After forming the second groove G2, a diffusion region D is formed using the insulating film 17 as a mask, as shown in Figure 16B. The diffusion region D is formed on the sidewalls of the first semiconductor layer 12 and the second semiconductor layer 13. Furthermore, if the diffusion region D on the sidewall of the first semiconductor layer 12 connects to the contact layer 20, the dark current may increase. Therefore, it is necessary to control the etching amount of the first semiconductor layer 12 and the thickness of the diffusion region D so that the diffusion region D on the sidewall of the first semiconductor layer 12 does not come into contact with the contact layer 20.

[0126] The first diffusion step is more preferably carried out in a phosphine (PH3) atmosphere. This is because the light-absorbing layer 14 is not exposed, and the first semiconductor layer 12 and the second semiconductor layer 13 are exposed on the surface. As a result, the desorption of P (phosphorus) from the first semiconductor layer 12 and the second semiconductor layer 13 (e.g., InP) exposed on the surface is suppressed.

[0127] After forming the diffusion region D, an insulating film 17a is added as shown in Figure 16C, and then the third groove G3 is formed.

[0128] The insulating film 17a is formed to cover the diffusion region D of the side walls of the first semiconductor layer 12 and the second semiconductor layer 13. It is more preferable that the insulating film 17a is an insulating film such as an oxide film suitable for the first semiconductor layer 12 and the second semiconductor layer 13 (e.g., InP). This is because the insulating film 17a is in contact with the first semiconductor layer 12 and the second semiconductor layer 13 but not with the light absorption layer 14. The material of the insulating film 17a is, for example, the same material as the insulating film 17.

[0129] The third groove G3 exposes the sidewall of the light-absorbing layer 14. For example, photoresist and etching are performed using a mask. For etching, dry etching is used. As a result, the third groove G3 is formed in the second semiconductor layer 13, the light-absorbing layer 14, and the contact layer 15. The third groove G3 may be formed only partway through the light-absorbing layer 14, or it may penetrate all the way to the contact layer 15.

[0130] Furthermore, the third groove G3 is narrower than the second groove G2. This makes it possible to make the width of the first semiconductor layer 12 and the second semiconductor layer 13, including the sidewall diffusion region D, narrower than the width of the light-absorbing layer 14, including the sidewall diffusion region D.

[0131] After forming the third groove G3, a second impurity diffusion process is performed as shown in Figure 16D. The diffusion region D formed in the first diffusion process extends even deeper into the first semiconductor layer 12 and the second semiconductor layer 13. In the second diffusion process, diffusion regions D are formed almost simultaneously on the side walls of the light absorption layer 14 and the contact layer 15. As a result, the diffusion regions D formed in the first semiconductor layer 12 and the second semiconductor layer 13 become thicker than the diffusion regions D formed in the light absorption layer 14 and the contact layer 15.

[0132] Making the diffusion region D too thick reduces quantum efficiency. Also, if a damaged layer remains from the sidewall processing, it is necessary to diffuse impurities throughout the entire damaged layer to suppress the increase in dark current. Therefore, the thickness of the diffusion region D in the first and second diffusion processes is set considering quantum efficiency and dark current. Furthermore, if the diffusion region D of the sidewall of the first semiconductor layer 12 connects to the contact layer 20, the dark current may increase. Therefore, it is necessary to control the etching amount of the first semiconductor layer 12 and the thickness of the diffusion region D so that the diffusion region D of the sidewall of the first semiconductor layer 12 does not come into contact with the contact layer 20.

[0133] The second diffusion step is performed in an arsine (AsH3) atmosphere, for example. This is because the sidewalls of the first semiconductor layer 12 and the second semiconductor layer 13 are already covered with an insulating film 17a, and the majority of the compound semiconductor layer exposed on the sidewall surface is the light-absorbing layer 14. As a result, the desorption of As (arsenic) from the light-absorbing layer 14 (e.g., InGaAs) exposed on the surface can be suppressed.

[0134] After the second diffusion step, a coating film 18 is formed to cover the insulating film 17a, the second semiconductor layer 13, the light absorption layer 14, and the contact layer 15, as shown in Figure 16E. The coating film 18 is formed to cover the diffusion region D of the side wall of the light absorption layer 14.

[0135] The coating film 18 is more preferably an insulating film such as an oxide film suitable for the light-absorbing layer 14 (e.g., InGaAs). This is because the sidewalls of the first semiconductor layer 12 and the second semiconductor layer 13 are already covered with the insulating film 17a, and the majority of the compound semiconductor layer among the sidewall surfaces exposed from the insulating film 17a is the light-absorbing layer 14. Therefore, the coating film 18 is formed from a material different from the insulating film 17a, for example.

[0136] After forming the coating film 18, a protective film 19 is formed to cover the coating film 18. Next, as described in the second embodiment, the first electrode 11 and the second electrode 16 are formed. This completes the solid-state image sensor 1 shown in Figure 14.

[0137] As shown in this modified example, the width of the semiconductor layer may be made into a two-stage shape, and the diffusion process may be performed in two separate steps to control the width and diffusion region D for each compound semiconductor. In this case as well, the same effects as those of the first and second embodiments can be obtained.

[0138] Furthermore, as shown in Figure 14, insulating films 17a and coating films 18 suitable for InP in the first semiconductor layer 12 and the second semiconductor layer 13, and for InGaAs in the light absorption layer 14, can be formed. From the viewpoint of being able to form appropriate insulating films for each material, dark current can be further suppressed.

[0139] <Second modified example of the second embodiment> Figure 17 shows a schematic cross-sectional configuration of the solid-state image sensor 1 according to a second modification of the second embodiment described above. The second modification of the second embodiment differs from the second embodiment in that the conductivity type is reversed.

[0140] The solid-state image sensor 1 shown in Figure 11, described in the second embodiment, has p-type pixels, i.e., an electronic readout structure. On the other hand, the solid-state image sensor 1 shown in Figure 17 has n-type pixels, i.e., a Hole readout structure. Furthermore, since the diffusion region D in Figure 17 is n-type, the dopant of the diffusion region D is, for example, silicon (Si) or germanium (Ge).

[0141] As shown in this modified example, holes may be read out as signal charges. In this case as well, the same effects as in the first embodiment can be obtained.

[0142] <Third modified example of the second embodiment> Figure 18 shows a schematic cross-sectional configuration of the solid-state image sensor 1 according to the third modification of the second embodiment described above. The third modification of the second embodiment differs from the first modification of the second embodiment in that the conductivity type is reversed.

[0143] The solid-state image sensor 1 shown in Figure 14, described in the first modified example of the second embodiment, has p-type pixels, i.e., an electronic readout structure. On the other hand, the solid-state image sensor 1 shown in Figure 18 has n-type pixels, i.e., a Hole readout structure. Furthermore, since the diffusion region D in Figure 18 is n-type, the dopant of the diffusion region D is, for example, silicon (Si) or germanium (Ge).

[0144] As shown in this modified example, holes may be read out as signal charges. In this case as well, the same effects as in the first embodiment can be obtained.

[0145] <<Application Examples>> The technology disclosed herein can be applied to a variety of products. For example, the technology disclosed herein may be implemented as a device mounted on any type of mobile vehicle, such as automobiles, electric vehicles, hybrid electric vehicles, motorcycles, bicycles, personal mobility devices, airplanes, drones, ships, robots, construction machinery, or agricultural machinery (tractors).

[0146] Figure 19 is a block diagram showing a schematic configuration example of a vehicle control system 7000, which is an example of a mobile control system to which the technology described herein can be applied. The vehicle control system 7000 comprises a plurality of electronic control units connected via a communication network 7010. In the example shown in Figure 19, the vehicle control system 7000 comprises a drive system control unit 7100, a body system control unit 7200, a battery control unit 7300, an external information detection unit 7400, an internal information detection unit 7500, and an integrated control unit 7600. The communication network 7010 connecting these plurality of control units may be an in-vehicle communication network conforming to any standard such as CAN (Controller Area Network), LIN (Local Interconnect Network), LAN (Local Area Network), or FlexRay®.

[0147] Each control unit comprises a microcomputer that performs calculations according to various programs, a storage unit that stores programs executed by the microcomputer or parameters used in various calculations, and a drive circuit that drives various controlled devices. Each control unit is equipped with a network interface for communication with other control units via the communication network 7010, and a communication interface for communication with devices or sensors inside or outside the vehicle via wired or wireless communication. Figure 19 illustrates the functional configuration of the integrated control unit 7600, which includes a microcomputer 7610, a general-purpose communication interface 7620, a dedicated communication interface 7630, a positioning unit 7640, a beacon receiver 7650, an in-vehicle equipment interface 7660, an audio / image output unit 7670, an in-vehicle network interface 7680, and a storage unit 7690. Other control units similarly include a microcomputer, a communication interface, and a storage unit.

[0148] The drivetrain control unit 7100 controls the operation of devices related to the vehicle's drivetrain according to various programs. For example, the drivetrain control unit 7100 functions as a control device for generating driving force for the vehicle, such as an internal combustion engine or a drive motor; a driving force transmission mechanism for transmitting driving force to the wheels; a steering mechanism for adjusting the steering angle of the vehicle; and a braking device for generating braking force for the vehicle. The drivetrain control unit 7100 may also function as a control device such as ABS (Antilock Brake System) or ESC (Electronic Stability Control).

[0149] A vehicle state detection unit 7110 is connected to the drivetrain control unit 7100. The vehicle state detection unit 7110 includes, for example, a gyro sensor for detecting the angular velocity of the vehicle's axial rotational motion, an acceleration sensor for detecting the vehicle's acceleration, or at least one of the sensors for detecting the amount of operation of the accelerator pedal, the amount of operation of the brake pedal, the steering angle of the steering wheel, the engine speed, or the rotational speed of the wheels. The drivetrain control unit 7100 performs calculations using signals input from the vehicle state detection unit 7110 and controls the internal combustion engine, drive motor, electric power steering system, brake system, etc.

[0150] The body system control unit 7200 controls the operation of various devices mounted on the vehicle body according to various programs. For example, the body system control unit 7200 functions as a control device for a keyless entry system, a smart key system, a power window system, or various lamps such as headlights, reverse lights, brake lights, turn signals, or fog lights. In this case, the body system control unit 7200 may receive radio waves transmitted from a portable device that replaces a key or signals from various switches. The body system control unit 7200 receives these radio waves or signals and controls the vehicle's door lock system, power window system, lamps, etc.

[0151] The battery control unit 7300 controls the secondary battery 7310, which is the power source for the drive motor, according to various programs. For example, the battery control unit 7300 receives information such as battery temperature, battery output voltage, or remaining battery capacity from the battery device equipped with the secondary battery 7310. The battery control unit 7300 uses these signals to perform calculations and controls the temperature of the secondary battery 7310 or the cooling device provided in the battery device.

[0152] The external information detection unit 7400 detects information from outside the vehicle equipped with the vehicle control system 7000. For example, at least one of the imaging unit 7410 and the external information detection unit 7420 is connected to the external information detection unit 7400. The imaging unit 7410 includes at least one of the following: a ToF (Time Of Flight) camera, a stereo camera, a monocular camera, an infrared camera, and other cameras. The external information detection unit 7420 includes at least one of the following: an environmental sensor for detecting the current weather or climate, or an ambient information detection sensor for detecting other vehicles, obstacles, or pedestrians around the vehicle equipped with the vehicle control system 7000.

[0153] The environmental sensor may be at least one of the following: a raindrop sensor for detecting rain, a fog sensor for detecting fog, a sunshine sensor for detecting the degree of sunlight, and a snow sensor for detecting snowfall. The ambient information detection sensor may be at least one of the following: an ultrasonic sensor, a radar device, and a LIDAR (Light Detection and Ranging, Laser Imaging Detection and Ranging) device. These imaging unit 7410 and external information detection unit 7420 may be provided as independent sensors or devices, or as a device in which multiple sensors or devices are integrated.

[0154] Here, Figure 20 shows examples of the installation locations of the imaging unit 7410 and the external information detection unit 7420. The imaging units 7910, 7912, 7914, 7916, and 7918 are installed, for example, at least one of the following locations on the vehicle 7900: the front nose, side mirrors, rear bumper, back door, and the upper part of the windshield inside the passenger compartment. The imaging unit 7910 installed on the front nose and the imaging unit 7918 installed on the upper part of the windshield inside the passenger compartment mainly acquire images of the front of the vehicle 7900. The imaging units 7912 and 7914 installed on the side mirrors mainly acquire images of the sides of the vehicle 7900. The imaging unit 7916 installed on the rear bumper or back door mainly acquires images of the rear of the vehicle 7900. The imaging unit 7918 installed on the upper part of the windshield inside the passenger compartment is mainly used for detecting preceding vehicles, pedestrians, obstacles, traffic lights, traffic signs, or lanes.

[0155] Figure 20 shows an example of the imaging range of each imaging unit 7910, 7912, 7914, and 7916. Imaging range a shows the imaging range of imaging unit 7910 located on the front nose, imaging ranges b and c show the imaging ranges of imaging units 7912 and 7914 located on the side mirrors, respectively, and imaging range d shows the imaging range of imaging unit 7916 located on the rear bumper or back door. For example, by superimposing the image data captured by imaging units 7910, 7912, 7914, and 7916, an overhead view image of the vehicle 7900 can be obtained.

[0156] The external information detection units 7920, 7922, 7924, 7926, 7928, and 7930, which are installed on the front, rear, sides, corners, and the upper part of the windshield inside the vehicle 7900, may be, for example, ultrasonic sensors or radar devices. The external information detection units 7920, 7926, and 7930, which are installed on the front nose, rear bumper, back door, and the upper part of the windshield inside the vehicle 7900, may be, for example, LIDAR devices. These external information detection units 7920 to 7930 are mainly used to detect preceding vehicles, pedestrians, or obstacles.

[0157] Returning to Figure 19, the explanation continues. The external information detection unit 7400 causes the imaging unit 7410 to capture images of the area outside the vehicle and receives the captured image data. The external information detection unit 7400 also receives detection information from the connected external information detection unit 7420. If the external information detection unit 7420 is an ultrasonic sensor, radar device, or LIDAR device, the external information detection unit 7400 emits ultrasonic waves or electromagnetic waves and receives information on the received reflected waves. Based on the received information, the external information detection unit 7400 may perform object detection processing such as detecting people, vehicles, obstacles, signs, or characters on the road surface, or distance detection processing. Based on the received information, the external information detection unit 7400 may perform environmental recognition processing to recognize rainfall, fog, or road surface conditions. Based on the received information, the external information detection unit 7400 may calculate the distance to an object outside the vehicle.

[0158] Furthermore, the external information detection unit 7400 may perform image recognition processing or distance detection processing to recognize people, vehicles, obstacles, signs, or characters on the road surface based on the received image data. The external information detection unit 7400 may perform distortion correction or alignment processing on the received image data, and may also synthesize image data captured by different imaging units 7410 to generate an overhead view image or a panoramic image. The external information detection unit 7400 may also perform viewpoint transformation processing using image data captured by different imaging units 7410.

[0159] The in-vehicle information detection unit 7500 detects information inside the vehicle. The in-vehicle information detection unit 7500 is connected to, for example, a driver status detection unit 7510 that detects the driver's state. The driver status detection unit 7510 may include a camera that images the driver, a biosensor that detects the driver's biometric information, or a microphone that collects sounds inside the vehicle. The biosensor is installed, for example, on the seat or steering wheel and detects the biometric information of a passenger sitting in the seat or a driver holding the steering wheel. Based on the detection information input from the driver status detection unit 7510, the in-vehicle information detection unit 7500 may calculate the driver's level of fatigue or concentration, or determine whether the driver is dozing off. The in-vehicle information detection unit 7500 may perform processing such as noise cancellation on the collected audio signals.

[0160] The integrated control unit 7600 controls the overall operation of the vehicle control system 7000 according to various programs. An input unit 7800 is connected to the integrated control unit 7600. The input unit 7800 is implemented by a device that can be operated by the passenger, such as a touch panel, buttons, a microphone, a switch, or a lever. The integrated control unit 7600 may also receive data obtained by voice recognition of voice input from the microphone. The input unit 7800 may be a remote control device using infrared or other radio waves, or an external device such as a mobile phone or PDA (Personal Digital Assistant) that is compatible with the operation of the vehicle control system 7000. The input unit 7800 may be a camera, in which case the passenger can input information by gesture. Alternatively, data obtained by detecting the movement of a wearable device worn by the passenger may be input. Furthermore, the input unit 7800 may include, for example, an input control circuit that generates an input signal based on the information input by the passenger using the above input unit 7800 and outputs it to the integrated control unit 7600. Passengers and others can input various data or instruct the vehicle control system 7000 to perform processing operations by operating this input unit 7800.

[0161] The memory unit 7690 may include a ROM (Read Only Memory) for storing various programs executed by a microcomputer, and a RAM (Random Access Memory) for storing various parameters, calculation results, or sensor values. The memory unit 7690 may also be implemented using a magnetic storage device such as an HDD (Hard Disk Drive), a semiconductor storage device, an optical storage device, or a magneto-optical storage device.

[0162] The general-purpose communication interface 7620 is a general-purpose communication interface that mediates communication between the vehicle and various devices present in the external environment 7750. The general-purpose communication interface 7620 may implement cellular communication protocols such as GSM (Global System of Mobile communications), WiMAX (registered trademark), LTE (registered trademark) (Long Term Evolution), or LTE-A (LTE-Advanced), or other wireless communication protocols such as wireless LAN (also known as Wi-Fi (registered trademark)) or Bluetooth (registered trademark). The general-purpose communication interface 7620 may connect to devices (e.g., application servers or control servers) located on an external network (e.g., the Internet, a cloud network, or a carrier-specific network) via, for example, a base station or access point. The general-purpose communication interface 7620 may also connect to terminals located near the vehicle (e.g., terminals for drivers, pedestrians, or shops, or MTC (Machine Type Communication) terminals) using, for example, P2P (Peer To Peer) technology.

[0163] The Dedicated Communication I / F 7630 is a communication interface that supports communication protocols developed for use in vehicles. The Dedicated Communication I / F 7630 may implement standard protocols such as WAVE (Wireless Access in Vehicle Environment), DSRC (Dedicated Short Range Communications), or cellular communication protocols, which are combinations of lower-layer IEEE 802.11p and upper-layer IEEE 1609. The Dedicated Communication I / F 7630 typically performs V2X communication, a concept that includes one or more of the following: vehicle-to-vehicle communication, vehicle-to-infrastructure communication, vehicle-to-home communication, and vehicle-to-pedestrian communication.

[0164] The positioning unit 7640 performs positioning by receiving GNSS signals from GNSS (Global Navigation Satellite System) satellites (for example, GPS signals from GPS (Global Positioning System) satellites) and generates location information including the vehicle's latitude, longitude, and altitude. The positioning unit 7640 may also determine its current location by exchanging signals with a wireless access point, or it may acquire location information from a terminal such as a mobile phone, PHS, or smartphone that has a positioning function.

[0165] The beacon receiver 7650 receives radio waves or electromagnetic waves transmitted from, for example, a radio station installed on a road, and obtains information such as the current location, traffic congestion, road closures, or travel time. The functions of the beacon receiver 7650 may also be included in the dedicated communication interface 7630 described above.

[0166] The In-Vehicle Equipment I / F 7660 is a communication interface that mediates connections between the microcomputer 7610 and various in-vehicle equipment 7760 located inside the vehicle. The In-Vehicle Equipment I / F 7660 may establish a wireless connection using wireless communication protocols such as Wi-Fi, Bluetooth®, NFC (Near Field Communication), or WUSB (Wireless USB). Furthermore, the in-vehicle equipment I / F 7660 may establish a wired connection such as USB (Universal Serial Bus), HDMI (Registered Trademark) (High-Definition Multimedia Interface), or MHL (Mobile High-Definition Link) via connection terminals (and, if necessary, cables) not shown. The in-vehicle equipment 7760 may include, for example, at least one of the following: a mobile device or wearable device owned by a passenger, or an information device brought into or installed in the vehicle. The in-vehicle equipment 7760 may also include a navigation device that performs route searching to any destination. The in-vehicle equipment I / F 7660 exchanges control signals or data signals with these in-vehicle equipment 7760s.

[0167] The in-vehicle network interface 7680 is an interface that mediates communication between the microcomputer 7610 and the communication network 7010. The in-vehicle network interface 7680 transmits and receives signals and other data in accordance with a predetermined protocol supported by the communication network 7010.

[0168] The microcomputer 7610 of the integrated control unit 7600 controls the vehicle control system 7000 according to various programs based on information acquired via at least one of the general-purpose communication I / F 7620, dedicated communication I / F 7630, positioning unit 7640, beacon receiver 7650, in-vehicle equipment I / F 7660, and in-vehicle network I / F 7680. For example, the microcomputer 7610 may calculate control target values ​​for the drive force generator, steering mechanism, or braking device based on acquired in-vehicle and out-of-vehicle information and output control commands to the drive system control unit 7100. For example, the microcomputer 7610 may perform coordinated control aimed at realizing ADAS (Advanced Driver Assistance System) functions, including vehicle collision avoidance or impact mitigation, following driving based on distance between vehicles, maintaining vehicle speed, vehicle collision warning, or vehicle lane departure warning. Furthermore, the microcomputer 7610 may perform cooperative control for purposes such as autonomous driving, where the vehicle drives autonomously without driver intervention, by controlling the drive force generating device, steering mechanism, or braking device, etc., based on the acquired information about the vehicle's surroundings.

[0169] The microcomputer 7610 may generate three-dimensional distance information between the vehicle and surrounding structures, people, and other objects based on information acquired via at least one of the general-purpose communication I / F 7620, dedicated communication I / F 7630, positioning unit 7640, beacon receiver 7650, in-vehicle equipment I / F 7660, and in-vehicle network I / F 7680, and create local map information including surrounding information of the vehicle's current location. Furthermore, the microcomputer 7610 may predict dangers such as vehicle collision, proximity of pedestrians, or entry into a closed road based on the acquired information, and generate a warning signal. The warning signal may, for example, be a signal to generate a warning sound or illuminate a warning lamp.

[0170] The audio-image output unit 7670 transmits at least one of audio and image output signals to an output device capable of visually or audibly notifying the vehicle's occupants or those outside the vehicle. In the example in Figure 19, the output devices are exemplified as an audio speaker 7710, a display unit 7720, and an instrument panel 7730. The display unit 7720 may include, for example, at least one of an onboard display and a head-up display. The display unit 7720 may also have an AR (Augmented Reality) display function. The output device may be other devices besides these, such as headphones, wearable devices such as glasses-type displays worn by occupants, projectors, or lamps. If the output device is a display device, the display device visually displays the results obtained from various processes performed by the microcomputer 7610 or information received from other control units in various formats such as text, images, tables, and graphs. If the output device is an audio output device, the audio output device converts the audio signal, consisting of reproduced audio data or sound data, into an analog signal and outputs it audibly.

[0171] In the example shown in Figure 19, at least two control units connected via the communication network 7010 may be integrated into a single control unit. Alternatively, each control unit may be composed of multiple control units. Furthermore, the vehicle control system 7000 may include other control units not shown. Also, in the above description, some or all of the functions performed by one control unit may be assigned to other control units. In other words, as long as information is transmitted and received via the communication network 7010, predetermined calculation processing may be performed by any of the control units. Similarly, a sensor or device connected to one control unit may be connected to another control unit, and multiple control units may transmit and receive detection information to each other via the communication network 7010.

[0172] Furthermore, this technology can take the following configuration. (1) A photoelectric conversion layer containing a compound semiconductor material, Two stacked semiconductor layers are arranged on the opposite side of the photoelectric conversion layer from the light incident surface, each containing impurities of different conductivity types. The photoelectric conversion layer and the two semiconductor layers are disposed on the side walls of the two semiconductor layers, and the diffusion layer contains impurities with a higher impurity concentration than the two semiconductor layers, A solid-state image sensor in which the planar width of the two semiconductor layers, excluding the diffusion layer on the side wall, is narrower than the planar width of the photoelectric conversion layer, excluding the diffusion layer on the side wall. (2) The two semiconductor layers are A first semiconductor layer containing a first-conductivity type impurity, The first semiconductor layer and the photoelectric conversion layer are disposed between the first semiconductor layer and the second semiconductor layer which contains an impurity of a second conductivity type, The solid-state image sensor according to (1), wherein the diffusion layer is arranged on the side walls of the first semiconductor layer and the second semiconductor layer and contains impurities of a second conductivity type with a higher impurity concentration than that of the second semiconductor layer. (3) The solid-state image sensor according to (1) or (2), wherein the diffusion layer on the sidewall of the two semiconductor layers is thicker than the diffusion layer on the sidewall of the photoelectric conversion layer. (4) The solid-state image sensor according to (3), wherein the planar width of the two semiconductor layers, including the diffusion layer of the side wall, is substantially the same as the planar width of the photoelectric conversion layer, including the diffusion layer of the side wall, or the planar width narrows continuously from the light incident surface side of the photoelectric conversion layer, including the diffusion layer of the side wall, to the two semiconductor layers. (5) A third semiconductor layer is disposed on the light incident surface side of the photoelectric conversion layer and further comprises the same conductivity type as the photoelectric conversion layer, The solid-state image sensor according to (3) or (4), wherein the diffusion layer disposed on the side wall of the third semiconductor layer is thicker than the diffusion layer on the side wall of the photoelectric conversion layer and thinner than the diffusion layer on the side walls of the two semiconductor layers. (6) The two semiconductor layers are A first semiconductor layer containing a first-conductivity type impurity, The first semiconductor layer and the photoelectric conversion layer are disposed between the first semiconductor layer and the second semiconductor layer which contains an impurity of a second conductivity type, The first insulating film is further disposed on the first semiconductor layer and is located inside the first semiconductor layer when viewed from a plan view from the opposite side of the light incident surface. The solid-state image sensor according to any one of (3) to (5), wherein the diffusion layer on the side wall of the first semiconductor layer is thicker than the diffusion layer on the side wall of the second semiconductor layer. (7) The solid-state image sensor according to (1) or (2), wherein the two semiconductor layers, including the diffusion layer on the side wall, have a planar width that is progressively narrower than the photoelectric conversion layer, including the diffusion layer on the side wall. (8) The solid-state image sensor according to (7), wherein the diffusion layer on the sidewall of the two semiconductor layers has a thickness substantially the same as the thickness of the diffusion layer on the sidewall of the photoelectric conversion layer. (9) The solid-state image sensor according to (7) or (8), wherein the diffusion layer on the sidewalls of the two semiconductor layers is thicker than the diffusion layer on the sidewall of the photoelectric conversion layer. (10) A first insulating film disposed so as to cover the diffusion layer on the side walls of the two semiconductor layers, The solid-state image sensor according to (9), further comprising a second insulating film, which is disposed to cover the diffusion layer on the side wall of the photoelectric conversion layer and is different from the first insulating film. (11) Further comprising an electrode that is positioned between the two semiconductor layers and the photoelectric conversion layer, and reads out the charge photoelectrically converted by the photoelectric conversion layer, The solid-state image sensor according to any one of (1) to (10), wherein the diffusion layer on the side wall of the two semiconductor layers is arranged to be close to the electrode while maintaining a distance from it. (12) An electrode is positioned between the photoelectric conversion layer and the two semiconductor layers, and reads out the charge photoelectrically converted by the photoelectric conversion layer, The system further comprises a fourth semiconductor layer disposed between the two semiconductor layers and the electrode, and having a conductivity different from that of the photoelectric conversion layer. The solid-state image sensor according to any one of (1) to (10), wherein the diffusion layer on the side walls of the two semiconductor layers is arranged to be close to the fourth semiconductor layer while maintaining a distance from it. (13) The solid-state image sensor according to any one of (1) to (12), wherein the two semiconductor layers have a band gap energy greater than the band gap energy of the photoelectric conversion layer. (14) A laminate is formed comprising a photoelectric conversion layer containing a compound semiconductor material and two stacked semiconductor layers, each containing impurities of different conductivity types from one another. A diffusion layer containing impurities with a higher impurity concentration than that of the two semiconductor layers is formed on the two semiconductor layers. A first groove is formed that exposes the diffusion layer on the sidewalls of the two semiconductor layers and the sidewall of the photoelectric conversion layer. A method for manufacturing a solid-state image sensor, comprising forming the diffusion layer on the side wall of the photoelectric conversion layer, and making the diffusion layer on the side wall of the two semiconductor layers thicker than the diffusion layer on the side wall of the photoelectric conversion layer. (15) After forming the laminate, A first insulating film is formed on the laminate, with each pixel having its own insulating film. Using the first insulating film as a mask, the diffusion layer is formed on the two semiconductor layers. After forming the first groove, When viewed from a plan view from the opposite side of the light incident surface of the photoelectric conversion layer, the outer periphery of the first insulating film is removed so that the first insulating film is positioned inside the two semiconductor layers. A method for manufacturing a solid-state image sensor according to (14), comprising forming the diffusion layer on the side wall of the photoelectric conversion layer using the first insulating film as a mask, and making the diffusion layer on the side wall of the two semiconductor layers thicker than the diffusion layer on the side wall of the photoelectric conversion layer. (16) A laminate is formed comprising a photoelectric conversion layer containing a compound semiconductor material and two stacked semiconductor layers, each containing impurities of different conductivity types from one another. A first groove is formed that exposes the sidewalls of the two semiconductor layers and the sidewall of the photoelectric conversion layer. By removing a portion of the two semiconductor layers from the side wall, A method for manufacturing a solid-state image sensor, comprising forming a diffusion layer containing impurities with a higher impurity concentration than the two semiconductor layers on the side walls of the photoelectric conversion layer and the two semiconductor layers. (17) A laminate is formed comprising a photoelectric conversion layer containing a compound semiconductor material and two stacked semiconductor layers, each containing impurities of different conductivity types from one another. A second groove is formed to expose the side walls of the two semiconductor layers. A diffusion layer containing impurities with a higher impurity concentration than that of the two semiconductor layers is formed on the side walls of the two semiconductor layers. A third groove, narrower than the second groove, is formed to expose the side wall of the photoelectric conversion layer. A method for manufacturing a solid-state image sensor, comprising forming the diffusion layer on the side wall of the photoelectric conversion layer, and making the diffusion layer on the side wall of the two semiconductor layers thicker than the diffusion layer on the side wall of the photoelectric conversion layer. (18) After forming the diffusion layer on the side walls of the two semiconductor layers, A first insulating film is formed to cover the diffusion layer on the side walls of the two semiconductor layers. The diffusion layer is formed on the side wall of the photoelectric conversion layer, and the diffusion layer on the side walls of the two semiconductor layers is thickened, The method for manufacturing a solid-state image sensor according to (17), further comprising forming a second insulating film different from the first insulating film that covers the diffusion layer on the side wall of the photoelectric conversion layer.

[0173] The aspects of this disclosure are not limited to the individual embodiments described above, but include various modifications that a person skilled in the art could conceive, and the effects of this disclosure are not limited to those described above. In other words, various additions, modifications, and partial deletions are possible, as long as they do not depart from the conceptual idea and spirit of this disclosure derived from the claims and their equivalents. [Explanation of Symbols]

[0174] 1 Solid-state image sensor, 11 First electrode, 12 First semiconductor layer, 13 Second semiconductor layer, 14 Light absorption layer, 15 Contact layer, 16 Second electrode, 17 Insulating film, 17a Insulating film, 18 Coating film, 19 Protective film, 20 Contact layer, D Diffusion region, G1 First groove, G2 Second groove, G3 Third groove, P Pixel, S1 First plane, S2 Second plane

Claims

1. A photoelectric conversion layer containing a compound semiconductor material, Two stacked semiconductor layers are arranged on the opposite side of the photoelectric conversion layer from the light incident surface, each containing impurities of different conductivity types. The photoelectric conversion layer and the two semiconductor layers are disposed on the side walls of the two semiconductor layers, and the diffusion layer contains impurities with a higher impurity concentration than the two semiconductor layers, The planar width of the two semiconductor layers, excluding the diffusion layer on the sidewall, is narrower than the planar width of the photoelectric conversion layer, excluding the diffusion layer on the sidewall. A solid-state image sensor in which the diffusion layer on the sidewalls of the two semiconductor layers is thicker than the diffusion layer on the sidewall of the photoelectric conversion layer.

2. The two semiconductor layers mentioned above are A first semiconductor layer containing a first-conductivity type impurity, The first semiconductor layer and the photoelectric conversion layer are disposed between the first semiconductor layer and the second semiconductor layer which contains an impurity of a second conductivity type, The solid-state image sensor according to claim 1, wherein the diffusion layer is arranged on the side walls of the first semiconductor layer and the second semiconductor layer and contains an impurity of a second conductivity type with a higher impurity concentration than that of the second semiconductor layer.

3. The solid-state image sensor according to claim 1, wherein the planar width of the two semiconductor layers, including the diffusion layer of the side wall, is substantially the same as the planar width of the photoelectric conversion layer, including the diffusion layer of the side wall, or the planar width continuously narrows from the light incident surface side of the photoelectric conversion layer, including the diffusion layer of the side wall, to the two semiconductor layers.

4. The photoelectric conversion layer is disposed on the light incident surface side and further comprises a third semiconductor layer of the same conductivity type as the photoelectric conversion layer, The solid-state image sensor according to claim 1, wherein the diffusion layer disposed on the side wall of the third semiconductor layer is thicker than the diffusion layer on the side wall of the photoelectric conversion layer and thinner than the diffusion layer on the side walls of the two semiconductor layers.

5. The two semiconductor layers mentioned above are A first semiconductor layer containing a first-conductivity type impurity, The first semiconductor layer and the photoelectric conversion layer are disposed between the first semiconductor layer and the second semiconductor layer which contains an impurity of a second conductivity type, The first insulating film is further disposed on the first semiconductor layer and is located inside the first semiconductor layer when viewed from a plan view opposite the light incident surface. The solid-state image sensor according to claim 1, wherein the diffusion layer on the side wall of the first semiconductor layer is thicker than the diffusion layer on the side wall of the second semiconductor layer.

6. The solid-state image sensor according to claim 1, wherein the two semiconductor layers, including the diffusion layer on the side wall, have a planar width that gradually narrows from the photoelectric conversion layer, including the diffusion layer on the side wall.

7. A first insulating film is disposed so as to cover the diffusion layer on the side walls of the two semiconductor layers, The solid-state image sensor according to claim 6, further comprising a second insulating film, which is disposed to cover the diffusion layer on the side wall of the photoelectric conversion layer and is different from the first insulating film.

8. The device further comprises electrodes arranged between the photoelectric conversion layer and the two semiconductor layers, which read out the charge photoelectrically converted by the photoelectric conversion layer. The solid-state image sensor according to claim 1, wherein the diffusion layer on the side wall of the two semiconductor layers is arranged to be close to the electrode while maintaining a distance from it.

9. An electrode is positioned between the photoelectric conversion layer and the two semiconductor layers, and reads out the charge photoelectrically converted by the photoelectric conversion layer, The system further comprises a fourth semiconductor layer disposed between the two semiconductor layers and the electrode, and having a conductivity different from that of the photoelectric conversion layer. The solid-state image sensor according to claim 1, wherein the diffusion layer on the side walls of the two semiconductor layers is arranged to be close to the fourth semiconductor layer while maintaining a distance from it.

10. The solid-state image sensor according to claim 1, wherein the two semiconductor layers have a bandgap energy greater than the bandgap energy of the photoelectric conversion layer.

11. A laminate is formed comprising a photoelectric conversion layer containing a compound semiconductor material and two stacked semiconductor layers, each containing impurities of different conductivity types. A diffusion layer containing impurities with a higher impurity concentration than that of the two semiconductor layers is formed on the two semiconductor layers. A first groove is formed that exposes the diffusion layer on the sidewalls of the two semiconductor layers and the sidewall of the photoelectric conversion layer. A method for manufacturing a solid-state image sensor, comprising forming the diffusion layer on the side wall of the photoelectric conversion layer, and making the diffusion layer on the side wall of the two semiconductor layers thicker than the diffusion layer on the side wall of the photoelectric conversion layer.

12. After forming the aforementioned laminate, A first insulating film is formed on the laminate, with each pixel having its own insulating film. Using the first insulating film as a mask, the diffusion layer is formed on the two semiconductor layers. After forming the first groove, When viewed from a plan view from the opposite side of the light incident surface of the photoelectric conversion layer, the outer periphery of the first insulating film is removed so that the first insulating film is positioned inside the two semiconductor layers. A method for manufacturing a solid-state image sensor according to claim 11, comprising forming the diffusion layer on the side wall of the photoelectric conversion layer using the first insulating film as a mask, and making the diffusion layer on the side wall of the two semiconductor layers thicker than the diffusion layer on the side wall of the photoelectric conversion layer.

13. A laminate is formed comprising a photoelectric conversion layer containing a compound semiconductor material and two stacked semiconductor layers, each containing impurities of different conductivity types. A second groove is formed to expose the side walls of the two semiconductor layers. A diffusion layer containing impurities with a higher impurity concentration than that of the two semiconductor layers is formed on the side walls of the two semiconductor layers. A third groove, narrower than the second groove, is formed to expose the side wall of the photoelectric conversion layer. A method for manufacturing a solid-state image sensor, comprising forming the diffusion layer on the side wall of the photoelectric conversion layer, and making the diffusion layer on the side wall of the two semiconductor layers thicker than the diffusion layer on the side wall of the photoelectric conversion layer.

14. After forming the diffusion layer on the sidewalls of the two semiconductor layers, A first insulating film is formed to cover the diffusion layer on the side walls of the two semiconductor layers. The diffusion layer is formed on the side wall of the photoelectric conversion layer, and the diffusion layer on the side walls of the two semiconductor layers is thickened, The method for manufacturing a solid-state image sensor according to claim 13, further comprising forming a second insulating film different from the first insulating film, which covers the diffusion layer on the side wall of the photoelectric conversion layer.

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