Element substrate, liquid ejection head, and recording device

Abstract

To solve the following problem that: in a conventional element substrate, in order to fix to either a mode for selecting a recording element or a mode for selecting an antifuse element, signal data of at least 1 bit is required; therefore, every time a recording element or an antifuse element is selected, the signal data amount increases, and particularly in the case of printing using a recording element, an increase in the signal data amount leads to an increase in time for selecting the recording element.SOLUTION: In an element substrate, a control data supply circuit includes: a plurality of stages of shift registers that hold serial data signals; a decoder circuit that outputs a selection signal for selecting either a recording element or a memory element; and a mask circuit connected to the decoder circuit. The mask circuit outputs a high-level or low-level signal to the decoder circuit based on bit data signals for switching memory elements input to the mask circuit.SELECTED DRAWING: Figure 7

Description

Technical Field

[0001] The present invention relates to an element substrate having a recording element and a memory element, a liquid ejection head having the element substrate, and a recording apparatus that performs recording using the liquid ejection head.

Background Art

[0002] In recent years, after a product is completed, an OTP (One Time Programmable) memory for recording various product-specific information such as chip ID, setting parameters, and the state of change over time during product use is mounted on a semiconductor substrate. There are two types of OTP memories: those using a Poly fuse element and those using an anti-fuse element AF. The memory using the anti-fuse element can reduce the memory module size compared to the conventional Poly fuse memory, which is advantageous for saving space on the semiconductor substrate.

[0003] Also, in the liquid ejection head having a semiconductor substrate described in Patent Document 1, in order to further save space on the semiconductor substrate, it has one selection circuit including a shift register circuit and a latch circuit. And it is described that the selection circuit can be used for both selection of the recording element and selection of the anti-fuse element.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] However, in the example described in Patent Document 1, it is necessary to select either a recording element mode or an antifuse element mode. And at least one bit of signal data is required for this selection. As a result, there was a problem that the amount of signal data increased each time a recording element or antifuse element was selected.

[0006] In particular, with printing that uses recording elements, an increase in the amount of signal data leads to an increase in the time required to select the recording element, resulting in a problem of reduced printing speed.

[0007] The object of the present invention is to solve at least one of the problems of the prior art described above.

[0008] The object of the present invention is to provide a technique for suppressing the increase in the amount of data supplied to the element substrate in order to select a recording element during recording operation. [Means for solving the problem]

[0009] To achieve the above objective, an element substrate according to one aspect of the present invention has the following configuration. That is, Multiple recording elements, A recording element drive element for driving the aforementioned recording element, A logical AND circuit for selecting a recording element to be driven by the aforementioned recording element drive element, Multiple memory elements, A memory element drive element for driving the aforementioned memory element, A logical AND circuit for selecting a memory element to be driven by the aforementioned memory element driver element, Control data supply circuit, In an element substrate having, The control data supply circuit is A multi-stage shift register that holds serial data signals, A latch circuit that latches the serial data signal held in the shift register, A decoder circuit that outputs a selection signal for selecting either the recording element or the memory element, the Latch circuit and a mask circuit connected thereto, The mask circuit is input to the mask circuit Rubi bit data signal If it is a predetermined signal and The output of the shift register is output to the latch circuit, If the bit data signal is not the predetermined signal, the output of the shift register is masked. The latch circuit is When the output of the shift register is output from the mask circuit, the output of the shift register is used as the output selection signal for the decoder circuit. and outputs to the decoder circuit. The device substrate is characterized by this.

Advantages of the Invention

[0010] According to the present invention, it becomes possible to suppress an increase in the amount of data supplied to the device substrate in order to select a recording element during a recording operation.

[0011] Other features and advantages of the present invention will become apparent from the following description with reference to the accompanying drawings. In the accompanying drawings, the same or similar configurations are given the same reference numerals.

Brief Description of the Drawings

[0012] The accompanying drawings are included in the specification, form a part thereof, show embodiments of the present invention, and are used to explain the principles of the present invention together with the description. [Figure 1] A diagram showing a part of the circuit configuration of a recording element substrate according to an embodiment. [Figure 2] I A circuit diagram for explaining the configuration of a memory module used for a substrate according to an embodiment. [Figure 3] A diagram schematically showing an example of a cross-sectional structure of a part of a substrate corresponding to a capacitance element Ca and a driving element MD2 for a memory element according to an embodiment. [Figure 4] A plan view of a recording element substrate according to Embodiment I of the present invention. [Figure 5] A plan view of a recording element substrate according to Embodiment 2 of the present invention. [Figure 6]A diagram for explaining an inkjet recording apparatus, a recording head unit, and a recording head according to an embodiment of the present invention. [Figure 7] A diagram showing an example of the circuit configuration of the control data supply circuit 201 according to Embodiment 1. [Figure 8] A diagram showing an example of the circuit configuration of the control data supply circuit 201b according to Embodiment 1. [Figure 9] A block diagram showing the schematic configuration of a recording apparatus according to an embodiment. [Figure 10] Flowchart (A) for explaining the process of controlling the recording head when the recording apparatus according to Embodiment 1 performs recording processing for one line, and flowchart (B) for explaining the process of controlling the recording head when the recording apparatus according to Embodiment 1 performs access processing to the memory module.

Mode for Carrying Out the Invention

[0013] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Note that the following embodiments do not limit the invention according to the claims. Although a plurality of features are described in the embodiments, not all of these plurality of features are essential for the invention, and the plurality of features may be arbitrarily combined. Further, in the accompanying drawings, the same or similar configurations are denoted by the same reference numerals, and redundant descriptions are omitted.

[0014] Note that "recording" includes not only the case of forming significant information such as characters and figures, but also the case of forming an image, pattern, pattern, etc. on a recording medium widely, regardless of whether it is significant or not, or performing processing on the medium, regardless of whether it is manifested so that a human can perceive it visually. Also, in this embodiment, a sheet-like paper is assumed as the "recording medium", but it may be cloth, plastic film, or the like.

[0015] FIG. 6 is a diagram for explaining an inkjet recording apparatus 1000, a recording head unit 20, and a recording head 10 according to an embodiment of the present invention.

[0016] Figure 6(a) is a schematic perspective view of the inkjet recording apparatus 1000 according to an embodiment. As shown in Figure 6(a), the lead screw 5004 rotates via drive force transmission gears 5008 and 5009 in conjunction with the forward and reverse rotation of the drive motor 5013. The carriage HC is capable of mounting the recording head unit 20 and has a pin (not shown) that engages with the helical groove 5005 of the lead screw 5004, and moves back and forth in the directions of arrows a and b in the figure as the lead screw 5004 rotates.

[0017] Figure 6(b) is a perspective view showing an example of a recording head unit 20 equipped with a recording head 10 according to this embodiment.

[0018] The recording head unit 20 comprises a recording head 10 and a housing section 24 that houses the recording agent (liquid; ink) supplied to the recording head 10, and these together constitute a cartridge. Here, the recording head 10 is located on the surface facing the recording medium P shown in Figure 6(a). Note that these do not necessarily have to be integrated, and the housing section 24 can be detachable. The recording head unit 20 also includes a tape member 22. This tape member 22 has terminals for supplying power to the recording head 10, and receives power from the main body of the inkjet recording device 1000 via contacts 23, and also exchanges various signals.

[0019] Figure 6(c) is a schematic perspective view of the recording head 10 according to this embodiment.

[0020] The recording head 10, which functions as a liquid ejection head, comprises a recording element substrate 11 and a flow channel forming member 120. The recording element substrate 11 is provided with a plurality of thermal action sections 117 arranged in a row for transferring thermal energy generated by an electrothermal conversion element to the recording material. The flow channel forming member 120 is also an ejection port member, with a plurality of ejection ports 121 for ejecting the recording material arranged in a row corresponding to the thermal action sections 117. Power and signals are sent from the main body of the recording device 1000 to the recording element substrate 11 via the tape member 22, the thermal energy generated by driving the electrothermal conversion element is transferred to the recording material (liquid) via the thermal action sections 117, and the recording material is ejected from the ejection ports 121.

[0021] Figure 9 is a block diagram showing a schematic configuration of the recording device 1000 according to this embodiment.

[0022] The controller 900 controls the operation of the recording device 1000. The controller 900 has a CPU 901, RAM 902, ROM 903, and an input / output interface (I / OI / F) 904. The CPU 901 reads the program stored in the ROM 903 and executes the program, thereby executing the processes shown in the flowchart described later. The CPU 901 also controls various operations of the recording device 1000, such as the printing process. The input / output interface (I / OI / F) 904 is connected to a motor driver 905 that rotates the aforementioned transport motor 5013. In addition to these, the recording device 1000 according to this embodiment also has an operation panel, various sensors, a paper feed unit, etc., but these are omitted here.

[0023] Next, with reference to Figures 1 to 3, the circuit configurations of the ejection module and memory module mounted on the recording element substrate 11 (hereinafter also simply referred to as "substrate 11") as a semiconductor substrate according to an embodiment of the present invention will be described.

[0024] Figure 1 shows a part of the circuit configuration of the recording element substrate 11 according to the embodiment.

[0025] The substrate 11 includes an ejection module 204 and a memory module 206. The ejection module 204 includes a recording element Rh (for example, an electrical-to-thermal conversion element that generates heat when energized), a driving element (transistor) MD1 for driving the recording element Rh, and a logical AND circuit AND1 for selecting the recording element. When the output of the logical AND circuit AND1 becomes high level, the driving element MD1 is turned on, energizing and driving the recording element Rh, so that a recording material such as ink is ejected from the ejection port 121 and recording can be performed.

[0026] The memory module 206 also includes an antifuse element AF as a memory element, a drive element MD2 for the memory element to write information to the antifuse element AF, and a logical AND circuit AND2 for selecting the memory element. The antifuse element AF permanently holds information when an overvoltage is supplied and functions as a memory that can be programmed only once.

[0027] The driving of the recording element Rh and the antifuse element AF is controlled based on logic data signals transmitted from the control data supply circuit 201, which acts as a signal supply circuit. The control data supply circuit 201, as detailed below with reference to Figure 7, includes a first shift register circuit 501, a second shift register circuit 502, latch circuits 503 and 504, a data mask circuit 505, a decoder circuit 506, and the like. Logic data signals such as the clock signal CLK, serial data signal DATA1, bit data signal DATA2 for antifuse switching, latch signal LT, and recording element control signal HE (heat enable signal: not shown) can be input to this control data supply circuit 201 via the recording device 1000 main unit or a host PC (not shown). Furthermore, the logic AND circuit AND1, logic AND circuit AND2, and the control data supply circuit 201 are supplied with a first power supply voltage VDD (e.g., 3-5V) as the power supply voltage for the logic.

[0028] Here, the control data supply circuit 201 selects one of the output modules 204 in a predetermined order for each of the m groups, each having n output modules 204, and drives the recording element Rh (so-called time-division drive). The control data supply circuit 201 outputs an m-bit group selection signal 210 and an n-bit block selection signal 211. Each output module 204 receives at least one bit of the group selection signal 210 and at least one bit of the block selection signal 211, thereby driving the recording element Rh in a time-division manner.

[0029] Furthermore, the control data supply circuit 201 controls the memory modules 206 for each of the y groups, each having x memory modules 206, to perform time-division driving control of the antifuse elements AF. Specifically, the antifuse elements AF are controlled by time-division driving when each memory module 206 receives at least one bit each of the group selection signal 210 and the block selection signal 212. At this time, the ejection module 204 and the memory modules 206 are driven exclusively, and the logic is configured so that not all recording elements Rh and all antifuse elements AF are driven at the same time (details will be described later).

[0030] The AND1 logic AND circuit for selecting recording elements receives the corresponding group selection signal 210, block selection signal 211, and recording element control signal HE. When the output of the AND1 logic AND circuit turns on in response to the input signals, the corresponding recording element drive element MD1 becomes conductive, and the recording element Rh connected in series with the recording element drive element MD1 is driven.

[0031] Here, for the drive element MD1 for the recording element, for example, a high-voltage MOS transistor such as a DMOS transistor (Double-diffused MOSFET) is used. In the case of antifuse memory, generally, the drive current for the memory element is smaller than the drive current for the recording element, and therefore the current driving capability of the DMOS transistor can be smaller. Consequently, the area of ​​the drive element MD2 for the memory element may be smaller than the area of ​​the drive element MD1 for the recording element.

[0032] Furthermore, a MOS transistor, for example, is used as the AND1 logic circuit for selecting the recording element. Here, the output module 204 is supplied with a second power supply voltage VH (for example, 24V) as the power supply voltage for driving the recording element, and the ground potential is set to GNDH.

[0033] Furthermore, the AND2 logic AND circuit for memory selection receives the corresponding group selection signal 210, block selection signal 212, and memory element control signal ME (not shown). A signal corresponding to the input signals is output to the memory element drive element MD2, and the conduction / non-conduction state of the drive element MD2 is switched. Similar to the recording element drive element MD1, a DMOS transistor is used for the memory element drive element MD2. A MOS transistor is also used for the AND2 logic AND circuit for memory element selection. The memory module 206 is supplied with a third power supply voltage VID (e.g., 24V) for writing information to the antifuse element AF, and the ground potential is set to GNDH. As shown in Figure 1, the recording element drive element MD1 and the memory element drive element MD2 may be configured to be connected to a common GNDH pad via a common ground wire.

[0034] Although power supply voltages VID and VH are independent power supply lines, if the minimum voltage required to write to the antifuse element AF is less than or equal to power supply voltage VH, power supply voltage VH may be used, for example, in combination with a step-down circuit.

[0035] Figure 2 is a circuit diagram illustrating the configuration of a memory module 206 used in the substrate 11 according to this embodiment.

[0036] Here, the AND gate for memory selection, AND2, is composed of a NAND gate 306 and an inverter INV. The inverter INV has a PMOS transistor MP1 and an NMOS transistor MN1, with MOSFETs used for transistors MP1 and MN1. The output signal Sig from the NAND gate 306 is input to the inverter INV, and the output signal Vg from the AND gate AND2 is output to the gate of the memory drive element MD2. Note that Figure 2 shows the arrangement of the drive element MD2 and the AND gate AND2 as shown in Figure 1, but with the left and right reversed.

[0037] Before information is written to it, the antifuse element AF functions as a capacitive element Ca, for example. Figure 2 shows the state of the antifuse element AF before information is written to it, and the antifuse element AF is represented as a capacitive element Ca. Similarly, in other figures, the antifuse element AF may also be shown as a capacitive element Ca.

[0038] Thus, the capacitive element Ca, acting as an antifuse element AF, is connected in series with the memory drive element MD2 at one end. The power supply voltage VID is supplied to the other end of the capacitive element Ca when reading or writing information.

[0039] Furthermore, the device includes a resistor (with resistance value Rp, hereafter simply referred to as "resistor Rp") connected in parallel with the antifuse element AF. This prevents a situation where, even though the drive element MD2 for the memory element is in a non-conductive state, an overvoltage is applied across the antifuse element AF, causing information to be erroneously written to the antifuse element AF.

[0040] Figure 3 is a schematic diagram showing an example of the cross-sectional structure of the substrate 11 in the portion corresponding to the capacitive element Ca and the drive element MD2 for the memory element according to the embodiment.

[0041] For example, a P-type well region 101 and N-type well regions 102a and 102b are formed on a P-type silicon substrate 100. The P-type well region 101 can be formed simultaneously in the process of forming the P-type well of the NMOS transistor MN1, and this P-type well and the P-type well region 101 have similar impurity concentration distributions. The same applies to the relationship between the N-type well regions 102a and 102b and the N-type well of the PMOS transistor MP1. When the breakdown voltage VB is the PN junction between the N-type well regions 102a and 102b and the P-type silicon substrate 100, VB > VID is set so that breakdown does not occur at the PN junction when writing information. Therefore, it is preferable to form the N-type well regions 102a and 102b considering their respective impurity concentrations.

[0042] Reference numeral 103 indicates a field oxide film having a LOCOS structure. The gate oxide film 104 is formed simultaneously with the formation of the gate insulating films of transistors MP1 and MN1. The gate electrode 105a of the memory drive element MD2 and the electrode 105b of the capacitive element Ca used as the antifuse element AF are each formed from polysilicon. These are formed simultaneously with the formation of the gate electrodes of transistors MP1 and MN1. Similarly, the high-concentration N-type diffusion regions 106a to 106c and the high-concentration P-type diffusion region 107 are formed simultaneously with the formation of the high-concentration diffusion regions for the drain, source, and bulk of transistors MP1 and MN1. Reference numeral 108 indicates a contact portion, and reference numerals 109a to 109d indicate metal wiring. Note that the manufacturing method and structure of the metal wiring 109a to 109d and each electrode are not limited as long as they are electrically connected.

[0043] Next, we will explain the configuration of a high-voltage NMOS transistor.

[0044] The gate electrode 105a is positioned on adjacent P-well regions 101 and N-well regions 102a via a gate oxide film 104. The overlapping region of the P-well region 101 and the gate electrode 105a forms the channel region. The high-concentration N-type diffusion region 106a is the source electrode, and the high-concentration P-type diffusion region 107 is the back gate electrode. The N-well region 102a, which extends to the bottom of the gate electrode 105, is positioned as the electric field relaxation region of the drain. The high-concentration N-type diffusion region 106b formed within the N-well region 102a becomes the drain electrode. Furthermore, the drain side of the gate electrode 105a has a structure that rides on top of the field oxide film 103 formed in the N-well region 102a, a so-called LOCOS offset structure.

[0045] This ensures that the gate-drain breakdown voltage is maintained even when the high-voltage NMOS transistor is in the off state, i.e., when the gate electrode voltage is at GND and the drain electrode voltage rises to the high voltage VID.

[0046] Next, we will explain the structure of the antifuse element AF.

[0047] The electrode 105b is positioned on the N-well region 102b via the gate oxide film 104, serving as the upper electrode of the antifuse element AF, while the high-concentration N-type diffusion region 106c serves as the lower electrode.

[0048] In Figure 2, a high-concentration N-type diffusion region 106c is formed only at the opening of the upper electrode, but a high-concentration N-type diffusion region may be formed over the entire lower area of ​​the upper electrode. Furthermore, in Figure 2, the lower electrode of the antifuse element AF is connected to the drain of the high-voltage NMOS transistor, but the upper electrode may be connected to the drain of the high-voltage NMOS transistor and the lower electrode may be connected to the high-voltage VID.

[0049] Note that while Figure 2 shows capacitance formed by the N-well region and polysilicon, capacitance using PMOS transistors is also acceptable.

[0050] Next, we will explain the connection status of each electrode.

[0051] Metal wiring 109a is connected to the source electrode and back gate electrode of the high-voltage NMOS transistor via contact portion 108, and is supplied with a GND potential. Metal wiring 109b is connected to the gate electrode of the high-voltage NMOS transistor via contact portion 108, and the output signal Vg of the inverter circuit INV shown in Figure 1 is input to it. Metal wiring 109c is connected to the drain electrode of the high-voltage NMOS transistor MD1 and the lower electrode of the antifuse element AF via contact portion 108. Metal wiring layer 109d is connected to the upper electrode of the antifuse element AF via contact portion 108, and is supplied with the high voltage VID during writing.

[0052] Next, we will explain the operation when writing to the antifuse element AF.

[0053] To write information to the antifuse element AF, the output signal Sig of the NAND circuit 306 is set to a low level, thereby turning on the memory driver element MD2. This applies a high voltage VID to the gate oxide film that constitutes the antifuse element AF. This destroys the gate oxide film, and the information is written to the antifuse element AF. In other words, before writing, the antifuse element AF was a capacitive element Ca, while after writing, it becomes a resistive element.

[0054] Methods for reading the information written to this antifuse element AF include measuring the change in the impedance of the antifuse element AF.

[0055] The information recorded in the antifuse element AF is product-specific information such as the chip ID and setting parameters, and this information is written at the factory using inspection equipment or the like when the product is shipped. Alternatively, if the information is written to the element by the user after the product is put into use, a voltage equivalent to the high voltage VID is supplied from the main unit of the product.

[0056] [Embodiment 1] Based on the above premises, embodiments 1 and 2 of the present invention will be described.

[0057] Figure 7 shows an example of the circuit configuration of the control data supply circuit 201 according to Embodiment 1.

[0058] The control data supply circuit 201 includes the first shift register circuit 501, the second shift register circuit 502, latch circuits 503 and 504, data mask circuit 505, decoder circuit 506, etc., as described above. Logical data signals such as the clock signal CLK for transferring data from the shift register circuits 501 and 502, signal DATA1, signal DATA2, LT for inputting the latch signal, and control signals for recording elements (not shown) are input to the input side of the control data supply circuit 201. Signals such as the group selection signal 210, the block selection signal 211 for selecting recording elements, and the block selection signal 212 for selecting memory elements are output to the output side of the control data circuit 201.

[0059] The first shift register circuit 501 is composed of multiple registers, while the second shift register circuit 502 is composed of a single register. The first shift register circuit 501 is serially connected to the second shift register circuit 502, and the serial data input signal DATA1 is first input to the first shift register circuit 501, output from the first shift register circuit 501, and input to the second shift register circuit 502.

[0060] Furthermore, the output of each register in the first shift register circuit 501 is connected to the corresponding first latch circuit 503, which receives the output of each register in the first shift register circuit 501 in parallel. Similarly, the output of the first bit of the second shift register circuit 502 is connected to the second latch circuit 504 via the data mask circuit 505.

[0061] The decoder circuit 506 also receives the output of a portion of the latch circuit of the first latch circuit 503 and the output from the second latch circuit 504. The data mask circuit 505 sends the output of the second shift register circuit 502 to the second latch circuit 504 only when the signal DATA2 is a high-level signal. When that output is latched by the second latch circuit 504, the output of the second latch circuit 504 is output as the output selection signal of the decoder circuit 506. When the output of the second latch circuit 504, i.e., the output selection signal, is high-level, the decoder circuit 506 outputs a block selection signal 212 for memory element selection.

[0062] On the other hand, when the signal DATA2 is a low-level signal, the output of the second shift register circuit 502 is not sent to the second latch circuit 504 via the data mask circuit 505. Therefore, in this case, the output selection signal is not output to the decoder circuit 506 at a high level from the second latch circuit 504, and the decoder circuit 506 outputs the block selection signal 211 for selecting the recording element.

[0063] In other words, when using recording elements for printing, regardless of whether the signal from the second shift register circuit 502 is received or not, setting the signal DATA2 to a low level masks the output of the second shift register circuit 502 by the data mask circuit 505. As a result, the block selection signal 211 for the recording element is automatically output, and the recording element is selected. Therefore, during printing, the recording element can be selected using only the first shift register circuit 501. Consequently, compared to conventional examples, it is possible to suppress the increase in the amount of data associated with the selection of recording elements.

[0064] In Figure 7, one second shift register circuit 502, one data mask circuit 505, and one second latch circuit 504 are provided. However, multiple second shift register circuits 502, data mask circuits 505, and second latch circuits 504 may be provided and used to switch between modes such as reading and writing to memory elements.

[0065] Figure 4 is a plan view of the recording element substrate 11 according to Embodiment 1 of the present invention.

[0066] This circuit board 11 has input terminals for inputting a latch signal (LT), a clock input terminal for inputting a shift clock signal (CLK), a data input terminal for inputting serial data signals (DATA1, DATA3), and an input terminal for inputting a bit data signal (DATA2).

[0067] This substrate 11 includes multiple groups of recording element modules and multiple groups of memory element modules. The recording element module includes a recording element Rh, a drive element MD1 for energizing and driving the recording element, and a logical AND circuit AND1 for selecting the recording element. The memory element module includes an antifuse element AF (also shown as a "capacitive element Ca" in Figure 4) as a memory element, a drive element MD2 for the memory element, and a logical AND circuit AND2 for selecting the memory element.

[0068] Furthermore, a common logic bus wiring 402 (common wiring) is provided that can supply signals from the control data supply circuit 201a to the AND1 and AND2 logic AND circuits. The control data supply circuit 201a is the same circuit as the one shown in Figure 7. In Embodiment 1, the common logic bus wiring 402 includes a group selection signal 210, a block selection signal 211 for recording element selection, and a block selection signal 212 for memory element selection, all of which are output from the control data supply circuit 201 as described with reference to Figure 1.

[0069] First, let's explain the arrangement of elements and circuits on the substrate 11.

[0070] The substrate 11 is provided with a supply port 408 for supplying ink as a recording medium, which extends in the longitudinal direction of the substrate 11. Along the extension direction of this supply port 408, a recording element array 4041 is provided, which consists of multiple recording elements Rh arranged in at least one row. In addition, a recording element drive element array 4042 is provided adjacent to the recording element array 4041 on the side opposite to the side where the supply port 408 is provided, and which consists of recording element drive elements MD1 corresponding to each recording element Rh. Furthermore, a recording element selection logic AND circuit array 4043 is provided adjacent to the drive element array 4042, which consists of recording element selection logic AND circuits AND1 corresponding to each recording element Rh. In Embodiment 1, the recording element array 4041, the drive element array 4042, and the logic AND circuit array 4043 extend along the Y direction shown in Figure 4.

[0071] Similarly, the substrate 11 is provided with an antifuse element array 4061 (memory element array) composed of multiple antifuse elements AF (capacitive elements Ca) arranged along the direction of the recording element array 4041. This antifuse element array 4061 is provided near the edge of the substrate 11. Adjacent to the antifuse element array 4061 is a resistor element array 4064 composed of resistor elements Rp corresponding to each antifuse element AF. Furthermore, adjacent to the resistor element array 4064 is a drive element array 4062 composed of drive elements MD2 for memory elements corresponding to each antifuse element AF. Furthermore, adjacent to the drive element array 4062 is a logic circuit array 4063 composed of logic circuits AND2 for memory element selection corresponding to each antifuse element AF.

[0072] Furthermore, the common logic bus wiring 402 described above is provided between the recording element array 4041 and the output module array 704, which includes arrays of elements and circuits for recording elements, and the memory element array and the memory module array 706, which includes arrays of elements and circuits for memory elements. In Embodiment 1, the common logic bus wiring 402 extends along the direction of the recording element array 4041. The logic circuit array 4043 for recording elements and the logic circuit array 4063 for memory elements extend along the direction of the common logic bus wiring 402. In other words, the common logic bus wiring 402, the logic circuit array 4043 for recording elements, and the logic circuit array 4063 for memory element arrays extend along the Y direction in Figure 4. The logic circuit array 4063 for memory element arrays, the common logic bus wiring 402, and the logic circuit array 4043 for recording element arrays are arranged in this order from left to right in the X direction in Figure 4. Furthermore, the control data supply circuit 201 (201a) is located at the end of the substrate 11 in the Y direction.

[0073] Furthermore, the circuit board 11 is provided with a recording element array 4041, a drive element array 4042, and a logic circuit array 4043 on each side (in the X direction) of the supply port 408. An antifuse element array 4061 is provided in one row on one side of the supply port 408. Therefore, one of the two recording element arrays 4041 (the left side in Figure 4) also serves as the antifuse element array 4061 and the common logic bus wiring 402.

[0074] On the other hand, the other recording element array 4041 (right side in Figure 4) is connected to the control data supply circuit 201b via a logic bus wiring 403 dedicated to the recording element array. This logic bus wiring 403 dedicated to the recording element array includes a group selection signal 210 and a block selection signal 211 for selecting recording elements. It should be noted that the recording element array 4041, the drive element array 4042, and the logic circuit array 4043 may be provided on only one side of the supply port 408.

[0075] Figure 8 shows an example of the circuit configuration of the control data supply circuit 201b according to Embodiment 1.

[0076] In the control data supply circuit 201b, the signal DATA2 and mask circuit 505 shown in Figure 7 are omitted, and the decoder circuit 506 outputs only the block selection signal 211 for selecting the recording element.

[0077] The configuration of the control data supply circuits 201a and 201b according to Embodiment 1 is as described above with reference to Figures 7 and 8, but here we will mainly describe the operation of the circuits.

[0078] In the example shown in Figure 7, the decoder circuit 506 acts as a multiplexer, inputting a multi-bit signal, in this case a 4-bit signal, decoding it, and outputting 16 selection signals. When the output of the second latch circuit 504 is low, it outputs a selection signal 211 to select a group of recording elements, and when the output of the second latch circuit 504 is high, it outputs a selection signal 212 to select a group of memory elements. In the example shown in Figure 7, there are 5 blocks each of recording elements and memory elements, and each block contains 16 elements.

[0079] Furthermore, in Figure 8, the second latch circuit 504, data mask circuit 505, second shift register circuit 502, block selection signal 212 for memory element selection, and signal DATA2 from Figure 7 are absent.

[0080] Figure 10(A) is a flowchart illustrating the process by which the recording device 1000 according to Embodiment 1 controls the control data supply circuit 201a when performing recording processing for one line. The process shown in this flowchart is achieved by the CPU 901 reading and executing a program stored in the ROM 903. The process for controlling the control data supply circuit 201b is the same as the conventional process, so its explanation is omitted.

[0081] First, in S1001, the CPU 901 sets DATA2 to a low level. Next, in S1002, the CPU 901 outputs a 10-bit serial signal to DATA1, synchronized with the CLK signal. Then, in S1003, it outputs a latch signal LT, latching the 10-bit data set in the first shift register circuit 501 into the first latch circuit 503. However, since DATA2 is low at this time, the data from the second shift register circuit 502 is not latched into the second latch circuit 504. At this time, the upper 2-6 bits are used to select one group of recording elements, and the lower 7-10 bits are used to select a block of recording elements included in the group selected by the upper bits. This determines the recording elements to be driven by the recording operation. Then, in S1004, the image data to be printed at that time is output. Then, in S1005, the CPU 901 outputs a recording element control (heat enable (HE)) signal to the recording head 20 to drive the recording elements. This ensures that a single drive of a recording element simultaneously drives a number of recording elements corresponding to the maximum number of groups. The process then proceeds to S1006, where it is determined whether, for example, the output of one line of image data has finished. If not, the process returns to S1002 and the aforementioned processing is executed.

[0082] Figure 10(B) is a flowchart illustrating the process by which the recording device 1000 according to Embodiment 1 controls the control data supply circuit 201a when performing access processing to a memory module. The process shown in this flowchart is achieved by the CPU 901 reading and executing a program stored in the ROM 903. Note that the control data supply circuit 201b is not used in the case of memory module access processing.

[0083] First, at S1011, the CPU 901 sets DATA2 to high level. Next, at S1011, the CPU 901 outputs a 10-bit serial signal to DATA1, synchronized with the CLK signal. However, in this case, the first bit of the 10-bit serial signal is set to high level. Then, at S1012, the latch signal LT is output, latching the 10-bit data set in the first shift register circuit 501 into the first latch circuit 503. However, since DATA2 is high level at this time, the high-level data ("1") from the second shift register circuit 502 is latched into the second latch circuit 504. At this time, the upper 2-6 bits are used to select one group of memory elements, and the lower 7-10 bits are used to select a block of memory elements included in the group selected by the upper bits. This determines the memory element to be read or written to. Then, at S1013, the memory control signal is output, making it possible to write or read data to or from that memory element. Then, proceeding to S1005, the CPU 901 determines whether the writing or reading of data to or from the memory element has finished. If it determines that it has finished, it terminates this process; otherwise, it returns to S1011 and executes the aforementioned process.

[0084] In Embodiment 1, for example, there are 5 memory blocks, and each block contains 16 memory elements. Therefore, when the CPU 901 of the recording device 1000 accesses a memory element, it sets DATA2 to a high level and outputs a 10-bit serial signal with the leading bit set to "1" to DATA1, synchronized with the CLK signal. It then outputs a latch signal LT to latch the 10-bit data set in the first shift register circuit 501 into the first latch circuit 503. However, since DATA2 is high at this time, the data from the second shift register circuit 502 is latched into the second latch circuit 504. At this time, the upper 2 to 6 bits are used to select one group of memory elements, and the lower 7 to 10 bits are used to select a block of memory elements included in the group selected by the upper bits.

[0085] As explained above, according to Embodiment 1, when recording elements are used for printing, the output of the second shift register circuit 502 is masked by the signal DATA2 and not sent to the decoder circuit. Therefore, when the signal DATA2 is at a low level, the decoder circuit always outputs a selection signal to select a block of recording elements. Consequently, compared to the conventional example, there is an effect of reducing the number of bits in the signal used to select the recording elements.

[0086] [Embodiment 2] Figure 5 is a plan view of the recording element substrate 11 according to Embodiment 2 of the present invention.

[0087] In the recording element substrate shown in Figure 4 according to the above-described embodiment 1, the control data supply circuit 201a used the signal DATA2 for image data.

[0088] In contrast, in Embodiment 2, the signal DATA4 for image data used in the control data supply circuit 201b is supplied to the control data supply circuit 201a as the aforementioned DATA2. As a result, in the board 11 according to Embodiment 2, the output of the selection signal for the recording element block from the control data supply circuit 201a is prohibited (masked) by a single signal DATA4.

[0089] Thus, according to Embodiment 2, the number of signal lines input to the element substrate can be reduced from two to one, that is, from signals DATA3 and DATA2 in Figure 4 to just signal DATA4, thereby reducing the number of electrode pads on the substrate. Alternatively, the remaining electrode pads can be used for other purposes.

[0090] (Other embodiments) The present invention can also be realized by supplying a program that implements one or more of the functions of the above-described embodiments to a system or device via a network or storage medium, and by having one or more processors in the computer of that system or device read and execute the program. It can also be realized by a circuit (e.g., an ASIC) that implements one or more functions.

[0091] The present invention is not limited to the embodiments described above, and various modifications and variations are possible without departing from the spirit and scope of the invention. Accordingly, the following claims are attached to make the scope of the invention public. [Explanation of Symbols]

[0092] 201...Control data supply circuit, 210...Group selection signal, 211...Block selection signal for recording element selection, 212...Block selection signal for memory element selection, 501...First shift register circuit, 502...Second shift register circuit

Claims

1. Multiple recording elements, A recording element drive element for driving the aforementioned recording element, A logical AND circuit for selecting a recording element to be driven by the aforementioned recording element drive element, Multiple memory elements, A memory element drive element for driving the aforementioned memory element, A logical AND circuit for selecting a memory element to be driven by the aforementioned memory element driver element, Control data supply circuit, In an element substrate having, The control data supply circuit is A multi-stage shift register that holds serial data signals, A latch circuit that latches the serial data signal held in the shift register, A decoder circuit that outputs a selection signal to select either the recording element or the memory element, The latch circuit and the mask circuit connected thereto The aforementioned mask circuit is If the bit data signal input to the mask circuit is a predetermined signal, the output of the shift register is output to the latch circuit. If the bit data signal is not the predetermined signal, the output of the shift register is masked. The latch circuit is The element substrate is characterized in that, when the output of the shift register is output from the mask circuit, the output of the shift register is output to the decoder circuit as an output selection signal for the decoder circuit.

2. The element substrate according to claim 1, characterized in that the recording element or the group of memory elements is selected by a portion of the output of the latch circuit, and the selection signal for selecting the block of recording elements or memory elements is a 1-bit signal obtained by decoding a portion of the remaining output of the latch circuit with the decoder circuit.

3. The element substrate according to claim 1, characterized in that the bit data signal is a 1-bit data signal input via a data input terminal.

4. The element substrate according to any one of claims 1 to 3, further comprising a clock input terminal for inputting a shift clock signal to be input to the shift register, which receives the serial data signal.

5. The element substrate according to claim 1, further comprising an input terminal for inputting a latch signal that causes the serial data signal to be latched by the latch circuit.

6. The element substrate according to claim 1, characterized in that when the mask circuit masks the output of the shift register, the decoder circuit outputs a selection signal to select a block of the recording element.

7. The device substrate according to any one of claims 1 to 6, characterized in that the decoder circuit includes a multiplexer that receives a data signal of multiple bits and outputs a selection signal of each single bit obtained by decoding the data signal of multiple bits.

8. The element substrate according to any one of claims 1 to 7, characterized in that the recording element comprises an electrical-to-thermal conversion element that generates heat when energized, a first transistor that energizes and drives the electrical-to-thermal conversion element, and a logic circuit that controls the driving of the first transistor by receiving a block selection signal of the recording element, a group selection signal of the recording element, and a control signal of the recording element.

9. The element substrate according to any one of claims 1 to 8, characterized in that the memory element comprises an antifuse element that writes or reads information by energizing, a second transistor that energizes the antifuse element, and a logic circuit that controls the driving of the second transistor by receiving a block selection signal of the memory element, a group selection signal of the memory element, and a control signal of the memory element.

10. A liquid dispensing head characterized by having an element substrate according to any one of claims 1 to 9.

11. A recording device characterized by performing recording using the liquid discharge head described in claim 10.

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