Pipeline successive approximation analog-to-digital converters, integrated circuits, and electronic devices

Abstract

We provide pipeline successive approximation analog-to-digital converters, integrated circuits, and electronic devices. [Solution] The pipeline successive approximation analog-to-digital converter includes a first-stage successive approximation analog-to-digital converter 10, an interstage gain amplifier 30, a second-stage successive approximation analog-to-digital converter 20, and a digital encoding unit 40.

Description

[Technical Field]

[0001] This application is filed pursuant to a Chinese patent application with application number 202111407728.2 and filing date November 24, 2021, claiming priority from said Chinese patent application, and all its contents are incorporated herein by reference.

[0002] This application relates to the field of integrated circuit technology, and more particularly to pipeline successive approximation analog-to-digital converters, integrated circuits, and electronic devices. [Background technology]

[0003] Pipelined successive approximation register analog to digital converters (Pipelined SAR ADCs) are widely applied in various analog-to-digital conversion scenarios due to their high speed and high accuracy. A pipelined SAR ADC generally includes at least two stages of SAR ADCs, each stage containing a digital-to-analog converter (DAC), a comparator, and a SAR control logic unit. An interstage gain amplifier is provided between the DACs of two adjacent SAR ADC stages to amplify the sampling residual signal from the preceding SAR ADC and transmit it to the succeeding SAR ADC. In deep submicron CMOS technology, the intrinsic gain of transistors gradually decreases, making it difficult for the interstage gain amplifier to achieve high-gain linear amplification. To address this technical challenge, conventional technology proposes reducing the reference voltage in the succeeding ADC to half the reference voltage in the preceding ADC, thereby realizing a two-stage interstage gain halving technique and reducing the gain of the interstage gain amplifier. However, halving the reference voltage significantly reduces the ADC's conversion speed and power consumption. [Overview of the Initiative] [Problems that the invention aims to solve]

[0004] Embodiments of the present application provide a pipeline successive approximation analog-to-digital converter, an integrated circuit, and electronic equipment. [Means for solving the problem]

[0005] In a first embodiment, the embodiment of the present application is a first-stage successive approximation analog-to-digital converter comprising a sequentially connected first digital-to-analog converter, a first comparator, and a first digital control logic unit, wherein the first digital-to-analog converter includes a first capacitance array, the first capacitance array includes one first compensation capacitor and an M-bit first capacitor, the first end of each of the first capacitors being connected to an analog input voltage, and the second end of each of the first capacitors being connected to a forward reference voltage and a negative reference voltage via a multiple selection switch, respectively, and the first compensation capacitor A second-stage successive approximation analog-to-digital converter includes a first-stage successive approximation analog-to-digital converter, an interstage gain amplifier whose input terminal is connected to the residual voltage output from the first digital-to-analog converter, a second digital-to-analog converter connected sequentially, a second comparator, and a second digital control logic unit. An analog-to-digital converter, wherein the second digital-to-analog converter includes a second capacitance array, the second capacitance array includes one gain-half capacitor, one second compensation capacitor, and an N-1 bit second capacitor, the gain-half capacitor, the second compensation capacitor, and the first terminals of each of the second capacitors are connected to the output terminals of the interstage gain amplifier, respectively, the second terminals of each of the second capacitors are connected to a forward reference voltage and a negative reference voltage via a multiple selection switch, the second terminals of the gain-half capacitor and the second compensation capacitor are connected to the negative reference voltage, and the capacitance value of the second compensation capacitor is A pipeline successive approximation type analog-to-digital converter is provided, comprising a second-stage successive approximation type analog-to-digital converter, wherein the capacitance value of the N-1 bit second capacitance is equal to the capacitance value of the first capacitance among the N-1 bit second capacitances, the capacitance value of the N-1 bit second capacitance increases in powers of 2 in order from the smallest number of bits to the largest number of bits, the capacitance value of the gain-half capacitance is the sum of the capacitance values ​​of the N-1 bit second capacitance and the second compensation capacitance, and N is an integer greater than 1; and a digital encoding unit connected to the output terminals of the first digital control logic unit and the second digital control logic unit.

[0006] In a second aspect, an embodiment of the present application provides an integrated circuit including the pipeline successive comparison type analog-to-digital converter described in the first aspect above.

[0007] In a third aspect, an embodiment of the present application provides an electronic device including the integrated circuit described in the second aspect above.

Brief Description of the Drawings

[0008] [Figure 1] FIG. 1 is a schematic frame diagram of a pipeline successive comparison type analog-to-digital converter provided by an embodiment of the present application. [Figure 2] FIG. 2 is a schematic circuit structure diagram of a first-stage successive comparison type analog-to-digital converter provided by an embodiment of the present application. [Figure 3] FIG. 3 is a schematic circuit structure diagram of a second-stage successive comparison type analog-to-digital converter provided by an embodiment of the present application. [Figure 4] FIG. 4 is a schematic diagram of an encoding process of a digital encoding unit provided by an embodiment of the present application.

Modes for Carrying Out the Invention

[0009] Hereinafter, the technical solutions in the embodiments of the present application will be described in combination with the drawings in the embodiments of the present application. It is clear that the described embodiments are only a part of the embodiments of the present application, not all of the embodiments. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the scope of the claims of the present application.

[0010] Where expressions such as "first," "second," etc., are used in the description of the embodiments of this application, they are used solely for the purpose of distinguishing technical features and should not be understood as indicating or implying relative importance, the number of technical features shown, or the sequence of technical features shown. The phrase "at least one" means one or more, and the phrase "multiple" means two or more. The phrase "and / or" describes the relationship between related objects and indicates that there may be three types of relationships. For example, A and / or B can indicate that A exists alone, A and B exist simultaneously, or B exists alone. Here, A and B may be singular or plural. The symbol " / " generally indicates that the preceding and succeeding related objects are in an "or" relationship. "At least one of the following" and similar expressions refer to any group of these items and include any combination of one or more items. For example, at least one of a, b, and c can represent a, b, c, a and b, a and c, b and c, or a and b and c, where a, b, and c may be singular or plural.

[0011] To facilitate understanding of the technical proposal of the embodiment of this application, we will first briefly introduce the conventional technology of pipeline successive approximation type analog-to-digital converters.

[0012] Pipeline successive approximation analog-to-digital converters generally include multi-stage SAR ADCs and are used to encode the digital signals output from the multi-stage SAR ADCs and ultimately output a digital signal that is a converted analog input signal.

[0013] Each stage SAR ADC primarily consists of three parts: a digital-to-analog converter (DAC), a comparator, and a SAR control logic unit (SAR logic). The basic operating principle of each stage SAR ADC is as follows: In the first cycle after sampling, the DAC's most significant bit (MSB) is set to 1, and the remaining bits are set to 0. The comparator compares the analog input voltage with the initial value of the DAC output voltage (generally half the full-range voltage). If the analog input voltage is greater than the DAC output voltage, the sign of the current bit is 1, and the DAC's switching state remains unchanged. If the analog input voltage is less than the DAC output voltage, the sign of the current bit is 0, and the DAC's switching state returns to its pre-operation state. The SAR logic control then moves to the next bit, changes the DAC's switching state again, and compares it with the analog input voltage. This process is repeated until the comparison of the last bit is complete, obtaining all A / D conversion codes. The core principle of the SAR ADC's operating principle is a dichotomy; the change in the DAC output voltage each time is 1 / 2, and it successively approaches the analog input voltage to achieve analog-to-digital conversion.

[0014] In a pipeline successive approximation analog-to-digital converter, an interstage gain amplifier is provided between the DACs of two adjacent SAR ADCs. The interstage gain amplifier amplifies the remaining amount (residual voltage) of the analog input voltage of the preceding SAR ADC, and this is then used as the analog input for the subsequent SAR ADC.

[0015] In deep submicron CMOS technology, the intrinsic gain of transistors gradually decreases, making it difficult for interstage gain amplifiers to achieve high-gain linear amplification. To address this technical challenge, conventional technology proposes reducing the reference voltage in the subsequent ADC to half the reference voltage in the preceding ADC, thereby realizing a two-stage interstage gain halving technique and lowering the gain of the interstage gain amplifier. For example, if the number of bits in the preceding SAR ADC is M bits, the amplification factor of the interstage gain amplifier is generally 2. M-1It should be set to a small amount, but if the interstage gain halving technique is adopted, the amplification factor of the interstage gain amplifier can be set to 2 M-2 It can be reduced to this extent. However, halving the interstage gain by halving the reference voltage significantly reduces the ADC's conversion speed and power consumption.

[0016] From the above, the drawback of conventional two-stage or more-stage pipeline successive approximation analog-to-digital converter structures is that the interstage gain amplifier has high gain, making it unsuitable for deep submicron CMOS technology. In the conventional technology, the reference voltage is reduced, which enables interstage gain halving technology, but this limits the overall speed and accuracy of the pipeline successive approximation analog-to-digital converter and increases power consumption. Based on this, the embodiment of the present invention provides a pipeline successive approximation analog-to-digital converter, integrated circuit, and electronic device that halves the interstage gain without requiring halving of the reference voltage in order to improve the conversion speed and power consumption of the ADC.

[0017] Please refer to Figure 1. Figure 1 is a structural block diagram of a pipeline successive approximation analog-to-digital converter provided in one embodiment of the present invention. As shown in Figure 1, the pipeline successive approximation analog-to-digital converter of the present invention includes a first-stage successive approximation analog-to-digital converter 10, an interstage gain amplifier 30, a second-stage successive approximation analog-to-digital converter 20, and a digital encoding unit 40. Here, the first-stage successive approximation analog-to-digital converter 10 is connected to the second-stage successive approximation analog-to-digital converter 20 via the interstage gain amplifier 30, and the first-stage successive approximation analog-to-digital converter 10 and the second-stage successive approximation analog-to-digital converter 20 are connected to the digital encoding unit 40, respectively.

[0018] The first stage successive approximation analog-to-digital converter 10 (hereinafter abbreviated as the first stage SAR ADC) of the embodiment of the present invention is provided as an M-bit SAR ADC, that is, the first stage SAR ADC is for outputting an M-bit digital signal to the digital encoding unit 40, where M is an integer greater than 1. The second stage successive approximation analog-to-digital converter 20 (hereinafter abbreviated as the second stage SAR ADC) of the embodiment of the present invention is provided as an N-bit SAR ADC, that is, the second stage SAR ADC is for outputting an N-bit digital signal to the digital encoding unit 40, where N is an integer greater than 1. The digital encoding unit 40 encodes the M-bit digital signal (B11:B1M) output from the first-stage SAR ADC and the N-bit digital signal (B21:B2N) output from the second-stage SAR ADC using an interstage transition integration method to obtain a final (M+N-1)-bit binary digital signal (D1:D(M+N-1)).

[0019] Please refer to Figure 2. Figure 2 is a schematic diagram of the circuit structure of a first-stage SAR ADC provided by an embodiment of the present invention. The first-stage SAR ADC includes sequentially connected first digital-to-analog converters, a first comparator, and a first digital control logic unit. Here, the first digital-to-analog converter includes a first capacitance array, the first capacitance array having one first compensation capacitor C0 (to make the total capacitance 2^n * Cunit) and M-bit first capacitors C1~C M Includes.

[0020] The aforementioned M-bit first capacitance C1~C M The capacity values ​​increase in powers of 2, from smallest to largest number of bits. First capacity C i The capacity value is given by equation C i =2 i-1 *It can be represented by CU, where i = any integer from 1 to M, and CU is the unit capacity.

[0021] The capacitance value of the first compensation capacitance C0 is equal to the capacitance value of the first bit capacitance C1 of the M-bit first capacitance, i.e., C0 = CU.

[0022] As shown in FIG. 2, the first compensation capacitor C0, each of the first capacitors C1 to C M The first ends of are respectively connected to the analog input voltage, and the second ends of each of the first capacitors C1 to C M are respectively connected to the positive reference voltage V ref and the negative reference voltage (in this example, the reference ground GND is used as the negative reference voltage) via a multiplexing switch, and the second end of the first compensation capacitor C0 is constantly connected to the negative reference voltage.

[0023] It can be understood that the analog input voltage can be connected to the input end of the first digital-to-analog converter via a sample-and-hold circuit (S / H). When performing A / D conversion on an analog signal, a certain conversion time is required. During this conversion time, the analog signal is basically held so as not to change, and only by doing so can the conversion accuracy be guaranteed. The sample-and-hold circuit is a circuit that realizes such a function.

[0024] As shown in FIG. 2, the first-stage SAR ADC samples the analog input voltage using the upper plate. In the first-stage SAR ADC, the upper plates of each capacitor are connected to the analog input voltage, and the lower plates of the M-bit first capacitors C1 to C M are connected to a multiplexed reference signal source via a multiplexing switch. Exemplarily, the reference signal source can include a positive reference voltage V ref and a negative reference voltage (in this example, the reference ground GND is used as the negative reference voltage). In some examples, the reference signal source further includes a common-mode voltage V CM The lower plate of the first compensation capacitor C0 is constantly connected to the negative reference voltage.

[0025] In the example shown in FIG. 2, the sampling method of the first-stage SAR ADC is differential upper plate sampling, and the analog input voltage input to the first-stage SAR ADC is the differential voltages V ip1 and V in1 where V ip1 is the positive analog input voltage and V in1is the negative analog input voltage. In the upper-plate difference sampling scheme, the first stage SAR ADC has two first capacitance arrays, the structure of the two first capacitance arrays is the same, and the two first capacitance arrays are connected corresponding to the forward analog input voltage and the negative analog input voltage. For an M-bit difference output first stage SAR ADC, each first capacitance array contains M+1 capacitances, and the first stage SAR ADC shares 2M+2 capacitances.

[0026] Of the M bits of the first capacity of the first capacity array, C1 to C M-1 It belongs to the weighted capacitance, and in the successive conversion process, the output voltage of the first capacitance array can be increased or decreased by switching the corresponding weighted capacitance, C M This can be understood as being for generating a residual voltage signal for the second-stage SAR ADC.

[0027] The circuit structure of the first-stage SAR ADC shown in Figure 2 should be understood as merely an example. In actual implementation, the circuit structure of the first-stage SAR ADC can be appropriately modified according to different analog sampling methods. For example, when using a single-ended sampling method, the first-stage SAR ADC only needs to have one first capacitance array.

[0028] The interstage gain amplifier 30 in this embodiment is provided between the first-stage SAR ADC and the second-stage SAR ADC. Specifically, the input terminal of the interstage gain amplifier 30 is connected to the residual voltage output from the first digital-to-analog converter.

[0029] As shown in Figure 2, when the sampling method of the first stage SAR ADC is differential upper plate sampling, the interstage gain amplifier 30 uses a differential amplifier. When a differential amplifier is used, the interstage gain amplifier 30 has two input terminals and corresponds to the residual voltages (forward residual voltage and negative residual voltage) connected to the outputs of the two first capacitance arrays. The interstage gain amplifier 30 is V ip1 and V in1 The residual voltage is amplified, and the difference is the analog input voltage V ip2 and Vin2 To obtain this, the interstage gain amplifier 30 has two output terminals, V ip2 and V in2 This is output to the second stage SAR ADC.

[0030] It can be understood that the two input terminals of the interstage gain amplifier 30 may each be equipped with switches (S1, S2) to control the input of the residual voltage via the switches.

[0031] Please refer to Figure 3. Figure 3 is a schematic diagram of the circuit structure of a second-stage SAR ADC provided in an embodiment of the present application. As shown in Figure 3, the second-stage SAR ADC includes a second digital-to-analog converter, a second comparator, and a second digital control logic unit, where the second digital-to-analog converter includes a second capacitance array, and the second capacitance array includes one gain half-capacitor C a and one second compensation capacitance C0 and N-1 bit second capacitances C1~C N-1 Includes.

[0032] The aforementioned N-1 bit second capacitance C1~C N-1 The capacity values ​​increase in powers of 2, from smallest to largest number of bits. The capacity value of the second capacity Ci is given by equation C i =2 i-1 *It can be represented by CU, where i = any integer between 1 and N-1, and CU is the unit capacity.

[0033] The capacitance value of the second compensation capacitance C0 is the N-1 bit second capacitance C1~C N-1 It is equal to the capacity value of the first largest capacity C1, i.e., C0 = CU.

[0034] The capacitance value of the gain half-capacitance Ca is the N-1 bit second capacitance C1~C N-1 and the sum of the capacity values ​​of the second compensation capacity C0, where the capacity value of Ca is given by the formula Ca=2 N-1 *This can be represented by CU.

[0035] As shown in Figure 3, the gain half-capacitance C a, the second compensation capacitance C0, N-1 bit second capacitance C1~C N-1 The first ends are connected to the output terminals of the interstage gain amplifier 30. N-1 bit second capacitors C1~C N-1 The second end of each is connected via a multiple selection switch to a forward reference voltage V ref , connected to a negative reference voltage (in this example, the reference ground GND is used as the negative reference voltage), and the gain half-capacitor C a The second terminals of the second compensating capacitance C0 are permanently connected to a negative reference voltage.

[0036] As shown in Figure 3, the second-stage SAR ADC samples the analog input voltage using its upper plate. In the second-stage SAR ADC, the upper plate of each capacitor is connected to the output terminal of the interstage gain amplifier 30, and the analog input voltage is accessed from the interstage gain amplifier 30 (obtained by amplifying the residual voltage of the first-stage SAR ADC by the interstage gain amplifier 30), and the N-1 bit second capacitors C1~C N-1 The lower plate is connected to multiple reference signal sources via multiple selection switches. For example, the reference signal source is a forward reference voltage V ref This may include a negative reference voltage (in this example, the reference ground GND is the negative reference voltage). In some examples, the reference signal source is a common-mode voltage V CM The gain half-capacitance C further includes. a The lower plate of the second compensating capacitor C0 is permanently connected to a negative reference voltage.

[0037] In the example shown in Figure 3, the sampling method of the second-stage SAR ADC is differential upper-plate sampling, and the two output terminals of the interstage gain amplifier 30 are differential voltage V ip2 and V in2 (The V of the first stage SAR ADC is output by the interstage gain amplifier 30) ip1 and V in1 (Obtained by amplifying the residual voltage of ). Here, V ip2 V is the forward analog input voltage. in2 This is a negative analog input voltage.

[0038] In the upper plate differential sampling method, the second stage SAR ADC has two second capacitance arrays, and the structure of the two second capacitance arrays is the same. The two second capacitance arrays are connected to the forward analog input voltage V ip2 and negative analog input voltage V in2 They are connected in correspondence. For a second-stage SAR ADC with N-bit difference output, each first-stage capacitance array contains N+1 capacitances (one gain-half capacitance, one second compensation capacitance, and an N-1 bit second capacitance), and the second-stage SAR ADC shares 2N+2 capacitances.

[0039] Of the N-1 bits of the second capacity array, C1 to C N-1 These all belong to the weighted capacitance category, and it can be understood that the output voltage of the second capacitance array can be increased or decreased by switching the corresponding weighted capacitance during the successive conversion process.

[0040] The circuit structure of the second-stage SAR ADC shown in Figure 3 should be understood as merely an example. In actual implementation, the circuit structure of the second-stage SAR ADC can be appropriately modified according to different analog sampling methods. For example, when using a single-ended sampling method, the second-stage SAR ADC only needs to have one second capacitance array.

[0041] The digital coding unit 40 in this embodiment is connected to the output terminals of the first digital control logic unit and the second digital control logic unit. The analog input voltage generates an (M+N) bit code through amplification and quantization by a two-stage successive approximation analog-to-digital converter and an interstage gain amplifier 30, and finally the digital coding unit 40 completes the output of the final (M+N-1) bit digital code.

[0042] Figure 4 is a schematic diagram of the encoding process of the digital encoding unit 40. The first-stage SAR ADC (M-bit SAR ADC) and the second-stage SAR ADC (N-bit SAR ADC) jointly generate an (M+N) bit code, and obtain a final (M+N-1) bit binary digital output code (D1:D(M+N-1)) according to the interstage transposition addition scheme in Figure 3. Since it is necessary to maintain full amplitude quantization, a subtraction process for entry digital encoding is required. The decoding circuit can realize the encoding process in Figure 4 using a full adder (FA) and a half adder (HA).

[0043] In the embodiment of the present invention, a gain-halving capacitor is provided in the second digital-to-analog converter of the second-stage successive approximation analog-to-digital converter 20, and the capacitance value of the gain-halving capacitor is the sum of the capacitance values ​​of the remaining capacitors in the second digital-to-analog converter. This doubles the capacitance DAC of the second-stage successive approximation analog-to-digital converter 20, enabling a halving of the interstage gain in the two-stage structure. This reduces the gain of the interstage gain amplifier 30 (reducing the amplification factor of the interstage gain amplifier 30 from 2 M-1 to 2 M-2), but the forward reference voltage of the second-stage successive approximation analog-to-digital converter 20 remains the same as the forward reference voltage of the first-stage successive approximation analog-to-digital converter 10 without being halved. This is effective in reducing power consumption and improving conversion speed, and is also adaptable to deep submicron CMOS technology. The analog input signal is amplified and quantized by a two-stage successive approximation analog-to-digital converter and an interstage amplifier to generate an (M+N) bit digital signal, and finally an (M+N-1) bit digital signal is output via the digital encoding unit 40.

[0044] Furthermore, the embodiment of this invention can be applied not only to two-stage successive approximation analog-to-digital converters, but also to three-stage or more successive approximation analog-to-digital converters.

[0045] The present embodiment further provides an integrated circuit comprising a pipeline successive approximation type analog-to-digital converter as described in any of the embodiments described above.

[0046] Furthermore, the present embodiment provides an electronic device comprising a device body and the above-mentioned integrated circuit, wherein the integrated circuit is provided within the device body. Exemplarily, the electronic device may be a network device (such as a base station device).

[0047] In the embodiment of this invention, a gain-halving capacitor is provided in the second digital-to-analog converter of the second-stage successive approximation analog-to-digital converter, and the capacitance value of this gain-halving capacitor is the sum of the capacitance values ​​of the remaining capacitors in the second digital-to-analog converter. This realizes a two-stage interstage gain-halving technology, which reduces the gain of the interstage gain amplifier. However, the forward reference voltage of the second-stage successive approximation analog-to-digital converter is not halved and remains the same as the forward reference voltage of the first-stage successive approximation analog-to-digital converter. This is effective in reducing power consumption and improving conversion speed, and is also adaptable to deep submicron CMOS technology. The analog input signal generates an (M+N) bit digital signal through amplification and quantization by the two-stage successive approximation analog-to-digital converter and the interstage amplifier, and finally outputs an (M+N-1) bit digital signal via a digital encoding unit.

[0048] Although several embodiments of the present application have been described in detail above, the present application is not limited to the embodiments described above. A person skilled in the art can make various equivalent modifications or substitutions without violating the shared spirit of the present application, and all such equivalent modifications or substitutions fall within the scope limited by the claims of the present application.

Claims

1. A first-stage successive approximation analog-to-digital converter comprising sequentially connected first digital-to-analog converters, a first comparator, and a first digital control logic unit, wherein the first digital-to-analog converter includes a first capacitor array, the first capacitor array includes one first compensation capacitor and an M-bit first capacitor, the first end of the first compensation capacitor and each of the first capacitors are connected to an analog input voltage, the second end of each of the first capacitors is connected to a forward reference voltage and a negative reference voltage via a multiple selection switch, the second end of the first compensation capacitor is connected to a negative reference voltage, the capacitance value of the first compensation capacitor is equal to the capacitance value of the first bit of the M-bit first capacitor, and the capacitance value of the M-bit first capacitor increases in powers of 2 from smallest to largest number of bits, where M is an integer greater than 1, An interstage gain amplifier whose input terminal is connected to the residual voltage output from the first digital-to-analog converter, A second-stage successive approximation analog-to-digital converter comprising a second digital-to-analog converter, a second comparator, and a second digital control logic unit, wherein the second digital-to-analog converter includes a second capacitance array, the second capacitance array includes one gain-half-capacitor, one second compensation capacitor, and an N-1 bit second capacitor, the gain-half-capacitor, the second compensation capacitor, and the first end of each of the second capacitors are respectively connected to the output terminal of the interstage gain amplifier, and the second end of each of the second capacitors is forward-referenced via a multiple selection switch. A second-stage successive approximation analog-to-digital converter is provided, wherein the voltage and negative reference voltage are connected, the gain-half-capacitor and the second end of the second compensation capacitor are connected to the negative reference voltage, the capacitance value of the second compensation capacitor is equal to the capacitance value of the first capacitor among the N-1 bit second capacitors, the capacitance values ​​of the N-1 bit second capacitors increase in powers of 2 in order from the smallest to the largest number of bits, the capacitance value of the gain-half-capacitor is the sum of the capacitance values ​​of the N-1 bit second capacitor and the second compensation capacitor, and N is an integer greater than 1. The system comprises a first digital control logic unit and a digital encoding unit connected to the output terminal of the second digital control logic unit. Pipeline successive approximation type analog-to-digital converter.

2. The analog input voltage is a differential voltage, and two first capacitance arrays are provided, with the two first capacitance arrays accessing the forward input voltage and the negative input voltage of the differential voltage. The pipeline successive approximation type analog-to-digital converter according to claim 1.

3. The interstage gain amplifier is a differential amplifier, and the two input terminals of the differential amplifier are connected in accordance with the residual voltages output by the two first capacitance arrays. The pipeline successive approximation type analog-to-digital converter according to claim 2.

4. The differential amplifier is provided with two output terminals, and two second capacitance arrays are provided, each of which corresponds to the two output terminals of the differential amplifier to which it is connected. The pipeline successive approximation type analog-to-digital converter according to claim 3.

5. The amplification factor of the interstage gain amplifier is 2 to the power of (M-2). The pipeline successive approximation type analog-to-digital converter according to claim 1.

6. The second terminal of each of the first capacitors is further connected to the common mode voltage via the multiple selection switch. The pipeline successive approximation type analog-to-digital converter according to claim 1.

7. The second terminal of each of the second capacitors is further connected to the common mode voltage via the multiple selection switch. The pipeline successive approximation type analog-to-digital converter according to claim 1.

8. The system further comprises a sample-and-hold circuit, the sample-and-hold circuit being connected to the analog input voltage and the first digital-to-analog converter. The pipeline successive approximation type analog-to-digital converter according to claim 1.

9. A pipeline successive approximation type analog-to-digital converter according to any one of claims 1 to 8, Integrated circuit.

10. The device comprises a main body and an integrated circuit as described in claim 9, wherein the integrated circuit is provided within the main body of the device. electronic equipment.

Images