Integrated circuits, processing methods, electronic devices, and media for memory access

Abstract

[0009] The present disclosure provides an integrated circuit, a processing method, an electronic device, and a medium for memory access, the integrated circuit including: a first bit width conversion module for converting a first write access signal of a processor into a second write access signal including two portions of original data to be written; a first memory control module for converting the target data to be written in the second write access signal into at least one set of first data to be written that meets a first protocol supported by a memory physical layer interface and determining a corresponding set of third write access signals, each set of first data to be written including two portions of the same first data to be written from the two portions of the original data to be written; and a memory physical layer interface for converting each set of third write access signals into two-path fourth write access signals that meet the memory protocol and transmitting each fourth write access signal to a corresponding memory module. The present disclosure can effectively meet the storage requirements of a relatively high security level function based on a relatively low security level memory.

Description

Cross-reference to Related Applications

[0001] This disclosure claims the priority of a Chinese patent application filed with the China National Intellectual Property Administration on January 17, 2023, with the application number CN202310079654.7 and the title of the invention "Integrated Circuit for Memory Access, Processing Method, Electronic Device and Medium", and all of its contents are incorporated herein by reference.

Technical Field

[0002] This application relates to semiconductor technology, and particularly to an integrated circuit for memory access, a processing method, an electronic device and a medium.

Background Art

[0003] In the field of intelligent driving, the DDR (Double Data Rate SDRAM (Synchronous Dynamic Random Access Memory)) of an intelligent driving chip is mainly used for the detection and prediction function of intelligent driving. Supporting related memories Although the current functional safety level requirement for this function is ASIL B (Automotive Safety Integrity Level B), with the evolution of the algorithms of the control and decision-making functions whose safety level in the intelligent driving function is ASIL D (Automotive Safety Integrity Level D), the computing power and memory requirements necessary for the algorithms of the control and decision-making functions are becoming increasingly large. When developing the control and decision-making algorithms by a processor (or a core inside the processor) and a RAM, the problem of memory shortage is likely to exist, thereby causing a shortage of relatively high-level memory corresponding to relatively high-level functions.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of this disclosure provide integrated circuits, processing methods, electronic devices, and media for memory access to satisfy the memory storage requirements of a relatively high level of security. [Means for solving the problem]

[0005] An integrated circuit for memory access according to one embodiment of the present disclosure includes: a first bit width conversion module for converting the original data to be written in a first write access signal of a processor into target data to be written, which includes two parts of the original data to be written, according to a first predetermined conversion mode, and for determining a converted second write access signal based on the target data to be written; and connected to the first bit width conversion module for converting the target data to be written in the second write access signal into at least one set of first data to be written that satisfy a first protocol supported by a memory physical layer interface, and for each set of the first write access signals A first memory control module for determining a corresponding set of third write access signals based on target data, wherein each set of the first write target data comprises two identical sets of first write target data from two sets of the original write target data, and each set of the third write access signals comprises a first memory control module including two paths of third write access signals, and a memory physical layer interface connected to the first memory control module for converting each set of the third write access signals into two paths of fourth write access signals that satisfy a memory protocol, and transmitting each of the fourth write access signals to its corresponding memory module.

[0006] A processing method for memory access according to another embodiment of the embodiments of the present disclosure includes the steps of: converting original data to be written in a first write access signal of a processor into target data to be written, which includes two copies of the original data to be written, according to a first predetermined conversion mode; determining a converted second write access signal based on the target data to be written; converting the target data to be written in the second write access signal into at least one set of first data to be written that satisfy a first protocol supported by a memory physical layer interface; determining a corresponding set of third write access signals based on each set of the first data to be written, wherein each set of first data to be written includes two copies of the same first data to be written, each from two copies of the original data to be written, and each set of third write access signals includes two paths of third write access signals; and converting each set of third write access signals into two fourth write access signals that satisfy a memory protocol; and transmitting each of the fourth write access signals to the corresponding memory module.

[0007] A computer-readable storage medium according to yet another embodiment of the embodiments of the present disclosure stores a computer program for performing the method described in the above embodiments of the present disclosure, or stores data that needs to be stored by at least one hardware logic circuit of the integrated circuit described in the above embodiments of the present disclosure, so that the hardware logic circuit can perform the corresponding function when in operation.

[0008] An electronic device according to yet another embodiment of the embodiments of the present disclosure includes a processor and a memory for storing instructions that the processor can execute, wherein the processor reads the instructions from the memory and executes the instructions to implement the method described in the embodiments of the present disclosure, or the electronic device includes an integrated circuit as described in the embodiments, wherein at least one module in the integrated circuit is implemented by a hardware logic circuit. [Effects of the Invention]

[0009] The integrated circuit, processing method, electronic device, and medium for memory access according to the above embodiment of the present application perform bit width conversion on the first write access signal of the processor to convert the original data to be written into target data to be written, which includes two parts of the original data to be written. Furthermore, a second write access signal after conversion is determined based on the target data to be written. The first memory control module and memory physical layer interface write the two parts of the original data to be written to two memory modules. As a result, when reading data, the same data can be read from these two memory modules. The consistency of the access results of the two memory modules ensures the functional safety of a relatively high level of safety. Even in scenarios where the memory controller only satisfies a relatively low level of safety, it enables the completion of access operations for a relatively high level of safety. This allows relatively low-safety memory to be used for relatively high-safety memory, and relatively high-safety memory to access relatively low-safety memory. This helps to provide greater storage support for relatively high-safety memory while satisfying functional safety, thereby effectively meeting the storage requirements of relatively high-safety memory and solving problems such as insufficient relatively high-safety memory.

[0010] The technical configuration of this disclosure will be described in more detail below with reference to the drawings and embodiments. [Brief explanation of the drawing]

[0011] [Figure 1] This is one exemplary application scenario of the integrated circuit for memory access relating to this disclosure. [Figure 2] This figure shows the structure of an integrated circuit for memory access according to one exemplary embodiment of the present disclosure. [Figure 3] This figure shows the structure of an integrated circuit for memory access according to another exemplary embodiment of the present disclosure. [Figure 4] This figure shows the structure of a read data verification module 27 according to an exemplary embodiment of the present disclosure. [Figure 5] This figure shows the structure of an integrated circuit for memory access according to yet another exemplary embodiment of the present disclosure. [Figure 6] This figure shows the structure of a memory physical layer interface 23 according to an exemplary embodiment of the present disclosure. [Figure 7] This figure shows the structure of a memory physical layer interface 23 according to another exemplary embodiment of the present disclosure. [Figure 8] This figure shows the principle of conversion from original data to be written to target data to be written according to one exemplary embodiment of the present disclosure. [Figure 9] This figure shows the structure of an integrated circuit for memory access according to yet another exemplary embodiment of the present disclosure. [Figure 10] This figure shows the structure of an integrated circuit for memory access according to yet another exemplary embodiment of the present disclosure. [Figure 11] This figure shows the principle of conversion from third data to fourth data according to one exemplary embodiment of the present disclosure. [Figure 12] This figure shows a flow chart of a processing method for memory access according to an exemplary embodiment of the present disclosure. [Figure 13] This figure shows a flow chart of a processing method for memory access according to another exemplary embodiment of the present disclosure. [Figure 14] This figure shows the data read flow for memory access according to one exemplary embodiment of the present disclosure. [Figure 15] A diagram showing a flow of a processing method for memory access according to yet another exemplary embodiment of the present disclosure. [Figure 16] A diagram showing a structure of another application embodiment of an electronic device of the present disclosure. Aspects for implementing the invention

[0012] Hereinafter, in order to interpret the present disclosure, exemplary embodiments of the present disclosure will be described in detail with reference to the drawings. The described embodiments are only a part of the embodiments of the present disclosure, not all of the embodiments, and the present disclosure is not limited to the exemplary embodiments.

[0013] Note that unless there is another specific description, the relative deployment, mathematical formulas, and numerical values of the members and steps described in these embodiments do not limit the scope of the present disclosure.

[0014] [Summary of the Present Disclosure] In the process of realizing the present disclosure, the inventor has discovered the following. In the field of intelligent driving, the DDR (Double Data Rate SDRAM (Synchronous Dynamic Random Access Memory), double data rate synchronous dynamic random access memory) of an intelligent driving chip is mainly used for the detection and prediction function of intelligent driving. To support related memoriesIt is used, and the requirement for the current functional safety level of this function is ASIL B (Automotive Safety Integrity Level B). However, with the evolution of the algorithms of the control and decision-making functions where the safety level in the intelligent driving function is ASIL D (Automotive Safety Integrity Level D), the computing power and memory requirements necessary for the algorithms of the control and decision-making functions are increasing. When developing the algorithms of the control and decision-making by the processor (or the core inside the processor) and RAM, the problem of memory shortage is likely to exist, thereby causing a shortage of relatively high-level memory corresponding to functions with a relatively high safety level.

[0015] [Exemplary Overview] FIG. 1 is one exemplary application scenario of an integrated circuit for memory access according to the present disclosure.

[0016] In a predetermined level of functional scene (ASILD level), such as intelligent driving control and decision-making, the integrated circuit for memory access of this disclosure allows a processor responsible for executing the corresponding control and decision-making functional algorithm to access DDR under conditions that satisfy its functional safety level ASILD, thereby providing strong storage capabilities based on DDR to meet its ever-growing storage requirements. Here, the processor can be any possible processor or processor core within an intelligent driving chip, such as a central processing unit (CPU), graphics processor (GPU), brain processor (BPU), artificial intelligence processor (NPU), deep learning processor (DPU), etc., and is not specifically limited. Specifically, the integrated circuit for memory access of this disclosure may include a first bit width conversion module, a first memory control module, and a memory physical layer interface. The first bit width conversion module can convert the original data to be written in the processor's first write access signal into target data to be written, which includes two parts of the original data to be written, according to a first predetermined conversion mode, and determine a converted second write access signal based on the target data to be written. A first memory control module can be connected to a first bit width conversion module, which can convert the target data to be written in a second write access signal into at least one set of first data to be written that satisfies a first protocol supported by the memory physical layer interface, and can determine a corresponding set of third write access signals based on each set of first data to be written. Each set of first data to be written may contain two identical sets of first data to be written from two sets of original data to be written, and each set of third write access signals may contain two paths of third write access signals.The memory physical layer interface can be connected to a first memory control module, which converts each pair of third write access signals into two paths of fourth write access signals that satisfy the memory protocol, and transmits each fourth write access signal to its corresponding memory module. This allows memory access to two memory modules simultaneously, and the consistency of the access results of the two memory modules achieves a relatively high level of memory access security. This enables memory devices with relatively large storage capacity based on a relatively low level (e.g., ASILB level) to provide storage capacity for relatively high-level (e.g., ASILD level) functional scenes, helping to solve problems such as insufficient storage for relatively high-level functional scenes.

[0017] Furthermore, the integrated circuits of this disclosure are not limited to being applied to the intelligent driving control and decision-making scenarios described above, but can be applied to any scenario where a relatively high level of safety is required, depending on the actual requirements, and are not limited to such scenarios.

[0018] [Example device] Figure 2 shows the structure of an integrated circuit for memory access according to an exemplary embodiment of the present disclosure. This embodiment can be applied to electronic devices, specifically automotive computing platforms, and as shown in Figure 2, the integrated circuit for memory access ("integrated circuit") 20 may include a first bit width conversion module 21, a first memory control module 22, and a memory physical layer interface 23.

[0019] The first bit width conversion module 21 can convert the original data to be written in the processor's first write access signal into target data to be written, which includes two parts of the original data to be written, according to a first predetermined conversion mode, and determine the converted second write access signal based on the target data to be written.

[0020] The first memory control module 22 can be connected to the first bit width conversion module 21, and the first memory control module 22 can convert the target data to be written in the second write access signal into at least one set of first data to be written that satisfies a first protocol supported by the memory physical layer interface, and can determine a corresponding set of third write access signals based on each set of first data to be written, each set of first data to be written may contain two identical sets of first data to be written from two sets of original data to be written, and each set of third write access signals may contain two paths of third write access signals.

[0021] The memory physical layer interface 23 can be connected to the first memory control module 22, and the memory physical layer interface 23 can convert each set of third write access signals into two paths of fourth write access signals that satisfy the memory protocol, and transmit each fourth write access signal to its corresponding memory module.

[0022] Here, the processor can be any possible processor or processor core within the intelligent driving chip, such as a central processing unit (CPU), graphics processor (GPU), or artificial intelligence (AI) processor (or AI processor core), and is not specifically limited. The first write access signal may include a data signal (including the original data to be written), a control signal, and an address signal. The first predetermined conversion mode can be set according to the actual requirements. The first predetermined conversion mode may duplicate the original data to be written into two parts, and the two parts of the original data to be written, according to a predetermined format, become the target data to be written, which then becomes the data signal for the second write access signal.

[0023] The first memory control module 22 may be a control module connected to the first bit width conversion module 21 and the memory physical layer interface 23, and the first memory control module 22 can convert the second write access signal converted by the first bit width conversion module 21 into a write access signal that satisfies the memory physical layer interface protocol. To enable writing two parts of the original data to be written to two memory modules, the first memory control module 22, when performing a protocol conversion, can convert the target data to be written, which includes two parts of the original data to be written, into at least one set of first data to be written, each set of which may include two identical sets of first data to be written, and each set of two sets of first data to be written may be derived from two parts of the original data to be written in the target data to be written. For example, if the original data to be written is 128 bits and the first data to be written is 16 bits, then it can be converted into eight sets of first data to be written, where the first set of two sets of first data to be written may each include bits 0 to 15 of the original data to be written, the second set of two sets of first data to be written may each include bits 16 to 31 of the original data to be written, ..., and the eighth set of two sets of first data to be written may each include bits 112 to 127 of the original data to be written. Since the first data to be written to each part can be used as the data signal for the third write access signal of one path, at least one set of converted third write access signals can be obtained, and each set can contain the third write access signals of two paths.

[0024] When actually using the system, the specific bit widths of the original data to be written and the first data to be written can be set according to the actual requirements.

[0025] The memory physical layer interface 23 can be a bridge connecting the first memory control module 22 and the memory. The memory physical layer interface 23 can convert the two paths of the third write access signal for each pair converted by the first memory control module 22 into two paths of the fourth write access signal that satisfy the memory protocol, and transmit these two paths of the fourth write access signal to their respective corresponding memory modules. For example, one path of the fourth write access signal can be transmitted to the first memory module, and the other path of the fourth write access signal can be transmitted to the second memory module. This allows the two parts of the original data to be written to be divided into multiple sets and written to the two memory modules.

[0026] In one selectable embodiment, various conversion processes of write access signals may further include conversion of control signals in addition to conversion of the data to be written. For example, in the process of converting a first write access signal to a second write access signal, in addition to converting the original data to be written to the target data to be written, the signal representing the data length in the control signal may be converted. Also, for example, when the first memory control module converts the second write access signal to each set of third write access signals, in addition to converting the target data to be written to the first data to be written, the data length may be converted, specifically, according to actual requirements.

[0027] In one selectable embodiment, the conversion of each module can be represented by the conversion of an access signal, of which the conversion of the data portion can be performed according to the conversion form. For example, the first bit width conversion module 21 can convert a first write access signal to a second write access signal, where the target data to be written in the second write access signal is obtained by converting the original data to be written in the first write access signal according to a first predetermined conversion form, and the target data to be written may include two parts of the original data to be written. The process of converting the first write access signal to the second write access signal may further include the conversion of a control signal, which can be set according to the actual requirements. In one selectable embodiment, the first memory control module 22 may be a DDR controller.

[0028] In one selectable embodiment, the memory physical layer interface 23 may be a DDR PHY (DDR Physical Interface), the corresponding first protocol may be a DFI (DDR PHY Interface) protocol, and the memory protocol may be a DDR protocol. The DDR PHY may include two independent transmission channels, and the two transmission channels of the DDR PHY may transmit a fourth write access signal for each pair of two paths.

[0029] In one selectable embodiment, the specific structures of the first bit width conversion module 21, the first memory control module 22, and the memory physical layer interface 23 can be configured according to actual requirements.

[0030] In one selectable embodiment, each fourth write access signal can correspond to one memory module and can convert the two paths of the third write access signals in each pair to obtain the two paths of the fourth write access signals, thus corresponding to two memory modules, which can be called the first memory module and the second memory module, respectively. These two memory modules can be any two memory devices connected within the intelligent driving chip or two memory regions in the same memory device, for example, two memory regions at the same address in the DDR within the intelligent driving chip, which can be specifically configured according to actual requirements.

[0031] Optionally, the integrated circuits of the embodiments of the present disclosure can be connected to a processor via any applicable bus, such as AXI, AHB, APB, or CHI, so that the processor can access the first and second memory modules via the bus.

[0032] The integrated circuit for memory access according to this embodiment can convert the original data to be written into target data to be written, which includes two parts of the original data to be written, by performing a bit width conversion on the first write access signal of the processor, and can further determine the converted second write access signal based on the target data to be written. The first memory control module and the memory physical layer interface write the two parts of the original data to be written to two memory modules, so that when reading data, the same data can be read from these two memory modules. The consistency of the access results of the two memory modules guarantees the functional safety of a relatively high safety level function, and enables the completion of access operations for a relatively high safety level function even when the memory controller satisfies a relatively low safety level. As a result, a relatively low safety level memory can be used as a relatively high safety level function, and a relatively high safety level function can access a relatively low safety level memory. This provides greater storage support for a relatively high safety level function in order to satisfy functional safety, and thereby effectively satisfies the storage requirements of a relatively high safety level function, solving problems such as insufficient relatively high safety level storage.

[0033] Figure 3 shows the structure of an integrated circuit for memory access according to another exemplary embodiment of the present disclosure.

[0034] In one selectable embodiment, the integrated circuit of the embodiment of the present disclosure may further include a second memory control module 24 and a first comparison module 25.

[0035] The second memory control module 24 can be connected to the first bit width conversion module 21, and the second memory control module 24 can convert the target data to be written in the second write access signal into at least one set of second data to be written that satisfies the first protocol supported by the memory physical layer interface 23, and can determine a corresponding set of fifth write access signals based on each set of second data to be written, each set of second data to be written consisting of two identical sets of second data to be written from two sets of original data to be written, and each set of fifth write access signals may consist of two paths of fifth write access signals.

[0036] The first comparison module 25 can be connected to the first memory control module 22 and the second memory control module 24, respectively. The first comparison module 25 compares each pair of third write access signals with each pair of fifth write access signals and can output an error signal in response to a mismatch in the comparison results.

[0037] Here, the specific conversion principle of the second memory control module 24 can be the same as that of the first memory control module 22. The difference is that the second memory control module 24 can transmit each set of fifth write access signals acquired by the second memory control module 24 to the first comparison module 25 without needing to transmit them to the memory physical layer interface 23, and can also transmit each set of third write access signals acquired by the first memory control module 22 to the first comparison module 25. The first comparison module 25 compares each set of third write access signals with each set of fifth write access signals to determine whether the processing result of the first memory control module 22 matches the processing result of the second memory control module 24. If the comparison result does not match, it outputs an error signal, allowing timely action to be taken. This improves the functional safety of the first memory control module 22 and avoids the occurrence of dangerous situations due to errors in the first memory control module 22.

[0038] In one selectable embodiment, the first comparison module 25 may, in addition to comparing each set of third write access signals with each set of fifth write access signals, also compare other operational output signals of the first memory control module 22 and the second memory control module 24, thereby enabling cross-verification of all functions of the first memory control module 22 and the second memory control module 24 and further improving the functional safety of the first memory control module 22.

[0039] In this embodiment, by providing a second memory control module with the same functions as the first memory control module to verify the processing results of the first memory control module, the accuracy and effectiveness of the processing results of the first memory control module can be effectively improved, thereby improving the safety of written data and enabling timely detection of errors in the first memory control module. As a result, write access to memory can meet a relatively high level of safety.

[0040] In one selectable embodiment, the integrated circuit of the embodiment of the present disclosure may further include a second bit width conversion module 26 and a read data verification module 27.

[0041] The memory physical layer interface 23 can further acquire at least one set of first data from the first memory module and the second memory module, convert each set of first data from the at least one set of first data into a set of second data that satisfies the first protocol, and transmit each set of second data to the first memory control module 22. Each set of first data may include first read data and second read data, and each set of second data may include third read data corresponding to the first read data and fourth read data corresponding to the second read data.

[0042] The first memory control module 22 can further convert each set of second data into third data that satisfies a second protocol supported by the second bit width conversion module 26, and transmit the third data to the second bit width conversion module 26.

[0043] The second bit width conversion module 26 can perform bit width conversion on the third data according to a second predetermined conversion mode to obtain the fourth data and the fifth data, and transmit the fourth data to the processor.

[0044] The read data verification module 27 can compare the fourth data with the fifth data and output an error signal in response to a mismatch in the comparison results.

[0045] Here, the second predetermined conversion form can be the inverse of the first predetermined conversion form. If it is necessary to read the same data after writing it to the first memory module and the second memory module, similarly, a set (including two parts) of the same data written in parallel from the first memory module and the second memory module can be read in parallel. To distinguish them, the data read from the first memory module can be called the first read data, and the data read from the second memory module can be called the second read data. The first read data and the second read data constitute a set of first data, and the memory physical layer interface 23 converts the first read data and the second read data in each set of first data into third read data and fourth read data that satisfy the first protocol. The third and fourth read data can be made into a pair of second data, and each pair of second data can be transmitted to the first memory control module 22. For example, the memory physical layer interface can transmit the third and fourth read data to the first memory control module 22 in parallel via two independent channels, and the first memory control module 22 can convert each pair of second data into third data that satisfies a second protocol supported by the second bit width conversion module 26. This conversion process is the reverse of the conversion process from target write data to first write data, and at least one pair of second data can be combined into third data according to a certain format. The second bit width conversion module 26 can perform a bit width conversion on the third data according to a second predetermined conversion form to obtain the fourth and fifth data, and if no errors occur during data reading, the fourth and fifth data should be the same data.The second bit width conversion module 26 transmits the acquired fourth or fifth data to the processor and can also transmit the acquired fourth and fifth data to the read data verification module 27 for verification. The read data verification module 27 can compare the fourth and fifth data and outputs an error signal if the comparison results do not match. Since data reading reads data that was written before it, the fourth and fifth data in the data reading process match the bit width of the original data to be written in part two of the data writing process, the third data in the data reading process matches the bit width of the target data to be written in the data writing process, the first and second read data in the data reading process match the bit width of the data to be written in the fourth write access signal of the data writing process, and the third and fourth read data in the read data process match the bit width of the first data to be written in the write data process.

[0046] In one selectable embodiment, the display mode of the error signal can be set according to actual requirements, for example, an output of 1 indicates that an error has occurred, and is not limited to these.

[0047] In one selectable example, the memory physical layer interface 23 can convert a set of 16 bits of first data (including the first and second read data) read from the first and second memory modules each time into a set of 16 bits of second data (the third and fourth read data) that satisfies the first protocol and transmit it to the first memory control module 22. The first memory control module 22 can convert the eight sets of second data transmitted from the memory physical layer interface 23 into 256 bits of third data and transmit it to the second bit width conversion module 26. The second bit width conversion module 26 can convert the third data into 128 bits of fourth and fifth data according to a second predetermined conversion mode, where the fourth data originates from the first memory module and the fifth data originates from the second memory module.

[0048] In one selectable embodiment, the error signals of the embodiments of this disclosure may be output to an error handling module in an intelligent driving chip or to a processor, specifically configured according to actual requirements, and not limited to the embodiments of this disclosure, so as to perform timely corresponding processing in response to an error that occurs, such as resetting an integrated circuit or sending alarm information to the user.

[0049] In this embodiment, when reading data, the second bit width conversion module compares the fourth and fifth data obtained from the two memory modules with the second bit width conversion module. If the comparison results do not match, it outputs an error signal, allowing for timely processing of the error. This helps to improve the safety of the read data, and as a result, read access to memory can meet a relatively high level of safety.

[0050] Figure 4 shows the structure of a read data verification module 27 according to an exemplary embodiment of the present disclosure.

[0051] In one selectable embodiment, the read data verification module 27 may include a predetermined number of exclusive OR circuits 271 and OR circuits 272.

[0052] The two inputs of the nth exclusive OR circuit 271 can be the nth bit value of the fourth data and the nth bit value of the fifth data, respectively, and each exclusive OR circuit 271 can output 1 in response to the two input values ​​being different, and output 0 in response to the two input values ​​being the same, and the predetermined number can be the same as the bit width of the fourth data.

[0053] The input terminals of the OR circuit 272 can be connected to the output terminals of each exclusive OR circuit 271, and the OR circuit 272 can output an error signal in response to the output of any of the exclusive OR circuits 271 being 1.

[0054] Here, the predetermined number can be set according to the bit width of the fourth data; for example, if the bit width of the fourth data is 128 bits, 128 exclusive OR circuits 271 can be provided, and the specific number is not limited.

[0055] In one selectable embodiment, the specific structure of the OR circuit 272 can be set according to actual requirements. For example, the number of inputs to the OR circuit 272 can be set according to the number of exclusive OR circuits 271, and the internal structure of the OR circuit 272 can be realized by multiple OR elements.

[0056] This embodiment achieves a bitwise comparison between the fourth data and the fifth data using a predetermined number of exclusive OR circuits and one OR circuit, and can output an error signal if the comparison result of any of the bits does not match with a single output, thereby effectively reducing the number of connection lines to other modules.

[0057] In one selectable embodiment, the predetermined number can be the same as the bit width of the first read data, in which case the fourth and fifth data can be grouped and compared. For example, if the bit width of the first read data is 16 bits, the read data verification module 27 may include 16 exclusive OR circuits 271 and one OR circuit 272, and verify each 16 bits of the fourth data and the corresponding 16 bits of the fifth data as inputs to the read data verification module 27.

[0058] In one selectable embodiment, the read data verification module 27 can be implemented by a serial register and a single exclusive OR circuit or comparator. For example, two serial registers store the fourth data and the fifth data, respectively, and the two input terminals of the exclusive OR circuit or comparator are connected to the two serial registers. By controlling the two serial registers, each bit is sequentially input to the exclusive OR circuit or comparator, and the nth bit of the fourth data and the nth bit of the fifth data are input to the exclusive OR circuit for comparison. If they do not match, an error signal is output.

[0059] Figure 5 shows the structure of an integrated circuit for memory access according to yet another exemplary embodiment of the present disclosure.

[0060] In one selectable embodiment, the integrated circuit of the embodiment of the present disclosure may further include a first delay module 28 and a second delay module 29.

[0061] The first delay module 28 can be connected to the first memory control module 22 and the first comparison module 25, respectively, and the first delay module 28 can transmit each set of third write access signals output from the first memory control module 22 to the first comparison module 25 after delaying them by a first time.

[0062] The second delay module 29 can be connected to the first bit width conversion module 21 and the second memory control module 24, respectively, and the second delay module 29 can transmit the second write access signal output from the first bit width conversion module 21 to the second memory control module 24 after delaying it by a first time.

[0063] Here, the specific structures of the first delay module 28 and the second delay module 29 can be set according to actual requirements so as to enable signal delay, and are not specifically limited. For example, the transmission time of the received signal can be controlled by a timer. The first time can be set according to actual requirements, and can be set to, for example, one clock cycle, two clock cycles, and are not specifically limited. For the first memory control module 22, the first delay module 28 delays the time it takes for the output result to reach the first comparison module 25 after the first memory control module 22 has completed processing. For the second memory control module 24, the delay module 28 delays the time it takes for the second write access signal to reach the second memory control module 24 before the second memory control module 24 processes the data. This ensures that the processing results of the two memory control modules reach the first comparison module 25 simultaneously. Furthermore, the first memory control module 22 and the second memory control module 24 can convert the same second write access signal at different times. This avoids a situation where the same error occurs when both memory control modules are operating simultaneously, and the error goes undetected. For example, if the same error occurs in two memory control modules during processing, and they are simultaneously subjected to interference from some factor (e.g., electromagnetic interference), causing the third write access signal and the fifth write access signal for each set where the acquired error exists to still match, the first comparison module 25 will not be able to detect the occurrence of the error after comparison.

[0064] Furthermore, the first delay module 28 can delay each set of third write access signals output from the first memory control module 22 by a first time before transmitting them to the first comparison module 25, as well as any other signals output from the first memory control module 22 by a first time before transmitting them to the first comparison module 25. Similarly, the second delay module 29 can delay the second write access signals output from the first bit width conversion module 21 by a first time before transmitting them to the second memory control module 24, as well as any other signals that need to be input to the second memory control module 24 by a first time. Specifically, these settings can be configured according to actual requirements.

[0065] This embodiment effectively avoids situations where errors go undetected due to simultaneous errors in the two memory control modules by applying signal delays at different stages to the first memory control module 22 and the second memory control module 24, thereby improving the safety of memory access.

[0066] Figure 6 shows the structure of a memory physical layer interface 23 according to an exemplary embodiment of the present disclosure.

[0067] In one selectable embodiment, the memory physical layer interface 23 may include a first channel 231, a second channel 232, a control unit 233, and a monitor 234.

[0068] The first channel 231 can transmit a fourth write access signal corresponding to each pair of third write access signals to the first memory module corresponding to the first channel 231.

[0069] The second channel 232 can transmit another fourth write access signal corresponding to each set of third write access signals to the second memory module corresponding to the second channel 232.

[0070] The control unit 233 can be connected to the first channel 231 and the second channel 232, respectively, and the control unit 233 can generate the operating clock and reset signals for the first channel 231 and the second channel 232.

[0071] The monitor 234 can be connected to the control unit 233, and the monitor 234 can monitor and measure the operating clock and / or reset signal, and output an alarm signal based on the monitoring and measurement results.

[0072] Here, the first channel 231 and the second channel 232 can each be connected to the first memory control module 22, the first channel 231 can also be connected to the first memory module, and the second channel 232 can also be connected to the second memory module. The first channel 231 can convert one third write access signal in each set of third write access signals into one fourth write access signal that satisfies the memory protocol and transmit this fourth write access signal to the first memory module, and similarly, the second channel 232 can convert another third write access signal in each set of third write access signals into another fourth write access signal that satisfies the memory protocol and transmit it to the second memory module. The operating clock drives the first channel 231 and the second channel 232 so that they begin operation, and the reset signal can control the first channel 231 and the second channel 232 so that the memory and the memory physical layer interface 23 are reset. The control unit 233 can be controlled by other modules of the intelligent driving chip (e.g., a processor, a reset management module, etc.) and can be configured according to actual requirements. For example, in the event of a failure, the processor may need to reset the integrated circuit of the embodiment of the disclosure in order to handle the failure in response to an interrupt, and may send a reset command to the reset management module or send a reset command directly to the control unit 233. The control unit 233 can then control the first channel 231 and the second channel 232 so that a memory reset is performed. The specific control of the operating clock and reset can be configured according to actual requirements and is not limited to the embodiments of the disclosure.The monitor 234 can monitor and measure the operation clock and / or reset signal of the control unit 233 in real time or at a timely manner. If it monitors and measures that an error has occurred in the operation clock and / or reset signal, or that predetermined conditions are not met, it can output an alarm signal to detect the problem in a timely manner, thereby improving the functional safety of the memory physical layer interface 23. For example, the monitor 234 can check whether the count value of the generated operation clock is within a desired range, and if it is not within the desired range, it can output an alarm signal. It can also monitor and measure whether an error has occurred in the reset signal, and if the reset signal is triggered when the memory is operating normally (for example, a pull-down indicates that a reset operation is triggered), it can output an alarm signal.

[0073] The memory physical layer interface of this embodiment enables the conversion and transmission of two identical sets of third write access signals through two independent channels, allowing for the storage of a portion of the data from two original write data sets into two memory modules, and the storage of two identical original write data sets into two memory modules, which facilitates verification when reading data and helps ensure that memory access meets a relatively high level of safety.

[0074] In one selectable embodiment, the first channel 231 may convert the first read data read from the first memory module into a third read data that satisfies the first protocol and transmit it to the first memory control module 22, and the second channel 232 may convert the second read data read from the second memory module into a fourth read data that satisfies the first protocol and transmit it to the first memory control module 22. The first memory control module 22 converts each third read data transmitted by the first channel 231 and each fourth read data transmitted by the second channel 232 into third data that satisfies a second protocol supported by the second bit width conversion module 26, and can also transmit the third data to the second bit width conversion module 26, which performs bit width conversion on the third data according to a second predetermined conversion mode to obtain fourth and fifth data, transmits the fourth data to the processor, and transmits the fourth and fifth data to the read data verification module 27, which compares the fourth data and the fifth data and can output an error signal in response to a mismatch in the comparison results.

[0075] In one selectable example, Figure 7 shows the structure of a memory physical layer interface 23 according to another exemplary embodiment of the present disclosure. Here, monitor represents the monitor 234, clock represents the operating clock, reset represents the reset signal, MASTER represents the control unit 233, DDR channel A and DDR channel B represent the two channels of a dual-channel memory (e.g., dual-channel SDRAM), the structure of the first channel 231 and the second channel 232 are identical and both include three channels: DQ, DQ and AC, where DQ represents the data channel for transmitting data and AC represents the address / command channel for transmitting addresses and commands.

[0076] In one selectable embodiment, the first bit width conversion module 21 specifically, The original data to be written, contained in the first write access signal, is granulated into a first bit width. For each portion of the original data corresponding to the first bit width, this portion of the original data is duplicated into two identical copies. These two identical copies of data are used as two consecutive target data of the first bit width. The first bit width and the bit width of the data supported by the first protocol are the same. For each portion of the original data corresponding to the target data, the target data to be written is determined according to the order of the original data in the original data to be written. The signal representing the length of the original data to be written, contained in the control signal of the first write access signal, is converted into a signal representing the length of the target data to be written to obtain the target control signal. Based on the target data to be written and the target control signal, the second write access signal is determined.

[0077] In one selectable example, Figure 8 shows the principle of conversion from original data to be written to target data to be written according to an exemplary embodiment of the present disclosure. Here, Byte represents a byte, where 1 Byte = 8 bits, and bit represents a bit, for example, Byte0 contains 8 bits from bit0 to bit7. As shown in Figure 8, the first bit width is 16 bits, and the original data to be written in the first write access signal is granulated into 16 bits, and the original data corresponding to each first bit width (e.g., Byte0 and Byte1) is duplicated into two identical copies of the data, and these two identical copies of the data are used as target data of two consecutive first bit widths, and further, the target data corresponding to each part of the original data (a total of 8 parts of original data) (a total of 8 copies of target data) are combined according to the order of the original data of each part in the original data to be written to obtain the target data to be written.

[0078] In one selectable example, Figure 9 shows the structure of an integrated circuit for memory access according to yet another exemplary embodiment of the present disclosure. Here, the specific operating principles of each part can be found in the preceding text, and redundant explanations are omitted here.

[0079] In one selectable embodiment, the conversion function of the first bit width conversion module 21 and the second bit width conversion module 26 Since this conversion function is the reverse of the previous conversion function, it can be implemented by a single bit width conversion module when actually used. For example, Figure 10 shows the structure of an integrated circuit for memory access according to yet another exemplary embodiment of the present disclosure, and as shown in Figure 10, taking as an example the bit width of the original data to be written as 128 bits, the bit width conversion module is the first bit width conversion module 21 and the second bit width conversion module described above. 26 The functionality can be realized, and when writing data, the bit width conversion module converts the first write access signal of the original 128-bit data to be written to target data that includes two parts of the original data to be written and has a bit width of 256 bits, using AXI (Advanced eXtensible Interface) protocol conversion. When reading data, the bit width conversion module converts the 256-bit third data transmitted from the first memory control module 22 to 128-bit fourth and fifth data, using AXI protocol conversion, and transmits a portion of it to the processor. In this case, a read data verification module 27 is provided within this bit width conversion module to verify the converted fourth and fifth data. The AXI protocol is a bus protocol in which the address / control (or command) and data phases are separated and supports the transmission of inconsistent data; a detailed explanation of the specific principles will be omitted to avoid repetition.

[0080] In one selectable example, Figure 11 shows the principle of conversion from third data to fourth data according to an exemplary embodiment of the present disclosure. As shown in Figure 11, taking the third data bit width as an example of 256 bits, the 256-bit third data is converted to 128 bits. In the third data, the remaining bytes other than each byte that constitutes the fourth data constitute the fifth data, and the principle of the fifth data is the same as that of the fourth data, and a redundant explanation is omitted here.

[0081] Any module or unit in this example can be implemented using hardware or software, and can be implemented using hardware logic circuits to ensure real-time performance.

[0082] In one possible example, to ensure the real-time performance of the device, each module, each unit within each module, and each subunit within each unit of the device in the embodiment of the present disclosure can be implemented using hardware logic circuits, thereby effectively reducing hardware overhead and power consumption overhead while maintaining real-time performance.

[0083] Each embodiment and optional example of this disclosure may be implemented individually or in any combination as long as they do not conflict, and can be specifically configured according to the actual requirements.

[0084] [Example Method] Figure 12 is a flowchart illustrating a processing method for memory access according to an exemplary embodiment of the present disclosure, which can be implemented by an integrated circuit for memory access of any one of the embodiments described above. As shown in Figure 12, the method of this embodiment may include the following steps 301 to 303.

[0085] In step 301, the original data to be written in the processor's first write access signal is converted into target data to be written, which includes two parts of the original data to be written, according to a first predetermined conversion mode, and the converted second write access signal is determined based on the target data to be written.

[0086] In one possible example, step 301 may be performed by calling a corresponding instruction stored in memory by the processor, or it may be performed by the first bit width conversion module described above.

[0087] In step 302, the target data to be written in the second write access signal is converted into at least one set of first data to be written that satisfies a first protocol supported by the memory physical layer interface, a corresponding set of third write access signals is determined based on each set of first data to be written, each set of first data to be written consists of two identical sets of first data to be written from two sets of original data to be written, and each set of third write access signals consists of two paths of third write access signals.

[0088] In one possible example, step 302 may be executed by calling a corresponding instruction stored in memory by the processor, or it may be executed by the first memory control module described above.

[0089] In step 303, each pair of third write access signals is converted into two fourth write access signals that satisfy the memory protocol, and each fourth write access signal is transmitted to its corresponding memory module.

[0090] In one possible example, step 303 may be executed by calling a corresponding instruction stored in memory by the processor, or it may be executed by the memory physical layer interface described above.

[0091] The specific operations of each step of the method of the embodiment of this disclosure have already been described in detail in the previously mentioned embodiment of the integrated circuit, and therefore, redundant explanations will be omitted here.

[0092] Figure 13 is a diagram showing a flow of a processing method for memory access according to another exemplary embodiment of the present disclosure.

[0093] In one selectable embodiment, the method of the embodiment of the present disclosure may further include steps 401, 402.

[0094] In step 401, the target data to be written in the second write access signal is converted into at least one set of second data to be written that satisfies a first protocol supported by the memory physical layer interface, a corresponding set of fifth write access signals is determined based on each set of second data to be written, each set of second data to be written consists of two copies of the same second data to be written from two copies of the original data to be written, and each set of fifth write access signals consists of two paths of fifth write access signals.

[0095] In one possible example, step 401 may be executed by calling a corresponding instruction stored in memory by the processor, or it may be executed by the second memory control module described above.

[0096] In step 402, the third write access signal for each set is compared with the fifth write access signal for each set, and an error signal is output in response to a mismatch in the comparison result.

[0097] In one possible example, step 402 may be performed by calling a corresponding instruction stored in memory by the processor, or it may be performed by the first comparison module described above.

[0098] Figure 14 shows a data read flow for memory access according to an exemplary embodiment of the present disclosure.

[0099] In one selectable embodiment, the method of the embodiment of the present disclosure may further include steps 501-504.

[0100] In step 501, at least one set of first data is obtained from the first memory module and the second memory module, and each set of first data from the at least one set of first data is converted into a set of second data that satisfies the first protocol, where each set of first data includes first read data and second read data, and each set of second data includes third read data corresponding to the first read data and fourth read data corresponding to the second read data.

[0101] In one possible example, step 501 may be executed by calling a corresponding instruction stored in memory by the processor, or it may be executed by the memory physical layer interface described above.

[0102] In step 502, the second data of each set is transformed into a third data that satisfies the second protocol.

[0103] In one possible example, step 502 may be executed by calling a corresponding instruction stored in memory by the processor, or it may be executed by the first memory control module described above.

[0104] In step 503, the third data is converted to a bit width according to a second predetermined conversion mode to obtain the fourth data and the fifth data, and the fourth data is transmitted to the processor.

[0105] In one possible example, step 503 may be performed by calling a corresponding instruction stored in memory by the processor, or it may be performed by the second bit width conversion module described above.

[0106] In step 504, the fourth data and the fifth data are compared, and an error signal is output in response to a mismatch in the comparison results.

[0107] In one possible example, step 504 may be executed by calling a corresponding instruction stored in memory by the processor, or it may be executed by the read data verification module described above.

[0108] In one selectable embodiment, step 504, which compares the fourth data with the fifth data and outputs an error signal in response to a mismatch in the comparison results, may include a step of comparing the value of the nth bit of the fourth data with the value of the nth bit of the fifth data and outputs an error signal in response to a difference in the comparison results of any of the bits.

[0109] Figure 15 shows a flow chart of a processing method for memory access according to yet another exemplary embodiment of the present disclosure.

[0110] In one selectable embodiment, the method of the embodiment of the present disclosure may further include steps 610, 620.

[0111] In step 610, the process proceeds to the next flow after a first time delay for each set of third write access signals.

[0112] In one possible example, step 610 may be executed by calling a corresponding instruction stored in memory by the processor, or it may be executed by the first delay module described above.

[0113] In step 620, the process proceeds to the next flow after a first time delay in response to the second write access signal.

[0114] In one possible example, step 620 may be executed by calling a corresponding instruction stored in memory by the processor, or it may be executed by the second delay module described above.

[0115] In one selectable embodiment, step 303 converts each pair of third write access signals into two fourth write access signals that satisfy the memory protocol, and transmits each fourth write access signal to the corresponding memory module. The process may include the steps of transmitting a fourth write access signal corresponding to each set of third write access signals to a first memory module, and transmitting another fourth write access signal corresponding to each set of third write access signals to a second memory module.

[0116] In one selectable embodiment, step 303 converts each pair of third write access signals into two fourth write access signals that satisfy the memory protocol, and transmits each fourth write access signal to the corresponding memory module. The process may include generating an operating clock to trigger the transmission of a fourth write access signal to a first memory module corresponding to each pair of third write access signals, and another fourth write access signal to a second memory module corresponding to each pair of third write access signals.

[0117] In one selectable embodiment, step 303 converts each pair of third write access signals into two fourth write access signals that satisfy the memory protocol, and transmits each fourth write access signal to the corresponding memory module. The procedure may further include generating a reset signal when it is necessary to reset the first memory module and / or the second memory module, and transmitting this reset signal to the first memory module and / or the second memory module.

[0118] In one selectable embodiment, step 303 converts each pair of third write access signals into two fourth write access signals that satisfy the memory protocol, and transmits each fourth write access signal to the corresponding memory module. The step may further include monitoring and measuring the operating clock and / or reset signals, and outputting an alarm signal based on the monitoring and measurement results.

[0119] In one possible embodiment, step 301 is: The method may include the steps of: granulating the original data to be written contained in the first write access signal into a first bit width; duplicating the original data of each portion corresponding to the first bit width into two identical copies of the original data, and using these two identical copies as two consecutive target data of the first bit width, wherein the first bit width and the bit width of the data supported by the first protocol are the same; determining the target data to be written according to the order of the original data of each portion in the original data to be written for each target data corresponding to the original data of each portion; obtaining a target control signal by converting a signal representing the length of the original data to be written contained in the control signal of the first write access signal into a signal representing the length of the target data to be written; and determining a second write access signal based on the target data to be written and the target control signal.

[0120] The beneficial technical effects corresponding to exemplary embodiments of this method can be found by referring to the corresponding beneficial technical effects of the exemplary apparatus parts described above, and redundant explanations are omitted here.

[0121] The memory access processing methods according to embodiments of this disclosure can be executed by any suitable device having data processing capabilities, which may include, but are not limited to, terminal devices and servers. Alternatively, the memory access processing methods according to embodiments of the present invention can be executed by a processor, for example, by calling corresponding instructions stored in memory to execute the memory access processing methods mentioned in embodiments of this disclosure. Alternatively, any method according to embodiments of this disclosure can be executed by a hardware logic circuit device. Repetitive explanations are omitted below.

[0122] As those skilled in the art will understand, all or some of the steps of the embodiments of the above method can be completed by a program instructing the relevant hardware, the program can be stored in a computer-readable storage medium, and when the program is executed, the steps of the embodiments of the above method are performed, the storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks or optical disks.

[0123] [Example electronic device] Embodiments of this disclosure include memory for storing computer programs, Further providing an electronic device comprising a processor for executing a computer program stored in the memory, wherein when the computer program is executed, the method of any of the above embodiments of this disclosure is realized.

[0124] Alternatively, the electronic device may include the apparatus according to any of the above embodiments (i.e., an integrated circuit for memory access) to implement the method described in any of the above embodiments of the present disclosure.

[0125] Here, at least one module in the device is implemented by hardware logic circuits, or at least one unit in at least one module is implemented by hardware logic circuits.

[0126] To improve real-time performance, each module in the device, each unit within each module, and each subunit within each unit are all implemented using hardware logic circuits; in other words, the entire device is a hardware logic circuit.

[0127] Figure 16 shows the structure of one application embodiment of the electronic device of the present disclosure. In this embodiment, the electronic device 10 includes one or more processors 11 and memory 12.

[0128] The processor 11 can be a central processing unit (CPU) or another form of processing unit having data processing capability and / or instruction execution capability, and can control other components in the electronic device 10 to perform a desired function.

[0129] The memory 12 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may include, for example, random access memory (RAM) and / or cache memory. The non-volatile memory may include, for example, read-only memory (ROM), hard disks and flash memory. The computer-readable storage media may store one or more computer program instructions, and the processor 11 may execute the program instructions to realize the methods and / or other desired functions according to each embodiment of the present disclosure described above. The computer-readable storage media may also store various contents, such as input signals, signal components, and noise components.

[0130] As an example, the electronic device 10 may further include input devices 13 and output devices 14 connected to each other via a bus system and / or other forms of connection mechanisms (not shown).

[0131] Furthermore, this input device 13 may include, for example, a keyboard or a mouse.

[0132] This output device 14 can output various types of information to the outside. This output device may include, for example, a display, a speaker, a printer, a communication network, and remote output devices connected thereto.

[0133] For simplicity, Figure 16 shows only some of the components of the electronic device 10 relevant to this disclosure, omitting components such as buses and input / output interfaces. The electronic device 10 may further include any other suitable components depending on the specific application.

[0134] In one selectable embodiment, an electronic device can be provided that includes an integrated circuit for memory access according to the above embodiment or example, or an electronic device that further includes other related devices in addition to this electronic device, where redundant descriptions are omitted. At least one module in the integrated circuit is implemented by hardware logic circuits, or at least one unit in the at least one module is implemented by hardware logic circuits.

[0135] [Examples of computer program products and computer-readable storage media] The embodiments of this disclosure provide a computer program product that includes computer program instructions in addition to the above-described method and apparatus. When the computer program instructions are executed by a processor, the processor is caused to perform the steps in the methods relating to the various embodiments of this disclosure described in the “Exemplary Methods” portion of this specification.

[0136] Computer program products can be created using one or any combination of programming languages ​​to produce program code for performing the operations of the embodiments of this disclosure, including object-oriented programming languages ​​such as Java and C++, and traditional procedural programming languages ​​such as the C language or similar programming languages. The program code may run entirely on a user computing device, partially on a user device, run as a standalone software package, run partially on a user computing device and partially on a remote computing device, or run entirely on a remote computing device or a server.

[0137] Furthermore, embodiments of the present disclosure further provide a computer-readable storage medium in which computer program instructions are stored. When the computer program instructions are executed by a processor, the processor is caused to perform steps in the methods relating to various embodiments of the present disclosure as described in the “Exemplary Methods” portion of this specification.

[0138] The storage medium of this disclosure may also store data that needs to be stored by at least one hardware logic circuit of the protection device of the image data processing module described in the “Exemplary Device” portion of this disclosure, so that the hardware logic circuit can perform the corresponding function when in operation. For example, the storage medium may be a register of the hardware logic circuit that stores initial configuration data or data that needs to be stored during operation, but is not specifically limited. Here, at least one hardware logic circuit may be a hardware logic circuit of a module in the device, a hardware logic circuit of a unit in a module, or a hardware logic circuit of a subunit in a unit, but is not specifically limited.

[0139] Any combination of one or more readable media can be used as the computer-readable storage medium. The readable media can be a readable signal medium or a readable storage medium. The readable storage medium may include, but is not limited to, electrical, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any combination thereof. More specific examples (non-exclusive list) of readable storage media include electrical connections with one or more wires, portable disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the above.

[0140] While the basic principles of this disclosure have been explained above with reference to specific examples, the advantages, merits, and effects mentioned in this disclosure are merely illustrative and not limiting, and these advantages, merits, and effects are not necessarily present in every example of this disclosure. Furthermore, the specific details of the above disclosure are merely illustrative and easy-to-understand effects and are not limiting, and the above details do not necessarily limit this disclosure to being realized by the above specific details.

[0141] Those skilled in the art can make various modifications and alterations to this disclosure without departing from the spirit and scope of the present application. Thus, if such modifications and alterations of the present application fall within the claims of this disclosure and the equivalent art thereto, this disclosure also includes such modifications and alterations.

Claims

1. An integrated circuit for memory access, A first bit width conversion module for converting the original data to be written in the first write access signal of the processor into target data to be written, which includes two parts of the original data to be written, according to a first predetermined conversion mode, and for determining the converted second write access signal based on the target data to be written, A first memory control module connected to the first bit width conversion module, for converting the target write data in the second write access signal into at least one set of first write data satisfying a first protocol supported by the memory physical layer interface, and determining a corresponding set of third write access signals based on each set of the first write data, wherein each set of the first write data comprises two identical sets of first write data from two sets of the original write data, and each set of the third write access signals comprises two paths of the third write access signals, An integrated circuit for memory access, comprising: a memory physical layer interface connected to the first memory control module, which converts each pair of the third write access signals into two paths of fourth write access signals that satisfy a memory protocol, and transmits each of the fourth write access signals to the corresponding memory module.

2. The aforementioned integrated circuit is A second memory control module connected to the first bit width conversion module, for converting the target write data in the second write access signal into at least one set of second write data satisfying a first protocol supported by the memory physical layer interface, and determining a corresponding set of fifth write access signals based on each set of the second write data, wherein each set of the second write data comprises two identical sets of second write data from two sets of the original write data, and each set of the fifth write access signal comprises two paths of the fifth write access signal, The integrated circuit according to claim 1, further comprising: a first comparison module connected to the first memory control module and the second memory control module, respectively, for comparing each set of the third write access signals with each set of the fifth write access signals, and outputting an error signal in response to a mismatch in the comparison results.

3. The integrated circuit further includes a second bit width conversion module and a read data verification module, The memory physical layer interface further acquires at least one set of first data from the first memory module and the second memory module, converts each set of first data from the at least one set of first data into a set of second data that satisfies the first protocol, transmits each set of second data to the first memory control module, each set of first data includes first read data and second read data, and each set of second data includes third read data corresponding to the first read data and fourth read data corresponding to the second read data. The first memory control module further converts each set of the second data into third data that satisfies the second protocol supported by the second bit width conversion module, and transmits the third data to the second bit width conversion module. The second bit width conversion module performs bit width conversion on the third data according to a second predetermined conversion mode to obtain the fourth data and the fifth data, and transmits the fourth data to the processor. The integrated circuit according to claim 2, characterized in that the read data verification module compares the fourth data with the fifth data and outputs an error signal in response to a mismatch in the comparison results.

4. The aforementioned read data verification module is: A predetermined number of exclusive OR circuits, wherein the two inputs of the nth exclusive OR circuit are the nth bit value of the fourth data and the nth bit value of the fifth data, each exclusive OR circuit outputs 1 in response to the two input values ​​being different and outputs 0 in response to the two input values ​​being the same, and the predetermined number is the same as the bit width of the fourth data, The integrated circuit according to claim 3, wherein each input terminal is connected to the output terminal of each of the exclusive OR circuits, and the OR circuit includes an OR circuit that outputs an error signal in response to the output of any of the exclusive OR circuits being 1.

5. The aforementioned integrated circuit is A first delay module connected to the first memory control module and the first comparison module, respectively, for transmitting each set of the third write access signals output from the first memory control module to the first comparison module after a first time delay, The integrated circuit according to claim 2, further comprising: a second delay module connected to the first bit width conversion module and the second memory control module, respectively, for transmitting the second write access signal output from the first bit width conversion module to the second memory control module after delaying it by the first time.

6. The aforementioned memory physical layer interface is A first channel for transmitting one of the fourth write access signals corresponding to each set of the third write access signals to a first memory module corresponding to the first channel, A second channel for transmitting another fourth write access signal corresponding to each set of the third write access signals to a second memory module corresponding to the second channel, A control unit connected to the first channel and the second channel, respectively, for generating the operating clock and reset signals for the first channel and the second channel, The integrated circuit according to claim 1, characterized in that it includes a monitor connected to the control unit for monitoring and measuring the operating clock and / or reset signal, and for outputting an alarm signal based on the monitoring and measurement results.

7. The first bit width conversion module is, The original data to be written, contained in the first write access signal, is granulated into a first bit width; for the portion of the original data corresponding to each first bit width, this portion of the original data is duplicated into two identical copies; these two identical copies of data are used as two consecutive target data of the first bit width; and the first bit width and the bit width of the data supported by the first protocol are the same. For each part of the original data, the target data to be written is determined according to the order of the original data of each part in the original data to be written. The signal representing the length of the original data to be written, included in the control signal of the first write access signal, is converted into a signal representing the length of the target data to be written to obtain the target control signal. The integrated circuit according to claim 1, characterized in that the second write access signal is determined based on the target data to be written and the target control signal.

8. A method for processing memory access, wherein each step is performed by an integrated circuit for memory access, The process involves converting the original data to be written in the first write access signal of the processor into target data to be written, which includes two parts of the original data to be written, according to a first predetermined conversion mode, and determining a second write access signal after conversion based on the target data to be written. The steps include: converting the target data to be written in the second write access signal into at least one set of first data to be written that satisfy a first protocol supported by the memory physical layer interface; determining a corresponding set of third write access signals based on each set of the first data to be written, wherein each set of the first data to be written includes two identical sets of first data to be written from two sets of the original data to be written, and each set of third write access signals includes two paths of third write access signals; A method for processing memory access, comprising the steps of: converting each set of the third write access signals into two fourth write access signals that satisfy a memory protocol, and transmitting each of the fourth write access signals to the corresponding memory module.

9. A computer-readable storage medium, A computer-readable storage medium characterized in that, when executed by a processor, the storage medium stores a computer program for the processor to perform the steps of the memory access processing method described in claim 8.

10. Processor and An electronic device including a memory for storing instructions that the processor can execute, The processor reads the executable instruction from the memory, and the processor executes the executable instruction, thereby realizing the memory access processing method described in claim 8, or The electronic device includes an integrated circuit for memory access according to any one of claims 1 to 7. An electronic device characterized in that at least one module in the integrated circuit for memory access is implemented by a hardware logic circuit.

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