Systems and methods involving a uniform quantum computing model based on a virtual quantum processor

Abstract

The present innovation relates to systems and methods related to performing virtualized quantum processing. According to embodiments herein, an exemplary method may include initializing qubits with classical meta-information, initializing gate circuits between qubits with classical meta-information, processing a given quantum circuit by transforming all qubits with a unitary matrix, measuring the qubits to retrieve classical information, and processing the classical information, the method being preferably implemented via an information processing stack, comprised of a hardware layer, an operating system coupled to the hardware stack, and a container environment coupled to the operating system. In some implementations, the Bloch sphere is incorporated into the intermediate representation of the memory pattern in main memory such that the same associated state vector |ψ> is fully represented in the memory pattern along with the classical information |0> and |1>.

Description

Background Art

[0001] [Cross - reference to Related Applications] This international PCT patent application claims the benefit of U.S. Provisional Patent Application No. 63 / 195692, which is hereby incorporated by reference in its entirety.

[0002] Certain background art relates to the fields of computer science, quantum information theory, quantum physics, computer architecture, quantum processing, and / or memory components having their physical structures.

[0003] As background, conventional computers are mainly based on the theory of computation by Alan Turing and different architectural concepts such as those by John von Neumann. Thus, current computers used in many applications in industry and commercial products are essentially called Turing machines that convert a set of input states called data into a set of output states that are also data but are called the "result" or "solution" of the problem. Since a Turing machine can only sequentially execute mathematical functions hard - wired into the arithmetic - logic unit (ALU) of the central processing unit, the intermediate calculations that produce this conversion of data are called algorithms. Thus, the program itself consists of a set of so - called machine code that simply selects the functions of the ALU one after another. Such a program for a Turing machine can encode a mathematical problem, and if the Turing machine halts execution after a finite number of steps, the problem is solved by a finite result that is another set of data.

[0004] All Turing machines (such as the illustrative one shown in Figure 1) share the common characteristic of being able to be physically constructed using classical mechanics. In this way, Turing machines are highly predictable and theoretically deterministic, which is represented by the fact that a particular set of input data will always produce the same set of output data, regardless of how often the program is executed. Turing machines are also limited in their ability to execute program steps only one at a time in sequence. While it is possible to run more Turing machines in a row, as soon as they begin to interact with each other through data exchange, one Turing machine will need to wait for the results of the others.

[0005] A fundamental solution to this problem lies in new types of computing machines, such as neural networks or quantum computers. Quantum computers represent a completely different approach that overcomes the fundamental computational limitations of Turing machines, and are directly based on quantum mechanics rather than classical deterministic mechanics. Furthermore, in various cases, a hybrid quantum computer capable of both quantum and sequential decision algorithms may be desirable. An example of this type of related technology is described in International Publication No. 2020 / 106777. Various embodiments of such related technologies can be further illustrated with reference to the attached Figures 1-4. For example, Figure 1 is a block diagram of a known Turing machine. Figure 2 is a block diagram of a typical universal quantum machine, consistent with a typical aspect of a particular embodiment of this disclosure. Figure 3 is a block diagram of a typical hybrid quantum computer, consistent with a typical aspect of a particular embodiment of this disclosure. Figure 4 is a block diagram of a typical hybrid quantum processor, consistent with a typical aspect of a particular embodiment of this disclosure.

[0006] As mentioned above, several theoretical concepts of such machines have already been proposed and / or are known in relation to quantum computers, but several key achievements were still lacking to realize a commercially successful implementation of quantum computers. Firstly, there was a lack of technical solutions to the existing technical problems of quantum analogs to the computational classes of Turing machines, and a model of a universal quantum machine that defines their connection to classes of computational complexity. Secondly, there was a lack of physical implementation forms of hybrid quantum computers that also have technical solutions to the existing technical problems of cache coherence between different types of processing units, while maintaining the broad bandwidth of data exchange between them that is actually required to achieve quantum information processing. Various technical solutions regarding how to overcome both of these innovations and / or other shortcomings of known technologies are described herein. [Overview of the Initiative]

[0007] Systems and methods involving and / or relating to a uniform computation model are disclosed. In certain exemplary embodiments, typical uniform computation models based on hybrid quantum computing and hardware-independent features, functions, and / or processing may be made available / provided via a virtual quantum processor, etc., which is used to emulate a general-purpose hybrid quantum machine based on a set of instructions in a Turing machine. The systems and methods herein can utilize more general forms of implementation of hybrid quantum computing, for example, which are hardware-independent on the one hand, but still rely on the laws of nature that govern any future quantum computing system, regardless of its design excellence. The relevant embodiments and advantages are implemented here via a virtual quantum processor, which is hypothetical hardware, constructed to emulate a general-purpose hybrid quantum machine based on a set of instructions in a Turing machine. Once such a virtual quantum processor is established, hybrid quantum software is generated, which can later be applied to any physical representation of quantum computing hardware, but is already running on current machines. In some implementations, the Bloch sphere is incorporated into an intermediate representation of a memory pattern in main memory, such that the same associated state vector |ψ> is fully represented in the memory pattern along with the classical information |0> and |1>. [Brief explanation of the drawing]

[0008] Various embodiments of this disclosure can be further described with reference to the accompanying drawings, where similar structures are shown by similar numbers in several figures. The drawings shown are not necessarily to scale and instead focus on illustrating the principles of this disclosure. Accordingly, certain structural and functional details disclosed herein should not be construed as limitations, but merely as representative grounds to teach those skilled in the art how to utilize one or more exemplary embodiments in various ways. [Figure 1] This is a block diagram of a known Turing machine. [Figure 2]This is a typical block diagram of a universal quantum machine, consistent with a typical embodiment of a particular part of the present disclosure. [Figure 3] This is a typical block diagram of a hybrid quantum computer, consistent with a typical embodiment of a particular part of the present disclosure. [Figure 4] This is a block diagram of a typical hybrid quantum processor, consistent with a typical embodiment of a particular part of the present disclosure. [Figure 5] This is a typical block diagram of a block sphere, consistent with a typical embodiment of a particular part of the present disclosure. [Figure 6] This is a block diagram of a typical set of uniform information processing hardware, consistent with a typical embodiment of a particular part of the present disclosure. [Figure 7] This is a block diagram of a typical uniform information processing hardware stack, consistent with a typical embodiment of a particular part of the present disclosure. [Figure 8] This is a block diagram of a typical virtual processor instance, consistent with a typical embodiment of a particular part of the present disclosure. [Modes for carrying out the invention]

[0009] Various detailed embodiments of the present disclosure are disclosed herein in conjunction with the accompanying drawings. However, it should be understood that the embodiments disclosed are merely illustrative. In addition, each of the examples given in relation to the various embodiments of the present disclosure is intended to be illustrative, not restrictive.

[0010] Throughout this specification, the following terms have the meanings expressly relating to this specification unless the context clearly indicates otherwise. The phrases “in one embodiment” and “in some embodiments” as used herein may, but not necessarily, refer to the same embodiment. Furthermore, the phrases “in another embodiment” and “in some other embodiments” as used herein may, but not necessarily, refer to different embodiments. Thus, various embodiments can be readily combined without departing from the scope or spirit of this disclosure, as described below.

[0011] While other embodiments may be included, this disclosure focuses on a uniform computing model based on hardware-independent hybrid quantum computing. As described in more detail below and consistent with the disclosed technology, the systems and methods herein involve innovative use and / or incorporation of Turing machines to emulate virtual quantum processors, which are general representations of any physical implementation of such technology. To examine the foundations of Turing machines and quantum machines, quantum computing is first identified as a special application of quantum physics. Physicists established a very clear mathematical model of quantum physics within the 20th century, based on linear algebra in multidimensional complex vector spaces called Hilbert spaces, so it is known that at least such quantum physics can be computed on classical computers. This is done by computing matrices of floating-point representations, such as the IEEE 754 binary floating-point format, in software called a "quantum computing simulator." The term simulation as used herein refers to a representation of the so-called "Bloch sphere" of a Turing machine. A matrix representing the state vector of qubits is operated on with a specific set of classical operations for any superposition within the Turing machine, which means a two-angle shift of the state vector. In quantum computers, this is called a rotation gate on a single qubit, and ideally, it can be performed on any number of qubits in a single step. Turing machines can also parallelize superposition computations with such a linear extension of computational power. Therefore, quantum machines do not have a significant advantage.

[0012] Therefore, classical computers can replicate the calculations performed by quantum computers on their qubit state vectors and their connections to quantum gates, thus constructing so-called quantum circuits without error. The difference between classical and quantum computers, and the reason for operating quantum computers, is the native processing of quantum information, which scales exponentially better while computing these large matrices with entangled state vectors. Superposition of quantum information, i.e., single-qubit operations only, can actually be performed in classical computers with almost the same efficiency as in quantum computers. However, due to the possibility of entanglement of state vectors, the calculation of each matrix scales exponentially in computer time in a Turing machine, but not in a quantum machine.

[0013] 1. Technical Overview of Universal Quantum Machines The class of problems that can be solved by a Turing machine in polynomial time is called P, while the class of problems that can be solved by a universal quantum machine in polynomial time can be called QP. There is also a theoretical extension to the class of P by adding a probabilistic source to the Turing machine, which in turn makes it possible to generate truly random numbers, leading to a class of problems that can be solved by such a non-deterministic Turing machine in regressive time, called NP. It should be noted that there is no final theory of complexity classes yet, due to the fact that it is not determined whether P ≤ NP or NP ≤ QP. Furthermore, it is not yet possible to fully distinguish a universal quantum machine from a restricted quantum machine by a definition that can compute all possible quantum algorithms in the shortest possible computation time. Nevertheless, quantum information theory contains information about this puzzle, and quantum computers such as those described herein will help to elaborate on these subtle differences.

[0014] As shown in FIG. 2, the technology described herein can utilize and / or incorporate the following exemplary aspects or modes for a general model effective on any universal quantum machine. Further, aspects of this specification are based on the principle / insight that there is no true probabilistic source in the universe other than quantum effects and thus quantum algorithms. Considering this, the theoretical extension of a deterministic Turing machine by a probabilistic source ultimately results in a limited quantum machine. On the other hand, a deterministic process, by definition, can never generate a true probabilistic source. This leads to the conclusion that P must be <NP, since the task of generating true random numbers never halts on a deterministic Turing machine but can be easily achieved by a nondeterministic Turing machine. Since NP in that sense is a subset of QP, it is considered that QP > NP > P.

[0015] As explained in connection with FIGS. 1 and 2, the comparison of the architectures of a Turing machine and a universal quantum machine is described as follows. Referring to FIG. 1, such a Turing machine can include a conventional register 110 of bits that can be supplied directly from an external source of symbols (a set of symbol inputs) and then interpreted by the machine as program instructions or data. The language is rather simple, having commands for moving a memory band 120 (read / write - tape) connected to the register, as well as commands for writing or reading symbols on this band. The individual positions on the tape are clearly defined, and in computer terms, i.e., such positions are "addressable". Each process step of a computer program is temporally separated from the others by a clock 140 (cycle).

[0016] Apart from program commands for moving, reading, and writing tape at arbitrary positions, the arithmetic logic unit 130 (ALU) of a Turing machine can implement all necessary mathematical functions to perform all kinds of operations. More complex functions can be broken down into sets of simpler functions. This is where so-called deterministic Turing machines differ from non-deterministic ones. While deterministic Turing machines can only utilize functions that can produce only one specific output from a given input, non-deterministic Turing machines also possess relational capabilities and can therefore produce several versions of an output from only one set of inputs. The possible versions of the result that are selected are purely random and determined by an unpredictable probabilistic source. Thus, so-called non-deterministic Turing machines (NDTMs) must be understood not as the opposite of deterministic (DTM) variations, but as a relational extension thereto.

[0017] Returning to the technology described here, the embodiment may include and / or encompass the system / implementation form shown in Figure 2, thereby realizing a prototype of a universal quantum machine, enabling both quantum and sequential decision operations as well as non-deterministic algorithms.

[0018] Viewed from the outside as a black box, the exemplary universal quantum machine (UQM) shown in Figure 2 employs similar mechanisms to non-deterministic Turing machines (NDTMs), which also allow for ambiguous relationships. Therefore, different sets of outputs can be derived from the exact same set of inputs, making the results of the universal quantum machine partially unpredictable. An algorithm exists between the input and output sets that involves quantum relations.

[0019] Regarding the differences between a universal quantum machine and a Turing machine, the quantum information stored in the quantum register 210 (upper region of the figure) cannot be copied, unlike classical information, due to the no-cloning requirement imposed by quantum mechanics. This is because an interaction with the quantum machine is required to perform an input that invalidates, deletes, or discards the quantum information inside the register. However, the quantum register only stores quantum states that are discarded by such efforts.

[0020] Therefore, the quantum machine currently being described uses a classical read / write-tape 230 not only for outputting calculation results, but also for returning the values stored in the register, and for inclusion of input data. To execute a quantum algorithm, an appropriate physical process of "initialization", i.e., introduction, is first utilized to convert these classical, and thus deterministic, data sets into quantum states 260, herein referred to as qubits. These qubits are stored on a qubit tape 220 called "QBIT-TIE" in FIG. 2. In this way, classical bits become superposed qubits that can be directly read, written, and processed by the quantum register. The operation here is similar to that of a Turing machine, but a quantum algorithm 270 operates instead of a classical algorithm, and information exists on the qubits instead of data stored on classical bits. The quantum register allows entanglement of qubits, and the qubit tie provides superposition of qubits. As shown in the typical implementation form of FIG. 2, such entanglement may be provided via an entanglement component 212 within the quantum register 210, and such superposition may be provided via a superposition component 222 within the qubit tie calculation component 220.

[0021] Here, for legacy reasons, for example as a technical term, the expression "tape" is used in this specification, but it should be further noted that such a storage medium may include one or more memory technologies beyond conventional tape (e.g., magnetic) storage devices.

[0022] In order to issue a calculation result by such a quantum machine, it is not sufficient to simply read the read / write-tape output. As represented by the device symbols in FIG. 2, the reverse process of initialization, i.e., the measurement 250 of qubits, must be performed in advance. This measurement involves a probabilistic collapse of the superposition state occurring within the qubits according to their respective probabilities, which arise from the previously established quantum gates within the register and result in a partially deterministic and random classical output quantity called the output bit. These output bits are written onto a classical memory tape 230 equally (e.g., via such previously established quantum gates) by a Turing machine or the like and are thus available as a result or as a classical cache for the algorithm of the universal quantum machine. Therefore, it is clear that such a universal quantum machine can execute both classical algorithms and quantum algorithms and can thus emulate a Turing machine. In fact, most known quantum algorithms, such as those by Shore, use both classically configured functions and quantum functions.

[0023] As can be seen, the evidence establishes that the quantum machine described herein is universal, beyond any suggestion that, for example, not all existing quantum relationships have been discovered. First, all physical models that describe natural quantum systems in the universe are simply composed of superpositions and entanglements. Second, the inventors' research in quantum information technology (QIT) using its basic graph theory has shown that all possible arrangements of information stored in the universe are fully described by superpositions and entanglements. Therefore, the universal characteristics of the architecture shown in FIG. 2, i.e., the universal quantum machine, can be defined and established in this context.

[0024] 2. Physical Implementation Forms of Hybrid Quantum Computers To achieve and explain the realization of a universal quantum computer in a complete, rational, and concise manner, such a technique is described based on existing Turing machines, also known as servers, as well as the building blocks for the quantum section implemented in the quantum processor 360, as shown in Figure 3.

[0025] Figure 3 is a block diagram of a typical hybrid quantum computer 300, consistent with a typical aspect of a particular embodiment of the present disclosure. Referring to Figure 3, as shown in Figure 3, which also illustrates a typical high-level block diagram of a hybrid quantum computer, system elements including a pre-processing unit and a post-processing unit 330, and a Turing processor such as Novarion's Quanton® server, can be utilized to provide the classic part of the universal quantum machine, read / write-tape, which is implemented as a so-called PCI (Peripheral Component Interconnect) express bus 340 or PCIe.

[0026] To add a quantum computing unit by industrial means, the implementations described herein allow such a quantum computing unit to be incorporated into a quantum processing unit or QPU360. Depending on operational requirements, to combine the classical and quantum parts of a hybrid quantum computer—that is, to smoothly interconnect them and enable high performance and collaboration—the classical and quantum processors are arranged within a memory-centric computing architecture including a memory storage system 320, as shown in the typical system of Figure 3. In some implementations, such a memory storage system can be implemented via a specific storage system, namely Novarion's PlatinStor® storage system. Generally, such a memory storage system 320 may be provided with a non-volatile memory bank configured to be directly addressable by the PCIe bus simultaneously from both the pre-processing and post-processing units 330 and the hybrid quantum processor platform 310. A key feature of such a memory storage system 320, to prevent data loss during transfer, is built-in cache coherence, which notifies of writes only when data has been physically written and is available for physical read operations on another device. In this way, the memory storage system 320 is specifically designed to support the memory-centric computing platform required here, which is key to the overall functionality of the hybrid quantum computer introduced herein.

[0027] The exemplary architectural configuration of the hybrid quantum computer shown in Figure 3 can utilize existing industrial technologies such as different types of pre-processing and post-processing units 330 or Turing processors (e.g., Novarion's Quanton® processor), a memory storage system 320 (e.g., a non-volatile memory bank such as PlatinStor® mentioned above), and a PCIe bus 340 for connecting the build blocks. As shown in Figure 3, the pre-processing and post-processing units 330 or Turing processors may comprise the general components shown in Figure 1. Furthermore, in some embodiments, the pre-processing and post-processing units 330 or Turing processors may be configured to utilize all different types of classical processing units, particularly at least, but not exclusively, a central processing unit (CPU), a matrix processing unit (MPU), a graphics processing unit (GPU), or a neural network, as in Quanton®. Any type of XPU requires the use of an integrated memory controller within the pre-processing and post-processing units 330, which allows XPU components to access a centralized memory architecture provided by the memory storage system 320 via the PCIe bus.

[0028] Furthermore, while subcomponents of memory-centric computing platforms are being developed by the industry, it should be noted that aspects of this system and method may involve innovations arising as software and hardware functions around the PCIe bus, such as through the implementation of cache-coherent data flow between heterogeneous processing units (XPU, QPU) using a memory-centric architecture. In addition, it should be noted that both pre-processing and post-processing units 330 (such as the Quanton® server system) and memory storage systems 320 (such as PlatinStor®) have already been developed by Novarion for interrelated applications.

[0029] A hybrid quantum processor 310, also known as the IONICS computing platform, which aligns with this innovation, is one of the focuses of the invention currently described and may be connected to a memory-centric computing architecture via a PCIe bus 340, as shown in Figure 3. The hybrid quantum processor 300 incorporates multiple quantum processors connected by a novel optical quantum information interface (PQI) 350. One innovative component of the hybrid quantum processor is the quantum processor core 360, which functions as shown in Figure 2 and can be constructed as shown in Figure 4.

[0030] Figure 4 is a block diagram of a typical hybrid quantum processor 400, consistent with a typical aspect of a particular embodiment of the present disclosure. Referring to Figure 4, the illustrated architecture separates the classical computing unit from the quantum machine, i.e., quantum gates, which are arithmetic logic units (ALUs) 430 built on qubits, but connects them by a relatively high-performance and scalable bus system based on industry standards (PCIe). The hybrid quantum processor 400 comprises a bus control unit 410 (BCU), which may be mounted and connected on a printed circuit board (PCB)-motherboard and implemented as an integrated circuit (FPGA), and a gate creation unit 450 (GCRU), which translates electronic signals from the BCU to parameters for the ALU 430 in order to superimpose and entangle qubits.

[0031] The gate creation unit 450 and gate control unit 460 separate the bus control unit 410 from the quantum register and thus represent the qubit tie 220 between the classical bus control unit and the quantum register 430 containing the quantum gate, so such a hybrid quantum processor, as shown in Figure 4, for example, introduces a significant architectural difference compared to any other qubit implementation to date. In addition, the gate control unit 460 (GCU) performs operations on the qubits so that during the execution of quantum information transactions within the quantum gate 430, the qubits are not susceptible to disturbances that would otherwise cause errors. These qubit control functions are error correction operators, which can be implemented as state-of-the-art algorithms and can be programmed by the bus control unit as a firmware update to existing equipment of a hybrid quantum computer operating in a data center, for example.

[0032] The qubit initializer 420 creates a set of qubits up to the same number as the qubits 430 possessed by the quantum ALU and delivers quantum information to be input to the quantum gate 430. The results of the quantum information processing are retrieved by the qubit measurement unit 440 to the right of the quantum ALU (Q-ALU). The measurement results are transported to the bus control unit 410 (BCU), where they find the classical memory cache for further transfer via the PCIe bus to the classical memory-centric computing architecture and the classical processors to which they are attached. The quantum processors are synchronized by a clock 470 (cycles), which enables the generation, processing, and measurement of a large number of superimposed and entangled qubits per unit of time. Thus, the computing power of the hybrid quantum processor is highly scalable in both the number of entangled and superimposed qubits and the number of quantum computations per second.

[0033] The Q-ALU (qubit arithmetic logic unit 430) illustrated and described herein allows for all possible entangled and superposition states of a qubit. The qubit is inherent in quantum information and simultaneously defines the lattice of the quantum gate. These prerequisites allow the implementation described herein to incorporate representations of all possible quantum states and functions within the Q-ALU. Thus, this hybrid quantum processor is, in practice, a universal quantum machine as defined by the description in Section 1.

[0034] The control unit itself is a Turing machine and can therefore feed back classical information to the Q-ALU via the gate control unit. This feature can be used for instantaneous error correction, and furthermore, the quantum processor can autonomously execute an entire set of quantum algorithms and return the results to a classical processor in a server. The system and method described herein enable efficient use of PCIe bandwidth and avoid latency via the PCIe bus.

[0035] Since the PCIe system described herein is a bus system, the implementation described herein can connect two or more quantum processors of this type to several different conventional processors within a server. Furthermore, integration of all described parts on a single microchip may be carried out so that there is a high-speed connection between the quantum unit and the classical computing unit. Such integration is useful not only for servers in data centers, as exemplified herein, but also for embedded systems such as personal computers, smartphones, and automobiles and airplanes.

[0036] 3. Technical features / appearances for the implementation of hybrid quantum processors The inventors' existing knowledge in quantum information theory explains how quantum information systems (QIS) can be used as quantum computers. Below, for the first time, the conditions under which quantum information systems (QIS) can be implemented and used as high-performance quantum computers, and which principles are part of this invention, are explained. Concepts capitalized are known views.

[0037] First, the principle of decoherence and separation. The QIS used herein is self-contained, separate from the qubit initialization unit, gate creation unit, gate control unit, and qubit measurement system, so that other entities in the universe cannot influence or interact with the Q-ALU of the quantum processor.

[0038] Second: The Principle of Fidelity and Limitations According to the physical implementation described herein, the elements (particles) of the QIS that carry the quantum information—Q—qubits in the ALU—used in computations provide physical qualities that allow them to be superimposed and entangled simultaneously. Since the particles themselves consist of quantum information, according to quantum information theory, the particles can spontaneously superimpose and entangle. Therefore, the physical implementation of qubits is carried out such that the degrees of freedom of the entire QIS are restricted as much as possible to qubit operations on selected physical parameters. This limits possible errors during quantum computation, which is essential for the success of such implementations.

[0039] Third: The Principle of Complexity and Manifolds Theorists prefer that QIS be described by applying their known, highly functional theories in place, but the comprehensive power of this quantum arithmetic logic unit is unleashed by manifolds on different paths of superposition and entanglement. This means that current advanced quantum computing capabilities cannot be dealt with in explicit theoretical forms, like the description of the functionality of neural networks, but can be dealt with essentially at the structural level. Therefore, programming such a hybrid quantum computer requires not algorithmic definitions by software engineers, but rather mathematicians, "quantum gate developers," to construct the structure of the quantum arithmetic logic unit, which can then be autonomously introduced at any next step of computation by, for example, a quantum processor as described herein. Using this principle of manifolds in quantum gates, this quantum machine is a hardware virtualization entity where hardware and software change together with any application.

[0040] According to the inventor's theory of quantum information, a new understanding of entanglement and superposition phenomena has been introduced.

[0041] The inventors describe this resulting entanglement as the sharing of specific quantum information (QIS) between different entities in the universe. Therefore, even if the changes in the qubits occur independently at each of the parties involved, such as in a universal quantum computer, any physical process that alters the state of the qubits can be used to entangle them.

[0042] The inventors describe this superposition as the duplication of different quantum information on a single entity in the universe. Therefore, different quantum gates can be constructed simultaneously using the same qubits in a universal quantum computer.

[0043] 4. Physical construction blocks for qubits According to the given principles in Section 3 concerning the physical system used in this Q-ALU, namely separation, constraint, and manifold, various explicit examples of possible physical entities as building blocks for qubits are as follows:

[0044] Photons and electrons One of the most accurate theories humans have ever achieved is the theory of quantum electrodynamics (QED), which explains the interaction between photons and electrons. This is because, according to the aforementioned QIT, both particles represent the simplest building blocks of the universe, which fall under the constraints of the second principle. These particles are easy to provide and measure. Interestingly, the first attempts to realize quantum processing units with qubits did not choose these easy-to-handle electrons as carriers for the qubits, but instead opted for much more complex superconducting quantum circuits on wafers, which need to be cooled to near absolute zero in order to maintain some degree of decoherence time for the qubits that can be handled. In addition, the second principle is also very difficult to achieve in Q-ALU prototypes by IBM, Google, and D-Wave because the macroscopically close elements of integrated circuits simply have too many degrees of freedom. Thus, the considerable efforts of these companies to build a practical quantum processing unit have yet to be successful.

[0045] The implementations described herein concern the physical implementations of such quantum arithmetic logic units obtained as a result of three given principles, having magnetic or electrical properties, particles such as electrons, simple ions like Li+, Be+, H-, He+, or mere protons held within a force field, and having no other connection to the environment, but addressable by photons, electrons, and simple particles as well as quasiparticles.

[0046] The proton in the aforementioned QIT is the third simplest particle in the universe and therefore satisfies the fidelity requirement of the second principle. Thus, the implementations herein use the spin of the proton as a property for storing the quantum information of the qubit. This also applies to simple electrons. To satisfy the third principle of complexity with these very simple particles, the probability of a multi-reference-based spin system with a complex magnetic field is discussed (where the spin can not only move up and down but also have many overlapping directions). Magnetic fields are easy to control in integrated circuits even at room temperature and are strong enough even at their microscopic distances. In the aforementioned QIT, it has been shown that using these magnetic fields, a sun of such technology can establish many superposition and entanglement states on these simple, pure qubits. In this way, the qubit is much more compliant with the third principle.

[0047] Furthermore, it has been shown that the effect is achieved with electrons in high-temperature superconducting materials, allowing for easy cooling with liquid nitrogen instead of the powerful micro-Kelvin machines required in existing solutions.

[0048] Furthermore, according to the definitions of entanglement and superposition in Section 3, gate creation and gate control in this Q-ALU430 are performed using other quantum objects such as photons and quasiparticles coming from outside the Q-ALU. This allows the gate control unit to zero-measure and error-correct quantum states during quantum computation.

[0049] 5. Hybrid Quantum Processor Platform The theoretical configuration described in Figure 2, called the Universal Quantum Machine, and the block diagram of the Hybrid Quantum Processor in Figure 4 represent the first universal architecture with a practical implementation of any quantum computer. Since the structures of quantum gates can be implemented as arithmetic and logic functions within the Q-ALU 430, stored in the gate creation unit 450, selected by the bus control unit 410, and appropriately executed by the gate control unit 460, a ubiquitous set of quantum gate structures can be achieved using such a universal quantum computing system, which is referred herein to as the Hybrid Quantum Processor and related systems and platforms.

[0050] entanglement The human brain, as a product of evolution in the macroscopic world, is specialized to perceive information from the senses, compiling those senses with previous impressions and understanding them using pre-installed or learned algorithms that lead to a model of thinking and understanding the surrounding world, now called general intelligence. However, in reality, the so-called generality of the human psyche distances humans from the realm of quantum physics, the underlying realm of human conscious reality. As Richard Feynman famously said, "It would be fair to say that no one really understands quantum mechanics," humans, through human perception, are baffled by the strange behavior of quantum systems that remained unexplained throughout the 20th century.

[0051] For the computer engineering community, it is clear that in order to create something like a virtual quantum processor, which is identified as desirable to be implemented as the basis for hardware-independent hybrid quantum computing models, one must at least understand the difference between classical and quantum information.

[0052] Therefore, starting with what is known about quantum entanglement, and as one of the most important principles for speeding up computer calculations, the simplest system of quantum entangled states is a two-particle system with only two measurable qualities for each particle, which translates to a two-qubit system. Using the physical notation of bra and ket (e.g., bracket) vectors, as well as two possible results of measurements such as 0 and 1, the state S of the entangled system can be described as follows:

[0053] |S〉=α|00〉+β|11〉 (1)

[0054] Here, since α and β are normalized complex numbers, the sum of their complex conjugate squares is equal to the following unit:

[0055] αα * +ββ * =1 (2)

[0056] This is a quantum mechanical form to describe what happens when a measurement of a state |S> is taken. The result may not be what the "actual" quantum state is, but simply what the measuring device perceives. The concept of reality implies that what is being measured, rather than a previous quantum state, is contained in a superposition of possible measurement outcomes or may be entangled with other quantum systems. This definition of reality is due to the human brain, as a product of evolution, perceiving what is being measured by human senses. In fact, to measure the outcome of a quantum state, the measuring device must also be entangled with the quantum system in question. This is also why actual measurements cannot be simulated in a deterministic Turing machine (DTM) because the outcome is purely probabilistic. However, some physical (quantum) systems can be connected outside the DTM to take a non-causal input regarding the computation of any given stage of that program. As soon as such measurements are simulated, the probabilistic outcome of a state vector measurement can be determined using this truly random input, which extends the capabilities of the DTM to the non-deterministic. The normalization of the coefficients α and β in (2) makes these coefficients available to the so-called Copenhagen interpretation of quantum mechanics, since, when given states |00> and |11> are precisely measured, their complex conjugate squares are interpreted as the probabilities of possible outcomes. Although it may seem somewhat formal, the difference between the notation of quantum states in square brackets, such as |00>, and the corresponding measurement output 00 is enormous, as it distinguishes quantum spaces, which possess all the features of superposition, entanglement, non-locality, and non-causality, from classical, local, and causal reality. Therefore, this important difference in notation and perspective should be noted. Between |00> and 00 lies the measurement process, which is not only by technical means but also conceptual, and is a major step in improving system quality from the quantum information plane to the meta-information classical layer.

[0057] P(00) = αα * P(11) = ββ * P(01)=0 P(10)=0 (3)

[0058] In the language of information theory, we can say that a quantum system w is queried to determine which of these states can be presented to the measuring device. The quantum system's answer can then be derived from the interaction between the quantum system and the measuring device. In this interaction, both are forced into new quantum states, that is, both are changed simultaneously.

[0059] Here, state |S> in (1) is entangled because it is composed of two quantum systems, both of which can be states |0> and |1>. If they were not entangled, this would correspond to four possible outcomes of two independent quantum systems, namely |00>, |10>, |11>, and |01>. However, since quantum systems are represented by states |S>, they are completely entangled. This means that if one of the two systems is measured, the future of the other system is determined. For any subsequent measurement, as long as the same question is asked, the answer will be the same as for the previously measured quantum system, which means that the same quality of the system is being measured.

[0060] One thing about human perception is that this quantum mechanism of entanglement immediately works over arbitrary distances. However, this does not mean that quantum entanglement is strange and eerie, as Albert Einstein stated, but merely reminds humans of the functional principle of the human brain that obtains information only from measurements in space and time. This type of information is called classical, while information within the state vector of a quantum system, i.e., qubits, is distinguished as quantum information.

[0061] Quantum information These observations of quantum systems reveal a deep dependency between classical and quantum information. Therefore, the problem for the best technical implementation of a hybrid quantum computer should be derived from a precise understanding of the dependency between bits b of classical information and bits |b> of quantum information.

[0062] To extract b, |b> must be measured. In the so-called classical world, only b is perceived. However, in reality, everything in this universe, and humans, regardless of their size, are quantum systems. The only difference between the "macroscopic" world and the "microscopic" world is a distinction based on the size of the human body, and therefore purely subjective, but simply the number of quantum measurements per unit time, or particle interactions in the terms of classical physics. Thus, humans are accustomed to the countless quantum measurements that automatically occur within the macroscopic human body, which give humans an imagination of a smooth, analogous reality of a world consisting of features of any quantity. However, this is an illusion.

[0063] The same applies to computers. If it weren't for the fact of the automatically occurring interactions between elementary particles within integrated circuits, quantum computers should have been invented first to extract the classical information used for computation. However, integration efforts have led the technology to the point where the likelihood of interactions between electrons and crystal lattices within integrated circuits is reduced, leaving time for quantum effects, such as the undesirable tunneling of electrons through the insulated gates of MOSFETs.

[0064] As can be seen here, classical information does not exist without quantum information; therefore, classical information correlates with quantum information as metadata, but conversely, there are no restrictions. Apart from this distinction, classical information functions as a subset of quantum information. Since the concept of metadata is known in computer and data science, it now becomes much clearer how classical and quantum information should be handled within computational models. Just as the instruction set of a classical processor represents metadata for the data being processed, classical information represents metadata for the quantum information being processed. In practice, if a processor does not have the capability of both classical and / or qubit registers, there is no need to handle them separately. This insight has obvious fundamental implications for the development of future quantum processors, but it is also very useful for the following description of generalized hybrid quantum computing models.

[0065] Next, referring to Figure 5, a figure is shown showing a Bloch sphere 500, which is consistent with a typical embodiment of a particular part of the disclosed technology. In this exemplary embodiment, the Bloch sphere can be used to guide efforts by integrating classical and quantum computation. Here, for example, a quantum state represented by the vector |Ψ> retains only two possible classical values ​​after measurement, namely 0 and 1 in opposite directions along the z axis.

[0066] It is important to note that since only mutually exclusive 0 or 1 can be measured, the opposite directions of these represent orthogonal measurement results. In practice, any axis passing through the origin of the sphere can be measured, but this reflects rotational symmetry, so given examples are omnipresent. Another important point is that after measuring a qubit, there is a fundamental difference between the quantum states |0> and |1> at 112A and 112B, for the state vector |Ψ>111, and the classical states 0 and 1 of the bit. During quantum computation, the state vector can reach any point on the Bloch sphere without being measured. If this is, for example, |0>112A and the qubit is measured, a classical 0 can be obtained as the output. However, if the qubit is not measured, no classical information in space-time can be obtained. For any other location on the sphere where the angle θ is not zero, the probability of a 0 measurement P(0) is:

number

[0067] Therefore, this probability is equal to the proportion of the surface of the Bloch sphere below the latitude circle pointed to by |Ψ> and the complementary portion above it. In other words, the integral over all state vectors on the Bloch sphere is equal to unit 1. The physical implications of this are simply that if we ask the quantum system about its state, we will certainly get an answer. However, since probability always implies the ratio of some elements in a set to the set as a whole, the probability equations (3) and (4) have a more subtle character. Thus, the entire set of quantum information must be clear.

[0068] Third Quantization This characteristic of quantum information, while reflecting the simple fact that it is quantized, ultimately leads to important technical implications, first explained by Werner Heisenberg as the uncertainty principle.

[0069]

number

[0070] Here, σ' represents the standard deviation of energy (E) and time (t). As can be seen, these cannot be arbitrarily low because there is a small but finite limit set by half of Planck's constant. Energy and time are such complementary, or so to speak, standard conjugate variables in physics. The implications of this are precisely unfolded during the measurement process, and in the same measurement, we must be satisfied with a certain degree of precision for the result, which is classical information. This is a fundamental principle of the universe, not an imperfection in the measurement process that can be improved later. In other words, as long as the quantum system itself consists of a finite amount of energy and there is only a finite amount of time to measure it, the number of distinguishable results of a measurement of any quantum system is finite, and in any case, both obviously hold.

[0071] This ends the observation from the stochastic equations for qubit measurement. Furthermore, due to the uncertainty principle, we can only obtain a limited amount of classical information from a quantum system, and we can infer that the entire quantum system does not necessarily need to maintain more quantum states and then provide this amount of information. Naturally, assuming that the finite amount of quantum information that every particle, molecule, planet, star, or galaxy constitutes is the fundamental reason for the uncertainty principle and, by extension, for the quantization of information in general, up to human consciousness, sheds more light on all the mysteries of quantum information theory.

[0072] According to this theory, the number of quanta belonging to a quantum system can be calculated in the observable universe. As used herein, the concept of quantum is referred to as a fundamental property of the quantum field, as shown in quantum field theory. Traditionally, this number of quanta was not limited, but insights from quantum information theory allow us to derive a limit on the amount of information, so that a quantum system must be able to provide sufficient answers to possible measurement procedures. Because this information is quantized—the number of quanta is represented by the capital letter I—a minimum energy can be calculated, which means I=1 for a system in the observable universe, and its wave function can be observed because it is delimited by the perspective of a human observer and the event horizon. Such a particle or quantum has a wavelength (λ) from a human being to the event horizon formed by the Big Bang—or the starting point of cosmic evolution—as follows:

[0073]

number

[0074] Here, c represents the speed of light, H is the Hubble constant at the time of measurement, and the equation for energy (E) is the usual one with Planck's constant h and the frequency (v) of the wave function, which in this particular case is converted to H. In the ground state, I is equal to 1, and in the excited states, I follows a natural number.

[0075] Equation (6) shows that there is a clear relationship between any object in the universe as a field or quantum system, regardless of its appearance, which is represented by I and has an information quantity measured by natural number quanta. This may be called the third quantization, following the first quantization initiated by Erwin Schrödinger and his wave equation, and the second quantization produced by Paul Dirac as particle number representation and extended by quantum field theory as canonical quantization. The third quantization represents all physical values ​​of quanta, even with respect to space-time itself, since all physical objects represent a certain amount of energy.

[0076] Therefore, qubits are also quantized in essence, and the number of possible state vectors (I) is defined as follows:

[0077]

number

[0078] Here, ΔE defines a measurement within a qubit and represents the energy difference between two state vectors across the entire information space. It is worth noting that for such a physical qubit, or any quantum system, the Hilbert space can be transformed into a discrete equivalence using a third quantization.

[0079] Therefore, any measurement along the z-axis forces the quantum system (qubit) into one of the quantum states |0> or |1>. However, in contrast to mainstream 20th-century literature in which the term "wave function collapse" was coined, the qubit withstands its state vector, and therefore its wave function remains intact, but now identified after interaction with the measurement mechanism, and in fact both the qubit and the measurement mechanism remain entangled for a while until one of them faces another encounter with another gear in the quantum machine or the rest of the universe. Thus, if a qubit is measured to 0 and remains undisturbed thereafter, the next measurement should also be 0. In physical implementations of qubits, this can be different, but is then recognized as erroneous behavior of the qubit. The average time from the last 0 reading to this erroneous behavior is called T1.

[0080] Such errors occur frequently in the current physical qubit implementations of native quantum registers, but these are not addressed in the following description of a uniform quantum computing model in which quantum registers are assumed to be error-free. While these are ignored at this stage, the possibility of such undesirable influences from the rest of the universe into quantum computers is noteworthy and is described below.

[0081] virtual quantum processor In line with typical aspects of a particular embodiment of the disclosed technology, the motivations that can be summarized from the physical implementation forms of quantum processors may be twofold. Firstly, the limitations and erroneous behavior of native quantum registers are known to improve with advances in design and manufacturing. Similarly, these depend heavily on the topology of the qubits. While emulating such physical systems is useful, these examinations are unfounded in the field of high-performance gate-based quantum computing, as they do not determine what can be done in quantum computer simulators to mitigate these errors in future applications. Recently, another rule of quantum computing, so-called "analog" quantum computing, has been developed, which prepares a native quantum processor that retains all its errors as they are for computing very specific problems, but this is not considered a universal quantum computing system as a gate-based variant of the subject.

[0082] Secondly, all the functions of the quantum processor are integrated into a unified processor model so that any simulated part of the model, such as quantum registers, can be replaced at any time by a suitable physical implementation form without this being emulated and / or without changing any part of the entire computation stack described above. Both aspects focus on the development of a theoretically optimized high-performance universal quantum computing system, from which the necessary technical results can be better predicted, as when doing the reverse, which is what the industry is currently doing to find suitable applications for noisy medium-scale quantum computers (NISQ), which are the most advanced systems today.

[0083] Furthermore, this approach allows today's ready high-performance computing techniques to be used to implement this novel unified quantum computing model in their own way. The foundational preparation for this is insight into the nature of classical information as metainformation to quantum information, and its inherent behavior as it is formed during the measurement process. A third quantization insight enables the estimation of the required resolution of such virtual qubits in order to mimic the quantum system within a Turing machine.

[0084] According to (6) and (7), for example, an RF qubit with a 1 GHz range between its |0> state and |1> state can be attributed to approximately 2 to the power of 90 possible quantum states, or in other words, with 90 classical bits, a Turing machine can simulate a qubit (qubit) without loss of precision. Naturally, the actual readability of a physical qubit is orders of magnitude lower and therefore can be emulated much more easily. Turing pseudo-qubits with single (32-bit) or double (64-bit) precision floating-point representations are far superior to any of today's NISQ implementations.

[0085] In conclusion, both quantum images and classical information can be stored in classical memory. However, this alone does not constitute a quantum computer. Quantum computers and virtual quantum processors consistent with the techniques disclosed herein are further comprised for the following:

[0086] A. Initialize the qubit with classical metadata. B. Initialize the gate circuit between qubits using classical metadata. C. Processing a given quantum circuit by transforming all qubits with a unitary matrix. D. Measuring qubits to extract classical information E. Processing classical information

[0087] The literature sometimes refers to quantum Turing machines as deterministic Turing machines involving the exchange of classical discrete bit spaces by Hilbert spaces. However, this is insufficient. According to some typical aspects of certain embodiments of the disclosed technology, one of the novelties simplifies the simulation of qubit registers by fusing quantum images in classical memory with classical information. Naturally, classically stored quantum information cannot be processed by a native QPU, but can in practice be processed by a virtual QPU.

[0088] To leverage the exponential advantages of specific quantum algorithms, native QPUs must be integrated into such systems. Therefore, a typical technical solution provided herein is the uniform quantum computing model described herein, which allows applications to run in parallel on both, for example, embedded virtual processors and native quantum processors.

[0089] The second inaccuracy is the nondeterminism required for the measurement procedure. This can be implemented in today's high-performance deterministic Turing machines, as simple sensor readings in a chassis with varying bit lengths of qubit precision provide the appropriate randomness for measurement simulations.

[0090] Returning to Figure 2, a block diagram is shown illustrating a typical universal quantum machine, consistent with a typical aspect of a particular embodiment of the present disclosure. In this exemplary embodiment of Figure 2, for the sake of accuracy, a typical native QPU can be used, for example, by plugging into a typical model of a universal quantum machine as shown in Figure 2. Here, for the sake of accuracy with respect to the information-theoretic complexity of all or part of the functionality of the native quantum computer and its components, such a part of the native quantum processor may be replaced with a suitable simulation whose performance is optimized for, for example, advanced quantum-triggered computation (AQIC).

[0091] According to a typical aspect of a particular embodiment of the disclosed technology, a third feature of a native quantum computer not represented within the conventional Turing model is the measurement process. Here, the uniqueness of quantum information may be built into the universe. This means that when measuring a native qubit, it may affect / entangle its stored quantum information in order for the measuring instrument to perceive its metarepresentation as classical information. This is why native quantum information cannot be copied as its classical counterpart. Such a process of copying would be attributed to reading, which instantaneously alters the source. Of course, however, it is possible to copy a classical image of quantum information. It is possible to initialize a qubit according to the precision of the instrument with very high precision as a physical representation of the quantum information image in classical memory.

[0092] Under these embodiments, it is possible to create a near-copy mechanism for native quantum information, where the accuracy of the copy process is higher than gate fidelity and therefore serves as a sufficiently good approximation for a particular algorithm.

[0093] Based on the above features A through E, Figure 2 shows a typical resulting block diagram of such a universal quantum machine. Here, in this illustrated embodiment, the universal quantum machine may include parts other than the read / write tape 230(2A), which becomes the actual quantum processor. Using the read / write tape 230(2A), the universal quantum machine can process classical information and can therefore be considered a hybrid quantum processor.

[0094] For example, as mentioned above, according to the concepts and relationships between quantum and classical information, it is clear that classical algorithms are a subset of quantum algorithms. In a technical sense, we can use only their |0>|1> values ​​and the qubits of a quantum register, and thus we can represent the duality between qubits and classical bits.

[0095] Therefore, Figure 2 here shows a typical universal quantum machine, in fact, since it provides classical memory 230(2A) and quantum memory 220(2E), both of which can be technically implemented as random-access memory (RAM).

[0096] In some embodiments, as specified in feature A above, the components shown in, for example, 264(2D) and / or 260 initialize the random-access qubit memory (QRAM) 220(2E) by creating a specific state vector within each Bloch sphere, controlled by classical metadata that can, or simply represent, two degrees of freedom for each qubit, for example, two angles θ and Φ that define the point where the state vector touches the surface of the Bloch sphere.

[0097] In some embodiments, with respect to the requirements of feature B described above, this is represented, for example, by the relationship between QRAM220(2E) and quantum register 210(2B). With respect to feature c described above, the processing of the quantum gate in the quantum register can be timed with the cycle generator 240(2F). The measuring device 250(2C) can synchronously measure feature D described above, which is the qubit after processing of the quantum circuit, and store the classical value in RAM220(2A), which then terminates the quantum part of the computation and passes it on to the classical post-processing of feature E described above.

[0098] Referring now to Figure 4, a block diagram of a typical hybrid quantum processor 400 is shown, consistent with a typical aspect of a particular embodiment of the present disclosure. Here, in this exemplary embodiment, in a typical technical implementation of a quantum processing unit (QPU), the qubit 3E and quantum register 3B can be expected to exist within a single physical system, represented as a quantum gate 430. This is due to the fact that current quantum technology engineering skills are still insufficient to construct a reliable QRAM.

[0099] Furthermore, the gate creation unit 450(3G) and the gate control unit 460(3H) may be specific hardware implementations depending on the physical structure of the qubit, such as a LASER or microwave pulse generator.

[0100] In this example, the bus control unit 410(3A) can represent a classical cache memory and logic unit that performs pre-processing and / or post-processing for quantum circuits and connects the hybrid quantum processor to an external Turing machine that handles the demands of massive data transfer and storage to complement high-performance computing, because this is what a quantum computer is, for example, a high-performance information processing machine. To technically achieve this goal, a classically configured cluster (HPC) merges with the QPU in the next crucial step.

[0101] Uniform information processing As mentioned earlier, due to the current technological state, high-quality, high-speed quantum processing units have not yet been implemented in the era of noisy, medium-scale quantum computing (NISQ). Simulations of quantum computers on classical Turing machines are known to perform far better in real-world use cases than arbitrary physical quantum computing devices.

[0102] Despite the uncertainties surrounding the future development of such technologies, the relevant characteristics of such computing systems are described above. Since Turing machines are already very powerful, they can leverage both the enormous transactional computing speed of HPC and their inherent quantum information logic.

[0103] According to certain embodiments of the disclosed technology, aspects of the innovations herein may include and / or encompass a uniform quantum computing model. Consistent with some embodiments, for example, implementations can generally store classical information in conjunction with or together with (e.g., in association with) classical representations of quantum information in Bloch registers (BREGs) for computation of these BREGs in a virtual quantum processing unit (vQPU). In some implementations, the Bloch sphere is incorporated into an intermediate representation of a memory pattern in main memory such that the same associated state vector |ψ> is fully represented in the memory pattern along with the classical information |0> and |1>.

[0104] Referring now to Figure 6, a block diagram 600 of a typical set of homogeneous information processing hardware is shown, which is consistent with a typical aspect of a particular embodiment of the disclosed technology. According to a particular embodiment, the vQPU may comprise the same technical components as shown in Figure 4, but may also be implemented as software code in a large main memory of a Turing machine, as shown in Figure 6. In this typical homogeneous computing architecture, the main memory 610(4A) may be accessible by all and / or some of the processing units 620(4B) which differ in the same way and to the same degree. Each of the processing units 620 (e.g., a central processing unit (CPU), a graphical processing unit; an NMPU (neuromorphic processing unit); a GQPU (gate-based quantum processing unit (GPU); a quantum annealing processing unit (QAPU); a data processing unit (DPU), etc.)) may be either a physical implementation or a virtual processor. In some embodiments, a gate-based quantum processing unit may be analyzed as a virtual processor, while all others may be considered as physical implementations. However, it should be understood that the same logic can be followed for any other processing unit implemented as a virtual instance, though this is not limited to such implementations.

[0105] In some embodiments, such as those described here, the minimum typical physical requirements may include a central main memory 610(4A), at least one physical processing unit 620(4B) (the most advanced at present being CISC, RISC, and graphics processing architectures), a data processing unit 640(4D) having its bridging function between the internal and external systems, and a memory bus system 650(4E) between the physical processing unit 620(4B) and the main memory 610(4A). In some embodiments, such as those with underlying performance reasons, a cache coherency interconnect (CXL) 630(4C) may also be physical, but this is not required.

[0106] According to exemplary embodiments of specific embodiments of the disclosed technology, using this typical architecture, uniform computation models can generally be implemented in a highly efficient and high-performance manner, similar to models for hybrid quantum computing. All different types of processing units, as well as any possible type of quantum processing unit such as gate-based systems or annealing systems, can be integrated into various embodiments. In some implementations, physical types of qubit registers may be unsuitable for their function, and only performance and quality constraints pass through the computation stack shown in Figure 7.

[0107] According to certain embodiments of the disclosed technology, this is made possible by the previously common virtualization of the entire functionality of the quantum processor relating to any of the features A through E described above, which can be translated into an exemplary Turing machine instruction set as follows:

[0108] Referring to Figure 7, a block diagram 700 is shown illustrating a typical uniform information processing stack that corresponds to a typical aspect of a particular embodiment of the disclosed technology. The following features and functions are described in this illustrated embodiment:

[0109] A. Initialize the qubit with classical metadata. In some embodiments, this task may require a memory pattern transformation 720 to a Bloch register, for example. In implementations, current quantum circuit simulators can easily allocate main memory for storing linear matrices that are later computed in exponential time in the event of entanglement. However, this is not an optimized process with respect to the specific details of the quantum circuit. For example, the resolution depth of the qubit is 2 on the Bloch sphere. 64 From double precision, which means a number of distinguishable points, to a sufficient number, for example, 2 16 The number can be reduced to as few as 1. Such optimization parameters in the memory representation of quantum information may have to be provided as metadata from the application layer 750 to the internal core or operating system of the hybrid quantum operating system 770(5G) via the kernel scheduler API 740 in order to efficiently use the overall transactional computing power of the uniform quantum computing model. In some embodiments, the internal core or operating system 770(5G) may be an operating system comprising a processor kernel extension and virtual memory, preferably including a memory pattern transformation layer 720(5B) and kernel extension 730(5C). Furthermore, as will be described in relation to the typical implementation forms below, the container environment 760(5F) may include or encompass an application layer 750(5E), such as a hybrid quantum and neuromorphic application layer, preferably a kernel scheduler API having MPI overlay functionality, as shown in the typical embodiment of Figure 7.

[0110] B. Initialize the gate circuit between qubits using classical metadata. In such exemplary embodiments, the same kernel scheduler API 740(5D) can be used to transfer the classical metainformation required for the quantum gate circuit to the memory pattern conversion layer 720(5B). In some embodiments involving physical qubit registers, this information can be computed by the gate control unit 460(3H) of the native quantum processor in Figure 4. In some embodiments, when the quantum processor is virtual, the gate matrix may be constructed using this information in the main memory of the uniform quantum computer. In this way, the processor hardware can be implemented using an architecture independent of this typical computation stack, such as the kernel scheduler API described above.

[0111] C. Processing a given quantum circuit by transforming all qubits with a unitary matrix. In some embodiments, for a native quantum processor, this is the task of its arithmetic logic unit (ALU). Thus, a pseudo-QPU may utilize the same unit, however as a single piece of software within a processor kernel extension of a hybrid quantum computing operating system, which is run by the physical resources of a Turing machine, which are, for example, part or all of 710(5A) (e.g., memory, processing, and / or network connectivity resources). Regardless of the physical implementation, the application layer 750(5E) can leverage the MPI overlay functionality of the kernel scheduler, providing programmers with all the useful known methods of thread parallelization. This transforms the uniform quantum computing model into a real high-performance computing environment (HPC), where programmers can distribute applications and even tasks within a single application across any number of different processors, computing nodes on the same operating system 770(5G) running there. Through its processor kernel extension and virtual memory layer, programmers can utilize the entire amount of computing resources for a single application and optimize its behavior, involving the exchange of relevant metadata between the application and the hybrid quantum operating system.

[0112] D. Measuring qubits to extract classical information It is clear within the computer technology community that, in order to create something like a virtual quantum processor, which is identified as desirable to be implemented as the basis for hardware-independent hybrid quantum computing models, one must at least understand the difference between classical and quantum information.

[0113] In the case of a native QPU, this process is also physical, but kernel extensions of hybrid quantum operating systems can be configured, as described above, to enable analog procedures in a pseudo-environment through classical representations of quantum information. However, it should be noted that the memory pattern transformation 5B can only read state vectors. This is true and therefore a feature of advanced quantum-stimulated computing that saves time for certain algorithms such as quantum approximate optimization algorithms (QAOA). However, when building hybrid quantum applications that run simultaneously on both native and virtual QPUs, such an unfair classical advantage with respect to the native QPU must be withheld. However, on the other hand, the parallelization capabilities of the uniform quantum computing model allow the systems and methods described herein to function even better, running versions of the application that automatically use shortcuts in AQIC on the virtual QPU and simultaneously use a different version of the same algorithm on the native QPU.

[0114] E. Processing classical information Here, this feature is provided because a typical uniform quantum computing model represents a seamless fusion of classical and quantum computing resources at the information-theoretic level. However, it is worth mentioning that switching between sequences of classical and quantum information processing in the same computing thread is extremely fast because the data between such two operations does not need to move in large amounts of shared memory across all different instances of processing units called virtual processor instances (VPIs), and is very close to its theoretical minimum within a uniform information processing stack.

[0115] Virtual processor instance As described above, in some embodiments, the VPI can include a processor kernel extension, which is a memory representation of the structure of the processing unit, regardless of the physical implementation of such computing equipment. This can represent the essence of the functional structure of such a device, which is represented as software code within a high-performance Turing machine. On the one hand, the VPI should not be considered an emulation of a physical instance, as it does not reproduce its undesirable behavior, or in the case of a quantum processor, its erroneous behavior, while storing and processing quantum information. Indeed, the VPI is an idealization of the device it represents, but it includes all the functional aspects required of such a device. On the other hand, it is not a simulator either, as it only represents the functional structure of an idealized processing unit and not the complete computing system, which is actually a part of it.

[0116] Figure 8 is a block diagram 800 showing a typical virtual processor instance, consistent with a typical aspect of a particular embodiment of the disclosed technology. In this exemplary embodiment of Figure 8, the VPIs may be integrated into the computing environment. All of these VPIs for instances of 810(6A) may have access to all of the main (e.g., shared) memory 850(6E), as the architecture implies shared memory characteristics. Data transfer between computer components is handled by a suitable bus system 860(6F), e.g., direct memory access (DMA) via a memory channel or PCIe. Thus, the architecture belongs to the group of non-uniform memory access (NUMA) constructions. The functions run on hardware best suited to their type and support a non-moving data strategy of the Uniform Information Processing Model (UIPM), which also holds true for instruction codes. Subroutines are preferably invoked via remote procedure calls (RPCs). According to some embodiments, the VPI 810(6A) may be coherently constructed regardless of their physical implementation, which may differ significantly from the idealized structure represented, for example, within each kernel extension 730(5C) in Figure 7. Since each of these elements has direct memory access and terminates with the same software virtualization layer within the VPI, they can be used for high-performance parallelization methods such as the Message Communication Interface Standard MPI, used, for example, by the kernel scheduler API 740(5D) in Figure 7. This API allows applications running in parallel in a hybrid processing container environment 820(6B) to parallelize their threads toward a universe of virtual processing units on any many instances of the kernel scheduler API 830(6C), each of which is a node in the entire operating system. For example, such an operating system with the processor kernel extension and virtual memory 770(5G) in Figure 7 is the first of its kind in which a homogeneous hardware-independent abstraction (virtualization) layer extends to heterogeneous physical and virtual processing units.

[0117] In some embodiments, both the physical and virtual processing units are represented by VPI810(6A), which is within a functional memory pattern, and in some embodiments, comprises the following three main typical parts.

[0118] Multiprotocol driver (MPD) 870 (6G) In some embodiments, the MPD can not only function as a driver interface to the operating system 830(6C), but can also handle communication between the entire VPI and its two other internal components. In some examples, the MPD may be capable of converting between different protocols and function as a switch between the internal components of the VPI and an external system. The MPD may also maintain a cache for the virtual processing units, which may be built in memory if there is no physical implementation form of the VPI behind it, or it may map the physical cache of the physical (quantum) processing units into main memory, thus providing a system-wide cache coherency to a protocol such as Compute Express Link (CXL).

[0119] Metaprotocol Controller (MPC) 880 (6H) In some embodiments, the MPC handles metadata exchanged via the MPD and holds intermediate representations (IRs) for information processing structures, such as quantum assembly language (QASM) or quantum circuits using link patterns of neuron networks. This metadata can then be used to handle physical or virtual resources, such as qubits or neurons.

[0120] Arithmetic logic unit (ALU) 890(6I) In some embodiments, the ALU, like any processing unit, may be the core for logical and arithmetic operations performed between the processor's registers. In the case of a gate-based quantum processor, this may be a linear algebraic representation of matrix operations.

[0121] It should be understood that various typical and innovative systems and methods, including the uniform information processing model, are suitable for simulating quantum computers using other hardware such as graphical processing units (GPUs). In fact, such implementations can be used to implement algorithms written for specific hardware, which will result in entirely different things and what impact on performance. Furthermore, in some embodiments, the data processing unit 840(6D) can be used to connect many of these memory-centric computing nodes to a larger coherent central memory structure that can extend across an entire data center facility with thousands of nodes.

[0122] According to various embodiments of the disclosed technology, a new computing architecture for high-performance, highly scalable applications within data centers is a shift from, for example, today's execution-centric operating systems in HPC nodes, which differ from any processor type in their specific kernels, to a memory-centric operating system with kernel extensions for all kinds of processing units, which are presented homogeneously to the application layer and functionally stored in a single central memory. Today's software development frameworks are well-suited to supporting innovative operating systems and methods, and new libraries enable them to derive enormous advantages from hybrid (quantum) computing approaches.

[0123] According to various embodiments of the disclosed technology, while hardware advancements only contribute to faster applications, they are hidden by the intermediate representation of virtual processor instances, so that applications built on this novel, uniform information processing platform can run on subsequent versions. Furthermore, this does not prevent programmers from adding new features based on newer versions of hardware and operating systems, and these features are backward compatible with future generations of the system. This is a very promising feature for the industry, as it saves investments made in software development, which already far exceeds 1 trillion euros for the installed base used today, as has been done with the x86 architecture for over 40 years.

[0124] Furthermore, this novel uniform quantum computing model facilitates great potential for computational optimization of hard problems w, as it enables today's advanced quantum-inspired high-performance computing, which can be seamlessly converted to hybrid quantum computing without the need to rewrite software as soon as new quantum processor technologies become available for use in, for example, comprehensive data centers.

[0125] As described herein, unless otherwise disclosed, the implementations and features of the present invention can be implemented through computer hardware, software, and / or firmware. For example, the systems and methods disclosed herein, or their embodiments, parts, and / or components involved, may be embodied in various forms including one or more data processors such as computers, servers, etc., and may also include or access at least one database, digital electronic circuitry, firmware, software, or a combination thereof. Furthermore, while some of the disclosed implementations describe specific components (e.g., hardware), systems and methods consistent with the innovations herein can be implemented in any combination of hardware, software, and / or firmware. Moreover, the features and other embodiments and principles of the innovations herein can be implemented in various environments. Such environments and associated applications may be specifically constructed to perform various processes and operations according to the present invention, and / or embodiments may include general-purpose computers or computing platforms selectively invoked or reconfigured by code to provide specific features / functions.

[0126] In this specification, the use of certain terms such as components, modules, and devices may refer to various types of logic or functional devices, processes, or blocks that can be implemented in various ways. For example, the functions of various blocks may be combined with others and / or distributed within any number of other modules. For example, a particular module may be implemented as a software program stored in or associated tangible memory (e.g., random access memory, read-only memory, CD-ROM memory, hard disk drive) within the computation elements disclosed above, etc., to be read by a processing unit to implement the functions of the innovations of this specification. Alternatively, a module may be implemented as hardware, logic / circuits, etc., that implement the functions covered by the innovations of this specification. Finally, a module may be configured for use in embodiments such as dedicated instruction sets (SIMD instructions), field-programmable logic arrays, or combinations thereof, that provide a desired level of performance and cost.

[0127] Embodiments of the systems and methods described herein may be implemented as programmable functions in any of the various circuits, including field-programmable gate arrays (FPGAs), programmable array logic (PAL) devices, electrically programmable logic and memory devices, and programmable logic devices (PLDs) such as standard cell-based devices, as well as application-specific integrated circuits. Several other possibilities for implementing embodiments include memory devices, microcontrollers with memory (such as EEPROM), embedded microprocessors, firmware, and software. Furthermore, embodiments may be incorporated into software-based circuit simulations, discrete logic (sequential and combinatorial), custom devices, fuzzy logic, neural networks, other AI (artificial intelligence) or machine learning systems, quantum devices, and microprocessors having hybrids of any of the above device types.

[0128] It should also be noted that the various logics and / or features disclosed herein can be made effective as data and / or instructions embedded in various machine-readable or computer-readable media with respect to their behavior, register transfers, logic components, and / or other characteristics, using any number of combinations of hardware and firmware. Computer-readable media that can embed such formatted data and / or instructions include, but are not limited to, various forms of tangible non-volatile storage media (e.g., optical, magnetic, or semiconductor storage media), but do not encompass temporary media.

[0129] Other implementations of the present invention will become apparent to those skilled in the art from the considerations herein and the innovative practices disclosed herein. This specification and the examples are intended to be illustrative only, and the true scope and spirit of the invention are shown by this disclosure and the examples / technologies disclosed herein.

Claims

1. A virtual quantum computer system that includes a hardware-independent quantum computing model, Main memory (610) and One or more memory bus systems (650) coupled to the main memory (610), One or more physical processing units (620) having access to the main memory (610), A data processing unit (640) coupled to at least one of the one or more physical processing units (620), wherein the data processing unit (640) functions as a bridge between the internal and external systems of the virtual quantum computer system. One or more cache coherency interconnects (630) connecting one or more physical processing units (620), An information processing stack, The system comprises a hardware layer, an operating system coupled to the hardware layer, and a container environment coupled to the operating system. The aforementioned information processing stack, (A) Initialize the qubit with classical metadata, (B) Initialize the quantum gate circuit between the qubits with the classical metadata, (C) Process a given quantum circuit by transforming all qubits with a unitary matrix, (D) To extract classical information, measure the qubit, (E) Processing classical information It comprises an information processing stack configured as follows, When the application is executed, the information processing stack, The application is configured to run in parallel on both a virtual quantum processing unit (virtual QPU) and a native quantum processing unit (native QPU). A virtual quantum computer system.

2. The one or more cache coherency interconnects (630) comprises physical hardware components and / or The initialization of the qubit using classical metadata includes the step of performing a memory pattern transformation (720). The system according to claim 1.

3. Optimization parameters in the memory representation of quantum information are provided as metadata from the application layer (750) to the internal core of the operating system (770) via the kernel scheduler (API 5D) in order to efficiently utilize the overall transactional computing power of the information processing stack. The system according to claim 1 or 2.

4. The information processing stack is further configured to transfer the classical metadata required for the quantum gate circuit to a memory pattern conversion layer (720) associated with the operating system (770) via a kernel scheduler API (740, 830). The system according to claim 1 or 2.

5. The system further includes a physical qubit register, and the classical metadata required for the quantum gate circuit is computed by the gate control unit of the native quantum processor. The system according to claim 1 or 2.

6. The gate matrix in the main memory is constructed with the classical metadata required for the quantum gate circuit, so that the processor hardware is implemented in an architecture independent of the information processing stack. The system according to claim 1 or 2.

7. The hybrid quantum computing operating system further comprises a quantum processing unit (QPU) configured to utilize an arithmetic logic unit (ALU) as a piece of software within the processor kernel extension, The system according to claim 1 or 2.

8. The container environment (760) includes a kernel scheduler API having an MPI overlay function (740) that provides the programmer with known methods of thread parallelization so that the programmer can distribute applications and / or tasks within a single application across any number of different processors and compute nodes running the same version of the operating system (770). The system according to claim 1 or 2.

9. When the aforementioned application is running via the native QPU, The memory pattern conversion unit (720) is configured to read a state vector, and / or When the aforementioned application is running via a virtual QPU, the virtual quantum computer system is configured to automatically utilize advanced quantum-activated computation (AQIC) shortcuts. The system according to claim 1 or 2.

10. The aforementioned information processing stack uses virtual processor instances (VPIs) configured with processor kernel extensions to handle different native and virtual processes in shared memory. It is configured to store data used in the instance. The system according to claim 1 or 2.

11. The memory pattern within the main memory (720) itself functions as metadata for each processing unit to control the execution of processed data in order to realize cache coherency, implement a unique intermediate representation, or deliver topology dependency information to the processor's control unit. The system according to claim 1 or 2.

12. The Bloch sphere (100) is incorporated into an intermediate representation of the memory pattern in the main memory (720) such that the same state vector |ψ>(111) is fully represented in the memory pattern together with or in conjunction with the classical information |0> and |1>(112). The system according to claim 1 or 2.

13. The aforementioned information processing stack is It is configured to store data in shared memory and process the data using a virtual processor instance (VPI), and the VPI is Multiple subcomponents, including a multiprotocol driver (MPD) (870), a metaprotocol controller (MPC) (880), and an arithmetic logic unit (ALU) (890), A bus system (860) configured to provide the subcomponent with access to the shared memory within the main memory and to handle direct memory access (DMA) exchanges involving the subcomponent, It is a processor kernel extension that includes the following: The system according to claim 1 or 2.

14. The aforementioned multiprotocol driver (MPD) (870) It functions as a driver interface to the aforementioned operating system (830), It handles communication between subcomponents of a virtual processor instance (VPI), including the multiprotocol driver (MPD) (870), the metaprotocol controller (MPC) (880), and the arithmetic logic unit (ALU). Converting between different protocols, Switching between the VPI's subcomponents and the external system, and / or Holds a cache for the virtual processing unit. It is structured in such a way. The system according to claim 13.

15. The aforementioned virtual processing unit is If there is no physical implementation of the VPI, it is constructed by the multiprotocol driver in memory, and / or The physical cache of the physical (quantum) processing unit is mapped into the main memory, thereby providing overall cache coherence for the system. It is structured in such a way. The system according to claim 14.

16. The metaprotocol controller (880) is It is configured to handle metadata exchange via the multiprotocol driver (MPD) and to maintain an intermediate representation (IR) for the information processing structure of a quantum circuit. The system according to claim 14.

17. When the system utilizes a gate-based quantum processor, the arithmetic logic unit (ALU) (890) is configured to perform logical and arithmetic operations using linear algebraic representations with matrix operations. The system according to claim 14.

18. A method for a computer to perform virtualized quantum processing, wherein the method is The steps involve initializing the qubit with classical metadata, The steps include initializing the quantum gate circuit between the qubits with the classical metadata, A step of processing a given quantum circuit by transforming all the aforementioned qubits with a unitary matrix, A step of measuring the qubit in order to extract classical information, The step of processing the aforementioned classical information, The method is carried out via an information processing stack comprising a hardware layer, an operating system coupled to the hardware layer, and a container environment coupled to the operating system. When the application is executed, the information processing stack, The application is configured to run in parallel on both a virtual quantum processing unit (virtual QPU) and a native quantum processing unit (native QPU). method.

19. The processing of the aforementioned classical information is performed by a hardware-independent virtual hardware processor, and the virtual hardware processor is: Main memory (610) and One or more memory bus systems (650) coupled to the main memory (610), One or more physical processing units (620) having access to the main memory (610), A data processing unit (640) coupled to at least one of the one or more physical processing units (620), wherein the data processing unit (640) functions as a bridge between the internal and external systems of the virtual quantum computer system. One or more cache coherency interconnects (630) connecting one or more physical processing units (620), The aforementioned information processing stack, Implemented via the virtual quantum computer system comprising, The method according to claim 18.

20. The step further includes incorporating a Bloch sphere (100) into an intermediate representation of the memory pattern in the main memory (720) such that the same state vector |ψ>(111) is fully represented in the memory pattern together with or in conjunction with the classical information |0> and |1>(112). The method according to claim 19.

21. The further step includes implementing memory patterns in the main memory (720) to serve as metadata for each processing unit to control the execution of processed data, in order to achieve cache coherency, implement unique intermediate representations, or deliver topology-dependent information to the processor's control unit, The method according to claim 19.

22. The one or more cache coherence interconnects described above include physical hardware components. The method according to claim 19.

23. The initialization of the qubit using classical metadata includes the step of performing a memory pattern transformation (720). The method according to claim 18 or 19.

24. Optimization parameters for the memory representation of quantum information are provided as metadata from the application layer (750) to the internal core of the operating system (770) via the kernel scheduler API (740, 830). The method according to claim 18 or 19.

25. The information processing stack is further configured to transfer the classical metadata required for the quantum gate circuit to a memory pattern conversion layer (720) associated with the operating system (770) via a kernel scheduler API (740, 830). The method according to claim 18 or 19.

26. The aforementioned information processing stack is further configured for implementation using physical qubit registers, and the classical metadata required for the quantum gate circuit is computed by the gate control unit of the native quantum processor. The method according to claim 18 or 19.

27. The method is further carried out by a virtual quantum processor, wherein the gate matrix in the main memory is constructed with the classical metadata required for the quantum gate circuit, such that the processor hardware is implemented in an architecture independent of the information processing stack. The method according to claim 19.

28. The method described above is further carried out via a quantum processing unit (QPU) configured to utilize an arithmetic logic unit (ALU) as one piece of software within a processor kernel extension of a hybrid quantum computing operating system. The method according to claim 18 or 19.

29. The further step includes enabling the programmer to distribute applications and / or tasks within a single application across any number of different processors and compute nodes running the same version of the operating system (770) by implementing the container environment (760) using a kernel scheduler API having an MPI overlay function (740) that provides known methods for thread parallelization. The method according to claim 18 or 19.

30. When the aforementioned application is running via the native QPU, the memory pattern conversion unit (720) is configured to read the state vector, and / or When the aforementioned application is running via a virtual QPU, the virtual quantum computer system is configured to automatically utilize advanced quantum-activated computation (AQIC) shortcuts. The method according to claim 19.

31. The aforementioned information processing stack is configured to store data used by different instances of native and virtual processing in shared memory, using virtual processor instances (VPIs) configured with processor kernel extensions. The method according to claim 18 or 19.

32. The aforementioned information processing stack is It is configured to store data in shared memory and process the data using a virtual processor instance (VPI), and the VPI is Multiple subcomponents, including a multiprotocol driver (MPD) (870), a metaprotocol controller (MPC) (880), and an arithmetic logic unit (ALU) (890), A processor kernel extension comprising: a bus system (860) configured to provide the subcomponent with access to shared memory within the main memory and to handle direct memory access (DMA) exchanges involving the subcomponent; The method according to claim 19.

33. The aforementioned multiprotocol driver (MPD) (870) It functions as a driver interface to the aforementioned operating system (830), It handles communication between subcomponents of a virtual processor instance (VPI), including the multiprotocol driver (MPD) (870), the metaprotocol controller (MPC) (880), and the arithmetic logic unit (ALU). Converting between different protocols, Switching between the VPI's subcomponents and the external system, and / or It is configured to maintain a cache for the virtual processing unit. The method according to claim 32.

34. The aforementioned virtual processing unit is If there is no physical implementation of the VPI, it is constructed by the multiprotocol driver in memory, and / or The physical cache of the physical (quantum) processing unit is mapped into the main memory, and thus the system is configured to provide overall cache coherence for the virtual quantum computer system. The method according to claim 33.

35. The metaprotocol controller (880) is configured to handle metainformation exchange via the multiprotocol driver (MPD) and to hold an intermediate representation (IR) for the information processing structure of the quantum circuit. The method according to claim 33.

36. In an implementation utilizing a gate-based quantum processor, the arithmetic logic unit (ALU) (890) is configured to perform logical and arithmetic operations using linear algebraic representations with matrix operations. The method according to claim 33.

37. A virtual quantum computer system comprising one or more servers, computer processors, memory, and / or computer-readable media configured to constitute the system described in claim 1 or 2, A virtual quantum computer system.

38. One or more computer-readable media configured to include and / or execute computer-readable instructions, wherein, when executed by one or more processors, the computer-readable instructions include instructions that cause the one or more processors to perform the method according to claim 18 or 19. One or more computer-readable media.

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