A system and method for the automatic generation of standard cells using a satisfaction modulo theory solver.

Abstract

An electronic design automation tool and method for operating the same are provided for placement and routing of intracellular devices in an integrated circuit (IC). In general, the method includes receiving input; generating an instance of a placement and routing SMT problem by converting the input into a set of Satisfiability Modulo Theory (SMT) constraints related to placement of intracellular transistors and routing of interconnects to the intracellular transistors; invoking an SMT solver to use the set of SMT constraints and generate a solution to the SMT problem; and if the solution satisfies the requirements of the input and a predetermined area requirement specified by a user, generating and outputting a layout for placement and routing of intracellular transistors in the IC. The process may be repeated until a predetermined number of ranked solutions or an optimal solution is found. Other embodiments are also disclosed.

Description

Technical Field

[0001] Cross - reference to Related Applications This international application claims the benefit of priority from U.S. Provisional Patent Application No. 63 / 126,260, filed on December 16, 2020, which is incorporated herein by reference in its entirety for all purposes.

[0002] Technical Field This disclosure generally relates to integrated circuit design, and more particularly to electronic design automation (EDA) tools for the design, layout, and wiring of elements within complex circuits that include multi - layer transistors.

Background Art

[0003] Background The latest generation of integrated circuits (ICs) typically includes hundreds of millions or billions of circuit elements or components, and thus electronic design automation (EDA) tools, also known as electronic computer - aided design (ECAD), are essential for their design and verification prior to fabrication. During the standard cell library design process, a designer inputs an initial layout scheme or template for one or more cells within a circuit, along with a list of components (netlist), into an EDA tool and identifies a set of design requirements (technology design rules) for the layout. The EDA tool performs many functional tests or simulations to ensure that the design not only performs its intended function and generates many possible layouts or in - cell placements of components within the sub - circuits (or cells) of the IC, but also generates electrical connections or wirings between components within the cell. Next, the designer can review the list of possible layouts of the in - cell placement and the in - cell wiring and select the design that best meets the design criteria.

[0004] Figure 1A is a block diagram showing a template 102 for defining a single cell 104 (shown in Figures 1A, 1B) to be fabricated or printed on a semiconductor substrate or wafer. Typically, each cell 104 contains one or more electronic integrated circuit (IC) devices (such as transistors, capacitors, or resistors), each formed from many different patterned semiconductor layers, insulating layers, and conductive layers. The template defines several shapes of the various layers; most notably, the power rails to the cell are defined by a top shape representing VDD 106, i.e., the positive power supply pin, and a bottom shape representing VSS 108, GND, or the negative power supply pin. The rectangle surrounding the cell 104 defines the cell area and has a height 110 and a pitch or width 112. Anything outside the rectangle can be superimposed by adjacent cells. As shown in Figures 1B, 1C, generally, each cell 104 is a single-height cell, which may have the same height as the template shown in Figure 1A but a different width 112. As shown in Figure 1B, cell 104 uses 2 pitches, while the cell shown in Figure 1C uses 7 pitches. Referring to Figure 1D, the template definition allows the cells 104 to be aligned and in contact within row 114 after synthesis, and to be electrically coupled via one or more interconnection layers to constitute the design. This design is then "printed" onto the wafer.

[0005] While existing EDA tools and methods have worked well enough for designing circuits containing only single-height cells, it has been found that they pose problems for modern developments in IC design that involve or require the use of multi-height cells (also known as multi-row cells). Figure 1E is a block diagram showing one such multi-height cell with a total height equal to multiple (two or more) of the template height in Figure 1A. Currently, the process for designing cells (i.e., standard cell libraries) in ICs containing multi-height cells is still largely manual, with design engineers drawing individual polygons to represent each cell. As this is a manual effort, it is very time-consuming and prone to human error. Apart from the productivity drawbacks, there are also reduced quality and consistency (especially when designing ICs containing multi-height cells).

[0006] Therefore, there is a need for an EDA tool for designing ICs, including multi-height cells, that can generate objectively better layouts with improved metrics (such as reduced area, higher circuit density, or higher metal utilization within wiring layers, which may be less achievable by using existing EDA tools and manual methods). It is even more desirable that the EDA tool and the method of operating it provide higher productivity through reduced design time and improved consistency compared to previous manual methods. [Overview of the project] [Problems that the invention aims to solve]

[0007] overview The object of the present invention is to provide an electronic design automation tool and a method for operating it for the placement and routing of intracellular devices or transistors in an integrated circuit (IC) including multi-height cells, in order to increase productivity and improve the consistency of the resulting outcomes. [Means for solving the problem]

[0008] In one embodiment, the method includes receiving an input including a netlist, template definitions, and technology design rules; determining a placement solution based on the received input by converting the placement of transistors within a cell into a Satisfiability Modulo Theory (SMT) placement problem for the minimum area solution, calling an SMT solver, and generating a layout for the placement of transistors; and determining a wiring solution for transistors within a cell based on the received input and layout by converting the wiring of electrical connections between transistors within a cell into an SMT wiring problem for technology design rules, calling an SMT solver, and generating a layout for the placement and wiring of transistors within a cell. The method may further include repeating the determination of placement and wiring solutions a predetermined number of times or until a placement and wiring solution satisfying a predetermined metric is encountered, automatically ranking the generated placement and wiring solutions based on the predetermined metric, and outputting a list of ranked solutions.

[0009] In another embodiment, the method may be divided into two separate SMT problems and solutions, which include: a first SMT placement problem and solver of any choice for the placement of a predetermined number of transistors; and a second SMT placement and routing problem, which may use the solution to the first SMT placement problem to restrict the possible positions of the transistors. It will be understood that the overall solution time may be reduced by performing an SMT placement and routing problem that restricts the possible transistor positions to be located around the SMT placement provided by the first SMT instance.

[0010] In short, this method may include: (i) receiving an input; (ii) generating a first instance of an SMT placement problem by converting the input into a first set of SMT constraints relating to the arrangement of a predetermined number of intracellular transistors in the IC; (iii) calling a first SMT solver and generating a first solution to the SMT placement problem; (iv) if the first solution to the SMT placement problem satisfies the input requirements, generating a first instance of an SMT placement and routing problem by using the first solution to the SMT placement problem; and (v) calling a second SMT solver and generating a first solution to the SMT routing problem. If the first solution to the SMT routing problem satisfies the input requirements and user-defined area requirements, a first layout of intracellular transistor arrangement and routing in the IC is generated and output to the user. If the first solution to the SMT placement and routing problem does not satisfy the input requirements, the final, or latest, solution is invalidated, and another instance of the SMT placement problem is generated using the input requirements, the first SMT solver is called, and a second solution to the SMT placement problem is generated that is different from all previously discovered solutions. This second solution is then used to generate a second instance of the SMT placement and routing problem, the second SMT solver is called, and a second solution to the SMT placement and routing problem is generated.

[0011] Similar to the method described above, a method of using placement and routing for the same SMT instance (optionally having a limited transistor positioning) may further include repeating the determination of placement and routing solutions a predetermined number of times or until a placement and routing solution satisfying a predetermined metric is encountered, automatically ranking the generated placement and routing solutions based on the predetermined metric, and outputting a list of ranked solutions.

[0012] In another aspect, the present invention is further directed to a non-temporary computer-readable medium having program instructions for the arrangement and routing of intracellular transistors within an IC. Preferably, the computer-readable medium is stored in or in part within an electronic design automation (EDA) tool that includes at least one processor for executing the program instructions. Briefly, the computer-readable medium includes: program instructions for receiving inputs including a netlist, template definitions and technology design rules; program instructions for generating a first instance of an SMT problem for arrangement and routing by converting the inputs into a set of SMT constraints relating to the arrangement of a predetermined number of intracellular transistors and the routing of interconnections to a predetermined number of intracellular transistors; program instructions for calling an SMT solver, using the set of SMT constraints and generating a first solution to the SMT problem; and program instructions for generating and outputting a first layout for the arrangement and routing of intracellular transistors within an IC, provided that the first solution satisfies the input requirements and the user-defined area requirements.

[0013] Brief explanation of the drawing Embodiments of the present invention will be better understood from the detailed description that follows and from the accompanying drawings and claims provided herein. [Brief explanation of the drawing]

[0014] [Figure 1A] This is a block diagram showing a template for defining a single cell on a circuit board. [Figure 1B] This is a block diagram showing single-height cells, each having the same height as the template definition in Figure 1A but with different widths. [Figure 1C] This is a block diagram showing single-height cells, each having the same height as the template definition in Figure 1A but with different widths. [Figure 1D] This is a block diagram showing a predetermined number of cells arranged in a row on a substrate, each having the same height as the template definition. [Figure 1E]A block diagram showing a single multi-height cell having a total height equal to a plurality (two or more) of the template heights of FIG. 1A. [Figure 2] A simplified block diagram of a computer system or tool suitable for use by the EDA software and method of the present disclosure for the placement and wiring of intra-cell devices within an IC. [Figure 3] A simplified flowchart showing a process or method for the intra-cell placement of transistors according to an embodiment of the present disclosure. [Figure 4A] One embodiment of a schematic diagram of a circuit of a minimum placement example according to the method of FIG. 3. [Figure 4B] A graphic interpretation of an example of a model generated by an SMT solver according to the method of FIG. 3. [Figure 5] A simplified flowchart showing a process or method for intra-cell wiring within a cell according to an embodiment of the present disclosure. [Figure 6A] An embodiment of a placed layout and wiring grid of a minimum wiring example according to the method of FIG. 5. [Figure 6B] Shows the layout of the polysilicon layer of a minimum wiring example according to the method of FIG. 5. [Figure 6C] Shows the placement of vias within the via layer of a minimum wiring example according to the method of FIG. 5. [Figure 6D] Shows the layout of the metal layer of a minimum wiring example according to the method of FIG. 5. [Figure 7] A simplified flowchart showing the entire process or method for the intra-cell placement and intra-cell wiring of transistors within a cell according to an embodiment of the present disclosure. [Figure 8] A simplified flowchart showing a process or method for integrated placement and wiring within a cell according to an embodiment of the present disclosure. [Figure 9] One embodiment of a wiring grid for terminal candidates of a minimum integrated placement and wiring example according to the method of FIG. 8. [Figure 10] A simplified flowchart showing a process or method for integrated placement and wiring having restricted transistor positioning within a cell according to another embodiment of the present disclosure.

Best Mode for Carrying Out the Invention

[0015] Detailed Description An electronic design automation tool for the placement and wiring of intra-cell devices within an integrated circuit (IC) and a method of operating the same are provided.

[0016] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of the present invention. It will be apparent to one of ordinary skill in the art that the present invention may be practiced without these specific details. In other instances, well-known structures and techniques are shown in block diagram form in order to avoid unnecessarily obscuring the description of the present specification.

[0017] References in this specification to "one embodiment" or "an embodiment" mean that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment of the invention. Appearances of the phrase "in one embodiment" in various places in this specification are not necessarily all referring to the same embodiment. The term "coupled" as used herein may include both directly electrically connecting two or more components or elements and indirectly connecting them through one or more intervening components.

[0018] [[ID=二十一]]At a high level, the process of manufacturing an integrated circuit (IC) begins with a product idea, which is then realized in an iterative and generally labor-intensive design process using electronic design automation (EDA) software. Once the design is complete, fabrication processes and packaging and assembly processes are performed, ultimately resulting in a finished IC chip.

[0019] In short, the design process involves the designer describing the functions to be implemented, writing logic modules in the system design using high-level description language (HDL) code such as VHDL or Verilog, and checking the design to ensure that it produces the correct output in response to specific input stimuli. Next, the VHDL / Verilog code is converted into a netlist through a process called technology mapping, which takes a standard cell library as input, to construct the overall floor plan or layout of the chip, and then the placement or positioning of the circuit elements.

[0020] During the development of a standard cell library, positioning or placing devices within cells in an IC (in-cell placement) and routing connections between devices (in-cell routing) can be particularly problematic and time-consuming if the library includes multi-height cells (meaning cells with a total height equal to multiple (2 or more) of the template height).

[0021] Figure 2 is a simplified block diagram of a computer system or tool suitable for use by the EDA software and methods of this disclosure for the arrangement and routing of intra-cell devices in an IC including multi-height cells. Referring to Figure 2, the computer system 210 typically includes at least one processor 214 that communicates with many peripheral devices via a bus subsystem 212. These peripheral devices may include a storage subsystem 224, including a memory subsystem 226 and a file storage subsystem 228; a user interface input device 222; a user interface output device 220; and a network interface subsystem 216. The user interface input device and user interface output device enable user interaction with the computer system 210. The network interface subsystem 216 provides an interface to an external network, including an interface to a communication network 218, and is coupled to corresponding interface devices in other computer systems via the communication network 218. The communication network 218 may include many interconnected computer systems and communication links. These communication links may be wired links, optical links, wireless links, or any other mechanism for the transmission of information. In one embodiment, the communication network 218 is the Internet, but in other embodiments, the communication network 218 can be any suitable computer network.

[0022] The user interface input device 222 may include a keyboard; a pointing device such as a mouse, trackball, touchpad, or graphics tablet; a scanner; a touchscreen integrated into a display; an audio input device such as a speech recognition system; a microphone; and other types of input devices. Generally, the use of the term “input device” is intended to include all possible types of devices and methods for inputting information into the computer system 210 or onto the communication network 218.

[0023] The user interface output device 220 may include non-visual displays such as a display subsystem, printer, fax machine, or audio output device. The display subsystem may include planar panel devices such as a cathode ray tube (CRT), liquid crystal display (LCD), projection devices, or several other mechanisms for generating visible images. The display subsystem may also provide non-visual displays such as an audio output device. Generally, the use of the term “output device” is intended to include all possible types of devices and methods for outputting information from the computer system 210 to a user or another machine or computer system.

[0024] The storage subsystem 224 stores basic programming and data structures that provide all or some of the functionality of the EDA tools described herein (including netlist reduction technology and verification tools applied for the analysis of the reduced netlist). These software modules are typically executed by the processor 214.

[0025] The memory subsystem 226 typically includes a large amount of memory, including a main random access memory (RAM) 230 for storing instructions and data during program execution and a read-only memory (ROM) 232 for storing fixed instructions. The file storage subsystem 228 provides persistent storage for program and data files and may include a floppy disk drive, CD-ROM drive, optical drive, or removable media cartridge along with a hard disk drive and associated removable media. Databases and modules implementing the functions of some embodiments may be stored in the file storage subsystem 228.

[0026] The bus subsystem 212 provides a mechanism for various components and subsystems of the computer system 210 to communicate with each other as intended. Although the bus subsystem 212 is schematically shown as a single bus, alternative embodiments of the bus subsystem may use multiple buses.

[0027] The computer-readable medium 240 may be a medium associated with the file storage subsystem 228 and / or the network interface subsystem 216. The computer-readable medium may be a hard disk, floppy disk, CD-ROM, optical medium, removable media cartridge, or electromagnetic wave. A computer-readable medium 240 containing a circuit design 280 (including, for example, an HDL description of the circuit design and a reduced netlist generated by the described technology) is shown. Also shown is a circuit 290 generated by the described technology.

[0028] The computer system 210 itself can be of various types, including personal computers, portable computers, workstations, computer terminals, network computers, televisions, mainframes, or any other data processing systems or user devices. Due to the ever-changing nature of computers and networks, the description of the computer system 210 depicted in Figure 2 is intended merely as a specific example for the purpose of illustrating a preferred embodiment. Many other configurations of the computer system 210 are possible, possibly having more or fewer components than the computer system depicted in Figure 2.

[0029] Next, a process or method for in-cell placement of transistors according to embodiments of the present disclosure will be described with reference to the simplified flowchart in Figure 3. Referring to Figure 3, the method begins by converting a multi-height in-cell transistor placement problem of many components or subcircuits in a netlist into an SMT (sufficiency modulo theory) problem (step 302) using or from inputs provided by the designer (step 304). The provided inputs (all inputs via the user interface input device 222 and / or from the file storage subsystem 228) include a netlist (step 306), a template definition (step 308), and one or more technology design rules (step 310). Generally, the netlist specifies the parameters (including the area or footprint of each component), functions, and requirements of the circuit to be designed, and includes a list of electronic components available for use in the IC, and a list of nodes of components to be connected. Template definitions primarily define common features that apply to all cells in the library, such as horizontal and vertical pin pitch, cell height, and power rail features. Cells can include both single-height and multi-height cells. A multi-height cell is defined as a cell whose total height is equal to all (two or more) of the template heights. That is, each cell can contain multiple instances of a template that are iteratively formed adjacent to one another. Technology design rules specify constraints such as timing constraints and rules for minimum width or spacing between components.

[0030] In short, generating an SMT problem instance for placement (step 302) involves describing the circuit components and connectivity in a CDL (Circuit Description Language) format file, and defining a set of SMT constants (including integers and Boolean constants) for each component (transistor) that represent the component's position on a virtual grid. To define the grid size, the designer must indicate in the input (netlist 306) whether the intended layout includes single-height cells or multi-height cells.

[0031] After all inputs have been received (step 304) and an SMT problem instance for placement has been generated (step 302), an SMT solver or subroutine is called (step 312). Briefly, the SMT problem instance includes constraints to ensure that no two components or transistors are placed on the same grid coordinates, and to analyze the connectivity of components to avoid generating short circuits. The SMT solver may be any one of many available SMT solvers, including, for example, CVC3, MathSAT, Yices, or Z3.

[0032] A minimal example of how to generate an SMT problem instance for placement (step 302) and then call and execute the SMT solver is shown in Example A below.

[0033] Example A - Minimum Layout Example Consider an AND2 netlist consisting of three PMOS transistors and three NMOS transistors as connected inputs described by the following CDL format file snippet: .SUBCKT AND2 ABZ VDD VSS *.PININFO A:IB:IZ:O VDD:P VSS:G MT1 VDD A Zn VDD PMOS MT2 VDD B Zn VDD PMOS MT3 VDD Zn Z VDD PMOS MT4 N1 A Zn VSS NMOS MT5 VSS B N1 VSS NMOS MT6 VSS Zn Z VSS NMOS .ENDS

[0034] A schematic diagram of such a circuit is shown in Figure 4A. Referring to Figure 4A, the following set of SMT constants is defined for each transistor Tn: two integer constants (T_n_x and T_n_y) representing the position of the transistor on the virtual grid and its flip state, and one Boolean constant (T_n_f). The flip state is arbitrarily chosen such that it is false if the transistor's source pin is to the left of the drain pin, and true otherwise. For the above example, the declaration of the constants in the SMT2 file format would be as follows: (declare-const T_1_x int) (declare-const T_1_y int) (declare-const T_1_f Bool) (declare-const T_2_x int) (declare-const T_2_y int) (declare-const T_2_f Bool) (declare-const T_3_x int) (declare-const T_3_y int) (declare-const T_3_f Bool) (declare-const T_4_x Int) (declare-const T_4_y Int) (declare-const T_4_f Bool) (declare-const T_5_x Int) (declare-const T_5_y Int) (declare-const T_5_f Bool) (declare-const T_6_x Int) (declare-const T_6_y Int) (declare-const T_6_f Bool)

[0035] To ensure proper placement of transistors, it is stated that all X and Y positions will be within the given grid limits. To define the grid size, we must choose whether the intended layout is single-height or multi-height.

[0036] As an example of a single-height configuration, we define that all NMOS transistors are located across row 0 and all PMOS transistors are located across row 1. Furthermore, we define that a cell will have three or fewer rows of transistors, since it is known beforehand that three or fewer rows of transistors are sufficient for this circuit. The process of discovering such constraints can be performed as an optimization, either by using an optimization extension to the SMT2 language or by external iteration.

[0037] In this situation, the following SMT2 code will be generated: (assert(and(>=T_1_x 0)(<=T_1_x 2))) (assert(and(>=T_2_x 0)(<=T_2_x 2))) (assert(and(>=T_3_x 0)(<=T_3_x 2))) (assert(and(>=T_4_x 0)(<=T_4_x 2))) (assert(and(>=T_5_x 0)(<=T_5_x 2))) (assert(and(>=T_6_x 0)(<=T_6_x 2))) (assert(=T_1_y 1)) (assert(=T_2_y 1)) (assert(=T_3_y 1)) (assert(=T_4_y 0)) (assert(=T_5_y 0)) (assert(=T_6_y 0))

[0038] Another example is a dual-height cell where the NMOS transistor is located on either row 0 or row 3 and the PMOS transistor is located on either row 1 or row 2. In this case, the minimum number of columns required is 2, which generates the following SMT2 code: (assert(and(>=T_1_x0)(<=T_1_x1))) (assert(and(>=T_2_x0)(<=T_2_x1))) (assert(and(>=T_3_x0)(<=T_3_x1))) (assert(and(>=T_4_x0)(<=T_4_x1))) (assert(and(>=T_5_x0)(<=T_5_x1))) (assert(and(>=T_6_x0)(<=T_6_x1))) (assert(or(=T_1_y1)(=T_1_y2))) (assert(or(=T_2_y1)(=T_2_y2))) (assert(or(=T_3_y1)(=T_3_y2))) (assert(or(=T_4_y0)(=T_4_y3))) (assert(or(=T_5_y0)(=T_5_y3))) (assert(or(=T_6_y0)(=T_6_y3)))

[0039] Next, the following SMT2 code ensures that no two transistors can be located on the same coordinate system. Since PMOS and NMOS transistors do not share rows, they cannot overlap, and therefore, all pairs of transistors of the same type are declared to be in singular positions: (assert(not(and(=T_1_x T_2_x)(=T_1_y T_2_y)))) (assert(not(and(=T_1_x T_3_x)(=T_1_y T_3_y)))) (assert(not(and(=T_2_x T_3_x)(=T_2_y T_3_y)))) (assert(not(and(=T_4_x T_5_x)(=T_4_y T_5_y)))) (assert(not(and(=T_4_x T_6_x)(=T_4_y T_6_y)))) (assert(not(and(=T_5_x T_6_x)(=T_5_y T_6_y))))

[0040] Finally, to avoid generating short circuits, the connectivity of the transistors is analyzed, and the following SMT2 code ensures that, for a given circuit, it is recommended to contact the transistors only laterally if the shared diffusion belongs to the same net. (assert(implies(and(=T_1_y T_2_y)(=T_1_x(+T_2_x1)))(not(=T_1_f T_2_f)))) (assert(implies(and(=T_1_y T_2_y)(=T_2_x(+T_1_x1)))(not(=T_1_f T_2_f)))) (assert(implies(and(=T_1_y T_3_y)(=T_1_x(+T_3_x1)))(and(not T_1_f T_3_f))) (assert(implies(and(=T_1_y T_3_y)(=T_3_x(+T_1_x1)))(and T_1_f(not T_3_f))) (assert(implies(and(=T_2_y T_3_y)(=T_2_x(+T_3_x1)))(and (not T_2_f T_3_f))) (assert(implies(and(=T_2_y T_3_y)(=T_3_x(+T_2_x1)))(and T_2_f(not T_3_f)))) (assert(implies(and(=T_4_y T_5_y)(=T_4_x(+T_5_x 1)))(and(not T_4_f(not T_5_f)))) (assert(implies(and(=T_4_y T_5_y)(=T_5_x(+T_4_x1)))(and T_4_f T_5_f))) (assert(not(and(=T_4_y T_6_y)(=T_4_x(+T_6_x1))))) (assert(not(and(=T_4_y T_6_y)(=T_6_x(+T_4_x1))))) (assert(implies(and(=T_5_y T_6_y)(=T_5_x(+T_6_x1)))(and(not T_5_f) T_6_f))) (assert(implies (and(=T_5_y T_6_y)(=T_6_x(+T_5_x1)))(and T_5_f(not T_6_f))))

[0041] Additional constraints can be optionally coded either by restricting undesirable types of solutions or by reducing the symmetry of the problem. For example, the following SMT2 code declares: With respect to this circuit, vertically adjacent PMOS and NMOS transistors must share a gate net as follows: (assert(and(=T_1_x T_4_x)(=(abs(T_1_y T_4_y))1))) (assert(and(=T_2_x T_5_x)(=(abs(T_2_y T_5_y))1))) (assert(and(=T_3_x T_6_x)(=(abs(T_3_y T_6_y))1)))

[0042] After collecting the results from the SMT solver, we can evaluate the generated model to find the coordinates and flip state of each transistor, and the generated model, along with its dimensions and grid definition, can define the placed layout of a given circuit.

[0043] An example of a model generated by the single-height SMT solver described above may be the following: (model (define-fun T_1_f()Bool false) (define-fun T_1_x()Int 0) (define-fun T_1_y()Int 1) (define-fun T_2_f()Bool true) (define-fun T_2_x()Int 1) (define-fun T_2_y()Int 1) (define-fun T_3_f()Bool false) (define-fun T_3_x()Int 2) (define-fun T_3_y()Int 1) (define-fun T_4_f()Bool true) (define-fun T_4_x()Int 0) (define-fun T_4_y()Int 0) (define-fun T_5_f()Bool true) (define-fun T_5_x()Int 1) (define-fun T_5_y()Int 0) (define-fun T_6_f()Bool false) (define-fun T_6_x()Int 2) (define-fun T_6_y()Int 0))

[0044] This can be interpreted graphically, as shown in Figure 4B.

[0045] Next, referring again to Figure 3, a determination is made as to whether the solution by the SMT solver was successful or not (step 314). If it was not successful, the method for in-cell placement is terminated (step 316). However, if the identified solution was successful, that is, if none of the components overlap each other or if no connections that would create short circuits are required, the placed layout is generated using the netlist, template definition and technology design rules previously provided in the input step (step 304) (step 318), and is provided to the designer via the user interface output device 220 in the output step (step 320), and / or provided as input via the network interface subsystem 216 to a module or subroutine for implementing the method for in-cell routing described below with reference to Figure 4. Generally, as shown in Figure 3, the placed layout 322 may be one of a predetermined number of layouts provided to the module or subroutine for in-cell routing.

[0046] Next, the EDA software waits for the next predetermined number of components or subcircuits in the netlist (step 324), and the process continues by generating an SMT problem instance for the placement of the next circuit or next predetermined number of components in the netlist 306 with additional input from the previously generated placed layout 322 (step 302).

[0047] Next, a process or method for intra-cell routing within a cell containing multi-height components according to embodiments of the present disclosure will be described with reference to the simplified flowchart in Figure 5. Referring to Figure 5, the method begins by converting a routing problem of a placed layout in a design containing a predetermined number of multi-height components or transistors from an input to an SMT problem instance of routing (step 502) or by using it as an input to an SMT problem instance of routing (step 504), and then executing or calling an SMT solver or subroutine (step 512). Briefly, the SMT problem instance includes constraints to ensure that all terminals of the same net are connected but terminals of different nets are not connected, thereby avoiding short circuits. The SMT problem instance may also include code for executing design rules on the final routed layout. The input may include a placed layout derived using the method of Figure 3 (step 506), and the designer provides an input including a template definition (step 508) and one or more technology design rules (step 510). Similar to the method shown in Figure 3 described above, all inputs are provided or received via the user interface input device 222 and / or from the file storage subsystem 228.

[0048] A minimal example of how to generate an SMT problem instance for wiring (step 502) and then call and run the SMT solver (step 512) is shown in Example B below.

[0049] Example B - Minimal Wiring Example Given a layout with pre-placed transistors, the first step is to define a grid that fits the available routing resources. An example of a pre-placed layout and routing grid is shown in Figure 6A.

[0050] Each intersection in this grid is called a node, each dotted line connecting two intersections is called an edge, and each marked connection point with a dot is called a terminal.

[0051] In this example, the grid was chosen so that there could be one transistor every two columns. The top and bottom rows are reserved for power supply, and there are four inner wiring tracks.

[0052] In this example, since there are wiring layers of polysilicon and metal 1, this grid is repeated and stacked twice, and also generates edges between nodes across the entire layer representing the via layer. In this way, any node can be referred to as a 3D point (x,y,z) in the coordinate system, where x represents the column, y represents the row, and z represents the layer. In this example, layer 0 is polysilicon and layer 1 is metal 1. Any edge intersecting from layer 0 to layer 1 becomes a shape within the via layer.

[0053] Conversely, each edge can be referred to by three coordinates and one direction (north, south, east, west, up, down). For example, the edge (x,y,z, up) represents the edge between node (x,y,z) and node (x,y,z+1), or the edge (x,y,z, west) represents the edge connecting node (x-1,y,z) and node (x,y,z). By this definition, an edge exists connecting two nodes (x1,y1,z1) and (x2,y2,z2) only if one of the following criteria is true: |x1-x2|=1, y1=y2, and z1=z2 x1=x2, |y1-y2|=1, and z1=z2 x1=x2, y1=y2, and |z1-z2|=1

[0054] Nets are arbitrarily indexed by integer values, with 0 reserved for "no net". In this example, the possible representations are {0:no_net,1:VDD,2:VSS,3:A,4:B,5:N1,6:ZN,7:Z}.

[0055] If a net has three or more terminals, it is recommended to further decompose the net into subnets that connect pairs of terminals in a way that all terminals are joined by subnets. The minimum number of subnets required for a net is less than the number of terminals in that net. These subnets are also arbitrarily indexed by integer values. For example, net ZN has the following four terminals: {(0,1,0),(2,4,0),(5,1,0),(5,4,0)}. A possible pair of subnets is {0: {(0,1,0),(2,4,0)},1:{(2,4,0),(5,1,0)},2:{(5,1,0),(5,4,0)}}.

[0056] For each edge on the grid, the following set of SMT constants will be generated: a Boolean constant E_used indicating whether a wire exists on a given edge, an integer constant E_net indicating which nets are wired by edges (if used), and a bitvector constant E_subnet indicating which subnets of E_net are wired by edges (if used). Below is an example of SMT2 code for a typical edge where the maximum number of subnets in a net is 4: (declare-const E_used Bool) (declare-const E_net Int) (declare-const E_subnet(_BitVec 4))

[0057] Since net variables have limited valid values, there are constraints that restrict them. Nets can range from 0 to the number of nets (7 in our example). Below is an example of SMT2 code that defines these constraints on each edge: (assert (and(>=E_net0)(<=E_net7))) For each edge, if there is a net associated with that edge, that edge must be used: (assert(implies(>E_net0)E_used))

[0058] To ensure that no edges are associated with a subnet without being associated with a network, the following conditions must be added to all edges: (assert(implies(not(=E_subnet#b0000))(>E_net0)))

[0059] Next, connectivity must be coded similarly. Therefore, it is recommended to consider two different cases: if a node is a subnet terminal, then the number of edges connected to the node containing the subnet is exactly 1. As an example, consider a typical node with three connected edges (E1, E2, and E3) that is a terminal to net 7 and subnet 0. This could be coded in SMT2 as follows: (assert(let ((e1(ite(and(=E1_net7)(=(bvand E1_subnet#b0001)#b0001))1 0)) (e2(ite(and(=E2_net7)(=(bvand E2_subnet#b0001)#b0001))1 0)) (e3(ite(and(=E3_net7)(=(bvand E3_subnet#b0001)#b0001))1 0))) (or=(+e1 e2 e3)1)))

[0060] If a node is not a subnet terminal, the number of edges that E_subnet connects to the node containing the subnet is either 2 or 0. Following the same example as before, consider the case where the node is not a terminal for net 7 and subnet 0. (assert(let (e1(ite(and(=E1_net7)(=(bvand E1_subnet#b0001)#b0001))1 0)) (e2(ite(and(=E2_net7)(=(bvand E2_subnet#b0001)#b0001))1 0)) (e3(ite(and(=E3_net7)(=(bvand E3_subnet#b0001)#b0001))1 0))) (or(=(+e1 e2 e3)0)(=(+e1 e2 e3)2)))

[0061] Finally, to avoid short circuits, we must ensure that if two used edges intersect, they must be assigned to the same net. As an example, consider a node with three edges connected to it. The possible ways to encode this in SMT2 are as follows: (assert(implies E1_used(and (implies E2_used(=E_2_net E1_net)) (implies E3_used(=E_3_net E1_net))))) (assert(implies E2_used(and (implies E1_used(=E_1_net E2_net)) (implies E3_used(=E_3_net E2_net))))) (assert(implies E3_used(and (implies E1_used(=E_1_net E3_net)(implies E2_used(=E_2_net E3_net))))

[0062] Additional constraints, such as design rules or template definitions, can be similarly encoded. An example of this might be the definition of a power rail within a single layer of metal. In this case, every horizontal edge within the top row of layer 1 must be within net 1: (assert(=E_net 1))

[0063] After submitting the problem instance to the SMT solver engine, we can interpret the results by looking at the "used" variables for each edge. If the result is true, it indicates the existence of a wire between the locations corresponding to the two nodes that define that edge.

[0064] This result is correct, but it may have poor metrics such as wire length. After guaranteeing that a solution exists, we have the option to use an optimization engine to adjust the result according to a given cost function, if desired.

[0065] Finally, ports can be easily represented by adding an extra layer in which only one node connects from the layer directly below to all other nodes. This new layer is exempt from the constraint of short circuits.

[0066] An example of the output of the completed example can be interpreted and graphically shown in Figures 6B to 6D. Here, Figure 6B shows the layout of the polysilicon layer; Figure 6C shows the arrangement of vias within the via layer; and Figure 6D shows the layout of the metal layer.

[0067] Next, referring again to Figure 5, a determination is made as to whether the solution by the SMT solver was successful or not (step 514). If it is not successful, the cell routing method is terminated (step 516). However, if the identified solution was successful, that is, all required terminals are connected and no connections that would result in a short circuit, then the routed layout is generated using the placed layout, the template definition and technology design rules previously entered in the input process (step 504), and the placed and routed layout 520 provided in the output buffer 522 via the network interface subsystem 216 (step 518). Generally, as shown in Figure 5, the placed and routed layout 520 may be one of a predetermined number of layouts stored in the output buffer 522.

[0068] Next, the EDA software determines whether the desired number of results (placed and routed layout 520) have been achieved (step 524), and if not, the SMT problem instance for routing (step 502) is repeated for another placed layout 506 derived using the method of Figure 3. If the desired number of results are achieved, the intra-cell routing is completed and the process is terminated (step 526). The placed and routed layout 520 can then be output to the designer via the user interface output device 220 and / or to the computer-readable medium 240 via the network interface subsystem 216, as a readable medium for use as a standard cell library during the synthesis of designs in the IC design process.

[0069] Figure 7 is a simplified flowchart showing the entire process or method for intracellular placement and intracellular routing of transistors in a cell containing multi-height components according to embodiments of the present disclosure. Referring to Figure 7, the method begins with a request for a new transistor placement (step 702), which is achieved by using the method of Figure 3. Next, once the placed layout is complete (step 704), intracellular routing of the placed layout (step 706) is achieved by using the placed layout, template definition, and technology design rules previously entered in the input step (step 708) of the methods of Figures 3 and / or 4. If the placed layout is not complete, the process ends. Next, it is determined whether the routed layout for the new transistor placement is complete. If not, a new transistor placement is requested (step 702). If a wired layout is complete, this result is stored in the output process (step 714) (step 712), and if the desired number of results (i.e., layout 716) are achieved, a decision is made (step 718), and if not, a new transistor arrangement is requested (step 702), and this process is repeated for another arranged layout. If the desired number of results are achieved, this process is terminated (step 720).

[0070] Other embodiments of the entire process or method for the automatic placement and routing of intracellular transistors in an integrated circuit (IC) using program instructions stored in a non-temporary computer-readable medium and executed by using at least one processor are described below with reference to Figures 8 and 10.

[0071] Figure 8 is a simplified flowchart illustrating a process or method for integrated arrangement and routing within a cell according to embodiments of the present disclosure. Referring to Figure 8, the method begins by receiving an input 802 containing a netlist 804, a template definition 806, and one or more technology design rules 808. Optionally or preferably, the input may further include a predetermined area requirement 810 defined by the circuit designer or user. As in the embodiments described above, all inputs may be received via a user interface input device 222 and / or from a file storage subsystem 228. Generally, the netlist defines the function and requirements of the circuit to be designed and includes a list of electronic components and a list of nodes of components to which the electronic components connect. The template means, among many other things, common features that apply to all cells on the library (such as horizontal and vertical pin pitch, cell height, and power rail features). Cells may include both single-height and multi-height cells. A multi-height cell means a cell whose total height is equal to all or more (two or more) of the template heights. In other words, each cell may contain multiple instances of a template that are formed iteratively adjacent to one another. Technology design rules specify constraints such as minimum width or spacing rules between parts.

[0072] After all inputs have been entered, a single SMT problem instance for both placement and routing is generated (step 812). In short, generating the SMT problem instance for placement and routing involves translating or describing the circuit components and connectivity in a CDL (Circuit Description Language) format file and defining a set of SMT constants (including integer and Boolean constants) for each component (transistor) that represent the component's position on a virtual grid. To define the grid size, the designer must indicate in the input (netlist 804) whether the intended layout will include single-height cells or multi-height cells. This input also includes code that ensures appropriate connectivity and technology design rules that must be followed.

[0073] A minimal example of a method for generating an SMT problem instance for placement and routing is shown in Example C below.

[0074] Example C - Minimal Integrated Arrangement and Wiring Example In this example, the objective is to merge the ordering and routing problems into a single SMT problem. Therefore, given the input netlist, the SMT solver can either generate the routes and placed cells, or prove that such a result is impossible given the current netlist, routing grid, and technology-dependent parameters.

[0075] The main idea is to link the ordering algorithm and placement algorithm (presented in Examples A and B) in such a way that whenever a transistor is placed in a certain location due to ordering constraints, the routing constraints recognize this and guarantee the routing of its terminals. To make this link, the same ordering constraints presented in Example A are used, in addition to the special constants and constraints used for routing. These constants are defined for all possible locations within the routing grid where ordered transistor terminals may be placed. These locations will be called terminal candidates. Using the same routing grid as in Example B, an example of terminal candidate definitions is shown in Figure 9.

[0076] Referring to Figure 9, in this example, positions C1, C3, C5, C7, C8, C10, C12, and C14 are diffusion terminals, and the remaining positions are polysilicon terminals. For each terminal candidate, an integer constant is defined that indicates its current net. (declare-const C1_net Int) (declare-const C2_net Int) (declare-const C3_net Int) (declare-const C4_net Int) (declare-const C5_net Int) (declare-const C6_net Int) (declare-const C7_net Int) (declare-const C8_net Int) (declare-const C9_net Int) (declare-const C10_net Int) (declare-const C11_net Int) (declare-const C12_net Int) (declare-const C13_net Int) (declare-const C14_net Int)

[0077] In addition, an integer constant is needed to indicate which transistor is associated with each polysilicon terminal candidate: (declare-const C2_xtor Int) (declare-const C4_xtor Int) (declare-const C6_xtor Int) (declare-const C9_xtor Int) (declare-const C11_xtor Int) (declare-const C13_xtor Int)

[0078] Next, transistors are associated with ordering constants. For example, if transistor MT1 is placed at the ordering position (0,0) and is not inverted, then C2_xtor must be MT1, C1_net must be net VDD (net index 1), C2_net must be net A (net index 3), and C3_net must be ZN (net index 6). And: (assert(implies(and(=T_1_x0)(=T_1_y0)(=T_1_f false)) (and(=C2_xtor1)(=C1_net1)(=C2_net3)(=C3_net6)))

[0079] Similarly, if MT1 is in the same position but does not reverse: (assert(implies(and(=T_1_x0)(=T_1_y0)(=T_1_f true)) (and(=C2_xtor1)(=C1_net6)(=C2_net3)(=C3_net1)))

[0080] When MT1 is in the predetermined position (1,0), the terminals are mapped to C3, C4, and C5: (assert(implies(and(=T_1_x1)(=T_1_y0)(=T_1_f false)) (and(=C4_xtor1)(=C3_net1)(=C4_net3)(=C5_net6)) (assert(implies(and(=T_1_x1)(=T_1_y0)(=T_1_f true)) (and(=C4_xtor1)(=C3_net6)(=C4_net3)(=C5_net 1)))

[0081] To cover all possible orderings, similar constraints must be generated for every transistor, connecting each transistor to each candidate terminal it may occupy.

[0082] Regarding wiring constraints, the same constraints as those shown in Example B are used, with the following two differences excluded: (1) subnets are generated based on transistors instead of placed terminals; (2) connectivity constraints depend on candidate terminal constants.

[0083] If a net appears in three or more transistors in the input netlist, the net is further broken down into subnets that connect pairs of transistors in such a way that all transistors are coupled by subnets. The minimum number of subnets required for a net is less than the number of transistors that contain the net as a terminal. These subnets are also arbitrarily indexed by integer values. For example, net ZN appears in the following five transistors: {MT1, MT2, MT3, MT4, MT6}. The possible subnet pairs are {0:{MT1,MT2}, 1:{MT2,MT3}, 2:{MT4,MT6}, 3:{MT3,MT6}}.

[0084] The constraint for determining the degree of a node's edge to any subnet for each non-terminal candidate node remains the same as in Example B: that is, the degree must be either zero or 2. For terminal candidate nodes, on the other hand, the degree is defined based on the net assigned to that terminal by ordering constraints. For any subnet s, the degree of a candidate node to s must be 1 if the terminal is assigned to that net and the transistor belongs to s. For any other candidate node that does not conform to this explanation, the degree to s must be either zero or 2.

[0085] As an example, consider the subnetting constraints for net A (net index 3) and subnet polysilicon terminal candidate C2 between transistors MT1 and MT4. This degree must be 1 if C2 is assigned to net A and either transistor MT1 or MT4. Otherwise, this degree must be zero or 2. (assert(let ((subnet_degree(+ ; the side opposite to the west of C2 (ite(and(=E_010_110_net3)(=(bvand E_110_210_subnet#b0001)#b0001))1 0); ; the side opposite to the south of C2 (ite(and(=E_100_110_net3)(=(bvand E_200_210_subnet#b0001)#b0001))1 0) ; the side opposite to the east of C2 (ite(and(=E_110_210_net3)(=(bvand E_210_310_subnet#b0001)#b0001))1 0) ; the side opposite to the north of C2 (ite(and(=E_110_120_net3)(=(bvand E_210_220_subnet#b0001)#b0001))1 0) ; Via connecting C2 to the layer above it (ite(and(=E_110_111_net3)(=(bvand E_210_211_subnet#b0001)#b0001))1 0))) (ite(and(=C2_net3)(or(=C2_xtor1)(=C2_xtor4)) (=subnet_degree1)(or(=subnet_degree0)(=subnet_degree2)))))

[0086] Here, E_ijk_xyz_net represents the net constant associated with the edge connecting the nodes at positions (i,j,k) and (x,y,z). E_ijk_xyz_subnet is the subnet constant associated with the same edge.

[0087] Special care must be taken when dealing with spread terminals, as spread shared cases do not need to be wired. The following example defines the subnet degree for candidate terminals in a subnet between net N1 (net index 5) and transistors MT4 and MT5. If the transistor for left (C2_xtor) is MT4 and the transistor for right (C4_xtor) is MT5 (or vice versa), then this is a spread shared case, and therefore this subnet does not need to be wired, and the subnet degree is zero or 2. The only case in which this subnet needs to be wired is when only one of the transistors in the subnet is connected to the current spread. (assert(let (subnet_degree(+)) ; the side opposite to the west of C3 (ite(and(=E_110_210_net5)(=(bvand E_110_210_subnet#b0001)#b0001))1 0) ; the side opposite to the south of C3 (ite(and(=E_200_210_net5)(=(bvand E_200_210_subnet#b0001)#b0001))1 0) ; the side opposite to the east of C3 (ite(and(=E_210_310_net5)(=(bvand E_210_310_subnet#b0001)#b0001))1 0) ; the side opposite to the north of C3 (ite(and(=E_210_220_net5)(=(bvand E_210_220_subnet#b0001)#b0001))1 0) ; Via connecting C3 to the layer above it (ite(and(=E_210_211_net5) (=(bvand E_210_211_subnet#b0001)#b0001))1 0))) ) (ite(and(=C3_net5)) (=(+(ite(or (=C2_xtor4)(=C4_xtor4))) (ite(or(=C2_xtor5)(=C4_xtor5))))) 1)) (=subnet_degree1) (or(=subnet_degree0)(=subnet_degree2)

[0088] To ensure that all networks are properly wired, similar subnet constraints must be generated for each subnet of each network in the input netlist, for each candidate terminal.

[0089] Once a solution is found by the SMT solver, the ordering and arrangement results can be interpreted by reading the constant results in the same way as described in Examples A and B.

[0090] After all inputs 802 have been input and an SMT problem instance for placement and routing has been generated (step 812), the SMT solver or subroutine is called and a solution is generated (step 814). In short, the SMT solver includes constraints to ensure that no two components or transistors are placed on the same grid coordinates and to analyze the connectivity of components to avoid generating short circuits.

[0091] Next, it is determined whether the solution obtained by the SMT solver was successful (step 816). The solution is successful if it satisfies the input requirements and the user-defined area requirements. If it is not successful, the process terminates and the user is notified. However, if the identified solution was successful, that is, if no components overlap or connections that would create short circuits are required, the IC layout 820, including both wired and placed cell transistors, is generated using the previously provided netlist, template definition and technology design rules (step 818) and output to the designer via the user interface output device 220 in the output process (step 822).

[0092] In some embodiments, once a solution satisfying the input requirements and predetermined area requirements is found, the layout associated with this solution is communicated to the user, the method terminates, and the SMT solver is not invoked again in an attempt to find another, more optimal solution that satisfies the input requirements and predetermined area requirements.

[0093] In other embodiments, as shown in Figure 8, the placed layout 820 is one of a predetermined number of generated layouts and is output to the user in the output process (step 822). Generally, in these embodiments, after a layout is generated (step 818), a determination is made as to whether a desired number of results (i.e., layouts) have been achieved (step 824). If the desired number of results or layouts have not been achieved and the latest solution does not satisfy the input requirements, the final i.e., latest solution is invalidated, and another instance of the SMT placement problem is generated using the input requirements (step 812), the SMT solver is called (step 814), and another solution to the SMT placement problem is generated that is different from all previously discovered solutions. This process is repeated until a predetermined number of layouts are generated and / or at least one solution satisfies the input requirements and predetermined area requirements. Another layout is generated (step 816) and output (step 822).

[0094] Optionally, in one embodiment, the method may further include determining the optimal solution from the generated and outputted layouts 820 based on, for example, the area required for the IC, the complexity of the layout (such as the number of masks required to fabricate the circuit), or a netlist or technology design rules, and identifying the layouts related to the optimal solution for the user.

[0095] In other embodiments, the method may further include ranking the generated layouts 820 and outputting a list of ranked solutions based on predetermined metrics including the area required for the layout, the number of masks required to fabricate the circuit, and / or the performance of the ICs.

[0096] Figure 10 is a simplified flowchart illustrating another process or method of integrated placement and routing with restricted transistor positioning within a cell according to other embodiments of the present disclosure. Referring to Figure 10, the method begins by receiving an input 1002 which includes a netlist 1004, a template definition 1006, and one or more technology design rules 1008. Optionally or preferably, the input may further include a predetermined area requirement 1010 defined by the circuit designer or user. As with the embodiments described above, all inputs may be received via a user interface input device 222 and / or from a file storage subsystem 228. Generally, the netlist defines the function and requirements of the circuit to be designed and includes a list of electronic components and a list of nodes of components to which the electronic components connect. The template implies, among many other, common features that apply to all cells on the library (such as horizontal and vertical pin pitch, cell height, and power rail features). Cells may include both single-height and multi-height cells. A multi-height cell means a cell whose total height is equal to all (two or more) of the template heights. That is, each cell may contain multiple instances of a template that are formed iteratively adjacent to each other. Technology design rules specify constraints such as minimum width or spacing rules between parts.

[0097] After all inputs have been entered, an instance of the SMT placement problem (SMT placement problem) is generated (step 1012). In short, generating an instance of the SMT placement problem involves translating or describing components in a CDL (Circuit Description Language) format file and defining a set of SMT constants (including integer and Boolean constants) for each component (transistor) that represent the component's position on the virtual grid. To define the grid size, the designer must indicate in the input (netlist 1004) whether the intended layout includes single-height cells or multi-height cells.

[0098] After all inputs 1002 have been input, an SMT problem instance of placement is generated (step 1012), a first SMT solver or subroutine is called, and a solution is generated (step 1014). In short, a first SMT instance, such as the SMT instance described above, may include constraints to ensure that no two components or transistors are placed on the same grid coordinates.

[0099] Next, it is determined whether the solution found by the first SMT solver is successful (step 1016). The solution is successful if none of the placed components or transistors overlap, and if the input requirements and the user-defined area requirements are satisfied. If it is not successful, the method is terminated and the user is notified.

[0100] If the identified solution is successful, an SMT problem instance of the arrangement and routing with restricted arrangements is generated (step 1018), a second SMT solver or subroutine is called, and a solution is generated (step 1020). Briefly, a second SMT instance, such as the SMT instance described above, may include constraints to ensure that no two components or transistors are placed on the same grid coordinates, and to analyze the connectivity of components to avoid generating short circuits. Restricted arrangements mean that the SMT problem instance allows the restricted arrangements of components or transistors to be successfully arranged by the solution generated in step 1014 with some additional degrees of freedom. For example, the acceptable final transistor position may be the original position, the original position shifted one pitch to the left, or the original position shifted one pitch to the right. It should be noted that this embodiment is illustrative and other constraints may be used.

[0101] Next, it is determined whether the solution found by the second SMT solver was successful (step 1012). The solution is successful if none of the components are superimposed, no connections that would create short circuits are required, and the solution satisfies all input requirements and user-defined domain requirements.

[0102] If the solution to the SMT problem instance for the layout and routing with restricted arrangement is not successful, another instance of the SMT problem layout is generated (step 1012), the first SMT solver is called, and a new restricted arrangement solution is generated (step 1014). If the new solution to the layout is successful (i.e., no components or transistors overlap and the input and area requirements are satisfied), and another SMT problem instance for the layout and routing with restricted arrangement is generated (step 1018), the second SMT solver is called, and a new solution is generated (step 1020).

[0103] If the solution is successful, the layout 1026 of the IC, including both wired and placed cell transistors, is generated using the previously provided netlist, template definition and technology design rules (step 1024), and then output to the designer via the user interface output device 220 in the output step (step 1028).

[0104] A minimal example of a method for generating an SMT problem instance of placement and routing with restricted transistor positioning is shown in Example D below.

[0105] Example D - Minimal Integrated Arrangement and Wiring Example with Restricted Transistor Motion The objective of this algorithm is to find a wireable order given a netlist with an initial order, while allowing the solver to deviate from the initial order to some extent. In fact, this is achieved by using the algorithm shown in Example C, in addition to using several constraints on the allowed transistor positions.

[0106] The initial ordering of the input netlist can be obtained using the method shown in Example A. From this ordering, constraints regarding the acceptable range of each transistor are added to the integrated placement and routing algorithm.

[0107] As an example, let's assume that the value T_i_x0 represents the position of transistor i in the initial ordering. Since it is desirable to restrict the transistor positions, if transistors are only allowed to move one column from their initial position, the following constraint is added to the solver: (assert(and(>=T_1_x(T_1_x0 1))(<=T_1_x(+T_1_x0 1)))) (assert(and(>=T_2_x(T_2_x0 1))(<=T_1_x(+T_2_x0 1)))) (assert(and(>=T_3_x(T_3_x0 1))(<=T_1_x(+T_3_x0 1)))) (assert(and(>=T_4_x(T_4_x0 1))(<=T_1_x(+T_4_x0 1)))) (assert(and(>=T_5_x(T_5_x0 1))(<=T_1_x(+T_5_x0 1)))) (assert(and(>=T_6_x(T_6_x0 1))(<=T_1_x(+T_6_x0 1)))))

[0108] When ordering dual-height cells, transistors may be constrained to ensure that their cell height does not change: (assert(=T_1_y T_1_y0)) (assert(=T_2_y T_2_y0)) (assert(=T_3_y T_3_y0)) (assert(=T_4_y T_4_y0)) (assert(=T_5_y T_5_y0)) (assert(=T_6_y T_6_y0))

[0109] Alternatively, any type of constraint can be applied to the final ordering by adding appropriate additional constraints to the SMT problem instance.

[0110] In some embodiments, once a solution satisfying the input requirements and predetermined area requirements is found, the layout associated with this solution is communicated to the user, the method terminates, and the SMT solver is not invoked again in an attempt to find another, more optimal solution that satisfies the input requirements and predetermined area requirements.

[0111] In other embodiments, as shown in Figure 10, the placed layout 1026 is one of a predetermined number of generated layouts and is output to the user in the output process (step 1028). Generally, in these embodiments, after a layout is generated (step 1024), it is determined whether the desired number of results (i.e., layouts) have been achieved (step 1030). If the desired number of results or layouts have not been achieved, another instance of the SMT problem is generated (step 1018), the SMT solver is called, and a new solution is generated (step 1020). If the new solution is successful (step 1022) (i.e., satisfies the input and predetermined area requirements), another layout 1026 is generated (step 1024) and output (step 1028). This process is repeated until the desired number of layouts have been generated.

[0112] Similar to the embodiments described above, the method may further include determining the optimal solution from the generated and outputted layout 1026 based on, for example, the area required for the IC, the complexity of the layout (such as the number of masks required to fabricate the circuit), or a netlist or technology design rules, and identifying the layouts related to the optimal solution for the user.

[0113] Alternatively, the method may further include ranking the generated layouts 1026 and outputting a list of ranked solutions based on predetermined metrics including the area required for the layout, the number of masks required to fabricate the circuit, and / or the performance of the ICs.

[0114] Several embodiments of EDA tools and methods for operating them for the placement and routing of intracellular devices within an IC have been described. While this disclosure has been described with reference to specific exemplary embodiments, it will become clear that various modifications or changes can be made to these embodiments without departing from the broader spirit and scope of this disclosure. Therefore, this specification and the accompanying drawings should be considered illustrative rather than restrictive.

[0115] This abstract of the Disclosure is provided in accordance with CFR §1.72(b), which requires an abstract that allows readers to quickly identify one or more embodiments of the technical disclosure. This abstract of the Disclosure is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. In addition, it is evident that in the aforementioned “Modes for Carrying Out the Invention,” various features are brought together within a single embodiment for the purpose of streamlining the Disclosure. This method of the Disclosure should not be construed as reflecting an intention that the claimed embodiments require more features than those explicitly enumerated in each claim. Rather, as reflected in the following claims, the subject matter of the Invention is fewer than all the features of a single disclosed embodiment. Accordingly, the following claims are incorporated herein into the “Modes for Carrying Out the Invention,” and each claim stands as a separate embodiment.

[0116] Any reference herein to “one embodiment” or “embodiment” means that a particular function, structure, or feature described in relation to that embodiment is included in at least one embodiment of the circuit or method. The phrase “one embodiment” appearing in various places within this specification does not necessarily refer to the same embodiment.

Claims

1. A method for arranging and routing intracellular transistors within an integrated circuit (IC), It receives input including netlists, template definitions, and technology design rules. To generate a first instance of the SMT problem for arrangement and wiring by converting the input into a set of satisfaction modulo theory (SMT) constraints relating to the arrangement of a predetermined number of transistors within a cell and the wiring of interconnections to said predetermined number of transistors within a cell, Call the SMT solver, use the set of SMT constraints, and generate a first solution to the SMT problem. If the first solution satisfies the input requirements and the user-defined area requirements, then a first layout for the arrangement and wiring of a predetermined number of intracellular transistors within the IC is generated and output. To determine whether a predetermined number of layouts have been generated. To generate another instance of the aforementioned SMT problem, Call the aforementioned SMT solver and generate another solution. Evaluating the solution against the input requirements and the predetermined area requirements, To generate and output an alternative layout for the arrangement and wiring of a predetermined number of intracellular transistors within the IC, The process involves repeatedly generating instances of the aforementioned SMT problem, generating a solution, and generating and outputting layouts until a predetermined number of layouts have been generated. Ranking the generated layouts based on a predetermined metric that includes one or more of the following: the number of masks required for the layout, the area required for the layout, and the performance of the ICs, and To output the ranked layout for the arrangement and wiring of intracellular transistors within the IC, Includes, A method in which intracellular transistors are arranged within cells that include both single-height cells and multi-height cells, wherein the multi-height cells have a total height equal to an integer multiple of the template height defined by the template definition.

2. The method according to claim 1, wherein if the first solution does not satisfy the input requirements and the predetermined area requirements, the method is terminated and the user is notified.

3. The method according to claim 1, wherein if the first solution satisfies the input requirements and the predetermined area requirements, the method is terminated and the SMT solver is not invoked again in an attempt to find another more optimal solution that satisfies the input requirements and the predetermined area requirements.

4. The method according to claim 1, further comprising determining an optimal solution from the generated and outputted layouts based on the required area or based on the netlist or the technology design rules, and identifying the layouts relating to the optimal solution for the user.

5. Prior to generating the first instance of the SMT problem for arrangement and wiring, To generate the SMT arrangement problem for the predetermined number of transistors within the cell, Calling the aforementioned SMT solver, To generate a solution to the aforementioned SMT arrangement problem, and If the solution to the SMT arrangement problem satisfies the requirements of the input, then it generates the first instance of the SMT problem of arrangement and wiring having a limited arrangement of a predetermined number of intracellular transistors. The method according to claim 1, further comprising:

6. A method for arranging and routing intracellular transistors within an integrated circuit (IC), Receiving input including a netlist of components available for use in the IC, user-defined template definitions and specified area requirements for the components of the IC, and technology design rules specifying the design requirements for the components. A first instance of the satisfaction modulo theory (SMT) placement problem is generated by converting the aforementioned input into a first set of SMT constraints relating to the arrangement of a predetermined number of intracellular transistors within the IC. Call the first SMT solver to generate a first solution to the SMT placement problem. If the first solution to the SMT placement problem satisfies the input requirements, then a first instance of the SMT placement and routing problem is generated by using the first solution to the SMT placement problem. Call a second SMT solver to generate a first solution to the SMT placement and routing problem, and If the first solution to the SMT arrangement and wiring problem satisfies the input requirements, then generate and output a first layout for the arrangement and wiring of intracellular transistors within the IC. Includes, A method in which intracellular transistors are arranged within cells that include both single-height cells and multi-height cells, wherein the multi-height cells have a total height equal to an integer multiple of the template height defined by the template definition.

7. The method according to claim 6, wherein if the first solution to the SMT arrangement problem does not satisfy the input requirements, the method terminates and the user is notified.

8. Determine whether a predetermined number of layouts have been generated, and if not, To generate a second instance of the aforementioned SMT placement problem, Call the first SMT solver to generate a second solution to the SMT placement problem. If the second solution to the SMT placement problem satisfies the requirements of the input, then a second instance of the SMT placement and routing problem is generated by using the second solution to the SMT placement problem. Call the second SMT solver to generate a second solution to the SMT wiring problem. If the second solution to the aforementioned SMT arrangement and wiring problem satisfies the input requirements, then generate and output a second layout for the arrangement and wiring of intracellular transistors within the IC, and The above process is repeated until the predetermined number of layouts are generated. The method according to claim 6, further comprising:

9. The method of claim 8, further comprising determining an optimal solution from the generated and outputted layouts based on the required area or based on the netlist or the technology design rules, and identifying the layout relating to the optimal solution for the user.

10. The method according to claim 8, further comprising ranking the generated and output layouts based on a predetermined metric including one or more of the number of masks required for the layout, the area required for the layout, and / or the performance of the IC, and outputting a list of ranked solutions.

11. The method according to claim 6, wherein the first SMT solver and the second SMT solver are the same SMT solver.

12. A non-temporary computer-readable medium for storing program instructions for causing a computer to arrange and wire transistors within cells in an integrated circuit (IC), Program instructions for receiving input including netlists, template definitions, and technology design rules. A program instruction for generating a first instance of the arrangement and wiring SMT problem by converting the input into a set of satisfaction modulo theory (SMT) constraints relating to the arrangement of a predetermined number of transistors within a cell and the wiring of interconnections to a predetermined number of transistors within a cell, A program instruction to call an SMT solver, use the set of SMT constraints, and generate a first solution to the SMT problem. If the first solution satisfies the input requirements and the user-defined area requirements, a program instruction is issued to generate and output a first layout for the arrangement and wiring of a predetermined number of intracellular transistors within the IC. A program instruction to determine whether a predetermined number of layouts have been generated. A program instruction to generate another instance of the aforementioned SMT problem, A program instruction to call the aforementioned SMT solver and generate another solution, A program instruction for evaluating the solution for the aforementioned input requirements and the aforementioned predetermined area requirements, A program instruction for generating and outputting an alternative layout for the arrangement and wiring of a predetermined number of transistors within the IC, A program instruction to repeatedly generate instances of the aforementioned SMT problem, generate a solution, and generate and output layouts until a predetermined number of layouts have been generated. A program instruction for ranking the generated layout based on a predetermined metric including one or more of the following: the number of masks required for the layout, the area required for the layout, and the performance of the IC, and Program instructions for outputting the ranked layout for the arrangement and wiring of transistors within cells in the IC, Includes, A non-temporary computer-readable medium in which intracellular transistors are arranged within cells that include both single-height cells and multi-height cells, the multi-height cells having a total height equal to an integer multiple of the template height defined by the template definition.

13. The computer-readable medium according to claim 12, further comprising a program instruction for notifying the user and stopping the execution of further program instructions if the first solution does not satisfy the input requirements and the predetermined area requirements.

14. The computer-readable medium according to claim 12, further comprising a program instruction that, if the first solution satisfies the input requirements and the predetermined area requirements, stops the execution of further program instructions and does not attempt to find another more optimal solution that satisfies the input requirements and the predetermined area requirements.

15. The computer-readable medium according to claim 12, further comprising program instructions for determining an optimal solution from the generated and outputted layouts based on the required area or based on the netlist or the technology design rules, and for identifying the layout relating to the optimal solution for the user.

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