Signal skew correction in integrated circuit memory devices

Abstract

A technique for signal skew correction in an integrated circuit memory device is described. The integrated circuit memory device includes a first interface for receiving command / address (CA) signals and a clock signal, a data interface, and a mode register. During a CA bus loopback mode, the first interface receives a pattern of the CA signals and the clock signal, and the data interface outputs a pattern of the CA signals. During the CA bus loopback mode, the mode register can be programmed with a value representing a timing offset between the clock signal and a sampling point of the first interface.

Description

Technical Field

[0001] Background Art

[0001] Modern computer systems generally include data storage devices such as memory components or devices. The memory component can be, for example, random access memory (RAM) or dynamic random access memory (DRAM). The memory device includes a memory bank composed of memory cells that are accessed via a command interface and a data interface within the memory device by a memory controller or a memory client.

Summary of the Invention

[0002]

[0002] In the figures of the accompanying drawings, the present disclosure is shown by way of example and not limitation.

Brief Description of the Drawings

[0003] [Figure 1]

[0003] A block diagram showing a computing environment having a memory controller and a DRAM device configured for individual DRAM skew correction between a clock edge and a command / address (CA) sampling point according to one embodiment. [Figure 2]

[0004] A diagram showing a set of eye diagrams showing different clock-to-CA skews in five DRAM devices of FIG. 1 according to one embodiment. [Figure 3]

[0005] A timing diagram of a signal received by a command buffer and sent from the command buffer and a signal received by each DRAM device according to one embodiment. [Figure 4]

[0006] A block diagram showing a delay circuit for performing timing adjustment between a clock edge and a CA sampling point according to one embodiment. [Figure 5]

[0007] This is a block diagram showing a DRAM CA interface having a programmable delay between a clock signal and a CA / CS signal, according to one embodiment. [Figure 6]

[0008] This is a block diagram showing a clock delay circuit for timing adjustment between a clock edge and a CA sampling point, according to one embodiment. [Figure 7A]

[0009] This is a timing diagram of a chip selection signal, a clock signal, and a CA signal for a loopback test mode to program a timing offset, according to one embodiment. [Figure 7B]

[0010] This table shows the results of a setup sweep and a hold sweep performed in loopback test mode according to one embodiment. [Figure 7C]

[0011] This is a table, according to one embodiment, showing the individual timing offsets of each DRAM device from a loopback test mode. [Figure 8]

[0012] This is a block diagram of a command buffer with a timing adjustment function according to one embodiment. [Figure 9]

[0013] This is a flowchart of a method for programming a delay circuit in a DRAM device according to one embodiment. [Figure 10]

[0014] This is a flowchart of a method 1000 for programming a delay circuit in a DRAM device according to one embodiment. [Figure 11]

[0015] This is a schematic diagram of at least one embodiment, comprising three receivers and delay elements that can be individually programmed to provide bitwise trim by the three receivers. [Figure 12]

[0016] This is a block diagram showing a DRAM CA interface having a programmable delay between a clock signal and a CA / CS signal, according to one embodiment. [Modes for carrying out the invention]

[0004]

[0017] The following description includes numerous specific details, such as examples of particular systems, components, and methods, to provide a full understanding of some embodiments of the Disclosure. However, it will be apparent to those skilled in the art that at least some embodiments of the Disclosure can be implemented without these specific details. In other examples, well-known components or methods are either not described in detail or are presented in simple block diagram form to avoid unnecessarily obscuring the Disclosure. Thus, the specific details described are merely illustrative. Certain implementations may differ from these illustrative details and still be considered within the scope of the Disclosure.

[0005]

[0018] When transmitting signals over a parallel bus, skew can occur between signals arriving at the bus-coupled devices due to various causes, as the devices sample signals according to a common timing reference. Skew variations in devices can be caused by clock signals with different signaling types. Signal line termination, drive strength, manufacturing variations, and other factors can cause skew between devices coupled to a common bus. For example, in a memory system with a fly-by command / address (CA) bus, skew variations can exist between the clock edge of the clock signal and the CA terminals of each memory location, due to the different signaling types, terminations, drive strengths, and slew rates between these two signals. In some cases, skew variations can be reduced, but not completely eliminated. For example, a dual in-line memory module (DIMM) may include a buffer device that receives CA and clock signals from the memory controller and re-drives these signals to the memory devices on the DIMM.

[0006]

[0019] Aspects of the present disclosure address the above and other considerations by providing clock skew correction to individual devices coupled to a common bus to improve the margin of the common bus when sampling all signals on the common bus by a common timing criterion. In at least one embodiment, clock skew correction can be provided within a DRAM device to improve the CA bus margin. Aspects of the present disclosure address the above and other considerations by providing a loopback mode and programming skew correction in individual memory devices receiving CA signals. In at least one embodiment, the loopback mode can improve the signaling margin on the CA bus of a DIMM or on a motherboard. Embodiments described herein use in-DRAM skew correction utilizing DRAM interface training and some additional logic within the DRAM.

[0007]

[0020] Figure 1 is a block diagram showing a computing environment 100 having a memory controller and DRAM devices configured for individual DRAM skew correction between the clock edge in each CA receiver circuit and the individual signals sampled using that clock signal, according to one embodiment. A memory module 120 is shown in the computing environment 100. In other embodiments, one or more memory devices may be connected to a memory controller on a motherboard. Optionally, one or more instances of environment 100 or any aspect thereof may be implemented in the context of the architecture and functionality of the embodiments described herein.

[0008]

[0021] As shown in Figure 1, the environment 100 includes a memory controller 102 coupled to a memory module 120 via one or more buses, as will be described in more detail below. In one embodiment, the memory module 120 is a dual inline memory module (DIMM). Such a memory module may be called a DRAM DIMM, a registered DIMM (RDIMM), or a load-reduced DIMM (LRDIMM), and can share memory channels with other DRAM DIMMs.

[0009]

[0022] In one embodiment, the memory controller 102 further includes a loopback test interface circuit 103, a clock signal generator 104, and a memory interface circuit 105. The memory controller 102 may include multiple instances of each of the loopback test interface circuit 103, the clock signal generator 104, and the memory interface circuit 105. The clock signal generator 104 may include a phase-locked loop (PLL) or other circuit for generating one or more clock signals. The clock signal generator 104 can generate strobe signals for data buses 1141-1145 and clock signals for CA buses 1161-1162. The interface circuit on the memory controller 102 and the DRAM device can send and receive data on the data bus. The interface circuit on the memory controller 102 can send bank addresses, row addresses, and column addresses, or any combination thereof, on the CA bus. The DRAM device can be organized into one or more ranks. A rank is a group of DRAM devices that share a common CA bus. A DIMM can have multiple ranks, and multiple DIMMs can reside in one channel. In other embodiments, the clock signal generator 104 may receive one or more clock signals from a source external to the memory controller 102. In any embodiment, the memory interface circuit 105 may include a driver that drives one or more clock signals from the clock signal generator 104 of the memory controller 102 (for example, to a component such as an RCD or buffer chip on the memory module 120).

[0010]

[0023] Specifically, the memory interface circuit 105 can write data to and / or read data from multiple sets of DRAM devices 1241-1242 using data buses 1141-1145. A DRAM device 124 may contain multiple banks, each bank having a 2D array (rows and columns) of memory cells, sense amplifiers, row and column decoders, and peripheral circuitry. Each memory module 120 may include, for example, an array of eight or nine memory devices arranged in various topologies (e.g., A / B side, single rank, dual rank, quad rank, etc.) (e.g., synchronous DRAM (SDRAM)). In some cases, as shown in the figure, data to and / or from DRAM devices 1241-1245 may be optionally buffered by a set of data buffers 1221-1225, respectively. Such data buffers can help reduce the high electrical load on large computing and / or memory systems by re-driving signals (e.g., data signals (DQ) or simply data) onto the bus. In other embodiments, data buffers 12211221-1225 are not present in the memory module 120.

[0011]

[0024] The memory interface circuit 105 of the memory controller 102 transmits CA signals and clock signals to the memory module 120 via one or more buses using the memory interface circuit 105. The CA signals and clock signals from the memory interface circuit 105 can be received via the command and address (CA) bus 116 by a command buffer 126, such as a register clock driver (RCD), in the memory module 120 using a receiver circuit on the RCD. For example, the command buffer 126 may be an RCD, such as one included in a registered DIMM (e.g., RDIMM, LRDIMM, etc.). The command buffer, such as the command buffer 126, may include logic registers and a phase-locked loop (PLL) to isolate the DRAM devices from the memory controller 102 and the system bus 110, thereby reducing the load on the clock, control, command, and address signals, by receiving command and address input signals from the memory controller 102 and re-driving them to the DRAM devices on the DIMM (e.g., DRAM device 1241, DRAM device 1242, etc.). In some cases, specific functions of the command buffer 126 can be programmed by configuration and / or control settings via registers on the RCD. In one embodiment, the command buffer 126 includes a receiver circuit that receives several command / address signals from the memory controller 102 via the CA bus 116 along with at least one clock signal. The command buffer 126 may divide the received command / address signals into two or more separate groups and generate one or more additional clock signals from the received clock signal. Alternatively, as shown in Figure 1, the command buffer 126 may receive a first group of CA signals (command / address A) on a first CA bus 1161 and a second group of CA signals (command / address B) on a second CA bus 1162. The command buffer 126 may further sample each of the groups of command / address signals (e.g., subsets of the received command / address signals) according to the received clock signal.As shown in FIG. 1, the command buffer 126 can receive a clock signal (CK) on the clock line 1163 of the CA bus 116. In other embodiments, the memory devices of the memory module 120 can receive the CA signal and the clock signal directly from the memory interface circuit 105.

[0012]

[0025] In one embodiment, the memory interface circuit 105 receives a CA signal from a processing core (not shown) of the memory controller 102 or from some other memory client that utilizes a memory system including the memory controller 102 and the memory module 120, and receives an external clock signal from the clock signal generator 104. The memory interface circuit 105 includes a transmitter circuit for driving a CA signal (e.g., CAA and CAB) and an external clock signal to the memory module 120 via various signal lines forming the CA bus 116. In one embodiment, the memory interface circuit 105 drives each 1-bit of the CA signals CAA and CAB at one or both of each rising edge and falling edge of the external clock signal. In one embodiment, the CA bus 116 transmits a plurality of CA signals CAA and CAB and a plurality of external clock signals. For example, CAA can include seven separate CA signals, CAB can include seven additional CA signals, and the clock signal can include a pair of differential clock signals. In one embodiment, all signals within the CA bus 116 are received by the command buffer 126 of the memory module 120.

[0013]

[0026] In one embodiment, the clock signal generator 104 of the memory controller 102 generates an external clock signal. The memory interface circuit 105 transmits various CA signals and the external clock signal to the memory module 120 via the CA bus 116. In one embodiment, the memory interface circuit 105 receives CA signals from a processing device (not shown) of the memory controller 102 or from any other memory client utilizing the memory system including the memory controller 102, and the memory module 120 receives an external clock signal from the clock signal generator 104. The memory interface circuit 105 drives CA signals (e.g., CAA and CAB) and an external clock signal (e.g., CK) to the memory module 120 via various signal lines forming the CA bus 116. In one embodiment, the memory interface circuit 105 drives one bit each of the CA signals CAA and CAB on either the rising or falling edge of the external clock signal CK.

[0014]

[0027] The memory module 120 shown in environment 100 merely presents a single partition. It should also be noted that the memory module 120 does not show all the DRAM devices and data buffers that may exist in, for example, a DDR5 DIMM. In other embodiments, additionally or alternatively, the memory module 120 may include other memory devices, such as volatile memory devices like SDRAM, Rambus DRAM (RDRAM), static random access memory (SRAM), NAND flash, etc. In other embodiments, the memory module can be a memory card such as an SD card, an eMMC device, etc. The specific example shown where the command buffer 126 and the DRAM devices 1241 - 1242 are separate components is purely illustrative, and other partitions are possible. For example, any or all of the components constituting the memory module 120 and / or other components can be configured as one device (such as a system - on - chip or SoC), multiple devices within a single package or printed circuit board, or multiple separate devices, and can have other variations, modifications, and alternatives. Also, the memory controller 102 may include additional and / or different components compared to those shown in FIG. 1. Further, the illustrated components may be arranged differently depending on the embodiment.

[0015]

[0028] In a source - synchronous system, the data signal sent from a source (e.g., the memory controller 102) to a receiver (e.g., the buffer chip on the memory module 120) is provided by the source and synchronized with a strobe signal (which may also be called a clock signal) transmitted along with the data signal.

[0016]

[0029] In a double data rate (DDR) memory system, for example, there may be eight data signals transmitted from the memory controller 102 to the memory module 120, with one bit from each of the eight signals forming a byte of data to be written to the memory module 120. Each 4-bit set (i.e., each nibble) may have a corresponding clock signal (e.g., a differential clock signal) used as a reference clock for transferring the signals. Within each nibble, the four data signals are synchronized to the same clock, but all signals need to be synchronized in a synchronization system. Therefore, many systems perform a nibble-skew alignment operation to synchronize all data signals (DQ) and clock signals (DQS) at the receiver.

[0017]

[0030] As described above, the memory module 120 may have a fly-by CA bus and point-to-point data lines, as shown in Figure 1. The command buffer 126 can receive a clock signal (CK) on the clock line 1163 and re-drive the internal clock signal 128 (CK_internal) on the clock line of the fly-by CA bus. The command buffer 126 can receive the CS signal (command / address A) of the first DRAM group and re-drive the CA signal 130 on the fly-by CA bus.

[0018]

[0031] As mentioned above, for signaling rates of 5600 Mbps or higher, such as those illustrated and described later in Figure 2, skew variation may exist between the clock edge of the clock signal and the CA terminal at each DRAM location on the flyby CA bus. Skew variation can occur because the signaling types of the CA signal and the CK signal are different. For example, the CK signal may be a differential signal, while the CA signal may be a single-ended signal. Termination, drive strength, and slew rate can also affect skew variation. To address skew variation, each DRAM device 124 includes a delay circuit 106. The delay circuit 106 may include a mode register for storing a value representing a timing offset of a programmable delay applied to signals received on the CA line, the CK line, or both. The programmable delay allows each DRAM device 124 to perform timing adjustments between the clock edge of the internal clock signal 128 and the CA sampling point in one or more receiver circuits. The delay circuit 106 may include circuits for performing individual timing adjustments in each DRAM device 124. The delay circuit 106 can be programmed by the memory controller, for example, in CA bus loopback mode. In CA bus loopback mode, the memory controller 102's loopback test interface circuit 103 can send a known signal pattern over the CA bus interface 116 and receive the looped-back signal via the data bus interface 114. More specifically, each DRAM device 124 includes a data interface that includes a transmitter that sends data to the memory controller 102 in normal mode and sends the received signal pattern in loopback mode. In one embodiment, the loopback test interface circuit 103 can determine the offset of each DRAM device 124, and the memory controller programs the delay circuit 106 with a value representing the individual timing offset of the programmable delay. In at least one embodiment, the memory controller 102 programs the mode register by sending a mode register set command along with the delay value.The memory controller 102 can program each DRAM device 124 by individually programming each mode register. The delay circuit 106 generates individual timing offsets for timing adjustment between the clock edge of the internal clock signal 128 and the CA sampling point in each DRAM device. By individually programming different delay circuits 106 for different DRAM devices 124, the clock edge in each individual DRAM device is aligned to the center or near the center of the respective eye aperture for sampling the CA signal in the individual DRAM device.

[0019]

[0032] In one embodiment, the loopback test interface circuit 103 can use a loopback mode process to correct skew in individual devices coupled to a common bus, which are sampled by a common timing reference. The loopback test interface circuit 103 can be implemented as individual logic, digital signal processing blocks, or circuit blocks having the capability to perform the operations described herein. Alternatively, the functionality of the loopback test interface circuit 103 can be a set of instructions executed by the processing devices of the memory controller 102.

[0020]

[0033] In one embodiment, the mode register of the delay circuit 106 stores a first digital value representing a first timing offset for the clock line and a second digital value representing a second timing offset for the CA bits (CA lines). In another embodiment, the mode register of the delay circuit 106 stores a first digital value for the clock line and a set of digital values, each corresponding to one of the CA bits. In yet another embodiment, the mode register of the delay circuit 106 stores a first set of digital values ​​for delaying the signal received by the receiver of each clock line corresponding to each CA line by a first set of programmable delays, one programmable delay per clock line, and a second set of digital values ​​for delaying the signal received by the receiver of each CA bit by a second set of programmable delays. Alternatively, the mode register can store one or more values ​​for timing adjustment between the clock edge and the CA sampling point of one or more CA bits.

[0021]

[0034] Figure 2 shows a set of eye diagrams illustrating different clock-to-CA skews in the five DRAM devices of Figure 1 according to one embodiment. Each of the DRAM devices 1141-1145 (labeled U10-U14 in Figures 1-2) receives an internal clock signal 128, but may have different skews between the clock edge and the center of the eye aperture. As shown in eye diagram 200 corresponding to the first DRAM device 1141, the clock edge 202 of the internal clock signal 128 is offset by a first offset amount 206 (e.g., about 48 ps) from the center of the eye aperture 204. Eye diagram 210 shows a second offset amount 212 (e.g., about 44 ps) between the clock edge and the center of the respective eye aperture in the second DRAM device 1142. Eye diagram 220 shows a third offset amount 222 (e.g., about 61 ps) between the clock edge and the center of the respective eye aperture in the third DRAM device 1143. Eye diagram 230 shows a fourth offset amount 232 (e.g., approximately 63 ps) between the clock edge and the center of each eye aperture in the fourth DRAM device 1144. Eye diagram 240 shows a fourth offset amount 242 (e.g., approximately 70 ps) between the clock edge and the center of each eye aperture in the fifth DRAM device 1145. As shown in Figure 2, the command buffer 126 (e.g., RCD) can position the clock signal near the center of the unit interval (UI), although the clock-to-CA skew (QCK-QCA) varies depending on the DRAM location. The clock edge can be offset from the center of the UI by a range of approximately 48 to 70 ps, ​​depending on the DRAM location, for example.

[0022]

[0035] As described above, the loopback test interface circuit 103 can measure each of the offset amounts in loopback mode and program each delay circuit 106 with a value representing the individual timing offset to adjust the timing between the clock edge of the clock signal and the CA sampling point (e.g., the center or near the center of the eye aperture) in each DRAM device 124. For example, the loopback test interface circuit 103 can program the first delay circuit 106 of the first DRAM device 1241 with a first value (e.g., about 48 ps) corresponding to the first offset amount 206. Similarly, the loopback test interface circuit 103 can program the second delay circuit 106 of the second DRAM device 1242 with a second value (e.g., about 44 ps) corresponding to the second offset amount 212. Other DRAM devices can be programmed with values ​​corresponding to offset amounts 222, 232, and 242, respectively. By programming the delay circuits 106 individually, skew variations between DRAM devices can be reduced. The delay circuits 106 can be programmed using ...

[0023]

[0036] Figure 3 is a timing diagram 300 of a signal 302 received by and sent from a command buffer and a signal 304 received by each DRAM device, according to one embodiment. Signal 302 includes a clock signal (CK) 306, an internal clock signal (ck_internal) 308, and chip select (CSn) and CA signals 310. Signal 304 includes a clock signal (CK) 306 (for reference), an internal clock signal (ck_internal) 312, and chip select (CSn) and CA signals 314. One unit interval (UI) can be a full clock cycle, for example, 357 ps for DDR5-5600. Note that DDR5-5600 is a specific exemplary speed bin, and other memory technologies and speeds may be used in other embodiments. Similarly, each device of a set of devices coupled to a common parallel bus can be programmed using the embodiments described herein, and signals on the common parallel bus are sampled at each of the set of devices using a common timing reference.

[0024]

[0037] Returning to Figure 3, the command buffer (RCD) receives the clock signal 306 and can re-drive each DRAM device. Each DRAM device receives the re-driven clock signal after it has been buffered by the clock receiver, and this is called the internal clock signal 308. The internal clock 308 can be a delayed version of the clock signal 306. For example, the internal clock 308 can be UI-postclocked to the clock signal 306, as indicated by the clock edge 318 of the clock signal 306 and the corresponding clock edge 320 of the internal clock signal 308. The clock edge 320 can be used to sample the CSn and CS_A signals 310 sent from the command buffer. As shown in Figure 3, the clock edge 320 of the internal clock signal 308 is aligned to the center of the UI as the CA sampling point. Signal 302 is output from the command buffer, but depending on the DRAM location, there may be a skew in the time at which the clock signal is received at each DRAM location, which becomes the internal clock signal 308 after it has been buffered by the clock receiver. As shown in Figure 3, the DRAM device receives a clock signal from the command buffer, which is buffered by the clock receiver and then becomes the internal clock signal 312. The internal clock signal 312 is delayed by a first amount (e.g., 70 ps). That is, the clock edge 322 of the internal clock signal 312 is delayed by a first amount from the clock edge 320 of the clock signal 308. As described herein, the delay circuit 106 can be programmed with a first value 324 (e.g., 70 ps).

[0025]

[0038] Figure 4 is a block diagram showing a delay circuit 106 for timing adjustment between a clock edge and a CA sampling point according to one embodiment. The delay circuit 106 receives a chip select (CS) signal 401, a CA signal 403, and a clock (CK) signal 405. The delay circuit 106 includes a mode register 420 and logic 422. The mode register 420 can be programmed to store one or more values ​​of programmable delays for the CK signal 401, the CA signal 403, and the CK signal 405, or any combination thereof. Logic 422 can be controlled by the mode register 420 to perform timing adjustment between the clock edge and the CA sampling point in each DRAM device where the delay circuit 106 resides. The delay circuit 106 outputs one or more delayed signals, including a CS signal 407, a CA signal 409, and a CK signal 411. Logic 422 can be controlled by the mode register 420 to perform timing adjustment. Logic 422 can include various logic gates and buffers to perform the necessary timing adjustments specified by the value stored in the mode register 420. Examples of logic 422 will be discussed later with reference to Figures 5 and 6.

[0026]

[0039] In one embodiment, the timing offset represents the amount of skew between the CK signal 405 and the CA signal 403. The timing offset can be set by a value stored in a mode register 420 associated with the delay circuit 106. Depending on the embodiment, the mode register 420 may be located locally in close proximity to the delay circuit 106 itself, or it may be located elsewhere in the DRAM device 124, where the contents of the mode register 420 can configure the delay circuit 106. In one embodiment, a processing unit coupled to the memory controller 102 or the memory controller 102 writes a corresponding value to the associated mode register 420, which represents a desired amount of signal skew (i.e., the corresponding timing offset) to be introduced for the CS signal 401, the CA signal 403, the CK signal 405, or any combination thereof, and when this is applied, skewed output signals (407, 409, 411) are generated at the output of the delay circuit 106.

[0027]

[0040] In one embodiment, the loopback test interface circuit 103 is configured to program register values ​​with timing offset amounts during loopback mode operation. Loopback mode operation may include measuring the amount of skew between the CA signal 403 and the CK signal 405, as well as interference resulting from signal transitions propagating along the signal line. The loopback test interface circuit 103 may measure the detected interference for several different offset amounts (for example, by systematically changing the offset amount in step values ​​as described below) to identify an offset amount at which the interference is minimized or at least shifted. Thus, the CA signal 409 can be sampled in response to the rising or falling edge of the CK signal 411. As a result of reducing or shifting the skew, the CK signal 411 is shifted to the center of the eye aperture of the CS signal 407, the CA signal 409, or both, thereby improving the eye aperture.

[0028]

[0041] Figure 5 is a block diagram of a DRAM CA interface 500 having a programmable delay between a clock signal and a CA / CS signal according to one embodiment. The DRAM CA interface 500 includes a first mode register 502, a first delay element 504, a second mode register 506, and a set of delay elements 508. The first delay element 504 is controlled by a first value stored in the first mode register 502. The first delay element 504 delays the clock edge of the clock signal 501 by a first programmable delay corresponding to the first value. The clock signal 501 can be buffered in front of the first delay element 504 by a first buffer 510, and the first delay element 504 can generate a delayed clock signal 503, which can be buffered by buffers 512 in individual clock lines coupled to a sampling circuit 514. In other embodiments, the first delay element 504 can be duplicated and placed after the buffers 512 in individual clock lines. Each of these multiple delay elements can be controlled by a single value or individual values.

[0029]

[0042] The second delay element 508 is controlled by a second value stored in the second mode register 506. One of the second delay elements 508 delays the chip selection (CS) signal 505 by a second programmable delay corresponding to the second value. The CS signal 505 can be buffered in front of the second delay element 508 by a buffer 516, and the second delay element 508 can generate a delayed CS signal 507, which is coupled to one of the sampling circuits 514. Multiple second delay elements 508 delay the CA signal 509 by a second programmable delay corresponding to a second value. The CA signal 509 can be buffered in front of the second delay element 508 by a buffer 518, and the second delay element 508 can generate a delayed CA signal 511, which is coupled to their respective sampling circuits 514.

[0030]

[0043] In one embodiment, the first mode register 502 and the second mode register 506 reside in a single register that stores two distinct values ​​(delay0, delay1). As described herein, the distinct values ​​can be programmed to individually adjust the timing offset between the clock edge and the sampling point.

[0031]

[0044] In other embodiments, the first delay element 504 is controlled to delay the clock edge of the clock signal 501 by a first value, and the plurality of second delay elements 508 are controlled to delay the receiver of each CA bit by a second programmable delay by a second value. In other embodiments, the first delay element 504 is controlled to delay the clock edge of the clock signal 501 by a first value, and each of the plurality of second delay elements 508 is controlled individually by its own programmable delay. That is, each of the individual CA lines and CS lines can be independently programmed to have a value specific to that particular line. As described herein, each of the individual lines, including the CS lines, CA lines, and CK lines, can be individually programmed using values ​​stored in one or more mode registers.

[0032]

[0045] Figure 6 is a block diagram showing a clock delay circuit 600 for timing adjustment between a clock edge and a CA sampling point according to one embodiment. The clock delay circuit 600 includes a programmable delay line 602 coupled between a clock terminal 604 and a clock buffer 606, and a delay-locked loop (DLL) circuit 608. The DLL circuit 608 includes a first delay element 610 and a second delay element 612. The DLL circuit 608 uses the first delay element 610 and the second delay element 612 to control the programmable delay of the programmable delay line 602. The programmable delay line 602 receives a clock signal 601, delays the clock signal 601 by the programmable delay, and generates a delayed clock signal 603. The first delay element 610 is controlled by a first value stored in a mode register 614, and the second delay element 612 is controlled by a second value stored in the mode register 614.

[0033]

[0046] In one embodiment, the DLL circuit 608 also includes a phase detector 616 that receives a first clock signal 601 from a first delay element 610 and a delayed clock signal 603 from a programmable delay line 602. The first delay element 610 can delay the first clock signal 604 by a first programmable delay corresponding to a first value. The second delay element 612 can delay the delayed clock signal 603 by a second programmable delay corresponding to a second value. The phase detector 616 detects the phase difference between the delayed first clock signal and the delayed second clock signal, outputs a display of the phase difference to the control circuit 618, and the control circuit 618 makes the corresponding adjustment to the programmable delay of the programmable delay line 602.

[0034]

[0047] Buffer 606 can buffer the delayed clock signal 603, which is then fed back and buffered again by buffer 620 before the second delay element 612, because the delayed clock signal 603 is buffered again by buffer 622 before it is applied to the sampling circuit 624 that samples the chip selection (CS) signal 605. The delayed clock signal 603 is also buffered again by buffer 626 before it is applied to the sampling circuit 628 that samples the CA signal 607. The sampling circuit 624 outputs the sampled CS signal 609, and the sampling circuit outputs the sampled CA signal 611.

[0035]

[0048] In other embodiments, a first set of delay elements can be controlled by a first set of values ​​stored in a mode register to delay the receiver of each clock line corresponding to each CA bit by a first set of programmable delays, and a second set of delay elements can be controlled by a second set of timing offsets stored in a mode register to delay the receiver of each CA bit (and / or CS bit) by a second set of programmable delays.

[0036]

[0049] In one embodiment, a first delay element located on the clock line is controlled by a first value stored in a mode register to delay the clock signal on the CK line by a first programmable delay. A second delay element located on the CA line is controlled by a second value stored in a mode register to delay the CA signal on the first CA line by a second programmable delay. In another embodiment, a third delay element located on the CS line is controlled by a third value stored in a mode register to delay the CS signal on the CS line by a third programmable delay. The second and third programmable delays can be the same. The first, second, and third delay elements can be duplicated once or more times to individually or collectively correct the skew between the clock signal and the CA / CA signals, respectively. For example, a fourth delay element located on the second CA line is controlled by a second value stored in a mode register to delay the second CA signal on the second CA line by a second programmable delay. Alternatively, the fourth delay element can be controlled by its own value, independently of the second programmable delay for the CA signal on the first CA line, thereby delaying the second CA signal by its own programmable delay.

[0037]

[0050] As described herein, one or more values ​​of the delay element can be programmed by the memory controller 102 during loopback test mode, as shown in Figures 7A-7C. The memory controller 102 can perform a loopback test mode 700 which includes a setup sweep 708 and a hold sweep 710. Figure 7A is a timing diagram of the chip selection (CS) signal 702, clock signal 704, and CA signal 706 for loopback test mode 700 to program values ​​corresponding to timing offsets, according to one embodiment. The memory controller 102 uses the loopback test interface circuit 103 to perform a setup sweep 708 and a hold sweep 710 for each DRAM device in loopback test mode (also called CA training mode (CATM)) and stores the results (CATM results) in a table 712 as shown in Figure 7B. Using loopback test mode, the memory controller can sweep the CA line to the DRAM interface to keep CK in phase, and outputs from the DRAM devices are sent to the memory controller via the data bus, with the outputs indicating CA setup time and hold time. Based on the simulation data, the CATM results for each DRAM are reflected as shown in Figures 7B and 7C. The memory controller 102 can use the CATM results in table 712 to create a timing offset table 714, as shown in Figure 7C, which includes the individual timing offsets for each DRAM device from the loopback test mode 700. That is, the memory controller can use the CATM results to compensate for CA vs. CK skew independently for each DRAM. Skew variations due to termination, drive strength, slew rate, and DIM manufacturing can be trained independently for each DRAM.Table 714 includes the first timing offset 716 for the first DRAM device, the second timing offset 718 for the second DRAM device, the third timing offset 720 for the third DRAM device, the fourth timing offset 722 for the fourth DRAM device, and the fifth timing offset 724 for the fifth DRAM device. The timing offsets are different values ​​and correspond to appropriate timing adjustments made between the clock signal 704 and the CS signal 702 and CA signal 706 in each DRAM device. In one embodiment, each first delay (delay0) can be programmed into the mode register (MR) of the DRAM device with a correction value to improve the setup margin and hold margin of all DRAM devices. The memory controller can program the MR of the DRAM devices using per-DRAM addressability (PDA) mode. Similarly, each second delay (delay1) can be programmed into the MR with a correction value to improve the setup margin and hold margin of all DRAM devices. In this particular example, since CK is to the left of the center of each eye, the second delay (delay1) is kept at zero under this condition. Alternatively, different combinations of the first and second delays can be used to improve the setup and hold margins of the DRAM device.

[0038]

[0051] In other embodiments, the controller can send a signal pattern to a device such as a DRAM device. The device receives the signal pattern at a first interface and sends the sampled result of the signal pattern back to the controller at a data interface. The controller can use a delay based on the sampled result to set an optimal sampling point for the device. The controller can program the device's mode register with a value that sets the optimal sampling point. For example, the controller can send a mode register command to program one or more delay elements to set the optimal sampling point for the device. In other embodiments, the controller can program multiple devices, such as multiple DRAM devices coupled to a common bus. In this embodiment, the controller can send a signal pattern to multiple devices and receive the sampled result of the signal pattern from each data interface of each device. Based on the different sampled results received from the multiple devices, the controller can set an optimal sampling point for each of the multiple devices.

[0039]

[0052] As described above, the memory controller can program the individual timing offsets for each DRAM device. In other embodiments, the functions and operations of the memory controller can also be performed in a command buffer such as the RCD of the memory module, as illustrated and described with respect to Figure 8.

[0040]

[0053] Figure 8 is a block diagram of a command buffer 826 with timing adjustment functionality according to one embodiment. The command buffer 826 can operate similarly to the command buffer 126 in Figure 1, except that the command buffer 826 includes a finite state machine (FSM) 803 for performing measurements on DRAM devices and programming values ​​corresponding to the individual timing offsets of each DRAM device. The FSM 803 can sweep the CA bus to each DRAM using PDA mode and obtain feedback on the error line 813. Each DRAM device can output data to an alert pin (ALERT_n) coupled to the error input pin (ERROR_in) of the command buffer 826. The FSM 803 can find the setup window and hold window of the CA bus for programming a particular DRAM at its DRAM location. The FSM 803 can program the corresponding timing offset (delay value) in the DRAM device at that particular DRAM location at the best sampling point. The FSM803 can also extend the process to program individual bit-by-bit timing adjustments with the DRAM if the DRAM has independently programmable bit-by-bit delay elements.

[0041]

[0054] Figure 9 is a flowchart of a method 900 for programming a delay circuit in a DRAM device according to one embodiment. Method 900 can be executed by processing logic which may include hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions executed on a processing device to perform hardware simulation), or a combination thereof. In one embodiment, method 900 is executed by a memory controller 102, as shown in Figure 1. In another embodiment, method 900 is executed by a command buffer 826, as shown in Figure 8.

[0042]

[0055] Referring to Figure 9, in block 902, method 900 begins by sending a known signal pattern on the CA bus of the memory module in loopback test mode. The memory module contains multiple DRAM devices at different DRAM locations on the flyby CA bus. The processing logic receives the loopback signal from the DRAM devices on the data bus (block 904). The processing logic determines the offset of each DRAM device (block 906). The processing logic programs each DRAM device with a value representing an individual timing offset of programmable delay, enabling timing adjustment between the clock edge of the clock signal and the CA sampling point in each DRAM device (block 908), and then method 900 ends.

[0043]

[0056] In a further embodiment, the processing logic determines a first timing offset between a first clock edge and a CA sampling point in the first DRAM device based on a loopback signal of the first DRAM device. The processing logic sends a first value representing the first timing offset to the first DRAM device. The first DRAM device can store the first value in a mode register. In another embodiment, the processing logic further determines a second timing offset between a second clock edge and a second CA sampling point in the second DRAM device based on a loopback signal of the second DRAM device, and sends a second value representing the second timing offset to the second DRAM device, the second timing offset being different from the first timing offset. The second DRAM device can store the second value in a mode register.

[0044]

[0057] In other embodiments, the processing logic determines a first timing offset for the clock signal and a second timing offset for the CA signal in the first DRAM device based on the loopback signal of the first DRAM device. The processing logic sends a first value representing the first timing offset and a second value representing the second timing offset to the first DRAM device. The first and second values, when applied to one or more delay elements in the first DRAM device, compensate for a first skew between the first clock edge and the CA sampling point in the first DRAM device. In further embodiments, the processing logic further determines a third timing offset for the second clock signal and a fourth timing offset for the second CA signal in the second DRAM device based on the loopback signal of the second DRAM device. The processing logic sends a third value representing the third timing offset and a fourth value representing the fourth timing offset to the second DRAM device. The second DRAM device may store the third and fourth values ​​in a mode register. The third and fourth values, when applied to one or more delay elements in the second DRAM device, correct a second skew between the second clock edge and the second CA sampling point in the second DRAM device.

[0045]

[0058] In other embodiments, the processing logic determines a first timing offset between a first clock edge and a chip selection (CS) sampling point in the first DRAM device based on a loopback signal from the first DRAM device, and sends a first value representing the first timing offset to the first DRAM device. The first DRAM device can store the first value in a mode register. In other embodiments, the processing logic determines a first timing offset between a first clock edge and a CA sampling point and between a first clock edge and a chip selection (CS) sampling point in the first DRAM device based on a loopback signal from the first DRAM device. The processing logic sends a first value representing the first timing offset to the first DRAM device. The first DRAM device can store the first value in a mode register.

[0046]

[0059] As described herein, due to the multi-destination nature of some types of buses, such as DDR5 backside buses from RCD to multiple DRAMs, reflections exist on the bus, resulting in different eye apertures for different DRAM devices and different bus bits. Adding skew trim on the receiver side can cause timing issues between the receiver and the internal clock of subsequent logic behind it.

[0047]

[0060] Aspects of this disclosure overcome timing problems by providing bitwise trim at the receiver. Aspects of this disclosure can apply a programmable amount of skew to each receiver for each individual clock signal, as described below with reference to Figures 10-12, and apply a delay to the output of each receiver. For example, if the delay of the clock signal is a first delay value Δt1 and the delay of the output receiver signal at the receiver output is a second delay value Δt2, this approach aligns the receiver's clock signal to the input eye center while maintaining a constant delay / eye at the receiver output, such that the sum of the first and second delay values ​​Δt1+Δt2 is equal to the offset between the earliest bit (leftmost eye center) and the latest bit (rightmost eye center). In at least one embodiment, the delay setting is generated using an algorithm such as that shown in Figure 10.

[0048]

[0061] Figure 10 is a flowchart of method 1000 for programming a delay circuit in a DRAM device according to one embodiment. Method 1000 can be executed by processing logic which may include hardware (e.g., circuitry, dedicated logic, programmable logic, microcode, etc.), software (e.g., instructions executed on a processing device to perform hardware simulation), or a combination thereof. In one embodiment, method 1000 is executed by a memory controller 102, as shown in Figure 1. In another embodiment, method 1000 is executed by a command buffer 826, as shown in Figure 8.

[0049]

[0062] Referring to Figure 10, in block 1002, method 900 begins with the processing logic determining the center of the eye aperture for each input bit with a minimum clock delay. The minimum clock delay makes it possible to find the input eye center for each input bit. Based on the eye aperture centers, the processing logic determines the time difference between the earliest and latest input bits (block 1004). For example, the earliest input bit is the leftmost eye center among all eye centers, and the latest input bit is the rightmost eye center. It can be assumed that the leftmost eye center is bit "e", the rightmost eye center is bit "n", and the eye centers for one or more bits "m" are between "e" and "n". The processing logic determines a first delay value for each of the input clock signals to the receiver and a second delay value for each of the output receiver signals (block 1006). Assuming the time difference between the eye centers of bit "n" and bit "e" is Δtn, the time difference between one or more bits "m" and bit "e" is Δtm. Then, for the earliest bit "e", a first delay value of zero (Δt=0) in the input clock signal (Rx clock) and a second delay value equal to the time difference Δtn at the receiver output are added to each receiver. This is because the earliest bit "e" is the leftmost eye center or the earliest eye center and does not require a delay in the input clock signal (Rx clock), but requires a delay equal to the delay seen in bit "n" at the Rx output. Then, for the latest bit "n", a first delay value equal to the time difference Δt=n in the input clock signal (Rx clock) and a second delay value of zero (Δt=0) at the receiver output are added to each receiver. This is because the slowest bit "n" is the rightmost or slowest eye center, requiring a delay in the input clock signal (Rx clock) but not in the Rx output. For the intermediate bit "m", a first delay value equal to Δt=m in the Rx clock and a second delay value equal to Δt=Δtn-Δtm in the Rx output are added.This is because the intermediate bit "m" lies between the eye centers of bits "e" and "n," and therefore the Rx clock requires a delay that is the difference between the delay of the eye center of bit "e" and its own input eye center. The difference in delay between its input eye center and the slowest bit "n" must then be added to the output of Rx.

[0050]

[0063] Referring again to Figure 10, the processing logic uses a first offset value of the input clock signal and a second delay value of the output receiver signal to program each receiver of the DRAM device, enabling timing adjustments between the clock edge of the clock signal and the sampling point for each bit (block 1008), and then method 1000 ends.

[0051]

[0064] The approach of Method 1000 is further illustrated using the example of three receivers for three bits in Figure 11.

[0052]

[0065] Figure 11 is a schematic diagram of three receivers and a delay element that can be individually programmed to provide bitwise trim by the three receivers, according to at least one embodiment. The first receiver 1102 receives a first input signal 1104 and provides a first output signal 1106. The second receiver 1108 receives a second input signal 1110 and provides a second output signal 1112. The third receiver 1114 receives a second input signal 1116 and provides a second output signal 1118. Using the method 1000 described above, the first receiver 1102 is determined to be the earliest bit e, the second receiver 1108 is determined to be the middle bit m, and the third receiver 1114 is determined to be the latest bit n. As described above, the time difference between the earliest bit e and the latest bit n is determined as Δtn. For the first receiver 1102 corresponding to the earliest bit "e", the first delay element 1120 is programmed with a first delay value of zero (Δt=0) of the input clock signal (Rx clock) 1122, and the second delay element 1124 is programmed with a second delay value equal to the time difference Δtn at the receiver output. The second delay element 1124 receives and delays the first output signal 1106, and provides the delayed output signal 1126 to the logic 1128, which is clocked by the internal clock 1130. This is because the earliest bit "e" is either the leftmost eye center or the earliest eye center and does not require a delay of the input clock signal (Rx clock), but requires a delay equal to the delay seen for bit "n" at the Rx output.

[0053]

[0066] For the second receiver 1108 corresponding to the intermediate bit "m", the third delay element 1132 controls the input clock signal (Rx clock) 1122's Dt m The first delay is programmed to be equal to (Δt=m), and the fourth delay element 1136 is programmed to be Dt=Dt at the receiver output. n -Dt mIt is programmed with a second delay value equal to (Δt = Δtn - Δtm). A third delay element 1132 receives and delays the input clock signal 1122 and provides the delayed clock signal 1134 to a second receiver 1132. A fourth delay element 1136 receives and delays the second output signal 1112 and provides the delayed output signal 1138 to logic 1128 which is clocked by the internal clock 1130. This is because the intermediate bit "m" is between the eye centers of bit "e" and bit "n", and therefore the Rx clock requires a delay which is the difference between the delay of the eye center of bit "e" and its own input eye center. The difference in delay between its input eye center and the slowest bit "n" must then be added to the output of Rx.

[0054]

[0067] For the third receiver 1108 corresponding to the slowest bit "n", the fifth delay element 1140 is programmed with a first delay value equal to the time difference Δt=n, and the sixth delay element 1144 is programmed with a second delay value of zero (Δt=0) at the receiver output. The fifth delay element 1140 receives and delays the input clock signal 1122 and provides the delayed clock signal 1142 to the third receiver 1132. This is because the slowest bit "n" is the rightmost eye center or the slowest eye center, requiring a delay in the input clock signal (Rx clock) but not a delay at the Rx output.

[0055]

[0068] Figure 12 is a block diagram showing a DRAM CA interface 1200 having a programmable delay between a clock signal and a CA / CS signal according to one embodiment. The DRAM CA interface 1200 is similar to the DRAM CA interface 500, as indicated by the same reference numerals, except that the DRAM CA interface 1200 additionally includes a third mode register 1202, a second set of delay elements 1204 (delay2), a fourth mode register 1206, and a third set of delay elements 1208. The second set of delay elements 1204 can be individually controlled by corresponding values ​​stored in the third mode register 1202. Each of the second set of delay elements 1204 delays the clock signal 503 by a programmable delay corresponding to the respective value in the third mode register 1202. In one embodiment, the values ​​stored in the third mode register 1202 and the fourth mode register 1206 correspond to the first and second delay values ​​described above with respect to Figures 10 and 11, respectively.

[0056]

[0069] In one embodiment, the approach described above with respect to Figures 10 to 12 can be used with the RCD-CPU interface and / or the RCD-memory interface (RDIMM / LRDIMM), CPU-memory address (UDIMM), and the RCD-DB interface (LRDIMM).

[0057]

[0070] Although the operation of the methods described herein is illustrated and described in a specific order, the order of operation of each method may be modified so that certain operations may be performed in reverse order, or so that certain operations may be performed at least partially concurrently with other operations. In a particular implementation, instructions or suboperations of separate operations may be performed intermittently and / or alternately.

[0058]

[0071] It should be understood that the above description is intended as an example, not an limitation. Many other implementations will be obvious to those skilled in the art upon reading and understanding the above description. Therefore, the scope of this disclosure should be determined by reference to the attached claims, together with the entire scope of equivalents to which such claims are entitled.

[0059]

[0072] The above description includes numerous details. However, it will be apparent to those skilled in the art that the aspects of this disclosure can be implemented without these specific details. In some cases, to avoid obscuring this disclosure, well-known structures and devices are shown in block diagram form rather than in detail.

[0060]

[0073] Some of the detailed explanations above present algorithms and symbolic representations of operations on data bits in computer memory. These algorithmic descriptions and representations are means used by those skilled in data processing techniques to most effectively communicate their work to others skilled in the art. An algorithm is generally considered here as a consistent set of steps leading to a desired result. A step is a process that requires the physical manipulation of physical quantities. Usually, but not always, these quantities take the form of electrical or magnetic signals that can be stored, transferred, combined, compared, and otherwise manipulated. It has been found that calling these signals bits, values, elements, symbols, characters, terms, numbers, etc., is sometimes more convenient, mainly for reasons of common use.

[0061]

[0074] However, it should be noted that these and similar terms should all be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. Unless otherwise specified, as will be evident from the following discussion, throughout this explanation, discussions using terms such as “receive,” “decide,” “select,” “memorize,” and “set” are understood to refer to the actions and processes of a computer system or similar electronic computing device that manipulate data represented as physical (electronic) quantities in the registers and memory of a computer system to convert it into other data similarly represented as physical quantities in computer system memory or registers, or other such information storage, transmission, or display devices.

[0062]

[0075] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may include a general-purpose computer that may be specifically constructed for a required purpose or selectively operated or reconfigured by a computer program stored in the computer. Such computer programs may be stored on computer-readable storage media, such as, but not limited to, any type of disk, e.g., floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0063]

[0076] The algorithms and representations presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used with the programs taught herein, or it may be advantageous to construct more specialized equipment to perform the steps in the manner required. The structures required for various such systems will become apparent with the descriptions herein. Furthermore, aspects of this disclosure are not described with reference to any particular programming language. It will be understood that various programming languages ​​may be used to implement the teachings of this disclosure as described herein.

[0064]

[0077] Aspects of the present disclosure may be provided as a computer program product or software which may include a machine-readable medium storing instructions that can be used to program a computer system (or other electronic device) to perform the processing provided for in the present disclosure. The machine-readable medium includes any procedure for storing or transmitting information in a form that can be read by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer)-readable storage medium (e.g., read-only memory ("ROM"), random-access memory ("RAM"), magnetic disk storage medium, optical storage medium, flash memory device, etc.).

Claims

1. A first interface for receiving command / address (CA) signals and clock signals, A data interface wherein the first interface is for receiving a pattern of CA signals in CA bus loopback mode, and the data interface is for outputting the received pattern of CA signals in CA bus loopback mode, A mode register for storing a value representing the timing offset between the clock signal and the sampling point of the first interface, A programmable delay line coupled between the clock terminal and the clock buffer, A delay-locked loop (DLL) circuit comprising a first delay element and a second delay element, wherein the DLL circuit is for controlling the programmable delay of the programmable delay line using the first and second delay elements, the first delay element being controlled by a first timing offset value in the mode register, and the second delay element being controlled by a second value stored in the mode register, An integrated circuit memory device comprising the above features.

2. Command / Address (CA) bus interface, Data bus interface, Circuits coupled to the CA bus interface and the data bus interface, The circuit is equipped with the following, and in CA bus loopback mode, Sending a known signal pattern via the CA bus interface, The data bus interface receives a loopback signal, Determining the offset for each of multiple integrated circuit memory devices, Each of the aforementioned multiple integrated circuit memory devices is programmed with a value representing the individual timing offset of the programmable delay, thereby enabling timing adjustment between the clock edge of the clock signal and the CA sampling point in each of the aforementioned integrated circuit memory devices. A memory controller, which is used to perform [this action].

3. The aforementioned circuit is Based on the loopback signal of the first integrated circuit memory device among the plurality of integrated circuit memory devices, a first timing offset between the first clock edge and the CA sampling point in the first integrated circuit memory device is determined. Sending a first value representing the first timing offset to the first integrated circuit memory device, The memory controller according to claim 2, which is for further execution of the above.

4. The aforementioned circuit is Based on the loopback signal of the second integrated circuit memory device among the plurality of integrated circuit memory devices, a second timing offset is determined between the second clock edge and the second CA sampling point in the second integrated circuit memory device. Sending a second value representing the second timing offset to the second integrated circuit memory device, wherein the second timing offset is different from the first timing offset, The memory controller according to claim 3, which is for further performing the above.

5. The aforementioned circuit is Based on the loopback signal of the first integrated circuit memory device among the plurality of integrated circuit memory devices, a first timing offset of the clock signal and a second timing offset of the CA signal in the first integrated circuit memory device are determined. Sending a first value representing the first timing offset and a second value representing the second timing offset to the first integrated circuit memory device, wherein the first value and the second value, when applied to one or more delay elements in the first integrated circuit memory device, correct a first skew between a first clock edge and a CA sampling point in the first integrated circuit memory device, and sending the second value to the first integrated circuit memory device. The memory controller according to claim 2, which is for further execution of the above.

6. The aforementioned circuit is Based on the loopback signal of the second integrated circuit memory device among the plurality of integrated circuit memory devices, the third timing offset of the second clock signal and the fourth timing offset of the second CA signal in the second integrated circuit memory device are determined. Sending a third value representing the third timing offset and a fourth value representing the fourth timing offset to the second integrated circuit memory device, wherein the third value and the fourth value, when applied to one or more delay elements in the second integrated circuit memory device, correct a second skew between a second clock edge and a second CA sampling point in the second integrated circuit memory device; and sending the fourth value to the second integrated circuit memory device. The memory controller according to claim 5, which is for further performing the above.

7. The aforementioned circuit is Based on the loopback signal of the first integrated circuit memory device among the plurality of integrated circuit memory devices, a first timing offset is determined between the first clock edge and the chip selection (CS) sampling point in the first integrated circuit memory device, Sending a first value representing the first timing offset to the first integrated circuit memory device, The memory controller according to claim 2, which is for further execution of the above.

8. The aforementioned circuit is Based on the loopback signal of the first integrated circuit memory device among the plurality of integrated circuit memory devices, a first timing offset is determined between the first clock edge and the CA sampling point and between the first clock edge and the chip selection (CS) sampling point in the first integrated circuit memory device. Sending a first value representing the first timing offset to the first integrated circuit memory device, The memory controller according to claim 2, which is for further execution of the above.

9. Depending on the device, in loopback test mode, known signal patterns are sent to multiple integrated circuit memory devices via the command / address (CA) bus, The aforementioned device receives loopback signals from the plurality of integrated circuit memory devices via a data bus, The device determines the offset for each of the plurality of integrated circuit memory devices, The device enables each of the plurality of integrated circuit memory devices to be programmed with a value representing the individual timing offset of the programmable delay, thereby allowing each of the integrated circuit memory devices to perform timing adjustment between the clock edge of the clock signal and the CA sampling point. Methods that include...

10. The device determines a first timing offset between a first clock edge and a CA sampling point in the first integrated circuit memory device based on the loopback signal of the first integrated circuit memory device among the plurality of integrated circuit memory devices. The device sends a first value representing the first timing offset to the first integrated circuit memory device, The method according to claim 9, further comprising:

11. The device determines a second timing offset between the second clock edge and the second CA sampling point in the second integrated circuit memory device based on the loopback signal of the second integrated circuit memory device among the plurality of integrated circuit memory devices. The device sends a second value representing the second timing offset to the second integrated circuit memory device, wherein the second timing offset is different from the first timing offset. The method according to claim 10, further comprising:

12. The device determines a first timing offset of the clock signal and a second timing offset of the CA signal in the first integrated circuit memory device based on the loopback signal of the first integrated circuit memory device among the plurality of integrated circuit memory devices. The device sends a first value representing the first timing offset and a second value representing the second timing offset to the first integrated circuit memory device, wherein the first value and the second value, when applied to one or more delay elements in the first integrated circuit memory device, correct a first skew between a first clock edge and a CA sampling point in the first integrated circuit memory device, and the second value is sent to the first integrated circuit memory device. The method according to claim 9, further comprising:

13. The device determines, based on the loopback signal of the second integrated circuit memory device among the plurality of integrated circuit memory devices, the third timing offset of the second clock signal and the fourth timing offset of the second CA signal in the second integrated circuit memory device. The device sends a third value representing the third timing offset and a fourth value representing the fourth timing offset to the second integrated circuit memory device, wherein the third value and the fourth value, when applied to one or more delay elements in the second integrated circuit memory device, correct a second skew between the second clock edge and the second CA sampling point in the second integrated circuit memory device; and the fourth value is sent to the second integrated circuit memory device. The method according to claim 12, further comprising:

14. The device determines a first timing offset between a first clock edge and a chip selection (CS) sampling point in the first integrated circuit memory device based on the loopback signal of the first integrated circuit memory device among the plurality of integrated circuit memory devices. The device sends a first value representing the first timing offset to the first integrated circuit memory device, The method according to claim 9, further comprising:

15. The device determines a first timing offset between the first clock edge and the CA sampling point and between the first clock edge and the chip selection (CS) sampling point in the first integrated circuit memory device, based on the loopback signal of the first integrated circuit memory device among the plurality of integrated circuit memory devices. The device sends a first value representing the first timing offset to the first integrated circuit memory device, The method according to claim 9, further comprising:

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