A circuit and method for automatically eliminating spi interface delay differences

Abstract

The application provides a kind of circuit and method for automatically eliminating SPI interface delay difference, belongs to serial peripheral interface technical field, solve the problem that due to delay difference in SPI interface communication, clock frequency cannot be high, and further affect transmission efficiency;Including De-skew circuit, SPI sending circuit is connected in turn multi-bit data line, De-skew circuit and receiving circuit, the De-skew circuit includes high-precision adjustable delay line group;The method for eliminating delay difference is: using double-edge sampling mode for SPI communication, eliminate the delay difference of SPI slave and SPI host, including first eliminating the delay difference between multi-bit data line connected with receiving circuit, then eliminate the delay difference between clock line and data line;The application realizes the effect of not producing delay difference in the process of SPI interface communication, so that the data effective sampling window is large, improve the clock frequency and transmission efficiency of SPI interface communication.

Description

Technical Field

[0001] This invention belongs to the field of Serial Peripheral Interface (SPI interface) technology, specifically relating to a circuit and method for automatically eliminating SPI interface delay differences. Background Technology

[0002] Serial Peripheral Interface (SPI) is a synchronous peripheral interface that enables microcontrollers to communicate with various peripheral devices in a serial manner to exchange information. In traditional SPI interface communication circuits, in order to improve the transmission bandwidth of the SPI interface communication circuit, the width of the data transmission lines used by the SPI interface is usually increased, such as increasing the single-wire SPI interface to a 4-wire SPI interface or an 8-wire SPI interface.

[0003] In existing multi-bit SPI interfaces, it is impossible to achieve equidistant routing between different data lines and between data lines and clock lines in printed circuit board (PCB) designs. This results in different transmission delays between different data lines and between data lines and clock lines at the receiving end during SPI interface communication, creating a delay difference. This delay difference reduces the effective sampling window for receiving data at the receiving end, making it difficult to achieve a high clock frequency for SPI interface communication, thus affecting the transmission efficiency of SPI interface communication. Summary of the Invention

[0004] To address the issue mentioned in the background art where delay differences during multi-line SPI interface communication make it difficult to increase the clock frequency and improve transmission efficiency, this invention achieves the effect of eliminating delay differences during SPI interface communication through dual-edge sampling and hardware circuit design and methods to eliminate delay differences. This results in a larger effective data sampling window and improves the clock frequency and transmission efficiency of SPI interface communication.

[0005] The present invention employs the following technical solutions to achieve its objective:

[0006] A circuit for automatically eliminating SPI interface delay differences includes an SPI master and an SPI slave. The SPI master includes a master transmitting circuit and a master receiving circuit, and the SPI slave includes a slave transmitting circuit and a slave receiving circuit. It also includes a master de-skew circuit and a slave de-skew circuit. The master transmitting circuit is sequentially connected to a multi-bit data line, the slave de-skew circuit, and the slave receiving circuit. The slave transmitting circuit is sequentially connected to the multi-bit data line, the master de-skew circuit, and the master receiving circuit. The master receiving circuit is further sequentially connected to an adjustable delay circuit and a clock gating circuit, with the clock gating circuit connected to the master de-skew circuit. Both the master and slave de-skew circuits include a high-precision adjustable delay line group, the number of bits in the high-precision adjustable delay line group corresponding to the number of bits in the multi-bit data line.

[0007] Furthermore, each high-precision adjustable delay line in the high-precision adjustable delay line group includes multiple delay units connected in sequence, and the multiple delay units are used together to change the delay value of the high-precision adjustable delay line.

[0008] This invention also provides a method for automatically eliminating SPI interface latency differences, comprising:

[0009] Communication between the SPI master and SPI slave is established using a dual-edge sampling method.

[0010] Eliminate the delay difference of the SPI slave, including SPI slave algorithm C: first eliminate the delay difference between the multiple data lines connected to the slave receiving circuit, and then eliminate the delay difference between the clock line and the slave data line;

[0011] Eliminate latency differences in the SPI master, including SPI master algorithm Z: first eliminate latency differences between multiple data lines connected to the master receiving circuit, and then eliminate latency differences between the clock line and the master data line.

[0012] Furthermore, the elimination of latency differences between SPI slave devices also includes SPI master algorithm C, the steps of which are as follows:

[0013] a1. Adjust the SPI master clock frequency to low frequency mode;

[0014] a2. The SPI master continuously sends training sequence data to the SPI slave;

[0015] a3. Wait for the SPI slave to receive data and complete the elimination of the SPI slave's delay difference;

[0016] a4. Adjust the SPI host clock frequency to high-frequency mode to perform SPI communication.

[0017] Furthermore, the elimination of latency differences between the SPI master and slave systems also includes the SPI slave algorithm Z, the steps of which are as follows:

[0018] b1. The SPI slave continuously sends training sequence data to the SPI master.

[0019] b2. Wait for the SPI master to receive data and complete the elimination of the SPI master's latency difference;

[0020] b3. Perform SPI communication.

[0021] Specifically, the training sequence data is 0x00FF00FF00FF00FF.

[0022] Furthermore, in the SPI slave algorithm C, the delay difference of the SPI slave is eliminated by adjusting the delay of the slave de-skew circuit; in the SPI master algorithm Z, the delay difference of the SPI master is eliminated by adjusting the delay of the master de-skew circuit; the de-skew circuit includes a high-precision adjustable delay line group, and the delay of the de-skew circuit is adjusted by adjusting the delay of each high-precision adjustable delay line in the high-precision adjustable delay line group.

[0023] Furthermore, in eliminating the latency difference of the SPI slave, the SPI slave algorithm C steps are as follows:

[0024] c1. Gradually increase the delay of data cRxd[n], where n represents the nth data line. Find the previous transition edge of cRxd[n], calculate the distance cDn between the rising edge of the clock signal and the previous transition edge of cRxd[n], and record the minimum value among all cDn as cDmin. Use the difference between cDn and cDmin as the delay value of the nth high-precision adjustable delay line corresponding to cRxd[n]. At this time, the delay difference between multiple data lines cRxd has been eliminated, and then proceed to step c3. If the delay of data line cRxd[n] is increased to the maximum value and the previous transition edge of cRxd[n] cannot be found, then proceed to step c2.

[0025] c2. Gradually increase the clock delay, find the next transition edge of the data cRxd[n], calculate the distance cRn between the rising edge of the clock signal and the next transition edge of cRxd[n], record the maximum value among all cRn as cRmax, and take the difference between cRn and cRmax as the delay value of the nth high-precision adjustable delay line corresponding to cRxd[n]. At this time, the delay difference between multiple data lines cRxd has been eliminated, and then proceed to step c4.

[0026] c3. Gradually increase the delay length of the clock line, find the next transition edge of the data cRxd, record the interval between the rising edge of the clock signal and the next transition edge of the data cRxd as cL. If cDmin > cL, delay the data cRxd by half of the difference between cDmin and cL. If cDmin < cL, delay the clock by half of the difference between cDmin and cL, thus eliminating the delay difference of the SPI slave.

[0027] c4. Gradually increase the delay length of the data line cRxd, find the previous transition edge of the data line cRxd, record the interval between the rising edge of the clock signal and the previous transition edge of the data line cRxd as cP. If cDmax < cP, delay the data by half of the difference between cDmax and cP. If cDmax > cP, delay the clock by half of the difference between cDmax and cP, thus eliminating the delay difference of the SPI slave.

[0028] Further, in eliminating the delay difference of the SPI master, the steps of the SPI master algorithm Z are as follows:

[0029] d1. Adjust the clock frequency of the SPI master to the low-frequency mode;

[0030] d2. Gradually increase the delay of the data zRxd[n], find the previous transition edge of zRxd[n], calculate the interval zDn between the rising edge of the clock signal and the previous transition edge of zRxd[n]. Denote the minimum value among all zDn as zDmin, and use the difference between zDn and zDmin as the delay value of the nth high-precision adjustable delay line corresponding to zRxd[n]. At this time, the delay difference between multiple data lines zRxd has been eliminated, and then proceed to step d4; if the delay length of the data line zRxd[n] has increased to the maximum value and the previous transition edge of zRxd[n] cannot be found, then proceed to step d3;

[0031] d3. Gradually increase the delay of the clock, find the next transition edge of the data zRxd[n], calculate the interval zRn between the rising edge of the clock signal and the next transition edge of zRxd[n]. Denote the maximum value among all zRn as zRmax, and use the difference between zRn and zRmax as the delay value of the nth high-precision adjustable delay line corresponding to zRxd[n]. At this time, the delay difference between multiple data lines zRxd has been eliminated;

[0032] d4. Adjust the clock frequency of the SPI master to the high-frequency mode;

[0033] d5. The SPI host reads the training sequence data. If the training sequence data can be correctly read, gradually increase the delay of the data zRxd, find the previous edge transition of the data zRxd, record the distance between the previous edge transition of the data zRxd and the rising edge of the clock as zP, then gradually increase the delay of the clock, find the next edge transition of the data zRxd, and record the distance between the next edge transition of the data zRxd and the rising edge of the clock as zL. If zP > zL, delay the data zRxd by half of the difference between zP and zL. If zP < zL, delay the clock by half of the difference between zP and zL to complete eliminating the delay difference of the SPI host. If the SPI host cannot correctly read the training sequence data, proceed to step d6;

[0034] d6. Gradually increase the delay of the clock until the SPI host correctly reads the training sequence data for the first time. Record the clock delay at this time as Tstart. Continue to gradually increase the delay of the clock until the training sequence data is read incorrectly again. Record the clock delay when the training sequence data was last correctly read as Tend. Take the average of the clock delays Tstart and Tend to complete eliminating the delay difference of the SPI host.

[0035] In summary, due to the adoption of this technical solution, the beneficial effects of the present invention are as follows:

[0036] The present invention realizes the function of automatically eliminating the communication delay difference of the SPI interface by designing a circuit for eliminating the delay difference of the SPI interface and a matching method. In the SPI communication process, the double-edge sampling method is adopted, so that the SPI communication bandwidth is doubled at the same SPI clock frequency; by eliminating the delay difference between multiple data lines and then eliminating the delay difference between the clock line and the data line, the effective window for receiving data in the SPI communication process is relatively large, and the rising edge and falling edge of the clock signal are aligned with the middle position of the data window. Therefore, the clock frequency can be increased without affecting the transmission quality, thereby further improving the transmission efficiency of the SPI communication process. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 is a schematic diagram of the principle of a traditional SPI interface circuit;

[0038] Figure 2 is a schematic diagram of the principle of a circuit for automatically eliminating the delay difference of the SPI interface;

[0039] Figure 3 is a schematic diagram of the hardware principle of the De-skew circuit;

[0040] Figure 4 is a schematic diagram of the principle of a high-precision adjustable delay line;

[0041] Figure 5This is a schematic diagram of the delay unit.

[0042] Figure 6 A diagram showing the clock data relationship of a dual-edge sampled SPI interface;

[0043] Figure 7 This is a schematic diagram of the training sequence data;

[0044] Figure 8 This diagram illustrates the distance between the rising edge of the clock and the preceding edge of different data lines.

[0045] Figure 9 This diagram illustrates the distance between the rising edge of the clock and the next transition edge of different data lines.

[0046] Figure 10 This is a schematic diagram showing the distance between the rising edge of the clock and the next transition edge of the data line after delay elimination;

[0047] Figure 11 This is a schematic diagram showing the distance between the rising edge of the clock and the preceding edge of the data line after delay elimination.

[0048] Figure 12 A schematic diagram illustrating that the data reception delay of the SPI master is less than the clock cycle;

[0049] Figure 13 A diagram illustrating an SPI master receiving data with a delay greater than the clock cycle.

[0050] Figure 14 Simulation waveform diagram for eliminating delay differences in the slave receiver circuit;

[0051] Figure 15 Before and after comparison of eliminating delay differences in the slave receiver circuit;

[0052] Figure 16 Simulation waveform diagram for eliminating delay differences in the host receiving circuit;

[0053] Figure 17 Before and after comparison of eliminating delay differences in the host receiving circuit;

[0054] Figure 18 This is a schematic diagram illustrating the principle of the method of the present invention. Detailed Implementation

[0055] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0056] Therefore, the following detailed description of the embodiments of the invention provided in the accompanying drawings is not intended to limit the scope of the claimed invention, but merely to illustrate selected embodiments of the invention. All other embodiments obtained by those skilled in the art based on the embodiments of the invention without inventive effort are within the scope of protection of the invention.

[0057] A schematic diagram of a traditional SPI interface circuit is shown below. Figure 1 As shown, it includes an SPI master and an SPI slave. The SPI master has a master transmitting circuit and a master receiving circuit, and the SPI slave has a slave transmitting circuit and a slave receiving circuit. The master transmitting circuit is connected to the slave receiving circuit through multiple data lines, and the slave transmitting circuit is connected to the master receiving circuit through multiple data lines.

[0058] The schematic diagram of the circuit for automatically eliminating SPI interface delay differences provided by this invention is shown below. Figure 2 As shown, it includes an SPI master and an SPI slave. The SPI master includes a master transmitting circuit and a master receiving circuit. The SPI slave includes a slave transmitting circuit and a slave receiving circuit. It also includes a master de-skew circuit and a slave de-skew circuit. The master transmitting circuit is sequentially connected to a multi-bit data line, the slave de-skew circuit, and the slave receiving circuit. The slave transmitting circuit is sequentially connected to a multi-bit data line, the master de-skew circuit, and the master receiving circuit. The master receiving circuit is also sequentially connected to an adjustable delay circuit and a clock gating circuit. The clock gating circuit is connected to the master de-skew circuit.

[0059] like Figure 3 As shown, both the master and slave de-skew circuits include a high-precision adjustable delay line group, and the number of bits in the high-precision adjustable delay line group corresponds to the number of bits in the multi-bit data line. In this embodiment, the master and slave devices that perform SPI communication are connected by an 8-bit data line, so the corresponding high-precision adjustable delay line group will have 9 high-precision adjustable delay lines, including 8 corresponding to the number of data lines and 1 corresponding to the clock line.

[0060] like Figure 4 As shown, each high-precision adjustable delay line in the high-precision adjustable delay line group includes multiple delay units connected in sequence. These multiple delay units are used together to change the delay value of the high-precision adjustable delay line. In this embodiment, the total number of delay units is 128. The specific structure of the delay unit is as follows: Figure 5 As shown, it includes one NOT gate and three NOR gates.

[0061] The method for automatically eliminating SPI interface delay differences using the above circuit is as follows: Figure 18As shown, in this implementation, the specific method is as follows: A dual-edge sampling method is used to establish communication between the SPI master and the SPI slave, which doubles the transmission bandwidth under the same SCLK clock frequency. Figure 6 As shown.

[0062] The delay difference between the SPI slave and the SPI master is eliminated separately. In this embodiment, the delay difference between the SPI slave is eliminated first. The SPI slave algorithm C is performed: first, the delay difference between the 8-bit data lines connected to the slave receiving circuit is eliminated, and then the delay difference between the clock line and the slave data line is eliminated.

[0063] When eliminating the latency difference of the SPI slave device, the SPI master will also cooperate by performing SPI master algorithm C, the steps of which are as follows:

[0064] a1. Adjust the SPI master clock frequency to low frequency mode; in low frequency mode, the delay difference is not sensitive, and the slave can correctly receive data.

[0065] a2. The SPI master continuously sends training sequence data to the SPI slave, and the training sequence data is 0x00FF00FF00FF00FF; this training sequence data causes the data line signal of the slave receiving circuit to continuously switch between 0 and 1, such as... Figure 7 As shown;

[0066] a3. Wait for the SPI slave to receive data and complete the elimination of the SPI slave's latency difference; the SPI slave will spend some time repeatedly receiving training sequence data and adjusting the latency until the latency difference is finally eliminated;

[0067] a4. Adjust the SPI host clock frequency to high-frequency mode to perform SPI communication.

[0068] When eliminating latency differences in SPI slave devices, SPI slave algorithm C is the main algorithm for latency difference elimination. The specific steps are as follows:

[0069] c1. Gradually increase the delay of data cRxd[n], where n represents the nth data line. Find the preceding edge of cRxd[n] and calculate the distance cDn between the rising edge of the clock signal and the preceding edge of cRxd[n]. Figure 8 As shown ( Figure 8Among them, d0 to d7 are the specific values of Dn described in this step, and the prefix c represents the meaning of slave device; similarly, Rxd[0] to Rxd[7] are the specific values of Rxd[n] described in this step, and the prefix c represents the meaning of slave device); in this embodiment, there are a total of 8 values including cD0 to cD7. Denote the minimum value among all cDn as cDmin, and use the difference between cDn and cDmin as the delay value of the nth high-precision adjustable delay line corresponding to cRxd[n]. That is, a total of 8 high-precision adjustable delay lines are adjusted to adjust the delay of the De-skew circuit. At this time, the delay difference between the 8-bit data lines cRxd has been eliminated, and then enter step c3; if the delay of the data line cRxd[n] increases to the maximum value and the previous transition edge of cRxd[n] cannot be found, then enter step c2;

[0070] c2. Gradually increase the delay of the clock to find the next transition edge of the data cRxd[n]. n represents the nth data line. Calculate the interval cRn between the rising edge of the clock signal and the next transition edge of cRxd[n], as Figure 9 shown in Figure 9 Among them, R0 to R7 are the specific values of Rn described in this step, and the prefix c represents the meaning of slave device; similarly, Rxd[0] to Rxd[7] are the specific values of Rxd[n] described in this step, and the prefix c represents the meaning of slave device); in this embodiment, there are a total of 8 values including cR0 to cR7. Denote the maximum value among all cRn as cRmax, and use the difference between cRn and cRmax as the delay value of the nth high-precision adjustable delay line corresponding to cRxd[n]. At this time, the delay difference between the 8-bit data lines cRxd has been eliminated, and then enter step c4;

[0071] c3. Gradually increase the delay length of the clock line to find the next transition edge of the data cRxd. Denote the interval between the rising edge of the clock signal and the next transition edge of the data cRxd as cL, as Figure 10 shown in Figure 10 Among them, L is cL in this step, and the prefix c represents the meaning of slave device); if cDmin > cL, delay the data cRxd by half of the difference between cDmin and cL. If cDmin < cL, delay the clock by half of the difference between cDmin and cL to complete eliminating the delay difference of the SPI slave device and end the SPI slave device algorithm;

[0072] c4. Gradually increase the delay length of the data line cRxd to find the previous transition edge of the data line cRxd. Denote the interval between the rising edge of the clock signal and the previous transition edge of the data line cRxd as cP, as Figure 11 shown in Figure 11In this case, P is cP in this step, and the prefix c represents the meaning of slave device); if cDmax < cP, delay the data by half of the difference between cDmax and cP, if cDmax > cP, delay the clock by half of the difference between cDmax and cP, complete eliminating the delay difference of the SPI slave device, and end the SPI slave device algorithm.

[0073] Through the above SPI master device algorithm C and SPI slave device algorithm C, the delay difference of the SPI slave device is eliminated.

[0074] Continue to eliminate the delay difference of the SPI master device, and the SPI master device algorithm Z will be performed: first eliminate the delay difference between the 8-bit data lines connected to the master device receiving circuit, and then eliminate the delay difference between the clock line and the data lines at the master device end.

[0075] When eliminating the delay difference of the SPI master device, the SPI slave device will also cooperate to perform the SPI slave device algorithm Z, and the steps are as follows:

[0076] b1. The SPI slave device continuously sends training sequence data to the SPI master device; the training sequence data is 0x00FF00FF00FF00FF; this training sequence data causes the data line signals of the slave device receiving circuit to continuously make jumps between 0 and 1, as Figure 7 shown; <000019⑧>

[0077] b2. Wait for the SPI master device to receive the data and complete eliminating the delay difference of the SPI master device; the SPI master device will spend some time repeating to receive the training sequence data and perform delay adjustment until finally the delay difference is eliminated;

[0078] b3. Perform SPI communication.

[0079] When eliminating the delay difference of the SPI master device, the SPI master device algorithm Z is the main algorithm for eliminating the delay difference, and the specific steps are as follows:

[0080] d1. Adjust the clock frequency of the SPI master device to the low-frequency mode;

[0081] d2. Gradually increase the delay of the data zRxd[n], find the previous transition edge of zRxd[n], and calculate the distance zDn between the rising edge of the clock signal and the previous transition edge of zRxd[n], as Figure 8 shown ( Figure 8Among them, d0 to d7 are the specific values of Dn described in this step, and the prefix z represents the meaning of the host; similarly, Rxd[0] to Rxd[7] are the specific values of Rxd[n] described in this step, and the prefix z represents the meaning of the host); the minimum value among all zDn is denoted as zDmin, and the difference between zDn and zDmin is used as the delay value of the nth high-precision adjustable delay line corresponding to zRxd[n], that is, the delay values of 8 high-precision adjustable delay lines are adjusted in total, thereby adjusting the delay of the De-skew circuit. At this time, the delay difference between the 8-bit data lines zRxd has been eliminated, and then step d4 is entered; if the delay length of the data line zRxd[n] increases to the maximum value and the previous transition edge of zRxd[n] cannot be found, then step d3 is entered;

[0082] d3. Gradually increase the delay of the clock, find the next transition edge of the data zRxd[n], and calculate the distance zRn between the rising edge of the clock signal and the next transition edge of zRxd[n], as Figure 9 shown ( Figure 9 Among them, R0 to R7 are the specific values of Rn described in this step, and the prefix z represents the meaning of the host; similarly, Rxd[0] to Rxd[7] are the specific values of Rxd[n] described in this step, and the prefix z represents the meaning of the host); the maximum value among all zRn is denoted as zRmax, and the difference between zRn and zRmax is used as the delay value of the nth high-precision adjustable delay line corresponding to zRxd[n]. At this time, the delay difference between the multi-bit data lines zRxd has been eliminated;

[0083] d4. Adjust the clock frequency of the SPI host to the high-frequency mode;

[0084] d5. The SPI host reads the training sequence data. If the training sequence data can be correctly read, as Figure 12 shown, that is, the delay of the received data is less than the clock period at this time; then gradually increase the delay of the data zRxd, find the previous transition edge of the data zRxd, and record the distance between the previous transition edge of the data zRxd and the rising edge of the clock as zP ( Figure 12 In P, the prefix z represents the host), then gradually increase the delay of the clock, find the next transition edge of the data zRxd, and record the distance between the next transition edge of the data zRxd and the rising edge of the clock as zL ( Figure 12 In L, the prefix z represents the host). If zP > zL, delay the data zRxd by half of the difference between zP and zL. If zP < zL, delay the clock by half of the difference between zP and zL to complete eliminating the delay difference of the SPI host and end the SPI host algorithm; if the SPI host cannot correctly read the training sequence data, then step d6 is entered;

[0085] d6. As Figure 13As shown, if the SPI master cannot correctly read the training sequence data, it means that the delay in receiving the data is greater than the clock cycle. Then, the clock delay is gradually increased until the SPI master correctly reads the training sequence data for the first time. The clock delay at this time is recorded as Tstart. The clock delay is gradually increased again until the training sequence data is read incorrectly again. The clock delay when the training sequence data is read correctly for the last time is recorded as Tend. The average of the clock delays Tstart and Tend is used to eliminate the delay difference of the SPI master and end the SPI master algorithm.

[0086] The latency difference of the SPI master is eliminated by using the above-mentioned SPI slave algorithm Z and SPI master algorithm Z.

[0087] Once the latency difference between the SPI slave and the SPI master is eliminated, the latency difference elimination process of the entire SPI communication interface is completed, and actual SPI communication can be performed.

[0088] In this embodiment, the maximum delay difference that can be eliminated is as shown in the following formula (1):

[0089] R de-skew =Dly max -0.5*T slow_ssiclk (1)

[0090] R de_skew For the maximum delay difference, Dly max T represents the maximum delay value of the high-precision adjustable delay line. slow_ssiclk This is the low-frequency clock cycle value of the SSI clock.

[0091] A verification environment was built using SYNOPSYS's VCS simulation software to test the performance of the above algorithms. The low-frequency SSI clock was 50MHz, the high-frequency SSI clock was 200MHz, and the maximum delay of the delay line was 15ns. The experiment proved that the algorithm can support delay differences within a range of 5ns.

[0092] like Figure 14 The figure shown is a simulation waveform diagram of the SPI slave receiver circuit eliminating delay differences, as follows: Figure 15 The image shows a comparison of the SPI slave receiving circuit before and after eliminating the delay difference. As can be seen from the image, due to the transmission delay difference, the effective data window is small and the data cannot be sampled correctly. After the delay difference elimination algorithm, the effective data window is larger, and the rising and falling edges of the SCLK clock are aligned with the middle position of the data window.

[0093] like Figure 16 The figure shown is a simulation waveform diagram of the SPI master receiving circuit eliminating delay differences, as follows: Figure 17The image shows a comparison of the SPI host receiving circuit before and after eliminating the delay difference. As can be seen from the image, due to the transmission delay difference, the effective data window is small and the data cannot be sampled correctly. After the delay difference elimination algorithm, the effective data window is larger and the rising edge of the SSI clock is aligned with the middle position of the data window.

Claims

1. A method for automatically eliminating delay differences in an SPI interface, characterized in that, The hardware basis of the method is a circuit for automatically eliminating SPI interface delay differences. This circuit includes an SPI master and an SPI slave. The SPI master includes a master transmitting circuit and a master receiving circuit, and the SPI slave includes a slave transmitting circuit and a slave receiving circuit. The circuit also includes a master de-skew circuit and a slave de-skew circuit. The master transmitting circuit is sequentially connected to a multi-bit data line, the slave de-skew circuit, and the slave receiving circuit. The slave transmitting circuit is sequentially connected to a multi-bit data line, the master de-skew circuit, and the master receiving circuit. The master receiving circuit is also sequentially connected to an adjustable delay circuit and a clock gating circuit, with the clock gating circuit connected to the master de-skew circuit. Both the master and slave de-skew circuits include a high-precision adjustable delay line group, the number of bits in which corresponds to the number of bits in the multi-bit data line. Each high-precision adjustable delay line in the high-precision adjustable delay line group includes multiple delay units connected in sequence, and the multiple delay units are used together to change the delay value of the high-precision adjustable delay line. The method includes: Communication between the SPI master and SPI slave is established using a dual-edge sampling method. Eliminate the delay difference of the SPI slave, including SPI slave algorithm C: first eliminate the delay difference between the multiple data lines connected to the slave receiving circuit, and then eliminate the delay difference between the clock line and the slave data line; Eliminate the delay difference of the SPI master, including SPI master algorithm Z: first eliminate the delay difference between the multiple data lines connected to the master receiving circuit, and then eliminate the delay difference between the clock line and the master data line.

2. The method for automatically eliminating SPI interface delay differences according to claim 1, characterized in that, The elimination of latency differences between SPI slave devices also includes SPI master algorithm C, the steps of which are as follows: a1. Adjust the SPI master clock frequency to low frequency mode; a2. The SPI master continuously sends training sequence data to the SPI slave; a3. Wait for the SPI slave to receive data and complete the elimination of the SPI slave's delay difference; a4. Adjust the SPI host clock frequency to high-frequency mode to perform SPI communication.

3. The method for automatically eliminating SPI interface delay differences according to claim 1, characterized in that: The elimination of latency differences between the SPI master and slave also includes the SPI slave algorithm Z, the steps of which are as follows: b1. The SPI slave continuously sends training sequence data to the SPI master. b2. Wait for the SPI master to receive data and complete the elimination of the SPI master's latency difference; b3. Perform SPI communication.

4. The method for automatically eliminating SPI interface delay differences according to claim 2 or 3, characterized in that: The training sequence data is used to make the signal on the data line continuously switch between 0 and 1.

5. The method for automatically eliminating SPI interface delay differences according to claim 1, characterized in that: In SPI slave algorithm C, the delay difference of the SPI slave is eliminated by adjusting the delay of the slave de-skew circuit; in SPI master algorithm Z, the delay difference of the SPI master is eliminated by adjusting the delay of the master de-skew circuit; the de-skew circuit includes a high-precision adjustable delay line group, and the delay of the de-skew circuit is adjusted by adjusting the delay of each high-precision adjustable delay line in the high-precision adjustable delay line group.

6. The method for automatically eliminating SPI interface delay differences according to claim 5, characterized in that, In eliminating the delay difference of the SPI slave, the steps of the SPI slave algorithm C are as follows: c1. Gradually increase the delay of the data cRxd[n], where n represents the nth data line. Search for the previous transition edge of cRxd[n], calculate the interval cDn between the rising edge of the clock signal and the previous transition edge of cRxd[n], record the minimum value of all cDn as cDmin, and use the difference between cDn and cDmin as the delay value of the nth high-precision adjustable delay line corresponding to cRxd[n]. At this time, the delay difference between multiple data lines cRxd has been eliminated, and then proceed to step c3; if the delay of the data line cRxd[n] is increased to the maximum value and the previous transition edge of cRxd[n] cannot be found, then proceed to step c2; c2. Gradually increase the delay of the clock, search for the next transition edge of the data cRxd[n], calculate the interval cRn between the rising edge of the clock signal and the next transition edge of cRxd[n], record the maximum value of all cRn as cRmax, and use the difference between cRn and cRmax as the delay value of the nth high-precision adjustable delay line corresponding to cRxd[n]. At this time, the delay difference between multiple data lines cRxd has been eliminated, and then proceed to step c4; c3. Gradually increase the delay length of the clock line, search for the next transition edge of the data cRxd, and record the interval between the rising edge of the clock signal and the next transition edge of the data cRxd as cL. If cDmin > cL, delay the data cRxd by half of the difference between cDmin and cL; if cDmin < cL, delay the clock by half of the difference between cDmin and cL, and complete the elimination of the delay difference of the SPI slave; c4. Gradually increase the delay length of the data line cRxd, search for the previous transition edge of the data line cRxd, and record the interval between the rising edge of the clock signal and the previous transition edge of the data line cRxd as cP. If cDmax < cP, delay the data by half of the difference between cDmax and cP; if cDmax > cP, delay the clock by half of the difference between cDmax and cP, and complete the elimination of the delay difference of the SPI slave.

7. The method for automatically eliminating SPI interface delay differences according to claim 5, characterized in that, In eliminating the delay difference of the SPI master, the steps of the SPI master algorithm Z are as follows: d1. Adjust the clock frequency of the SPI master to the low-frequency mode; d2. Gradually increase the delay of the data zRxd[n], search for the previous transition edge of zRxd[n], calculate the interval zDn between the rising edge of the clock signal and the previous transition edge of zRxd[n], record the minimum value of all zDn as zDmin, and use the difference between zDn and zDmin as the delay value of the nth high-precision adjustable delay line corresponding to zRxd[n]. At this time, the delay difference between multiple data lines zRxd has been eliminated, and then proceed to step d4; if the delay length of the data line zRxd[n] is increased to the maximum value and the previous transition edge of zRxd[n] cannot be found, then proceed to step d3; d3. Gradually increase the delay of the clock, find the next transition edge of the data zRxd[n], calculate the interval zRn between the rising edge of the clock signal and the next transition edge of zRxd[n], record the maximum value among all zRn as zRmax, and use the difference between zRn and zRmax as the delay value of the nth high-precision adjustable delay line corresponding to zRxd[n]. At this time, the delay difference between multiple data lines zRxd has been eliminated; d4. Adjust the clock frequency of the SPI master to the high-frequency mode; d5. The SPI master reads the training sequence data. If the training sequence data can be correctly read, gradually increase the delay of the data zRxd, find the previous transition edge of the data zRxd, record the interval between the previous transition edge of the data zRxd and the rising edge of the clock as zP, then gradually increase the delay of the clock, find the next transition edge of the data zRxd, and record the interval between the next transition edge of the data zRxd and the rising edge of the clock as zL. If zP>zL, delay the data zRxd by half of the difference between zP and zL. If zP<zL, delay the clock by half of the difference between zP and zL to complete the elimination of the delay difference of the SPI master; If the SPI master cannot correctly read the training sequence data, go to step d6; d6. Gradually increase the delay of the clock until the SPI master correctly reads the training sequence data for the first time. Record the clock delay at this time as Tstart. Continue to gradually increase the delay of the clock until the training sequence data is read incorrectly again. Record the clock delay at the last time when the training sequence data was correctly read as Tend. Take the average value of the clock delays Tstart and Tend to complete the elimination of the delay difference of the SPI master.

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