Unmanned aerial vehicle time synchronization method and module based on dynamic error compensation

Abstract

The application provides a kind of unmanned aerial vehicle time synchronization method and module based on dynamic error compensation, it is related to time synchronization technical field.The method includes confirming the real-time time error between two unmanned aerial vehicles according to the time information of the message sent and received by two unmanned aerial vehicles and the temperature data of the FPGA installed on unmanned aerial vehicle, inputting the recorded historical time error, temperature data and acceleration data into adaptive network model to obtain predicted time error, then determining comprehensive time error, obtaining compensated modified clock frequency according to comprehensive time error, time synchronization period and current clock frequency, and then converting into the control signal of digital phase-locked loop, adjusting the local clock frequency of unmanned aerial vehicle according to the control signal, and adjusting the unmanned aerial vehicle in advance, so that two unmanned aerial vehicles can be time synchronized thereafter.The above-mentioned method is not limited to hardware performance, and considers precision and real-time performance, to realize real-time compensation of time error in high dynamic environment.

Description

Technical Field

[0001] This invention relates to the field of time synchronization technology, and more specifically, to a time synchronization method and module for unmanned aerial vehicles (UAVs) based on dynamic error compensation. Background Technology

[0002] In distributed unmanned aerial vehicle (UAV) systems, time synchronization is a crucial foundation for ensuring collaborative operation. Traditional time synchronization methods typically rely on high-precision hardware (such as atomic clocks or GPS modules), resulting in high costs and limited large-scale application. Furthermore, existing technologies exhibit poor time synchronization accuracy and stability in highly dynamic environments (such as high-speed UAV movement and fluctuating communication latency).

[0003] Recent research has attempted to reduce costs through software optimization, but due to limitations in hardware performance, it is difficult to balance accuracy and real-time performance, and it cannot adapt to complex environments or meet the needs of large-scale drone swarms. Summary of the Invention

[0004] The problem that this invention aims to solve is that existing time synchronization methods are limited by hardware performance, resulting in poor synchronization accuracy, stability, and real-time performance.

[0005] To address the aforementioned problems, in a first aspect, the present invention provides a time synchronization method for unmanned aerial vehicles (UAVs) based on dynamic error compensation, comprising:

[0006] Obtain the time information of messages exchanged between the two drones;

[0007] Based on time information and temperature data, determine the real-time time error;

[0008] Historical time error, temperature data, and acceleration data are input into the adaptive network model to obtain the predicted time error.

[0009] The combined time error is obtained based on the real-time time error and the predicted time error;

[0010] Based on the comprehensive time error, time synchronization period, and current clock frequency, the compensated corrected clock frequency is obtained;

[0011] The corrected clock frequency is converted into a control signal for a digital phase-locked loop. The clock frequency of the drone is adjusted according to the control signal to control the time synchronization of the two drones.

[0012] Optionally, the two drones exchange information bidirectionally, with drone A sending data packets to drone B and drone B sending data packets back to drone A. The time information includes the sending time T of the data packets sent by drone A. A1 The reception time T of the feedback data packet received by UAV A A2 The reception time T of the data packets received by UAV B B1The time T for sending feedback data packets from drone B B2 ;

[0013] The real-time time error is: Δt raw =[(T B1 -T A1 )-(T A2 -T B2 )] / 2+α(T temp -25℃),

[0014] Where α represents the temperature compensation coefficient, T temp This represents the temperature data acquired in real time by the FPGA.

[0015] Optionally, the integrated time error is Δt comp =Δt raw +Δt pred ,

[0016] The corrected clock frequency is: f new =f old ×(1+Δt comp / T sync ),

[0017] Where, Δt raw Δt represents the real-time time error. pred f represents the prediction time error. old Indicates the current clock frequency, Δt comp T represents the overall time error. sync Indicates the time synchronization period.

[0018] Optionally, the adaptive network model undergoes periodic incremental training.

[0019] Optionally, the multiple drones can operate in a master-slave mode, in which the multiple drones include a master node drone and multiple slave node drones.

[0020] The time synchronization method in the master-slave working mode includes:

[0021] The master node's drones send synchronization signals to the slave node's drones according to the broadcast cycle;

[0022] After receiving the synchronization signal from the drone at the node, the control signal of the digital phase-locked loop is obtained by analysis, and the local clock frequency is adjusted using the control signal.

[0023] Optionally, the time synchronization method in the master-slave working mode further includes:

[0024] After the drone at the slave node completes the clock frequency adjustment, it sends a confirmation signal back to the drone at the master node.

[0025] The master node's drones calculate the synchronization success rate based on the received confirmation signals and adjust the broadcast cycle accordingly.

[0026] Optionally, the operating modes of the multiple drones include a distributed operating mode, and the time synchronization method for the distributed operating mode includes:

[0027] The historical error variance is obtained based on the historical time errors of multiple drones;

[0028] Based on historical error variance, the priority of multiple drones is determined;

[0029] Based on the aforementioned priority, drones that serve as temporary master nodes are periodically elected according to the election cycle.

[0030] The drone of the temporary master node sends synchronization signals to the drones of the other slave nodes according to the broadcast cycle;

[0031] After receiving the synchronization signal from the drone at the node, the control signal of the digital phase-locked loop is obtained by analysis, and the local clock frequency is adjusted using the control signal.

[0032] Optionally, the time synchronization method in the distributed working mode further includes:

[0033] After the drone at the slave node completes the clock frequency adjustment, it sends a confirmation signal back to the drone at the temporary master node.

[0034] If the number of times a drone of the temporary master node fails to receive a confirmation signal from a drone of the slave node exceeds a preset number, then the drone of the temporary master node will be excluded, and a new drone of the temporary master node will be re-elected.

[0035] Optionally, the time synchronization method in the distributed working mode further includes:

[0036] The broadcast cycle is dynamically adjusted based on the communication network load among multiple drones.

[0037] If the communication network load between multiple drones exceeds the preset load, the election cycle will be extended.

[0038] Secondly, the present invention also provides a UAV time synchronization module based on dynamic error compensation, comprising:

[0039] The timestamp recording unit is used to obtain the time information of messages exchanged between the two drones;

[0040] The error calculation unit is used to determine the real-time time error based on time information and temperature data.

[0041] The dynamic error compensation unit is used to input historical time error, temperature data, and acceleration data into the adaptive network model to obtain the predicted time error; it is also used to obtain the comprehensive time error based on the real-time time error and the predicted time error.

[0042] The clock adjustment unit is used to obtain a compensated corrected clock frequency based on the comprehensive time error, time synchronization period, and current clock frequency; it is also used to convert the corrected clock frequency into a control signal for a digital phase-locked loop, and adjust the clock frequency of the two drones according to the control signal to control the time synchronization of the two drones.

[0043] This invention provides a method and module for UAV time synchronization based on dynamic error compensation. Compared with existing technologies, it has the following advantages:

[0044] Based on the timing information of messages exchanged between the two drones and the temperature data from the FPGA installed on the drones, the real-time time error between the two drones can be determined. This real-time time error is recorded, and the recorded historical time error, temperature data, and acceleration data are input into an adaptive network model to obtain the predicted time error. This allows us to know the time error at a certain point in the future. Combining the real-time time error and the predicted time error, we can know the comprehensive time error at a certain point in the future. Based on the comprehensive time error, the time synchronization period, and the current clock frequency, the compensated corrected clock frequency is obtained and then converted into a control signal for a digital phase-locked loop (PLL). The local clock frequency of the drones is adjusted according to this control signal, allowing the drones to be pre-adjusted so that the two drones can be synchronized in time. The above method is not limited by hardware performance, balances accuracy and real-time performance, and integrates the adaptive network model with temperature / acceleration data to achieve real-time compensation for time errors in highly dynamic environments, adapting to complex environments and meeting the needs of large-scale drone swarms. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 A flowchart illustrating a UAV time synchronization method based on dynamic error compensation provided in an embodiment of the present invention;

[0047] Figure 2 A schematic diagram of a UAV time synchronization module based on dynamic error compensation provided in an embodiment of the present invention;

[0048] Figure 3 This is a schematic diagram of the structure for information interaction between two unmanned aerial vehicles (UAVs) provided in an embodiment of the present invention;

[0049] Figure 4 A logic diagram of the master-slave working mode provided in the embodiments of the present invention;

[0050] Figure 5 A logical diagram of the distributed working mode provided in the embodiments of the present invention. Detailed Implementation

[0051] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions in the embodiments of this application are described clearly and completely. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0052] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0053] like Figure 1 As shown in the embodiment of this application, a UAV time synchronization method based on dynamic error compensation is provided, including:

[0054] S1: Obtain the time information of messages exchanged between the two drones.

[0055] S2: Determine the real-time time error based on time information and temperature data.

[0056] S3: Input historical time error, temperature data, and acceleration data into the adaptive network model to obtain the predicted time error.

[0057] S4: Based on the real-time time error and the predicted time error, the comprehensive time error is obtained.

[0058] S5: Based on the comprehensive time error, time synchronization period and current clock frequency, obtain the compensated corrected clock frequency.

[0059] S6: Convert the corrected clock frequency into a control signal for the digital phase-locked loop, and adjust the clock frequency of the drone according to the control signal to control the time synchronization of the two drones.

[0060] In this embodiment, based on the timing information of messages exchanged between the two drones and the temperature data from the FPGA (Field-Programmable Gate Array) installed on the drones, the real-time time error between the two drones can be determined. This real-time time error is recorded, and the recorded historical time error, temperature data, and acceleration data are input into the adaptive network model to obtain the predicted time error. This allows for the prediction of the time error at a certain future time point. Combining the real-time time error and the predicted time error, the comprehensive time error at a certain future time point can be determined. Based on the comprehensive time error, the time synchronization period, and the current clock frequency, a compensated corrected clock frequency is obtained, which is then converted into a control signal for a digital phase-locked loop (PLL). The local clock frequency of the drones is adjusted according to this control signal, allowing for advance adjustment of the drones and enabling the two drones to synchronize their time subsequently. The above method is not limited by hardware performance, balances accuracy and real-time performance, and integrates the adaptive network model with temperature / acceleration data to achieve real-time compensation of time errors in highly dynamic environments, adapting to complex environments and meeting the needs of large-scale drone swarms.

[0061] like Figure 2 As shown in the figure, an embodiment of this application provides a UAV time synchronization module based on dynamic error compensation, comprising:

[0062] The timestamp recording unit 100 is used to obtain the time information of messages exchanged between the two drones.

[0063] Specifically, the hardware selection for the timestamp recording unit is as follows: a Kintex-7 series FPGA is used, which has abundant logic resources and high-speed peripheral interfaces, and can meet the requirements of high-precision timestamp recording. A high-precision temperature-compensated crystal oscillator (TCXO) is used as the clock source, such as the TXCO-5032 model, which can provide a reference clock with an accuracy of ±2ppm, ensuring the stability of the clock signal under different environments.

[0064] Circuit connection of the timestamp recording unit: According to the FPGA datasheet, its input capture pin is connected to the signal output terminal of the communication line to ensure that data packet transmission signals can be accurately transmitted to the FPGA. Simultaneously, the TCXO's clock output pin is connected to the FPGA's dedicated clock input pin to provide a stable clock signal for the TIME timer. During routing, differential signal transmission of the clock signal is used to reduce the impact of electromagnetic interference on clock accuracy.

[0065] Hardware debugging of the timestamp recording unit: The timestamp recording unit was debugged using a logic analyzer, monitoring signal changes on the input capture pin and the count value of the TIME timer. The accuracy of the timestamp recording was verified by sending and receiving test data packets, ensuring that the actual capture accuracy met the design requirement of ≤1ns. An FPGA-based TIME timer (2400MHz clock) was used to accurately record the data packet transmission and reception timestamps through the input capture function. Timer resolution: 1 / 2400MHz ≈ 0.4ns, actual capture accuracy ≤1ns. The clock chip provided a reference clock with ±2ppm accuracy to calibrate the TIME frequency drift in real time.

[0066] Error calculation unit 200 is used to determine real-time time error based on time information and temperature data.

[0067] Specifically, based on a two-way timestamp exchange protocol, the system implements precise recording of data packet transmission and reception times and error calculation logic. For example, when drone A sends a data packet, it records the local time T. A1 After receiving the data, UAV B records T. B1 Drone B sends back a data packet, recording the local time T. B2 After receiving the data, UAV A recorded T. A2 Define a register to store T. A1 T B1 T B2 T A2 The error calculation formula is implemented in hardware using combinational logic based on timestamp data. A temperature sensor is connected to the FPGA's general-purpose I / O port via a single bus. This enables timed acquisition and transmission of temperature data, handling operations such as sending temperature conversion commands and reading data. Functional simulation of the error calculation unit is performed using simulation tools such as ModelSim, inputting different timestamps and temperature data to verify the accuracy of the error calculation results. Simultaneously, timing analysis is conducted to ensure that the error calculation module functions correctly at the system clock frequency, meeting real-time requirements.

[0068] The dynamic error compensation unit 300 is used to input historical time error, temperature data and acceleration data into the adaptive network model to obtain the predicted time error; it is also used to obtain the comprehensive time error based on the real-time time error and the predicted time error.

[0069] Adaptive Network Model Construction and Training: An adaptive network model is built, which can be a temporal convolutional network or an improved version thereof. The input layer is defined as an interface for 50 steps of historical error, temperature, and acceleration data. The computational layer uses 32 parallel convolutional kernels to extract time-series features. The fully connected layer outputs three-step prediction values, corresponding to errors in the next 30ms, 60ms, and 90ms, respectively. Historical dynamic scene data is collected, including time error data under different temperature (-25℃~85℃) and acceleration (0-2g) conditions. The data is normalized and used for model training. By adjusting hyperparameters such as the learning rate and number of iterations, the model performance is optimized, enabling the model to accurately predict time errors.

[0070] Model Conversion and Hardware Implementation: The trained model parameters are converted into a format suitable for FPGA implementation, and fixed-point arithmetic is used instead of floating-point arithmetic to reduce hardware resource consumption. In the FPGA, the forward computation logic of the adaptive network model is implemented using the Verilog hardware description language. Input data is fed into the model through appropriate interfaces, and then processed sequentially through computational layers and fully connected layers to obtain the predicted time error.

[0071] Data Acquisition and Update System Setup: At the hardware level, a data acquisition and update system is built using timers and dual-port RAM. The timer triggers a data acquisition event every 30 minutes, storing new dynamic scene data (including time error, temperature, acceleration, etc.) into the dual-port RAM. Simultaneously, data is transmitted to the central terminal via serial communication for incremental model training. After training is complete, the updated model parameters are transmitted back to the FPGA via serial port, enabling online model updates.

[0072] The clock adjustment unit 400 is used to obtain a compensated corrected clock frequency based on the comprehensive time error, time synchronization period, and current clock frequency. It is also used to convert the corrected clock frequency into a control signal for a digital phase-locked loop, and adjust the UAV's clock frequency according to the control signal to control the time synchronization of the two UAVs.

[0073] Write the logic code to control the PLL in the FPGA, generating corresponding control signals based on the calculated synthesis error and synchronization cycle. Communicate with the PLL via the SPI interface to configure its internal registers and adjust the output clock frequency. For example, the clock frequency can be corrected according to the formula: f new =f old ×(1+Δt comp / T sync ), f old Indicates the current clock frequency, Δt comp T represents the overall time error. syncThe time synchronization period is used to calculate the adjusted frequency value, which is then converted into the corresponding register setting value and written to the PLL register via the SPI interface. PLL chip selection and circuit design: A low-power PLL chip is selected, which supports a frequency adjustment step size of 0.01ppm, meeting the requirements for high-precision clock adjustment. Based on the device characteristics, peripheral circuits are designed, including power supply filtering circuits and clock input / output buffer circuits. The power supply filtering circuit uses an LC filter network to reduce the impact of power supply noise on the PLL chip; the clock input / output buffer circuit uses a high-speed buffer to improve the signal driving capability.

[0074] Frequency Testing and Verification: The output frequency of the PLL chip is tested using a high-precision frequency meter to verify whether it can accurately adjust the clock frequency according to the expected adjustment logic. Changes in the output frequency are measured under different combined error and synchronization period conditions to ensure the accuracy and stability of frequency adjustment.

[0075] The UAV time synchronization module also includes a communication unit 500. The communication interface is configured in the FPGA, using its general-purpose I / O ports to simulate a serial communication interface, enabling communication functionality based on a custom protocol. Parameters such as the baud rate, data bits, and parity bits of the communication interface are set and adjusted according to actual needs to ensure reliable and efficient communication.

[0076] Specifically, based on the frame structure design of the communication protocol, a program for assembling and parsing data packets is written. When sending data, the synchronization header (0xAA55), timestamp, temperature data, payload reservation, and CRC check fields are sequentially assembled into a complete data packet according to the frame structure, and then sent out through the communication interface. When receiving data, the synchronization header is first checked to confirm the start position of the data packet; then a CRC check is performed to verify the integrity of the data; finally, the timestamp, temperature data, and other information are parsed according to the frame structure.

[0077] Interrupt Triggering and Delay Control: Configure the FPGA's interrupt controller to associate the receive and transmit events of the communication interface with interrupt service routines. When an interrupt occurs, the value of the TIME timer is immediately read in the interrupt service routine, and a timestamp is recorded to ensure that the communication delay is ≤1µs. Simultaneously, an appropriate interrupt priority is set to ensure that communication events are processed promptly. For example, when a rising or falling edge of a data packet's transmit / receive signal is detected, it indicates that a time synchronization process is in progress. At this point, an interrupt is triggered, interrupting other processes and prioritizing the time synchronization process, ensuring that the time synchronization delay is less than or equal to 1µs.

[0078] The aforementioned units are deployed on a PCB board with a 4-layer layout (top signal layer, inner power / ground layer, bottom device layer), measuring 4cm x 4cm. The FPGA is centered to reduce trace length, and the clock chip is placed close to the TIME timer to reduce clock jitter. A low-cost crystal oscillator and a high-precision temperature-compensated crystal oscillator are connected to the microcontroller via an intelligent switching circuit. The circuit design employs a multi-layer PCB board to physically isolate the clock source circuit from other circuits, reducing electromagnetic interference. Additionally, filter capacitors are added to the power supply pins of the crystal oscillator and the temperature-compensated crystal oscillator to further improve power supply stability. Based on the UAV's flight requirements and power consumption budget, the switching threshold and switching logic of the intelligent switching circuit are set via software programming. For example, when the temperature change exceeds 5°C or the flight attitude change rate exceeds a certain threshold, clock source switching is triggered, switching either the low-cost crystal oscillator or the high-precision temperature-compensated crystal oscillator to the circuit.

[0079] The following section provides a detailed description of each step in the UAV time synchronization method based on dynamic error compensation.

[0080] S1: Obtain the time information of messages exchanged between the two drones.

[0081] In the FPGA hardware logic, an input capture interrupt service routine is written. When a rising or falling edge of a data packet's transmit / receive signal is detected, an interrupt is triggered. The interrupt service routine immediately reads the value of the TIME timer and stores it in a specific register as a timestamp. Simultaneously, a flag is set so that the subsequent error calculation module can obtain the timestamp data promptly.

[0082] In addition, the TIME timer's count value is periodically corrected based on the reference clock signal provided by the clock chip. For example, at regular intervals (e.g., every second), the period of the reference clock and the TIME timer's count value are compared to calculate the frequency deviation. If the frequency deviation exceeds a certain threshold, the TIME timer's count value is adjusted accordingly, compensating for frequency drift by increasing or decreasing the count value.

[0083] S2: Determine the real-time time error based on time information and temperature data.

[0084] like Figure 3 As shown, the two drones exchange information (timestamps) bidirectionally. Drone A sends data packets to drone B, and drone B sends data packets back to drone A. The time information includes the sending time T of the data packets sent by drone A. A1 The reception time T of the feedback data packet received by UAV A A2 The reception time T of the data packets received by UAV B B1 The time T for sending feedback data packets from drone B B2Receive timestamp data (T) from timestamp recording units. A1 T B1 T B2 T A2 ) and temperature data T collected by temperature sensor temp This data is formatted to ensure it can be correctly used in error calculation. Based on the two-way timestamp exchange protocol and the real-time time error calculation formula Δt... raw =[(T B1 -T A1 )-(T A2 -T B2 )] / 2+α(T temp -25℃), α represents the temperature compensation coefficient (empirical value 0.05μs / ℃), determined through calibration experiments, T temp This section describes how to implement error calculation logic based on real-time temperature data acquired by the FPGA. During the calculation process, careful attention must be paid to the precision control of the data type. When using fixed-point arithmetic, the decimal point position must be set appropriately to ensure the accuracy of the calculation results. Simultaneously, overflow detection and handling are performed on the calculation results to prevent errors in error calculation due to data overflow.

[0085] S3: Input historical time error, temperature data, and acceleration data into the adaptive network model to obtain the predicted time error.

[0086] Data preprocessing: In the adaptive network model implemented on FPGA, a data preprocessing algorithm is written. The input historical error, temperature, and acceleration data are formatted and normalized according to the model's input layer requirements. For example, the historical error data is normalized to a range of 0-1, facilitating model training and computation.

[0087] Feature extraction and prediction are performed sequentially through a computational layer and a fully connected layer. In the computational layer, convolutional kernels are used to extract time-series features, and a sliding window is used to perform convolution operations on the input data to obtain feature maps. In the fully connected layer, the feature maps are flattened, multiplied by the weight matrix, and a bias term is added to obtain the prediction error values ​​Δt for the next 30ms, 60ms, and 90ms. pred .

[0088] The adaptive network model undergoes periodic incremental training. For example, new data is collected every 30 minutes, and incremental training updates the model parameters to adapt to environmental changes.

[0089] S4: Based on the real-time time error and the predicted time error, the comprehensive time error is obtained.

[0090] The prediction error value is added to the original time error value to obtain the comprehensive time error Δt. comp =Δtraw +Δt pred During the calculation process, attention should be paid to the consistency of data types and precision control to ensure the accuracy of the overall error, which will be used for subsequent clock adjustments.

[0091] S5: Based on the comprehensive time error, time synchronization period and current clock frequency, obtain the compensated corrected clock frequency.

[0092] The corrected clock frequency is: f new =f old ×(1+Δt comp / T sync ), Δt raw Δt represents the real-time time error. pred f represents the prediction time error. old Indicates the current clock frequency, Δt comp T represents the overall time error. sync This represents the time synchronization period. First, a division operation is performed to calculate the adjustment factor; then a multiplication operation is performed to obtain the adjusted clock frequency f. new When using fixed-point arithmetic in the calculation process, the decimal point position should be set appropriately to ensure the accuracy of the calculation results.

[0093] S6: Convert the corrected clock frequency into a control signal for the digital phase-locked loop, and adjust the clock frequency of the drone according to the control signal to control the time synchronization of the two drones.

[0094] The calculated adjusted clock frequency fnew is converted into a corresponding PLL control signal. According to the PLL chip's control protocol, the frequency value is converted into a corresponding register setting value and sent to the PLL chip via the SPI interface to adjust the local clock frequency. Before sending the control signal, data verification and error correction are performed to ensure the accuracy of the control signal.

[0095] The specific communication methods between multiple drones are as follows:

[0096] At the sending end, according to the frame structure of the communication protocol, the data to be transmitted (such as timestamps, temperature data, etc.) is assembled into a data packet in a prescribed format. First, a synchronization header (0xAA55) is filled, followed by the timestamp, temperature data, and payload reservation field. A CRC checksum is calculated and filled into the CRC check field. Finally, the data packet is sent out through the communication interface. During transmission, a transmission buffer is set to buffer the transmitted data and prevent data loss. Simultaneously, a transmission status flag is set to facilitate monitoring of the transmission process.

[0097] At the receiving end, a synchronization header check is performed on the received data packets. By continuously reading data from the communication interface and comparing it with the synchronization header (0xAA55), the start position of the data packet is confirmed. Once the synchronization header is detected, reception of the subsequent fields of the data packet begins. During reception, a receive buffer is set to cache the received data. After reception is complete, a CRC check is performed to verify the integrity of the data. If the check passes, information such as the timestamp and temperature data is extracted and processed accordingly; if the check fails, the data packet is discarded, and the sending end is notified to retransmit. Simultaneously, a receive status flag is set to facilitate monitoring of the reception process.

[0098] Timeout Mechanism: To ensure real-time communication, a suitable timeout mechanism is set in the communication algorithm. For example, after sending a data packet, a timer is started with a timeout period (e.g., 10ms). If no acknowledgment signal is received from the receiver within the specified time, the data packet is retransmitted. At the receiving end, a corresponding timeout mechanism is also set. If a data packet is not received completely for an extended period, a timeout is processed, the data packet is discarded, and the sending end is notified to retransmit it.

[0099] like Figure 4 As shown, the working modes of multiple drones include a master-slave working mode, in which multiple drones include a master node drone and multiple slave node drones.

[0100] The time synchronization method in the master-slave working mode includes:

[0101] The master node's drones send synchronization signals to the slave node's drones according to the broadcast cycle.

[0102] After receiving the synchronization signal from the drone at the node, the control signal of the digital phase-locked loop is obtained by analysis, and the local clock frequency is adjusted using the control signal.

[0103] After the drone at the slave node completes the clock frequency adjustment, it sends a confirmation signal back to the drone at the master node.

[0104] The master node's drones calculate the synchronization success rate based on the received confirmation signals and adjust the broadcast cycle accordingly.

[0105] Specifically, the master node drone broadcasts a synchronization signal (including a local timestamp) every 100ms. The slave node drones receive the signal, calculate the error Δt, and adjust their local clocks via DPLL. The slave node drones reply with an acknowledgment signal, and the master node drone calculates the synchronization success rate and dynamically adjusts the broadcast period (80-120ms). This mode is suitable for small-scale drone swarms (≤10 nodes) and is applicable to static or low-speed motion environments.

[0106] like Figure 5As shown, the operating modes of multiple drones include a distributed operating mode, and the time synchronization method for the distributed operating mode includes:

[0107] The historical error variance is obtained based on the historical time errors of multiple drones.

[0108] The priority of multiple drones is determined based on the historical error variance.

[0109] Based on the aforementioned priority, drones that periodically elect temporary master nodes are selected according to the election cycle.

[0110] The drone of the temporary master node sends synchronization signals to the drones of the other slave nodes according to the broadcast cycle.

[0111] After receiving the synchronization signal from the drone at the node, the control signal of the digital phase-locked loop is obtained by analysis, and the local clock frequency is adjusted using the control signal.

[0112] After the drone at the slave node completes the clock frequency adjustment, it sends an acknowledgment signal back to the drone at the temporary master node.

[0113] If the number of times a drone of the temporary master node fails to receive a confirmation signal from a drone of the slave node exceeds a preset number, then the drone of the temporary master node will be excluded, and a new drone of the temporary master node will be re-elected.

[0114] The broadcast cycle is dynamically adjusted based on the network load between multiple drones.

[0115] If the communication network load between multiple drones exceeds the preset load, the election cycle will be extended.

[0116] Specifically, multiple drones use an election mechanism to determine node priority based on clock stability (historical error variance), with higher stability resulting in higher priority. A temporary master node drone broadcasts a synchronization signal, and slave node drones reply with acknowledgment. If a temporary master node drone fails to receive acknowledgment three times, a re-election is triggered. The synchronization period is dynamically adjusted based on network load (50-500ms). This mode is suitable for large-scale drone swarms (≥100 nodes) and highly dynamic environments. Data packet compression reduces the original 12-byte heartbeat packet to 8 bytes, decreasing data requirements by 30%. A dynamic election mechanism is also employed; when the data network load exceeds 70%, the election period is extended from 100ms to 500ms.

[0117] After actually using the above method, in terms of time synchronization accuracy: the accuracy reaches 0.3ns in a static environment and 0.8ns (20m / s) in a dynamic environment, which is better than traditional solutions (100ns in NTP and 10ns in PTP). In terms of cost: the integration of a single module is improved by 30%, and the cost is reduced by 30% compared with existing solutions. In terms of power consumption: the module has a standby power consumption of 45mW and a peak operating power consumption of 55mW, supporting a drone flight time of ≥4 hours.

[0118] In summary, compared with existing technologies, it has the following beneficial effects:

[0119] 1. Dynamic error compensation mechanism: The adaptive network model is fused with temperature / acceleration data to achieve real-time error compensation in highly dynamic environments.

[0120] 2. Low-cost hardware integration: Costs are reduced through PCB stack-up optimization.

[0121] 3. Adaptive communication architecture: Supports seamless switching between master-slave / distributed modes, and improves the adaptive algorithm to reduce communication overhead by 30%.

[0122] 4. The above solution balances low cost, high precision, and dynamic adaptability. While ensuring microsecond-level synchronization accuracy, it integrates single modules at low cost and adapts to the real-time synchronization requirements of highly dynamic environments (UAV speed ≥ 20m / s, communication delay fluctuation ± 2ms), providing a reliable time synchronization solution for large-scale UAV swarm applications.

[0123] An electronic device provided in this application includes a memory and a processor; the memory is used to store a computer program; the processor is used to implement the UAV time synchronization method based on dynamic error compensation as described above when the computer program is executed.

[0124] This application provides a computer-readable storage medium storing a computer program. When the computer program is executed by a processor, it implements the UAV time synchronization method based on dynamic error compensation as described above.

[0125] In this embodiment, the beneficial effects of the electronic device and the computer-readable storage medium are similar to those of the above-described UAV time synchronization method based on dynamic error compensation, and will not be repeated here.

[0126] The present invention describes electronic devices that can serve as servers or clients of this application, which are examples of hardware devices that can be applied to various aspects of this application. Electronic devices are intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic devices can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the application described and / or claimed herein.

[0127] Electronic devices include a computing unit that can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) or loaded from a storage unit into random access memory (RAM). The RAM can also store various programs and data required for device operation. The computing unit, ROM, and RAM are interconnected via a bus. Input / output (I / O) interfaces are also connected to the bus.

[0128] Those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. In this application, the units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of the embodiments of this application according to actual needs. Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated units can be implemented in hardware or as software functional units.

[0129] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0130] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application.

Claims

1. A time synchronization method for unmanned aerial vehicles (UAVs) based on dynamic error compensation, characterized in that, include: Obtain the time information of messages exchanged between the two drones; Based on time information and temperature data, determine the real-time time error; Historical time error, temperature data, and acceleration data are input into the adaptive network model to obtain the predicted time error. The combined time error is obtained based on the real-time time error and the predicted time error; Based on the comprehensive time error, time synchronization period, and current clock frequency, the compensated corrected clock frequency is obtained; The corrected clock frequency is converted into a control signal for a digital phase-locked loop. The clock frequency of the drone is adjusted according to the control signal to control the time synchronization of the two drones. The comprehensive time error is , The corrected clock frequency is: , in, Indicates the real-time time error. Indicates the prediction time error. Indicates the current clock frequency. Indicates the overall time error. Indicates the time synchronization period.

2. The UAV time synchronization method based on dynamic error compensation as described in claim 1, characterized in that, The two drones exchange information bidirectionally. Drone A sends data packets to drone B, and drone B sends data packets back to drone A. The time information includes the time when drone A sends the data packets. The reception time of the feedback data packet received by UAV A The reception time of data packets received by UAV B The time when Drone B sends feedback data packets ; The real-time time error is: ， Where α represents the temperature compensation coefficient. This represents the temperature data acquired in real time by the FPGA.

3. The UAV time synchronization method based on dynamic error compensation as described in claim 1, characterized in that, The adaptive network model undergoes periodic incremental training.

4. The UAV time synchronization method based on dynamic error compensation as described in claim 1, characterized in that, The operation modes of multiple drones include a master-slave mode, in which multiple drones include a master node drone and multiple slave node drones. The time synchronization method in the master-slave working mode includes: The master node's drones send synchronization signals to the slave node's drones according to the broadcast cycle; After receiving the synchronization signal from the drone at the node, the control signal of the digital phase-locked loop is obtained by analysis, and the local clock frequency is adjusted using the control signal.

5. The UAV time synchronization method based on dynamic error compensation as described in claim 4, characterized in that, The time synchronization method in the master-slave working mode also includes: After the drone at the slave node completes the clock frequency adjustment, it sends a confirmation signal back to the drone at the master node. The master node's drones calculate the synchronization success rate based on the received confirmation signals and adjust the broadcast cycle accordingly.

6. The UAV time synchronization method based on dynamic error compensation as described in claim 1, characterized in that, The operation modes of multiple drones include a distributed operation mode, and the time synchronization method for the distributed operation mode includes: The historical error variance is obtained based on the historical time errors of multiple drones; Based on historical error variance, the priority of multiple drones is determined; Based on the aforementioned priority, drones that serve as temporary master nodes are periodically elected according to the election cycle. The drone of the temporary master node sends synchronization signals to the drones of the other slave nodes according to the broadcast cycle; After receiving the synchronization signal from the drone at the node, the control signal of the digital phase-locked loop is obtained by analysis, and the local clock frequency is adjusted using the control signal.

7. The UAV time synchronization method based on dynamic error compensation as described in claim 6, characterized in that, The time synchronization method for the distributed working mode also includes: After the drone at the slave node completes the clock frequency adjustment, it sends a confirmation signal back to the drone at the temporary master node. If the number of times a drone of the temporary master node fails to receive a confirmation signal from a drone of the slave node exceeds a preset number, then the drone of the temporary master node will be excluded, and a new drone of the temporary master node will be re-elected.

8. The UAV time synchronization method based on dynamic error compensation as described in claim 6, characterized in that, The time synchronization method for the distributed working mode also includes: The broadcast cycle is dynamically adjusted based on the communication network load among multiple drones. If the communication network load between multiple drones exceeds the preset load, the election cycle will be extended.

9. A time synchronization module for unmanned aerial vehicles (UAVs) based on dynamic error compensation, characterized in that, include: The timestamp recording unit is used to obtain the time information of messages exchanged between the two drones; The error calculation unit is used to determine the real-time time error based on time information and temperature data. The dynamic error compensation unit is used to input historical time error, temperature data, and acceleration data into the adaptive network model to obtain the predicted time error; it is also used to obtain the comprehensive time error based on the real-time time error and the predicted time error. The clock adjustment unit is used to obtain the compensated corrected clock frequency based on the comprehensive time error, time synchronization period and current clock frequency; it is also used to convert the corrected clock frequency into a control signal for a digital phase-locked loop, and adjust the clock frequency of the UAV according to the control signal to control the time synchronization of the two UAVs. The comprehensive time error is , The corrected clock frequency is: , in, Indicates the real-time time error. Indicates the prediction time error. Indicates the current clock frequency. Indicates the overall time error. Indicates the time synchronization period.

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