A clock signal generator and method capable of frequency trimming.

Abstract

The present invention provides a clock signal generator and a frequency trimming method that can trim the clock frequency with high resolution. [Solution] The clock signal generator includes an oscillator circuit and a charge transfer capacitor. The oscillator circuit is configured to generate a clock signal and includes a comparator and a resistor-capacitor (RC) circuit, the RC circuit including a capacitor. The charge transfer capacitor is connected to the RC circuit. The frequency of the clock signal is trimmed by injecting or extracting charge associated with the RC circuit through the charge transfer capacitor.

Description

[Technical Field]

[0001] The present invention relates to a clock signal generator and a frequency trimming method, and more specifically, to a clock signal generator and a frequency trimming method that can trim clock frequencies with high resolution. [Background technology]

[0002] Unless otherwise stated herein, the approaches described in this section are not prior art to the claims of this application, nor are they deemed prior art simply because they are included in this section.

[0003] U.S. Patent No. 11943585 Calligraphy This is the specification of U.S. Patent Application No. 19 / 035763 In the book This document discloses an air pulse generating (APG) device that can be used as an acoustic generating device. As described in Patent Document 1 or Patent Document 2, the operating frequency of an APG device affects the sound pressure level (SPL). Specifically, the SPL is determined by how close the operating frequency approaches the resonant frequency.

[0004] However, the resonant frequency of APG devices varies due to manufacturing variations. As a result, the operating frequency must be precisely calibrated to match the specific resonant frequency of each individual APG device.

[0005] Therefore, a clock signal generator capable of frequency trimming is desired to compensate for such variations and ensure optimal performance. [Prior art documents] [Non-patent literature]

[0006] [Non-Patent Document 1] Analog Engineer's Circuit, Relaxation Oscillator Circuit, Texas Instruments, https: / / www.ti.com / lit / pdf / snoa998 [Non-Patent Document 2] S. -Y. Lu and Y. -T. Liao, "A Low-Power, Differential Relaxation Oscillator With the Self-Threshold-Tracking and Swing-Boosting Techniques in 0.18-μm CMOS," in IEEE Journal of Solid-State Circuits, vol. 54, no. 2, pp. 392-402, Feb. 2019 [Non-Patent Document 3] J. Lee, AK George and M. Je, "An Ultra-Low-Noise Swing-Boosted Differential Relaxation Oscillator in 0.18-μm CMOS," in IEEE Journal of Solid-State Circuits, vol. 55, no. 9, pp. 2489-2497, Sept. 2020 [Overview of the project] [Problems that the invention aims to solve]

[0007] Therefore, the main objective of this application is to provide a clock signal generator and a frequency trimming method that can trim the clock frequency with high resolution. [Means for solving the problem]

[0008] Embodiments of the present invention disclose a clock signal generator comprising an oscillator circuit configured to generate a clock signal, the oscillator circuit comprising a comparator and a resistor-capacitor (RC) circuit, wherein the RC circuit comprises a capacitor, and a charge-transfer capacitor connected to the RC circuit, wherein the frequency of the clock signal is trimmed by injecting or extracting charge associated with the RC circuit through the charge-transfer capacitor.

[0009] Embodiments of the present invention disclose a frequency trimming method applicable to a clock signal generator and configured to trim the frequency of a clock signal of the clock signal generator, comprising injecting or extracting charge associated with a resistor-capacitor (RC) circuit, wherein the clock signal generator includes an oscillator circuit, the oscillator circuit includes a comparator and an RC circuit, and the oscillator circuit generates a clock signal.

[0010] These and other objectives of the present invention will be undoubtedly apparent to those skilled in the art from the following detailed description of preferred embodiments shown in various figures and drawings. [Brief explanation of the drawing]

[0011] [Figure 1] This is a schematic diagram of a clock signal generator capable of frequency trimming according to an embodiment of the present invention. [Figure 2] This diagram shows a schematic representation of an oscillator circuit and related waveforms. [Figure 3] This diagram illustrates a clock signal generator with frequency trimming capabilities and related waveforms. [Figure 4] This represents another (relaxed) oscillator or oscillator circuit and its corresponding waveform. [Figure 5] This diagram illustrates a schematic of a clock signal generator capable of frequency trimming. [Figure 6] This diagram illustrates a schematic of a clock signal generator capable of frequency trimming. [Figure 7] This is a schematic diagram of an oscillator circuit and its operation. [Figure 8]This is a schematic diagram of a clock signal generator capable of frequency trimming according to an embodiment of the present invention. [Figure 9] This shows the waveforms of the clock signal and capacitor voltage. [Figure 10] This shows the charge transfer capacitor in Figure 8, which is realized using an equivalent charge transfer capacitor. [Figure 11] This is a schematic diagram of a clock signal generator capable of frequency trimming according to an embodiment of the present invention. [Modes for carrying out the invention]

[0012] This invention proposes a clock signal generator capable of frequency trimming. Furthermore, frequency trimming is achieved by a charge injection / extraction mechanism, and the amount of injected / extracted charge and / or delay time are used as control parameters. The clock frequency can be adjusted monotonically, and the aforementioned manufacturing variations can be compensated with high resolution.

[0013] Figure 1 is a schematic diagram of a frequency-trimmable clock signal generator 10 according to an embodiment of the present invention. The frequency-trimmable clock signal generator 10 comprises an oscillation circuit 12 and a charge transfer capacitor C IE The oscillator circuit 12 may be a relaxation oscillator and includes a resistive-capacitor (RC) circuit 14 and a comparator 16. The output of the comparator 16 is typically fed back to the oscillator circuit 12 to switch between a charged state / phase and a discharged state / phase. The RC circuit 14 has a capacitor voltage V C The charging or discharging operation is performed so that the capacitor voltage V increases (during charging) or decreases (during discharging). C When the value increases or decreases and crosses the threshold, the comparator 16 changes its state and generates a clock signal CLK.

[0014] For example, Figure 2(a) shows a schematic diagram of the oscillator circuit 22, and Figure 2(b) shows the output voltage V O and capacitor voltage V Crepresents the waveform. Figure 2 is cited from https: / / www.ti.com / lit / pdf / snoa998. The oscillation circuit 22 includes an RC circuit 24 and a comparator 26. The oscillation circuit 22 includes a capacitor C. During the discharge period T D the output voltage V O is low, and since the capacitor C discharges, the capacitor voltage V C decreases. When the capacitor voltage V C decreases to the first level, the comparator 26 is triggered to change its state, so the output voltage V O transitions to the high state, and the charging period T C begins. During the charging period T C the capacitor C charges, and the capacitor voltage V C increases. When the capacitor voltage V C reaches the second level, the comparator 26 is triggered again to change its state (to the low state), and another discharge period T D begins. [[ID=​​​​​​​​​​​​​​​​​​The second end receives the signal PS. Generally, the signal PS can have a rising edge or a falling edge, with the rising edge occurring within the discharge period, or the falling edge occurring within the charging period. In the embodiment shown in Figure 3, the falling edge occurs within the charging period.

[0018] For example, Figure 3(b) shows various duty / delay time t d(1) , t d(2) , t d(3) The corresponding pulse signal PS (1) PS (2) PS (3) , and pulse signal PS (1) PS (2) PS (3) The corresponding capacitor voltage V C(1) , V C(2) , V C(3) This represents the waveform of a pulse signal. (1) PS (2) PS (3) This includes a falling edge within the charging period of capacitor C. Charge transfer capacitor C IE At its second end, a pulse signal PS (1) / PS (2) / PS (3) If a signal is received, then at the moment corresponding to the falling edge, the charge transfer capacitor C IE Charge is extracted from capacitor C via this, and the capacitor voltage V C(1) / V C(2) / V C(3) The voltage decreases slightly during the charging period. This causes the capacitor voltage V to decrease. C(1) / V C(2) / V C(3) The waveform includes bumps bp that point in the negative direction or have negative polarity. Therefore, charge extraction lengthens the charging period and trims the clock frequency to a lower value.

[0019] Figure 4 shows another (relaxation) oscillator or oscillating circuit 32 and its corresponding waveform, quoted from S. -Y. Lu and Y. -T. Liao, "A Low-Power, Differential Relaxation Oscillator With the Self-Threshold-Tracking and Swing-Boosting Techniques in 0.18-μm CMOS," in IEEE Journal of Solid-State Circuits, vol. 54, no. 2, pp. 392-402, Feb. 2019. The oscillating circuit 32 includes an RC circuit 34 and an (inverter-based) comparator 36. The RC circuit 34 contains a capacitor C T1 , C T2 Includes the same as oscillator circuit 22, (output) voltage V op / V on During the high / low state, capacitor C T1 / C T2 The device alternates between charging and discharging. The clock frequency of the oscillation circuit 32 is determined by the RC time constant and is not frequency-trimmable.

[0020] Figure 5 is a schematic diagram of a clock signal generator 30 capable of frequency trimming. In addition to the oscillator circuit 32, a charge transfer capacitor C IE(1) , C IE(2) It includes a charge transfer capacitor C. IE(1) , C IE(2) The first end is capacitor C T1 , C T2 It may be coupled to a charge transfer capacitor C. IE(1) , C IE(2) The second end is connected to capacitor C in RC circuit 34. T1 / C T2 Injecting charge into, or capacitor C T1 / C T2 A signal with rising / falling edges may be received in order to extract charge from it.

[0021] In this invention, "a signal having rising edge / falling edge" generally refers to a signal having a (sudden) voltage change from a first voltage to a second voltage.

[0022] In an embodiment, the second terminal of the charge transfer capacitor may receive another clock signal. In an embodiment, the other clock signal may be a delayed version of a clock signal output by an oscillator circuit of a frequency-trimmable clock signal generator.

[0023] Figure 6 shows a schematic diagram of a clock signal generator 10b with frequency trimming capability. The clock signal generator 10b is similar to the clock signal generator 10. In addition to the clock signal generator 10, the clock signal generator 10b includes an oscillator circuit 12 (actually the output terminal of the comparator 16) and a charge transfer capacitor C IE It further includes a delay element DE coupled to the second end of the device. The delay element DE is a charge transfer capacitor C generated according to the clock signal CLK. IE The delayed clock signal CLK to the second end d It is configured to generate a delayed clock signal CLK. d Details of its operation will be described later.

[0024] Figure 7(a) is a schematic diagram of the oscillator circuit 42. The oscillator circuit 42 is configured to generate a clock signal CLK. The oscillator circuit 42 includes a chopper circuit 43, an RC circuit 44, and a comparator 46. Figure 7 is quoted from J. Lee, AK George and M. Je, "An Ultra-Low-Noise Swing-Boosted Differential Relaxation Oscillator in 0.18-μm CMOS," in IEEE Journal of Solid-State Circuits, vol. 55, no. 9, pp. 2489-2497, Sept. 2020.

[0025] The chopper circuit 43 includes nodes A and B. In the embodiment shown in Figure 7(a), the chopper circuit 43 is powered by a power supply (first voltage, e.g., V DD (to receive power) and grounding (second / grounding voltage, e.g., V GND It is also connected to receive power. During the first time (for example, corresponding to the first state (e.g., high state) of the clock signal CLK), the chopper circuit 43 receives the first voltage (e.g., V from the power supply). DD ) is supplied to node A, and a second voltage (for example, V from ground) GND ) is supplied to node B. During the second time (for example, corresponding to the second state of the clock signal CLK (for example, the low state)), the chopper circuit 43 supplies the second voltage (for example, V from ground). GND ) is supplied to node A, and the first voltage (for example, V from the power supply) DD ) is supplied to node B.

[0026] RC circuit 44 includes capacitors C1 and C2 and resistors R1 and R2. Capacitor C1 and resistor R1 are connected as a first series connection. Capacitor C2 and resistor R2 are connected as a second series connection. The first and second series connections are connected in parallel between node A and node B.

[0027] It should be noted that the resistors R1, R2 and capacitors C1, C2 in the RC circuit 44 of the present invention are for illustrative purposes only. Any component with electrical resistance and / or electrical capacitance can be substituted for R1, R2, C1, and C2 in the RC circuit 44 of the present invention. In other words, the resistors and capacitors of the present invention are symbolic representations of components with resistance and / or capacitance. They refer not only to individual physical resistors and capacitors, but also to any component exhibiting equivalent resistance or capacitance.

[0028] Comparator 46 has a first input terminal (indicated as "+") and a second input terminal (indicated as "-"). The first input terminal is coupled between capacitor C1 and resistor R1. The second input terminal is coupled between capacitor C2 and resistor R2.

[0029] The operation of the oscillator circuit 42 can be shown in Figure 7(b). During time T1, the clock signal CLK is low (i.e., comparator 46 outputs a low state), and node B has a voltage V DD Node A receives power and the voltage V GND It receives power. V DD >V GND Then, current flows from node B to node A, capacitor C2 discharges, capacitor C1 charges, and voltage V C2 The voltage V decreases. C1 It increases. Time T1 can be considered as the charging period of capacitor C1 or the discharging period of capacitor C2.

[0030] When the threshold condition is reached (for example, V C1 =V C2 ), comparator 46 transitions / changes to a high state (i.e., the clock signal CLK transitions to a high state), and node A is voltage VDD The switch occurs, and node B receives voltage V GND It switches to V during time T2. DD >V GND Then, threshold condition (for example, V C1 =V C2 Current flows from node A to node B, capacitor C1 discharges, capacitor C2 charges, and voltage V ) is filled again. C1 The voltage V decreases. C2 It increases. Time T2 can be considered as the discharge period of capacitor C1 or the charging period of capacitor C2.

[0031] As shown in Figure 7, the frequency of the clock signal CLK generated by the oscillator circuit 42 is determined purely by the resistance and capacitance of the RC circuit. When the resistance or capacitance of the RC circuit is selected, the frequency of the clock signal CLK is fixed / constant.

[0032] However, a clock signal generator capable of trimming the frequency is desired for some applications. For example, a clock signal generator capable of trimming the frequency may be used to generate a system clock signal for a drive circuit to drive an air pulse generation (APG) device disclosed in Patent Document 1 or Patent Document 2 as an acoustic generation device in which the sound pressure level (SPL) is affected by the operating frequency as mentioned in Patent Document 1 and / or Patent Document 2. Specifically, the SPL is determined by how close the operating frequency approaches the resonance frequency. Since the resonance frequency of the APG device varies due to manufacturing variations, it is desirable to design a clock signal capable of trimming the frequency so as to compensate for such variations and ensure optimal performance.

[0033] An object of the present invention is to propose a clock signal generator whose frequency can be trimmed.

[0034] FIG. 8 is a schematic diagram of a clock signal generator 40 whose frequency can be trimmed according to an embodiment of the present invention. In addition to the oscillation circuit 42, the clock signal generator 40 includes a charge transfer capacitor C IE,1 and C IE,2 further. The charge transfer capacitor C IE,1 / 2 is configured to inject charge into or extract charge from the capacitance related to the RC circuit 44, so that the charging period (discharging period) can be extended and the frequency of the clock signal can be trimmed.

[0035] In other words, the first end of the charge transfer capacitor C IE,1 / C IE,2 is coupled to the RC circuit 44 and / or the comparator 46. The charge transfer capacitor C IE,1 / C IE,2The second terminal of may receive / experience a sudden (or short - term) voltage rise so as to inject charge into the RC circuit 44, or may receive / experience a sudden (or short - term) voltage drop so as to extract charge from the RC circuit 44.

[0036] In an embodiment, the second terminal of the charge - transfer capacitor C IE,1 / C IE,2 may receive a signal having a rising edge at a certain point during the discharge period and inject charge into the RC circuit 44. In an embodiment, the second terminal of the charge - transfer capacitor C IE,1 / C IE,2 may receive a signal having a falling edge at a certain point during the charging period and extract charge from the RC circuit 44.

[0037] In an embodiment, the second terminal of the charge - transfer capacitor C IE,1 may receive a delayed version of the clock signal (or a delayed clock signal) CLK d , while the second terminal of the charge - transfer capacitor C IE,2 may receive a delayed version of the complementary clock signal (or a delayed complementary clock signal) bar CLK d . As shown in FIGS. 7 and 8, the complementary clock signal bar CLK is the complementary signal of the clock signal CLK. The clock signal CLK is output from the first output terminal of the comparator 46, and the complementary clock signal bar CLK is output from the second output terminal of the comparator 46.

[0038] As shown in FIG. 8, the clock signal generator 40 (whose frequency is tunable) includes delay elements DE1 and DE2. The delay element DE1 is coupled between the charge - transfer capacitor C IE,1 and the first output terminal (denoted as “ - ”) of the comparator 46. The delay element DE2 is coupled between the charge - transfer capacitor C IE,2 and the second output terminal (denoted as “ + ”) of the comparator 46. The delay element DE1 provides a delayed clock signal CLK IE,1 to the charge - transfer capacitor C dIt generates the delay element DE2, which is a charge transfer capacitor C. IE,2 Delayed complementary clock signal bar CLK d Generates.

[0039] In this embodiment, the delay element DE1 has a delay time (for example, t) relative to the clock signal CLK. di A delayed clock signal CLK having ) d Charge transfer capacitor C IE,1 The delay element DE2 is generated relative to the complementary clock signal bar CLK, and the delay time (e.g., t) is set relative to the complementary clock signal bar CLK. di ) a delayed complementary clock signal bar CLK d Charge transfer capacitor C IE,2 It is generated for the delay element DE1. di and the delay time t applied to the delay element DE2 di They may be different or not, and in either case, it is within the scope of the present invention.

[0040] Clock signals CLK, CLK d , bar CLK, bar CLK d and capacitor voltage V C1 , V C2 The waveform is shown in Figure 9. Note that both the frequency-trimmable clock signal generators 30 and 40 have a capacitor voltage V C1 , V C2 It can generate waveforms.

[0041] During period T1, the clock signal CLK is low and the complementary clock signal bar CLK is high. Capacitor C1 is charged and capacitor C2 is discharged. T1 can be considered as the charging period of capacitor C1 and / or the discharging period of capacitor C2.

[0042] Delayed complementary clock signal bar CLK d Since it has a rising edge within the discharge period of capacitor C2, ΔV2·C IE,2 A charge with this quantity is a charge transfer capacitor C IE,2The voltage V is injected into capacitor C2 via the same channel. C2 This creates a bump bp2 (with positive polarity) in the waveform. On the other hand, the delayed clock signal CLK d Since it has a falling edge within the charging period of capacitor C1, ΔV1·C IE,1 A charge with this quantity is a charge transfer capacitor C IE,1 The voltage V is extracted from capacitor C1 via the capacitor C1. C1 This creates a bump bp1 (with negative polarity) in the waveform.

[0043] In other words, the waveform of the capacitor voltage can be considered to have a bump (e.g., bp2) during the exponential decrease in the discharge period of the capacitor (e.g., C2), or a bump (e.g., bp1) during the exponential increase in the charge period of the capacitor (e.g., C1).

[0044] During period T2, the clock signal CLK is high and the complementary clock signal bar CLK is low. Capacitor C1 is discharged and capacitor C2 is charged. T2 can be considered as the discharge period of capacitor C1 and / or the charging period of capacitor C2.

[0045] Delayed clock signal CLK d Since it has a rising edge within the discharge period of capacitor C1, ΔV1·C IE,1 A charge with this quantity is a charge transfer capacitor C IE,1 The voltage V is injected into capacitor C1 via the same means. C1 This creates a bump (with positive polarity) in the waveform. On the other hand, the delayed complementary clock signal bar CLK d Since it has a falling edge within the charging period of capacitor C2, ΔV2·C IE,2 A charge with this quantity is a charge transfer capacitor C IE,2 The voltage V is extracted from capacitor C2 via the capacitor C2. C2 This creates a bump (with negative polarity) in the waveform.

[0046] The injected / extracted charge or bump (e.g., bp1 or bp2) can lengthen the charging (discharging) period T1 / T2. Consequently, the frequency of the clock signal CLK can be adjusted / trimmed to a lower value.

[0047] The amount of frequency adjustment is ΔV1 or ΔV2 (voltage change at the second terminal of the charge transfer capacitor), and the charge transfer capacitor C IE,1 or C IE,2 capacitance and delay time t di It can be determined by [the method used].

[0048] In the embodiment shown in Figure 9, unless otherwise specified, ΔV1 = ΔV2 = V DD In another embodiment, a charge transfer capacitor C IE,1 or C IE,2 The second end may receive another clock signal or another signal having a step function, i.e., a sudden voltage change ΔV1 or ΔV2. In this case, ΔV1 or ΔV2 becomes a control variable / parameter for frequency trimming.

[0049] Charge transfer capacitor C IE,1 or C IE,2 The capacitance can be another control variable / parameter for frequency trimming. As described above, the capacitor of the present invention can be replaced by any component having capacitance. In this regard, the charge transfer capacitor C IE,1 or C IE,2 The capacitance may be adjustable. For example, referring to Figure 10, the charge transfer capacitor C in Figure 8. IE,1 or C IE,2 This is an equivalent charge transfer capacitor C shown in Figure 10. IE,(e) This can be achieved by, where an equivalent charge transfer capacitor C IE,(e) The internal switch is equivalent to a charge transfer capacitor C IE,(e)The capacitance may be configured to adjust. The greater the capacitance, the longer the charging (discharging) period, and therefore the lower the clock frequency is trimmed. In other words, as the capacitance increases, the charging and discharging periods become longer, and the trimmed clock frequency becomes lower.

[0050] Delay time t di This is also a control variable / parameter for frequency trimming and is adjustable. Since the charging current (discharging current) decreases monotonically (exponentially) with respect to time, if a constant amount of charge is injected / extracted, the delay time t di The larger t is, the weaker the charging current (discharging current) and the longer the charging period (discharging period), so the clock frequency is trimmed lower. In other words, the delay time t di As the value increases, the charging and discharging periods become longer, resulting in a lower trimmed clock frequency.

[0051] If the charging (discharging) of an RC circuit behaves monotonically (exponentially), then the trimmed clock frequency is equal to the charge transfer capacitor (e.g., C). IE,1 Or C IE,2 ) capacitance or delay time (e.g., t di As ) increases, it decreases monotonically. In this regard, the frequency-trimmable clock signal generator of the present invention (e.g., 40) can achieve very high resolution with respect to clock frequency trimming.

[0052] The frequency-trimmable clock signal generator (e.g., 40) of the present invention has several advantages. One advantage is that the amount of charge injected / extracted is constant or controllable. Charge transfer capacitor (e.g., C IE As long as the capacitance of the capacitor and the voltage change at the second terminal of the charge transfer capacitor (e.g., ΔV1 or ΔV2) remain constant, the amount of charge injected / extracted is constant.

[0053] Another advantage is that, because the frequency-trimmable clock signal generator of the present invention includes minimal active circuitry, noise introduced by the active circuitry is minimized. Even if a delay element is included, the delay element indirectly introduces jitter.

[0054] Another advantage is the charge transfer capacitor (e.g., C IE The capacitance of the RC circuit isolates the noise to some extent, and the active circuit is not connected to the RC circuit.

[0055] Furthermore, the present invention provides a reliable frequency trimming method logic. The trimmed clock frequency is transferred to a charge transfer capacitor (e.g., C). IE ) capacitance or delay time (e.g., t di It is monotonic with respect to ), and it is possible to achieve very high resolution in frequency trimming.

[0056] The above are merely embodiments of the present invention and are not limiting. Any modifications, equivalent substitutions, or improvements in accordance with the spirit and principles of the present invention should also be included within the scope of the invention.

[0057] For example, Figure 11 is a schematic diagram of a frequency-trimmable clock signal generator 50 according to an embodiment of the present invention. In Figure 11, a charge transfer capacitor C IE,1 / C IE,2 The second terminal can receive voltages V1 / V2 via switches SW1 / SW2. Switches SW1 / SW2 are charge transfer capacitors C IE,1 / C IE,2 A sudden voltage change can occur in the voltage V1 / V2 at the second terminal. This is also within the scope of the present invention.

[0058] In summary, the frequency-trimmable clock signal generator of the present invention provides a high-resolution solution for precisely calibrating the operating frequency to match the specific resonant frequency of individual air pulse generation (APG) devices. By using a charge injection / extraction mechanism through a charge transfer capacitor, the charging and discharging periods of the RC oscillator circuit can be monotonically adjusted with high precision. This approach not only ensures reliable frequency trimming to compensate for manufacturing variations but also offers significant advantages such as low-noise operation, reduced jitter, and improved signal isolation, as it minimizes reliance on active circuits directly connected to the RC timing path. As a result, the proposed invention achieves optimal sound pressure level (SPL) performance in APG devices for acoustic generation applications while maintaining stable and predictable oscillation behavior.

[0059] The above describes the features of several embodiments so that a person skilled in the art may fully understand aspects of the disclosure. A person skilled in the art will recognize that the disclosure provides a basis for designing or modifying other processes to achieve substantially the same functions and / or results as the embodiments described herein. Furthermore, such equivalent substitutions would not deviate from the spirit and scope of the disclosure, and various changes, substitutions, and modifications may be made without such deviation. [Explanation of symbols]

[0060] 10, 20, 30, 10b, 40, 50 Clock signal generator 12,22,32,42 Oscillator Circuit 14,24,34,44 RC circuit 16, 26, 36, 46 comparators 43 Chopper Circuit C Capacitor C IE Charge transfer capacitor CLK clock signal CLK d Delayed clock signal DE delay element TC Charging period T D Discharge period V C Capacitor voltage

Claims

1. An oscillator circuit configured to generate a clock signal, comprising a comparator and a resistor-capacitor (RC) circuit, wherein the RC circuit includes a capacitor, and the oscillator circuit, The RC circuit includes a charge transfer capacitor connected to the RC circuit, The frequency of the clock signal is trimmed by injecting or extracting the charge associated with the RC circuit through the charge transfer capacitor. Clock signal generator.

2. The RC circuit includes a resistor connected to the capacitor, The clock signal generator according to claim 1.

3. The resistor and the capacitor are connected between the first node and the second node. The oscillation circuit includes a chopper circuit coupled to the first node and the second node, During the first hour, the chopper circuit supplies a first voltage to the first node and a second voltage to the second node. During the second time, the chopper circuit supplies the second voltage to the first node and supplies the first voltage to the second node. The clock signal generator according to claim 2.

4. The first end of the charge transfer capacitor is connected to the RC circuit. The second terminal of the charge transfer capacitor changes from a second voltage to a first voltage. The clock signal generator according to claim 1.

5. The second end of the charge transfer capacitor receives a first signal having a rising edge. The clock signal generator according to claim 4.

6. The second end of the charge transfer capacitor receives the first signal having the rising edge during the discharge period. The clock signal generator according to claim 5.

7. The second end of the charge transfer capacitor receives a second signal having a falling edge. The clock signal generator according to claim 4.

8. The second end of the charge transfer capacitor receives the second signal having the falling edge during the charging period. The clock signal generator according to claim 7.

9. A delay element is coupled between the comparator and the charge transfer capacitor, The clock signal generator according to claim 1.

10. The delay element generates a delayed clock signal to the charge transfer capacitor according to the clock signal output from the comparator. The clock signal generator according to claim 9.

11. The delay element generates the delayed clock signal having a delay time relative to the clock signal. The clock signal generator according to claim 10.

12. The aforementioned delay time is adjustable. The clock signal generator according to claim 11.

13. The frequency of the clock signal is trimmed by adjusting the delay time or the capacitance of the charge transfer capacitor. The clock signal generator according to claim 11.

14. The frequency of the clock signal is trimmed by adjusting the delay time to be longer. The clock signal generator according to claim 13.

15. The frequency of the clock signal is trimmed by adjusting the capacitance to a higher value. The clock signal generator according to claim 13.

16. The waveform of the capacitor voltage of the aforementioned capacitor includes bumps. The clock signal generator according to claim 1.

17. The aforementioned bump occurs when a delay time has elapsed after the oscillation circuit has undergone a state transition. The clock signal generator according to claim 16.

18. The waveform of the capacitor voltage includes the bump in the exponential decrease during the discharge period of the capacitor. The clock signal generator according to claim 16.

19. The waveform of the capacitor voltage includes the bump in its exponential increase during the charging period of the capacitor. The clock signal generator according to claim 16.

20. The aforementioned RC circuit is A first capacitor coupled to the first input terminal of the comparator, The comparator includes a second capacitor coupled to the second input terminal, The clock signal generator according to claim 1.

21. A first charge transfer capacitor coupled to the first capacitor, The system includes a second charge transfer capacitor coupled to the second capacitor, The clock signal generator according to claim 20.

22. A first delay element coupled between the first output terminal of the comparator and the first charge transfer capacitor, A second delay element coupled between the second output terminal of the comparator and the second charge transfer capacitor, The clock signal generator according to claim 21.

23. The first delay element generates a delayed clock signal to the first charge transfer capacitor according to the clock signal output from the first output terminal of the comparator. The second delay element generates a delayed complementary clock signal to the second charge transfer capacitor according to the complementary clock signal output from the second output terminal of the comparator. The clock signal generator according to claim 22.

24. The delayed clock signal has a delay time relative to the clock signal. The delayed complementary clock signal has a delay time relative to the complementary clock signal. The clock signal generator according to claim 23.

25. The first waveform of the first capacitor voltage of the first capacitor includes a first bump toward the first polarity in the exponential decrease during the discharge period of the first capacitor. The second waveform of the second capacitor voltage of the second capacitor includes a second bump toward the second polarity in the exponential increase during the charging period of the second capacitor. The first polarity and the second polarity are opposite to each other. The discharge period of the first capacitor and the charge period of the second capacitor coincide with each other. The clock signal generator according to claim 20.

26. A frequency trimming method applied to a clock signal generator and configured to trim the frequency of the clock signal of the clock signal generator, This includes injecting or extracting charge associated with a resistor-capacitor (RC) circuit. The clock signal generator includes an oscillator circuit, and the oscillator circuit includes a comparator and the RC circuit. The oscillator circuit generates the clock signal. Frequency trimming method.

27. This includes injecting or extracting the charge associated with the RC circuit via a charge transfer capacitor connected to the RC circuit. The frequency trimming method according to claim 26.

28. Injecting the charge through the charge transfer capacitor means This includes increasing the voltage at the ends of the charge transfer capacitor during the discharge period of the capacitor in the RC circuit. The frequency trimming method according to claim 27.

29. Extracting the charge via the charge transfer capacitor is This includes reducing the voltage at the ends of the charge transfer capacitor during the charging period of the capacitor in the RC circuit. The frequency trimming method according to claim 27.

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