Display devices and electronic devices

Abstract

The present invention provides a novel display device. The display device comprises a first layer and a second layer on the first layer. The first layer comprises a functional circuit. The second layer comprises a display unit including a plurality of pixels and a storage unit including a plurality of memory cells. Each of the plurality of pixels comprises a pixel circuit and a light-emitting element on the pixel circuit. The functional circuit comprises a display unit drive circuit and a control circuit. The storage unit has a function of storing image data to be output to the display unit via the display unit drive circuit. The memory cell comprises a first transistor for maintaining a potential according to the image data and a second transistor for reading out the potential, the first transistor being provided on the second layer and the second transistor being provided on the first layer.

Description

display device

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, a power storage device, a memory device, an electronic device, a lighting device, an input device, an input / output device, a driving method thereof, or a manufacturing method thereof.

[0003] In recent years, there has been a demand for higher resolution display devices. Devices requiring high resolution display devices include, for example, devices for virtual reality (VR), augmented reality (AR), substitutional reality (SR), or mixed reality (MR), and these devices have been actively developed in recent years. Display devices used in these devices are required to be compact as well as high resolution.

[0004] VR, AR, SR, and MR are also collectively referred to as xR. Examples of display devices for xR include light-emitting devices equipped with light-emitting elements such as organic electroluminescence (EL) elements or light-emitting diodes (LEDs), and liquid crystal display devices.

[0005] For example, the basic structure of an organic EL element is a layer containing a light-emitting organic compound sandwiched between a pair of electrodes. By applying a voltage to this element, light can be emitted from the light-emitting organic compound. A display device using such an organic EL element does not require a backlight, which is necessary in liquid crystal display devices and the like, and therefore can realize a thin, lightweight, high-contrast, and low-power display device. For example, an example of a display device using an organic EL element is described in Patent Document 1.

[0006] JP 2002-324673 A

[0007] Display devices for xR are required to be compact, consume less power, and have more functions.

[0008] An object of one embodiment of the present invention is to provide a miniaturized display device.An object of one embodiment of the present invention is to provide a display device with high color reproducibility.An object of one embodiment of the present invention is to provide a high-resolution display device.An object of one embodiment of the present invention is to provide a display device with high emission luminance.An object of one embodiment of the present invention is to provide a highly reliable display device.An object of one embodiment of the present invention is to provide a novel display device.

[0009] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0010] One embodiment of the present invention is a display device including a first layer and a second layer over the first layer, in which the first layer has a functional circuit, and the second layer has a display portion including a plurality of pixels and a memory portion having a plurality of memory cells, each of the plurality of pixels having a pixel circuit and a light-emitting element in the pixel circuit, the functional circuit has a display portion driver circuit, and the memory portion has a function of storing image data to be output to the display portion via the display portion driver circuit.

[0011] In one embodiment of the present invention, the display device is preferably such that the memory cell is provided in a region where the pixel circuit is provided.

[0012] In one embodiment of the present invention, the display device preferably has the memory cell provided in at least a part of the outer periphery of the display portion.

[0013] In one embodiment of the present invention, a display device is preferably such that a memory cell includes a first transistor for holding a potential corresponding to image data and a second transistor for reading out the potential, the first transistor being provided in a second layer, and the second transistor being provided in a first layer.

[0014] In one embodiment of the present invention, the display device preferably includes a semiconductor layer having a channel formation region of the first transistor containing metal oxide, and a semiconductor layer having a channel formation region of the second transistor containing silicon.

[0015] In one embodiment of the present invention, the display device is preferably such that the display portion driver circuit is provided in a region overlapping with the display portion.

[0016] In one embodiment of the present invention, the display device preferably includes a control circuit, a sensor circuit, a communication circuit, and an input / output circuit as the functional circuit.

[0017] In one aspect of the present invention, a display device is preferred in which the display unit has a plurality of sub-display units, each of which has a display unit drive circuit, and the number of times image data is rewritten per unit time in any one of the sub-display units is less than the number of times image data is rewritten per unit time in the other sub-display units.

[0018] One embodiment of the present invention is a display device including a first layer, a second layer over the first layer, and a third layer over the second layer, in which the first layer has a functional circuit, the second layer has a display portion including a plurality of pixels, and the third layer has a memory portion including a plurality of memory cells, each of the plurality of pixels having a pixel circuit and a light-emitting element in the pixel circuit, the functional circuit has a display portion driver circuit, and the memory portion has a function of storing image data to be output to the display portion via the display portion driver circuit.

[0019] In one embodiment of the present invention, a display device is preferably such that the memory cell includes a first transistor for holding a potential corresponding to image data and a second transistor for reading out the potential, the first transistor being provided in a third layer, and the second transistor being provided in a first layer.

[0020] In one embodiment of the present invention, the display device preferably includes a semiconductor layer having a channel formation region of the first transistor containing metal oxide, and a semiconductor layer having a channel formation region of the second transistor containing silicon.

[0021] In one embodiment of the present invention, the display device is preferably such that the display portion driver circuit is provided in a region overlapping with the display portion.

[0022] In one embodiment of the present invention, the display device preferably includes a control circuit, a sensor circuit, a communication circuit, and an input / output circuit as the functional circuit.

[0023] One embodiment of the present invention is an electronic device including the above display device and a housing.

[0024] Other aspects of the present invention will be described in the following embodiments and in the drawings.

[0025] According to one embodiment of the present invention, a miniaturized display device can be provided. Alternatively, a display device with high color reproducibility can be provided. Alternatively, a high-definition display device can be provided. Alternatively, a display device with high emission luminance can be provided. Alternatively, a highly reliable display device can be provided. Alternatively, a novel display device can be provided.

[0026] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0027] FIGS. 1A and 1B are diagrams illustrating an example of the configuration of a display device. FIG. 2 is a diagram illustrating an example of the configuration of a display device. FIGS. 3A and 3B are diagrams illustrating an example of the configuration of a display device. FIG. 4 is a diagram illustrating an example of the configuration of a display device. FIGS. 5A and 5B are diagrams illustrating an example of the configuration of a display device. FIGS. 6A to 6C are diagrams illustrating an example of the configuration of a display device. FIGS. 7A to 7D are diagrams illustrating an example of the configuration of a display device. FIGS. 8A to 8D are diagrams illustrating an example of the configuration of a display device. FIGS. 9A and 9B are diagrams illustrating an example of the configuration of a display device. FIGS. 10A and 10B are diagrams illustrating an example of the configuration of a display device. FIGS. 11A to 11H are diagrams illustrating an example of the configuration of a display device. FIGS. 12A and 12B are diagrams illustrating an example of the configuration of a display device. FIGS. 13A and 13B are diagrams illustrating an example of the configuration of a display device. FIGS. 14A and 14B are diagrams illustrating an example of the configuration of a display device. FIGS. 15A and 15B are diagrams illustrating an example of the configuration of a display device. FIG. 16 is a diagram illustrating an example of the configuration of a display device. Fig. 17A and Fig. 17B are diagrams illustrating an example of the configuration of a display device. Fig. 18 is a diagram illustrating an example of the configuration of a display device. Fig. 19 is a diagram illustrating an example of the configuration of a display device. Figs. 20A and 20B are diagrams illustrating an example of the configuration of a display device. Figs. 21A and 21B are diagrams illustrating an example of the configuration of a display device. Fig. 22 is a diagram illustrating an example of the configuration of a display device. Fig. 23 is a diagram illustrating an example of the configuration of a display device. Figs. 24A to 24E are diagrams illustrating an example of an electronic device.

[0028] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different forms and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0029] In addition, in the drawings, the size, layer thickness, or area may be exaggerated for clarity, and therefore, are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes, values, etc. shown in the drawings.

[0030] In this specification and the like, unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). Unless otherwise specified, the off-state current refers to the drain current when a transistor is in an off state (also referred to as a non-conducting state or a cut-off state). ｇｓ is the threshold voltage V ｔｈ (For p-channel transistors, V ｔｈ This refers to a state of being (higher than)

[0031] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is used in an active layer of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0032] Embodiment 1 A display device according to one embodiment of the present invention will be described.

[0033] 1A and 2 are perspective views of a display device 100A according to one embodiment of the present invention. FIG. 1B is a block diagram illustrating a configuration of the display device 100A. The display device 100A includes a layer 30 on a layer 20 and a sealing substrate 40 on the layer 30. The layer 30 includes a memory unit 11 and a display unit 31, and a layer 60 is provided between the sealing substrate 40 and the display unit 31. The configuration in which the memory unit 11 is provided on the layer 30 at the periphery of the region where the display unit 31 is provided is illustrated as an example. In FIG. 2, the layer 20, the layer 30, the layer 60, the sealing substrate 40, and the like are shown separated from each other to make the configuration of the display device 100A easier to understand.

[0034] The layer 20 includes a functional circuit 90 and a terminal section 29. The functional circuit 90 includes a control circuit 21, a display section drive circuit 23, a memory section drive circuit 24, a sensor circuit 26, a communication circuit 27, and an input / output circuit 28.

[0035] The functional circuit 90 does not need to include all of these components, or may include other components. For example, the functional circuit 90 may include a power supply circuit and / or a power management circuit that controls the stopping of power supply. It may also include, for example, a DSP (Digital Signal Processor) and / or an FPGA (Field Programmable Gate Array). It may also include, for example, a super-resolution circuit. The super-resolution circuit has a function of up-converting image data with a lower resolution than the display unit. The super-resolution circuit also has a function of down-converting image data with a higher resolution than the display unit.

[0036] The functional circuit 90 is preferably configured with a Si CMOS, i.e., a transistor having silicon in a channel formation region (Si transistor). That is, the layer 20 having the functional circuit 90 is a layer having Si transistors. By configuring the functional circuit 90 with Si transistors, circuits having functions such as a control circuit 21, a display unit drive circuit 23, a memory unit drive circuit 24, a sensor circuit 26, a communication circuit 27, and an input / output circuit 28 can be provided in the functional circuit 90.

[0037] For the Si transistor, it is preferable to use silicon with high crystallinity, such as single crystal silicon or polycrystalline silicon, since high field effect mobility can be achieved and higher speed operation is possible.

[0038] The layer 30 includes an OS transistor, that is, a transistor having an oxide semiconductor in a channel formation region. With this structure, the memory unit 11 and the display unit 31 including the OS transistor can be stacked with the layer 20.

[0039] An OS transistor has a characteristic of having a very low off-state current. Therefore, when an OS transistor is used as a transistor provided in a pixel circuit, analog data written in the pixel circuit or a memory cell can be held for a long period of time.

[0040] Examples of metal oxides that can be used in OS transistors include Zn oxide, Zn—Sn oxide, Ga—Sn oxide, In—Ga oxide, In—Zn oxide, and In-M-Zn oxide (where M is Ti, Ga, Y, Zr, La, Ce, Nd, Sn, or Hf). Metal oxides using Ga as M are particularly preferred for use in OS transistors because they can provide transistors with excellent electrical characteristics, such as field-effect mobility, by adjusting the ratio of elements. The oxide containing indium and zinc may also contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0041] By providing the functional circuit 90 with functions such as up-conversion or down-conversion of image data, image processing that would otherwise be performed by an external circuit can be performed by the display device, and therefore image processing can be distributed between the external circuit and the functional circuit 90.

[0042] The control circuit 21 has a function of controlling the operation of the functional circuit 90 provided in the layer 20 based on signals from circuits that process image data, such as a CPU (Central Processing Unit) and a GPU (Graphics Processing Unit).

[0043] The display unit driving circuit 23 is electrically connected to the display unit 31 included in the layer 30, and has a function of supplying image data to the display unit 31. The display unit driving circuit 23 can use various circuits such as a shift register, a level shifter, an inverter, a latch, an analog switch, or a logic circuit. As shown in FIG. 2 , a layer 60 is provided over the display unit 31 included in the layer 30. The layer 60 includes a plurality of light-emitting elements, and the light emission brightness is controlled by a pixel circuit 51 provided in the display unit 31. Therefore, the layer 60 can also be considered as part of the display unit 31.

[0044] The display unit 31 includes pixels 50 each having a plurality of pixel circuits 51. The pixels 50 each include a pixel circuit 51 and a light-emitting element (not shown) provided in a layer 60 above the pixel circuit 51. The pixel circuit 51 corresponds to a pixel circuit included in a sub-pixel for displaying color. Details of the pixel circuit 51 and the light-emitting element will be described later.

[0045] Each of the three subpixels controls the amount of light emitted, for example, red light, green light, or blue light. The color of light controlled by each of the three subpixels is not limited to a combination of red (R), green (G), and blue (B), but may also be cyan (C), magenta (M), and yellow (Y). The areas of the three subpixels do not have to be the same. If the luminous efficiency and reliability differ depending on the luminous color, the area of ​​the subpixel may be varied for each luminous color. Four subpixels may be combined to function as a single pixel. For example, a subpixel controlling white light may be added to three subpixels controlling red, green, and blue light, respectively. Adding a subpixel controlling white light can increase the luminance of the display area. A subpixel controlling yellow light may be added to three subpixels controlling red, green, and blue light, respectively. A subpixel controlling white light may be added to three subpixels controlling cyan, magenta, and yellow light, respectively.

[0046] By increasing the number of sub-pixels that function as one pixel and by appropriately combining sub-pixels that control red, green, blue, cyan, magenta, and yellow light, it is possible to improve the reproducibility of intermediate tones, and therefore color reproducibility.

[0047] The memory unit driving circuit 24 is electrically connected to the memory unit 11 included in the layer 30, and has the function of writing data to the memory unit 11 and the function of reading data from the memory unit 11. The memory unit driving circuit 24 can be any of various circuits such as a word line driving circuit, a bit line driving circuit, or an analog-to-digital conversion circuit.

[0048] The sensor circuit 26 has a function of acquiring information from one or more of human vision, hearing, touch, taste, and smell. More specifically, the sensor circuit 26 has at least one of the functions of detecting or measuring force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, magnetism, temperature, sound, time, electric field, current, voltage, power, radiation, humidity, gradient, vibration, odor, and infrared light. The sensor circuit 26 may also have other functions.

[0049] The communication circuit 27 has a function of performing wireless or wired communication. In particular, a function of performing wireless communication is preferable because it can reduce the number of components such as cables for connection.

[0050] If the communication circuit 27 has a function of wireless communication, the communication circuit 27 can communicate via an antenna. Furthermore, as a communication protocol or communication technology, communication standards such as LTE (Long Term Evolution), GSM (Global System for Mobile Communication: registered trademark), EDGE (Enhanced Data Rates for GSM Evolution), CDMA2000 (Code Division Multiple Access 2000), and W-CDMA (registered trademark), or specifications standardized by IEEE such as Wi-Fi (registered trademark), Bluetooth (registered trademark), and ZigBee (registered trademark), can be used.

[0051] The communication circuit 27 can connect the display device 100A to other devices and input and output information via computer networks such as the Internet, an intranet, an extranet, a PAN (Personal Area Network), a LAN (Local Area Network), a CAN (Campus Area Network), a MAN (Metropolitan Area Network), a WAN (Wide Area Network), and a GAN (Global Area Network), which are the foundations of the World Wide Web (WWW).

[0052] The input / output circuit 28 has a function of distributing signals supplied to the display device 100A via the terminal unit 29 to each circuit such as the control circuit 21. The input / output circuit 28 also has a function of distributing signals supplied to the display device 100A via the communication circuit 27 to each circuit such as the control circuit 21.

[0053] The input / output circuit 28 also has a function of outputting a signal to the outside via a terminal unit 29. The input / output circuit 28 also has a function of outputting a signal to the outside via a communication circuit 27.

[0054] An FPC (flexible printed circuit) or the like is electrically connected to the terminal portion 29. Therefore, the layer 30 and the sealing substrate 40 are not formed in the area overlapping with the terminal portion 29.

[0055] The storage unit 11 includes a plurality of memory cells 12. The memory cells 12 function as memory elements. As the storage unit 11, various storage devices using various storage methods can be used. For example, a dynamic random access memory (DRAM), a static random access memory (SRAM), a phase-change memory (PCM), a resistive random access memory (ReRAM), a magnetoresistive random access memory (MRAM), a ferroelectric random access memory (FeRAM), an antiferroelectric memory, or the like may be used.

[0056] Furthermore, the storage unit 11 may be a nonvolatile oxide semiconductor random access memory (NOSRAM) or a dynamic oxide semiconductor random access memory (DOSRAM).

[0057] "NOSRAM (registered trademark)" is an abbreviation for "Nonvolatile Oxide Semiconductor Random Access Memory (RAM)." NOSRAM refers to a memory in which the memory cell is a two-transistor (2T) or three-transistor (3T) gain cell, and the access transistor is an OS transistor. The current that flows between the source and drain in the off state, that is, the leakage current, is extremely small. NOSRAM allows the stored data to be read without destroying it (non-destructive readout).

[0058] "DOSRAM (registered trademark)" is an abbreviation for "Dynamic Oxide Semiconductor RAM" and refers to a RAM having 1T (transistor) 1C (capacitor) type memory cells. Like NOSRAM, DOSRAM is a memory that utilizes the low off-state current of OS transistors.

[0059] NOSRAM and DOSRAM are types of memory devices that use transistors having an oxide semiconductor in a channel formation region (hereinafter also referred to as "OS transistors").

[0060] The memory cells 12 included in the memory unit 11 and the pixel circuits 51 included in the display unit 31 include OS transistors. This configuration allows the display unit 31 and the memory unit 11 to be arranged in the layer 30. By arranging the memory unit 11 and the display unit 31 in the same layer, the memory unit 11 can be arranged in an area of ​​the layer 30 where the display unit 31 is not arranged.

[0061] 2, the memory unit 11 is provided on the outer periphery of the area where the display unit 31 is provided. The memory unit 11 may be provided in at least a part of the outer periphery of the display unit 31. With this configuration, the memory unit 11 can be arranged so as to fill the area of ​​the layer 30 where the display unit 31 is not provided. Therefore, the memory capacity can be increased by arranging the memory unit 11 without reducing the area of ​​the display unit 31 or otherwise impairing the display quality.

[0062] In one embodiment of the present invention, the layer 30 including the display portion 31 may include the storage portion 11. This increases the storage capacity of the display device 100A. The storage portion 11 can be used as a frame memory by storing image data input from an external circuit. The image data is output to the display portion 31 via the display unit driver circuit 23.

[0063] 3A is a block diagram illustrating the configuration of the storage unit 11 that can be used as a frame memory. Illustrated in FIG. 3A are an external circuit 80 that processes image data, such as a CPU or GPU, a control circuit 21, the storage unit 11, a display unit drive circuit 23, and a display unit 31.

[0064] As described above, in one embodiment of the present invention, a configuration can be provided in which a plurality of frame memories each holding one frame of image data are provided because the storage capacity of the storage unit 11 can be increased. In FIG. 3A , a plurality of storage areas 11[1] to 11[N] (N is a natural number) are illustrated as the frame memories.

[0065] As described above, the memory unit 11 is configured to have memory cells using OS transistors, such as NOSRAM or DOSRAM. Therefore, unlike memory cells configured with Si transistors, such as static RAM (SRAM), the memory cells can be arranged in a layer different from the functional circuit 90 configured with Si transistors. In addition, while SRAM generally uses six transistors as memory cell components, NOSRAM uses two or three transistors. The circuit configuration combines OS transistors and Si transistors, and the data to be stored can be multi-valued. This allows for a larger capacity of data to be stored, enabling a configuration that can hold image data for multiple frames. Furthermore, when memory cells using OS transistors are used as frame memory, there is no need to provide a separate IC chip functioning as a frame memory in the display device, thereby reducing costs.

[0066] By including the storage unit 11 that functions as a frame memory requiring a large capacity, the display device of one embodiment of the present invention can be configured to hold image data for multiple frame periods. In this case, the amount of image data transferred from the external circuit 80 to the control circuit 21 can be reduced. Furthermore, the amount of image data transferred to and from the storage unit 11 via the control circuit 21 can be reduced.

[0067] Furthermore, a memory cell using an OS transistor can store analog values. Therefore, by storing analog data provided to a pixel circuit as data stored in the memory cell, image data can be directly provided to the display unit 31 from the storage unit 11. An example of a block diagram in this case is shown in FIG. 3B .

[0068] By having the storage unit 11 functioning as a frame memory for holding analog values ​​in this way, it is possible to omit the process of converting digital image data into analog image data, which is performed by the display unit drive circuit 23. As a result, the circuit scale of the display unit drive circuit 23 can be reduced.

[0069] In a configuration in which analog values ​​are held in the memory cells 12 of the storage unit 11 and provided to the pixel circuits, the memory cells 12 may be disposed in the region in which the pixel circuits are provided. An example of such a configuration is shown in FIG. 4. In the display device 100A_1 shown in FIG. 4, the display unit 31 and storage unit 11 are provided in the layer 30, and the memory cells 12 of the storage unit 11 are disposed in the pixel circuits 51 of the pixels 50. This configuration enables a so-called memory-in-pixel configuration in which memory cells using OS transistors are disposed in the pixel circuits. In this case, the capacity of the storage unit 11 functioning as a frame memory can be reduced.

[0070] 5A is a schematic diagram illustrating the connection relationship between the display unit drive circuit 23 and the display unit 31. As described above, in one aspect of the present invention, the display unit drive circuit 23 and the display unit 31 are provided in different layers, so that the display unit 31 can be provided above the display unit drive circuit 23.

[0071] The display unit drive circuit 23 has a first drive circuit 32 and a second drive circuit 33. The circuit included in the first drive circuit 32 functions as, for example, a scanning line drive circuit (gate line drive circuit). The circuit included in the second drive circuit 33 functions as, for example, a signal line drive circuit (source line drive circuit). The first drive circuit 32 is electrically connected to pixel circuits 51 of the display unit 31 provided above it via wiring GL (gate lines). The second drive circuit 33 is electrically connected to pixel circuits 51 of the display unit 31 provided above it via wiring SL (source lines).

[0072] The display unit driver circuit 23 may be referred to as a "peripheral driver circuit." The peripheral driver circuit may include various circuits such as shift registers, level shifters, inverters, latches, analog switches, and logic circuits. The peripheral driver circuit may include transistors and capacitive elements.

[0073] The schematic diagram shown in FIG. 5B is a configuration example in which a set of display units 31, first drive circuits 32, and second drive circuits 33 shown in FIG. 5A is arranged in a matrix of m rows and n columns (m and n are integers equal to or greater than 1). In this specification, the section in the first row and first column is referred to as display unit 31[1,1], and the section in the mth row and nth column is referred to as display unit 31[m,n]. Display units 31[1,1] through 31[m,n] can be combined to form display unit 31. Display units 31[1,1] through 31[m,n] may also be referred to as sub-display units. Display unit 31 can display a single image by combining multiple sub-display units. FIG. 5B shows a case in which m is 4 and n is 4. That is, display unit 31 is divided into 16 sections. Each of the divided display portions 31[1,1] to 31[m,n] includes a first driver circuit 32 connected to the wiring GL and a second driver circuit 33 connected to the wiring SL.

[0074] By providing the display unit 31 and the display unit drive circuit 23 in an overlapping region, the connection distance (wiring length) between the pixel circuit and the peripheral drive circuit can be made extremely short. As a result, wiring resistance and parasitic capacitance are reduced, which shortens the time required for charging and discharging, enabling high-speed driving. This also reduces power consumption. Furthermore, this also allows for a smaller, lighter device.

[0075] Furthermore, the display unit 31 is configured to have a first drive circuit 32 and a second drive circuit 33 for each of the display units 31[1,1] to 31[m,n]. Therefore, the display unit 31 can rewrite the image for each of the display units 31[1,1] to 31[m,n]. For example, it is possible to rewrite image data only in sections of the display unit 31 where changes have occurred in the image, and to retain the image data in sections where no changes have occurred, thereby reducing power consumption. In other words, it is possible to reduce the number of times per unit time that image data is rewritten in one of the sub-display units 31[1,1] to 31[m,n] compared to the number of times per unit time that image data is rewritten in the other sub-display units, thereby reducing power consumption.

[0076] Furthermore, the display device 100A can use the control circuit 21 to arbitrarily set the drive frequency (frame frequency, frame rate, refresh rate, etc.) for displaying images for each of the display units 31[1,1] to 31[m,n]. Therefore, by combining this with eye tracking or the like, it becomes possible to apply foveated rendering, a type of rendering that varies the frame rate for each region depending on the user's line of sight. This allows for a configuration that outputs images with excellent display quality and low load.

[0077] The control circuit 21 has a function of controlling the operation of each of the display units 31[1,1] to 31[m,n]. That is, the control circuit 21 has a function of controlling the drive frequency and operation timing of each of the plurality of display units 31[1,1] to 31[m,n] arranged in a matrix. The control circuit 21 also has a function of adjusting synchronization between the display units 31[1,1] to 31[m,n].

[0078] In the display device of one embodiment of the present invention, pixel circuits and peripheral driver circuits are stacked and the drive frequencies of the divided display portions 31 are made different from each other, thereby achieving low power consumption. For example, the drive frequencies of the divided display portions 31 are made different from each other according to the movement of the gaze. Note that information about the movement of the gaze (gazing point G) may be obtained by an eye tracking method such as a pupil center corneal reflection method or a bright / dark pupil effect method. Alternatively, the information may be obtained by an eye tracking method using a laser, ultrasound, or the like.

[0079] FIG. 6A shows a display unit 31 divided into 32 sections, or 4 rows and 8 columns. FIG. 6A also shows a first region S1 to a third region S3, each centered around a gaze point G. The display unit 31 divides each of the divided sections into either a first section 29A overlapping the first region S1 or the second region S2, or a second section 29B overlapping the third region S3. That is, the display unit 31 divides each of the divided sections into either a first section 29A or a second section 29B. In this case, the first section 29A overlapping the first region S1 and the second region S2 is a display section that includes an area overlapping with the gaze point G, and the second section 29B is located outside the first section 29A and far from the user's gaze point G (see FIG. 6B).

[0080] The operation of the first drive circuit 32 and the second drive circuit 33 of each divided display unit 31 is controlled by the control circuit 21. For example, the display unit corresponding to the second section 29B overlaps with the third region S3, which includes the stable fixation field, the guided field, and the auxiliary field, and is therefore a section with low user discrimination. Therefore, even if the number of times image data is rewritten per unit time (hereinafter also referred to as "image rewriting number") for the display unit belonging to the second section 29B is less than that for the display unit corresponding to the first section 29A, the actual display quality perceived by the user (hereinafter also referred to as "actual display quality") is only slightly reduced. In other words, even if the drive frequency of the display unit corresponding to the second section 29B is lower than that of the display unit corresponding to the first section 29A, the actual display quality is only slightly reduced.

[0081] Lowering the drive frequency can reduce the power consumption of the display device. On the other hand, lowering the drive frequency also reduces the display quality, particularly when displaying moving images. According to one aspect of the present invention, by setting the drive frequency of the display unit corresponding to the second section 29B lower than the drive frequency of the display unit corresponding to the first section 29A, it is possible to reduce the power consumption of sections with low user visibility while suppressing a substantial decrease in display quality. According to one aspect of the present invention, it is possible to maintain display quality while reducing power consumption.

[0082] The drive frequency of the display unit corresponding to the first section 29A may be 30 Hz to 500 Hz, preferably 60 Hz to 500 Hz. The drive frequency of the display unit corresponding to the second section 29B is preferably equal to or lower than the drive frequency of the first section 29A, more preferably equal to or lower than half the drive frequency of the display unit corresponding to the first section 29A, and even more preferably equal to or lower than one-fifth the drive frequency of the display unit corresponding to the first section 29A.

[0083] Furthermore, among the display units corresponding to the third region S3, a third section 29C may be set outside the second section 29B (see FIG. 6C ), and the drive frequency of the display unit corresponding to the third section 29C may be lower than that of the display unit corresponding to the second section 29B. The drive frequency of the display unit corresponding to the third section 29C is preferably equal to or lower than the drive frequency of the display unit corresponding to the second section 29B, more preferably equal to or lower than half the drive frequency of the display unit corresponding to the second section 29B, and even more preferably equal to or lower than one-fifth the drive frequency of the display unit corresponding to the second section 29B. By significantly reducing the number of times the image is rewritten, power consumption can be further reduced. Furthermore, if necessary, image data rewriting may be stopped. By stopping image data rewriting, power consumption can be further reduced.

[0084] When such a driving method is performed, it is preferable to use a transistor with extremely low off-state current as the transistor constituting the pixel circuit 51. For example, it is preferable to use an OS transistor as the transistor constituting the pixel circuit 51. Because the off-state current of an OS transistor is extremely low, image data supplied to the pixel circuit 51 can be held for a long period of time by stopping the output signal output from the first driver circuit.

[0085] Furthermore, when the video scene displayed on the display unit 31 changes, an image with significantly different brightness, contrast, or color tone from the immediately preceding image may be displayed. In such a case, a difference occurs in the timing of image switching between the first section 29A and a section with a lower drive frequency than the first section 29A, resulting in a significant difference in brightness, contrast, or color tone between the two sections, which may result in a loss of substantial display quality. In such a case, for example, the image in sections other than the first section 29A may be rewritten at the same drive frequency as the first section 29A, and then the drive frequency of the sections other than the first section 29A may be lowered.

[0086] Furthermore, when it is determined that the amount of change in the gaze point G has exceeded a certain amount, the display units other than the display unit corresponding to first section 29A may also rewrite the images at the same drive frequency as the display unit corresponding to first section 29A, and when it is determined that the amount of change is within the certain amount, the drive frequency of the display units other than the display unit corresponding to first section 29A may be reduced. Furthermore, when it is determined that the amount of change in the gaze point G is small, the drive frequency of the display units other than the display unit corresponding to first section 29A may be further reduced.

[0087] The divided display sections that make up the display unit 31 are not limited to the first section 29A, the second section 29B, and the third section 29C. Four or more sections may be set in the display unit 31. By setting multiple sections in the display unit 31 and gradually lowering the drive frequency, it is possible to further reduce the actual degradation of display quality.

[0088] Furthermore, high-speed rewriting can be realized by simultaneously rewriting image data on all divided display sections 31, instead of rewriting image data on each divided display section 31. In other words, high-speed rewriting can be realized by simultaneously rewriting image data on all divided display sections 31, instead of rewriting image data on each divided display section 31.

[0089] In addition, in the display device 100A exemplified in this embodiment, the display unit 31 is divided into eight sections in the column direction (FIGS. 6A to 6C), so the length of the wiring GL electrically connecting the first line driving circuit and the pixel circuit is reduced to one-eighth, which reduces the resistance and parasitic capacitance of the wiring GL to one-eighth, improving signal degradation and delay and making it easier to ensure the time required to rewrite image data.

[0090] According to the display device 100A according to one embodiment of the present invention, the time required for writing image data is short, and thus high-speed rewriting of a display image can be realized. As a result, a display device with high display quality can be realized, and in particular, a display device with excellent moving image display can be realized.

[0091] Furthermore, according to display device 100A of one aspect of the present invention, the output signal output by the first drive circuit can be controlled independently for each divided display section, so that the divided display sections can have different shapes or sizes. That is, display section 31 can be configured with display sections of different shapes or sizes. Therefore, the display section is not limited to a rectangular shape, and can be configured with a circular shape or other shape with excellent design.

[0092] 7 to 9 show configuration examples of pixel circuits applicable to the pixel circuit 51, and light-emitting elements connected to the pixel circuit 51. In the following description, the light-emitting element is not limited to an organic EL element, and may be a self-luminous light-emitting device such as an LED (Light Emitting Diode), a micro LED, a QLED (Quantum-dot Light Emitting Diode), or a semiconductor laser.

[0093] In this specification and the like, the term “element” may be replaced with “device.” For example, a display element and a light-emitting element may be replaced with a display device and a light-emitting device, respectively.

[0094] A pixel circuit 51A shown in Fig. 7A includes a transistor 55A, a transistor 55B, and a capacitor 56. Fig. 7A also shows a light-emitting element 61 connected to the pixel circuit 51A. Fig. 7A also shows a wiring SL, a wiring GL, a power supply line ANO, and a power supply line VCOM.

[0095] The transistor 55A has a gate electrically connected to the wiring GL, one of its source and drain electrically connected to the wiring SL, and the other electrically connected to the gate of the transistor 55B and one electrode of the capacitor 56. The transistor 55B has one of its source and drain electrically connected to the power supply line ANO and the other electrically connected to the anode of the light-emitting element 61. The other electrode of the capacitor 56 is electrically connected to the anode of the light-emitting element 61. The light-emitting element 61 has a cathode electrically connected to the power supply line VCOM. The anode and cathode of the light-emitting element 61 can be switched as needed by changing the magnitude of the potential supplied thereto.

[0096] 7B is a pixel circuit 51B obtained by adding a transistor 55C to the pixel circuit 51A. The transistor 55C has a gate electrically connected to a wiring GL, one of a source and a drain electrically connected to an anode of the light-emitting element 61, and the other electrically connected to a wiring V0.

[0097] A pixel circuit 51C shown in FIG. 7C is an example in which transistors having a pair of gates are used as the transistors 55A and 55B of the pixel circuit 51A. A pixel circuit 51D shown in FIG. 7D is an example in which the same transistors are used in the pixel circuit 51B. This can increase the current that the transistors can pass. Note that, although transistors having a pair of gates are used for all the transistors here, this is not a limitation. Alternatively, a transistor having a pair of gates electrically connected to different wirings may be used. For example, reliability can be improved by using a transistor in which one of the gates is electrically connected to the source.

[0098] 8A has a configuration in which a transistor 55D is added to the pixel circuit 51B. The pixel circuit 51E is electrically connected to three gate lines (a wiring GL1, a wiring GL2, and a wiring GL3).

[0099] The gate of the transistor 55D is electrically connected to a wiring GL3, one of the source and drain of the transistor 55B is electrically connected to the gate of the transistor 55B, and the other is electrically connected to a wiring V0. The gate of the transistor 55A is electrically connected to a wiring GL1, and the gate of the transistor 55C is electrically connected to a wiring GL2.

[0100] By simultaneously turning on transistors 55C and 55D, the source and gate of transistor 55B have the same potential, and when the threshold voltage of transistor 55B is higher than 0 V, transistor 55B can be turned off. This makes it possible to forcibly cut off the current flowing through light-emitting element 61. Such a pixel circuit is suitable for use in a display method in which display periods and off periods are alternately provided.

[0101] 8B is an example in which a capacitor 56A is added to the pixel circuit 51E. The capacitor 56A functions as a storage capacitor.

[0102] 8C and 8D are examples in which transistors each having a pair of gates are applied to the pixel circuit 51E or 51F. Transistors 55A, 55C, and 55D are transistors in which a pair of gates are electrically connected, and transistor 55B is a transistor in which one gate is electrically connected to a source.

[0103] 8A to 8D show examples in which the circuit can be configured using only n-channel OS transistors. However, one embodiment of the present invention is not limited to this. For example, a pixel circuit may include an OS transistor and a Si transistor. Specifically, in the pixel circuit 51A of FIG. 8A, the transistor 55A may be an OS transistor and the transistor 55B may be a Si transistor.

[0104] 9A shows an example of the circuit configuration of a pixel circuit (pixel circuit 51J). FIG. 9B is a diagram schematically showing the hierarchical relationship between a layer 20 including a display unit driving circuit 23, a layer 30 including pixel circuits 51, and a layer 60 including light-emitting elements 61.

[0105] 9A and 9B includes a pixel circuit 51J including a transistor 55A, a transistor 55B, a transistor 55C, and a capacitor 56. The transistors 55A, 55B, and 55C can be OS transistors. Each of the OS transistors 55A, 55B, and 55C preferably includes a back gate electrode. In this case, the back gate electrode can be configured to receive the same signal as the gate electrode, or a signal different from the gate electrode.

[0106] The transistor 55B includes a gate electrode electrically connected to the transistor 55A, a first electrode electrically connected to the light-emitting element 61, and a second electrode electrically connected to the power supply line ANO. The power supply line ANO is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0107] Transistor 55A includes a first electrode electrically connected to the gate electrode of transistor 55B, a second electrode electrically connected to a wiring SL that functions as a source line, and a gate electrode that has the function of controlling the conductive state or non-conductive state based on the potential of wiring GL1 that functions as a gate line.

[0108] The transistor 55C includes a first electrode electrically connected to the wiring V0, a ​​second electrode electrically connected to the light-emitting element 61, and a functional gate electrode that controls the conductive state or non-conductive state based on the potential of the wiring GL2 that functions as a gate line. The wiring V0 is a wiring for applying a reference potential and a wiring for outputting a current flowing through the pixel circuit 51 to the display unit drive circuit 23.

[0109] The capacitor 56 includes a conductive film electrically connected to the gate electrode of the transistor 55B and a conductive film electrically connected to the second electrode of the transistor 55C.

[0110] The light-emitting element 61 includes a first electrode electrically connected to the first electrode of the transistor 55B and a second electrode electrically connected to a power supply line VCOM. The power supply line VCOM is a wiring for applying a potential for supplying a current to the light-emitting element 61.

[0111] This allows the intensity of light emitted by the light-emitting element 61 to be controlled in accordance with an image signal applied to the gate electrode of the transistor 55B. Also, the reference potential of the wiring V0 applied via the transistor 55C can suppress variations in the gate-source potential of the transistor 55B.

[0112] Furthermore, a current value that can be used to set pixel parameters can be output from the wiring V0. More specifically, the wiring V0 can function as a monitor line for outputting to the outside the current flowing through the transistor 55B or the current flowing through the light-emitting element 61. The current output to the wiring V0 may be converted into a voltage by a source follower circuit or the like.

[0113] In the configuration example shown in FIG. 9B , the wiring electrically connecting the pixel circuit 51J and the display unit driver circuit 23 can be shortened, thereby reducing the wiring resistance of the wiring. Furthermore, the parasitic capacitance of the wiring can be reduced. Therefore, data can be written at high speed, allowing the display unit 31 to be driven at high speed. This ensures a sufficient frame period even when the number of pixel circuits 51 is increased, thereby increasing the pixel density of the display unit 31. Furthermore, increasing the pixel density of the display unit 31 can improve the resolution of images displayed on the display unit 31. For example, the pixel density of the display unit 31 can be set to 1,000 ppi or more, 5,000 ppi or more, or 7,000 ppi or more. Therefore, the display device 100A can be used, for example, as a display device for xR (xR) such as AR or VR. The display device 100A according to one embodiment of the present invention can be suitably applied to electronic devices, such as HMDs, in which the display unit is close to the user.

[0114] As described above, the display device 100A of one embodiment of the present invention has a stacked structure including a layer including the display portion 31 and the memory portion 11, and a layer including the functional circuit 90. Stacking the layers including the circuits enables the miniaturization of the display device 100A. Furthermore, providing the display portion driver circuit 23 overlapping the display portion 31 allows the width of the frame around the display portion 31 to be significantly narrowed, thereby increasing the area of ​​the display portion 31. Therefore, the resolution of the display portion 31 can be increased. Therefore, the display quality of the display device 100A can be improved.

[0115] Furthermore, when the resolution of the display unit 31 is constant, the occupied area per pixel can be increased. This allows for increased luminance of the display unit 31. This also allows for increased aperture ratio of the pixel. For example, the aperture ratio of the pixel can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, by increasing the occupied area per pixel, the current density supplied to the pixel can be reduced. This reduces the load on the pixel, thereby improving the reliability of the display device 100A.

[0116] Furthermore, by stacking the layer having the display unit 31 and the memory unit 11 and the layer having the functional circuit 90, the wiring electrically connecting them can be shortened. This reduces the wiring resistance and parasitic capacitance, and increases the operating speed of the display device 100A. Furthermore, the power consumption of the display device 100A is reduced.

[0117] 10A is a schematic diagram illustrating the connection relationship between the memory unit driving circuit 24 and the memory unit 11. As described above, in one aspect of the present invention, the memory unit driving circuit 24 and the memory unit 11 are provided on different layers, so that the memory unit 11 can be provided on the memory unit driving circuit 24.

[0118] The memory section drive circuit 24 includes a first drive circuit 35 and a second drive circuit 36. The circuit included in the first drive circuit 35 functions as, for example, a word line drive circuit or a row circuit. The circuit included in the second drive circuit 36 ​​functions as, for example, a bit line drive circuit or a column circuit. The first drive circuit 35 is electrically connected to the memory cells 12 of the memory section 11 provided above it via word lines WL. Note that there may be multiple word lines WL, such as a word line WWL for writing data and a word line RWL for reading data. The second drive circuit 36 ​​is electrically connected to the memory cells 12 of the memory section 11 provided above it via bit lines BL. Note that there may be multiple bit lines BL, such as a bit line WBL for writing data and a bit line RBL for reading data.

[0119] The first drive circuit 35 has a function of selecting a row to be accessed. For example, the first drive circuit 35 has a row decoder and a word line driver. The second drive circuit 36 ​​has functions such as precharging the bit lines BL, writing data to the bit lines BL, amplifying data on the bit lines BL, and reading data from the bit lines BL. The memory unit drive circuit 24 also has an input / output circuit as another circuit. The input / output circuit has functions such as holding data to be written and holding read data.

[0120] By stacking the memory unit 11 and the memory unit drive circuit 24, the connection distance (wiring length) between the memory cell and the memory unit drive circuit can be made extremely short. As a result, wiring resistance and parasitic capacitance are reduced, which shortens the time required for charging and discharging, enabling high-speed driving. In addition, power consumption can be reduced. Furthermore, miniaturization and weight reduction can be achieved. In addition, the integration degree of the memory cell array can be increased.

[0121] In the memory unit drive circuit 24, the first drive circuit 35 or the second drive circuit 36 ​​does not have to be located in an area overlapping with the memory unit 11. For example, the first drive circuit 35 or the second drive circuit 36 ​​may be located in an area overlapping with the display unit 31. Figure 10B illustrates a state in which, in the memory unit drive circuit 24, the first drive circuit 35 is provided in an area overlapping with the memory unit 11, and the second drive circuit 36 ​​is provided in an area not overlapping with the memory unit 11.

[0122] 11A to 11H, memory cells 12A to 12H shown in FIGS. 11A to 11H are memory cells using OS transistors, and can be roughly classified as NOSRAMs (non-stable random access memory) and DOSRAMs (dot-storage random access memory).

[0123] 11A shows an example of a circuit configuration applicable to the memory cell 12. Here, the memory cell 12A is a two-transistor (2T) gain cell. The memory cell 12A includes transistors MW1 and MR1 and a capacitor CS1. The transistor MW1 is a write transistor, and the transistor MR1 is a read transistor. The back gates of the transistors MW1 and MR1 are electrically connected to a wiring BGL.

[0124] Since the read transistor is an OS transistor, the memory cell 12A does not consume power to retain data. Therefore, the memory cell 12A is a low-power memory cell that can retain data for a long period of time, and the storage unit 11 can be used as a nonvolatile storage device.

[0125] The memory cell 12B shown in FIG. 11B is a 3T-type gain cell and includes transistors MW2, MR2, MS2, and a capacitor CS2. The transistors MW2, MR2, and MS2 are a write transistor, a read transistor, and a select transistor, respectively. The back gates of the transistors MW2, MR2, and MS2 are electrically connected to a wiring BGL. The memory cell 12B is electrically connected to word lines RWL and WWL, bit lines RBL and WBL, a capacitor line CDL, and a power supply line PL2. For example, a voltage GND (low-level power supply voltage) is input to the capacitor line CDL and the power supply line PL2.

[0126] 11C and 11D show other configuration examples of a 2T-type gain cell. In a memory cell 12C shown in FIG. 11C, the read transistor is an n-channel Si transistor. In a memory cell 12C shown in FIG. 11D, the read transistor is a p-channel Si transistor. As shown in FIGS. 11C and 11D, a configuration in which an OS transistor and a Si transistor are combined as transistors in a memory cell may also be used.

[0127] Since metal oxides used in OS transistors are n-type (n-channel) metal oxides, such as In—Ga—Zn oxide, a complementary metal oxide semiconductor (CMOS) circuit can be formed by combining an OS transistor with a Si transistor to form a memory cell. Therefore, compared with a memory cell formed solely with n-channel transistors, a circuit having both high driving capability due to the use of Si transistors and low power consumption due to the low off-state current of the OS transistor can be realized. Furthermore, since there is no need to separately fabricate n-type (n-channel) and p-type (p-channel) Si transistors, the process cost of the transistors can be reduced.

[0128] 11E and 11F show other configuration examples of a 3T gain cell. In a memory cell 12E shown in FIG. 11E, the read transistor and the select transistor are configured as n-channel Si transistors. In a memory cell 12F shown in FIG. 11F, the read transistor and the select transistor are configured as p-channel Si transistors. In the example of FIG. 11F, a voltage Vdd (high-level power supply voltage) is input to the power supply line PL2.

[0129] In the above gain cell, a bit line that serves as both a read bit line RBL and a write bit line WBL may be provided.

[0130] 11G and 11H show examples of a 1T1C (capacitor) type memory cell. A memory cell 12G shown in FIG. 11G is electrically connected to a word line WL, a bit line BL, a capacitance line CDL, and a wiring BGL. The memory cell 12G has a transistor MW3 and a capacitance CS3. The back gate of the transistor MW3 is electrically connected to the wiring BGL. Also, the memory cell 12H shown in FIG. 11H illustrates the configuration of a ferroelectric memory using a capacitance FE1 having a ferroelectric material in the capacitance CS3. For example, HfZrO Ｘ can be used.

[0131] The circuit configuration of the memory cell 12 in the storage unit 11 can be a circuit configuration including only OS transistors, a circuit configuration including a combination of OS transistors and Si transistors, or the like.

[0132] 12A shows an example of the circuit configuration of a memory cell (memory cell 12E). FIG. 12B is a diagram schematically showing the hierarchical relationship between layer 20 including memory unit drive circuit 24, layer 30 including memory cells 12, and layer 60. Note that in memory unit 11 in which memory cell 12E is provided, the configuration of layer 60 is not shown, but layer 60 may be provided with a light-emitting element 61, for example.

[0133] 12A and 12B , an example of a memory cell 12E includes transistors MW2, MR2, and MS2, and a capacitor CS2. The transistor MW2 can be configured as an OS transistor, and the transistors MR2 and MS2 can be configured as Si transistors. That is, as shown in FIG. 12B , the transistors MR2 and MS2 are provided in layer 20, and the transistor MW2 is provided in layer 30. Although the capacitor CS2 is illustrated in layer 30, it may also be provided in layer 20. Furthermore, although the wiring (word lines RWL, WWL, bit lines RBL, WBL) and the like are illustrated in layer 20, they may also be provided in layer 30.

[0134] 12B, memory cells 12E including OS transistors and Si transistors can be provided in layers 20 and 30. FIG. 13A is a schematic diagram illustrating the connection relationship between first drive circuit 35 and second drive circuit 36 ​​included in memory unit drive circuit 24 and memories 11A and 11B including memory cells provided in layers 20 and 30.

[0135] 13A, memory unit 11A is provided in layer 30 and is an area where circuit 13A, which corresponds to part of memory cell 12E, is provided. Memory unit 11B is provided in layer 20 and is an area where circuit 13B, which corresponds to part of memory cell 12E, is provided. Memory unit 11A and memory unit 11B together correspond to memory unit 11 described above. Circuit 13A and circuit 13B together correspond to memory cell 12E described above. In layer 20, first drive circuit 35 and second drive circuit 36 ​​may be provided in an area overlapping memory unit 11A as shown in FIG. 13A, or may be provided in an area overlapping memory unit 11A.

[0136] A configuration in which the circuits 13A and 13B are provided in different layers, i.e., layer 20 and layer 30, is described with reference to a schematic diagram shown in FIG. 13B. In the memory cell 12E having an OS transistor and a Si transistor, the transistors are provided separately from each other because wiring is used to connect the different layers, compared to when the transistors are provided in the same layer. Therefore, the parasitic capacitance at the node MN in FIG. 13B (the parasitic capacitance with the power supply line ANO is shown in FIG. 13B) can be made large, and the capacitance CS2 (shown by the dotted line in the figure) can be omitted.

[0137] 14A is a block diagram of the configuration of a display device 100A_2 in which the memory unit 11A and the memory unit 11B described in FIGS. 12A to 13B are provided in different layers. Also, FIG. 14B is a perspective view corresponding to the block diagram of the display device 100A_2 shown in FIG. 14A , and similarly to FIG. 2 , layers 20, 30, 60, and the sealing substrate 40 are shown separated to make the configuration of the display device 100A_2 easier to understand. Note that although the circuits 13A and 13B included in the memory units 11A and 11B are shown in regions different from the pixels 50 included in the display unit 31, they may be provided within the pixel circuits 51 as shown in FIG. 4 .

[0138] In a display device according to one embodiment of the present invention, a memory portion including an OS transistor and a display portion includes a memory cell using an OS transistor, such as a non-single-mode random access memory (NSRAM) or a double-sided static random access memory (DOSRAM). Therefore, compared with a memory cell including a Si transistor, such as a static RAM (SRAM), the memory cell can be arranged in a layer different from a circuit using a Si transistor, such as a display driver circuit or a memory driver circuit.

[0139] In one embodiment of the present invention, a storage unit including memory cells using OS transistors can be configured with memory cells having fewer transistors than an SRAM, and a circuit configuration combining OS transistors and Si transistors can be used. Furthermore, multi-level data can be stored. This allows for a large amount of data to be stored, enabling image data for multiple frames to be held. Therefore, the storage unit can be used as a frame memory capable of storing a large amount of image data. As a result, the display device of one embodiment of the present invention can be configured to hold image data for multiple frame periods. In this case, the amount of image data transferred from an external circuit to the display device can be reduced, thereby simplifying a display system including the display device.

[0140] In this embodiment, a modified example of a display device according to one embodiment of the present invention will be described. Note that in this embodiment, repeated description of components having the same reference numerals as those in the above embodiment may be omitted.

[0141] <Modification 1> Figures 15A and 16 are perspective views of a display device 100B according to one embodiment of the present invention. Figure 15B is a block diagram illustrating the configuration of display device 100B. Display device 100B includes a layer 10 on layer 20, a layer 30 on layer 10, and a sealing substrate 40 on layer 30. Layer 30 includes a display unit 31, and a layer 60 is provided between the sealing substrate 40 and the display unit 31. Layer 10 also includes a memory unit 11. In Figure 16, layers 20, 30, 60, and sealing substrate 40 are shown separated from one another to make the configuration of display device 100B easier to understand.

[0142] The description of the layer 20 is the same as that in the first embodiment.

[0143] The memory unit 11 provided in the layer 10 includes a plurality of memory cells 12. In the configuration of the display device 100B, the display unit and the memory unit are provided in different layers, that is, the layer 10 and the layer 30, respectively. This allows the display unit 31 to have a larger area and the memory unit 11 to have a larger capacity. Note that although the memory cells 12 included in the memory unit 11 and the pixel circuits 51 included in the display unit 31 are provided in different layers, they both include OS transistors.

[0144] In one embodiment of the present invention, the storage portion 11 can be provided in a layer 10 that is different from the layer 30 in which the display portion 31 is provided. This increases the storage capacity and the display area of ​​the display device 100B. The storage portion 11 can be used as a frame memory by storing image data output from an external circuit.

[0145] As described above, the display device 100B of one embodiment of the present invention has a stacked structure including a layer including the display portion 31, a layer including the memory portion 11, and a layer including the functional circuit 90. Stacking the layers including the circuits can reduce the size of the display device 100B. Furthermore, the display portion driver circuit 23 can be provided overlapping the display portion 31, thereby increasing the area of ​​the display portion 31. Therefore, the resolution of the display portion 31 can be increased, and the display quality of the display device 100B can be improved.

[0146] Furthermore, by stacking the layer having the display unit 31, the layer having the memory unit 11, and the layer having the functional circuit 90, the wiring electrically connecting them can be shortened. This reduces the wiring resistance and parasitic capacitance, and increases the operating speed of the display device 100B. Furthermore, the power consumption of the display device 100B is reduced.

[0147] <Modification 2> FIGS. 17A and 18 are perspective views of a display device 100C according to one embodiment of the present invention. In a display device according to one embodiment of the present invention, the stacking order of the layers can be changed depending on the purpose or application. FIG. 17B is a block diagram illustrating the configuration of the display device 100C. The display device 100C includes a layer 30 on a layer 20, a layer 10 on the layer 30, and a sealing substrate 40 on the layer 10. The layer 30 includes a display unit 31, and a layer 60 is provided between the sealing substrate 40 and the memory unit 11. The layer 10 includes the memory unit 11. In FIG. 16, the layers 20, 30, 60, and the sealing substrate 40 are shown separated from one another to make the configuration of the display device 100C easier to understand.

[0148] The description of the layer 20 is the same as that in the first embodiment.

[0149] The display unit 31 in the layer 30 is provided separately from the layer 60 having light-emitting elements, with the memory unit 11 in the layer 10 interposed therebetween. Therefore, wiring is provided in the memory unit 11 to connect the memory unit 11 in the layer 10 with the light-emitting elements of the layer 60. The wiring increases parasitic capacitance in the memory cells 12 in the memory unit 11. By using parasitic capacitance in the memory cells, other capacitances can be reduced. As a result, the area of ​​the display unit 31 can be increased, and the capacity of the memory unit 11 can be increased. Note that although the memory cells 12 in the memory unit 11 and the pixel circuits 51 in the display unit 31 are provided in different layers, they both include OS transistors.

[0150] In one embodiment of the present invention, the storage unit 11 can be provided in a layer 10 that is different from the layer 30 in which the display unit 31 is provided. This increases the storage capacity and the display area of ​​the display device 100C. The storage unit 11 can be used as a frame memory by storing image data output from an external circuit.

[0151] As described above, the display device 100C of one embodiment of the present invention has a stacked structure including a layer including the display portion 31, a layer including the memory portion 11, and a layer including the functional circuit 90. Stacking the layers including the circuits can reduce the size of the display device 100C. Furthermore, the display portion driver circuit 23 can be provided overlapping the display portion 31, thereby increasing the area of ​​the display portion 31. Therefore, the resolution of the display portion 31 can be increased, and the display quality of the display device 100C can be improved.

[0152] Furthermore, by providing a layer having the memory portion 11 between a layer having the display portion 31 and a layer having a light-emitting element, it is possible to increase the parasitic capacitance in the memory cell 12 included in the memory portion 11. Therefore, by using the parasitic capacitance in the memory cell, it is possible to reduce other capacitances.

[0153] 19 is a block diagram illustrating a configuration of a display device 100D according to one embodiment of the present invention. Display device 100D has a configuration in which a storage unit 39 is added to layer 20 in addition to the configuration of display device 100A described in the first embodiment.

[0154] The memory unit 39 included in the layer 20 includes memory cells formed of Si transistors, such as SRAM memory cells. That is, the display device 100D includes the memory unit 39 included in the layer 20 including Si transistors, in addition to the memory unit 11 included in the layer 30 including the OS transistors described in Embodiment 1.

[0155] This configuration allows the storage unit 11 and the storage unit 39 to be used in a switchable manner when functioning as a frame memory. For example, image data to be displayed at a high frame frequency is stored in the storage unit 39 having an SRAM, and image data to be displayed at a low frame frequency is stored in the storage unit 11 having memory cells using OS transistors.

[0156] 20A is a block diagram illustrating the configuration of the storage unit 11 and storage unit 39 that can be used as a frame memory. Illustrated in FIG. 20A are an external circuit 80 that processes image data, such as a CPU or GPU, a control circuit 21, the storage unit 11, the storage unit 39, the display unit drive circuit 23, and the display unit 31.

[0157] As described above, in one embodiment of the present invention, image data output from external circuit 80 can be stored in control circuit 21, divided between storage unit 39 and storage unit 11, depending on the frame frequency. Therefore, display device 100D can be configured to perform display with the added advantage of storage unit 39, which can speed up writing and reading of image data, in addition to the advantage of increased frame memory capacity achieved by providing storage unit 11.

[0158] As described in the above embodiment, a memory cell using an OS transistor can store analog values. Therefore, by storing analog data provided to a pixel circuit as data stored in the memory cell, image data can be directly provided to the display unit 31 from the storage unit 11. An example of a block diagram in this case is shown in FIG. 20B .

[0159] By providing the storage unit 11 that functions as a frame memory for storing analog values ​​in this manner, it is possible to omit the process of converting digital image data into analog image data, which is performed by the display unit drive circuit 23. This makes it possible to reduce the circuit scale of the display unit drive circuit 23. Furthermore, by providing the storage unit 39, it is possible to speed up the writing and reading of image data.

[0160] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be combined as appropriate with other configuration examples or drawings.

[0161] Embodiment 3 In this embodiment, a structural example of a display module to which a display device of one embodiment of the present invention can be applied will be described.

[0162] The display device of this embodiment can be a high-resolution display panel. For example, the display device of one embodiment of the present invention can be used for a display portion of a wristwatch-type or bracelet-type information terminal (wearable device), a VR device such as a head-mounted display, or a head-mountable wearable device such as a glasses-type AR device.

[0163] 21A shows a perspective view of a display module 980. The display module 980 has a display device 200A and an FPC 990. Note that the display panel of the display module 980 is not limited to the display device 200A, and may be a display device 200B described later.

[0164] The display module 980 includes a substrate 991 and a substrate 992. The display module 980 includes a display portion 981. The display portion 981 is a region for displaying an image.

[0165] 21B is a perspective view schematically illustrating the configuration on the substrate 991 side. A circuit portion 982, a display portion 983 on the circuit portion 982, and a pixel portion 984 on the display portion 983 are stacked on the substrate 991. A terminal portion 985 for connecting to an FPC 990 is provided in a portion of the substrate 991 that does not overlap with the pixel portion 984. The terminal portion 985 and the circuit portion 982 are electrically connected by a wiring portion 986 composed of a plurality of wirings.

[0166] The layer including the circuit portion 982 can be applied with circuits having each structure included in the layer 10 described in Embodiment 1 or the like. In addition to the pixel circuit 983a, circuits included in the memory portion or the like included in the layer 30 described in Embodiment 1 or the like can be applied to the layer including the display portion 983. By appropriately increasing the number of layers provided with elements, circuits having each structure included in the layer 20 described in Embodiment 1 or the like can be applied.

[0167] The pixel portion 984 has a plurality of periodically arranged pixels 984a. An enlarged view of one pixel 984a is shown on the right side of Fig. 21B. The pixel 984a has a light-emitting device 410R that emits red light, a light-emitting device 410G that emits green light, and a light-emitting device 410B that emits blue light.

[0168] The display portion 983 includes a plurality of pixel circuits 983a arranged periodically. Each pixel circuit 983a controls light emission of three light-emitting devices included in one pixel 984a. As described in Embodiment 1, a memory portion (not shown) may be provided in the layer where the display portion 983 is provided. Alternatively, the pixel circuit 983a may include a memory cell (not shown) included in the memory portion. Each pixel circuit 983a may include three circuits for controlling light emission of one light-emitting device. For example, the pixel circuit 983a may include at least one selection transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting device. A gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This achieves an active matrix display panel.

[0169] The circuit portion 982 includes a circuit for driving each pixel circuit 983a in the display portion 983. For example, it preferably includes one or both of a gate line driver circuit and a source line driver circuit. In addition, the circuit portion 982 may include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like. Furthermore, a transistor provided in the circuit portion 982 may constitute part of the pixel circuit 983a. That is, the pixel circuit 983a may be configured using a transistor included in the display portion 983 and a transistor included in the circuit portion 982.

[0170] The FPC 990 functions as wiring for supplying a video signal, a power supply potential, and the like from the outside to the circuit portion 982. An IC may be mounted on the FPC 990.

[0171] The display module 980 can have a structure in which a layer having a display portion 983 and a layer having a circuit portion 982 are stacked below the pixel portion 984, thereby enabling the aperture ratio (effective display area ratio) of the display portion 981 to be extremely high. For example, the aperture ratio of the display portion 981 can be 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixels 984a can be arranged at extremely high density, enabling the resolution of the display portion 981 to be extremely high. For example, it is preferable that the pixels 984a be arranged in the display portion 981 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20,000 ppi or less, or 30,000 ppi or less.

[0172] Because such a display module 980 has extremely high resolution, it can be suitably used in VR devices such as head-mounted displays or glasses-type AR devices. For example, even in a configuration in which the display unit of the display module 980 is viewed through lenses, the display module 980 has an extremely high-resolution display unit 981, so that even when the display unit is enlarged with lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 980 is not limited to this, and can be suitably used in electronic devices having relatively small display units. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0173] [Display Device 200A] A display device 200A shown in FIG. 22 has a stacked structure of a transistor 810 in which a channel is formed in a substrate 801 and a transistor 820 in which a channel is formed and a semiconductor layer containing metal oxide.

[0174] Substrate 801 corresponds to substrate 991 in FIGS. 21A and 21B.

[0175] The transistor 810 has a channel formation region in a substrate 801. The substrate 801 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 810 includes a part of the substrate 801, a conductive layer 811, a low-resistance region 812, an insulating layer 813, and an insulating layer 814. The conductive layer 811 functions as a gate electrode. The insulating layer 813 is located between the substrate 801 and the conductive layer 811 and functions as a gate insulating layer. The low-resistance region 812 is a region in which the substrate 801 is doped with impurities and functions as one of a source and a drain. The insulating layer 814 is provided to cover a side surface of the conductive layer 811.

[0176] An element isolation layer 815 is provided between two adjacent transistors 810 so as to be buried in the substrate 801 .

[0177] An insulating layer 961 is provided to cover the transistor 810, and a conductive layer 951 is provided over the insulating layer 961. An insulating layer 962 is provided to cover the conductive layer 951, and a conductive layer 952 is provided over the insulating layer 962. The conductive layer 951 and the conductive layer 952 each function as a wiring. An insulating layer 963 and an insulating layer 832 are provided to cover the conductive layer 952, and the transistor 820 is provided over the insulating layer 832.

[0178] The transistor 820 is a transistor (OS transistor) in which a metal oxide (also referred to as an oxide semiconductor) is used for a semiconductor layer in which a channel is formed.

[0179] The transistor 820 includes a semiconductor layer 821 , an insulating layer 823 , a conductive layer 824 , a pair of conductive layers 825 , an insulating layer 826 , and a conductive layer 827 .

[0180] An insulating layer 832 is provided over the insulating layer 963. The insulating layer 832 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 963 to the transistor 820 and prevents oxygen from being released from the semiconductor layer 821 toward the insulating layer 832. The insulating layer 832 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0181] A conductive layer 827 is provided over the insulating layer 832, and an insulating layer 826 is provided to cover the conductive layer 827. The conductive layer 827 functions as a first gate electrode of the transistor 820, and part of the insulating layer 826 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 826 that is in contact with the semiconductor layer 821. The top surface of the insulating layer 826 is preferably planarized.

[0182] The semiconductor layer 821 is provided over the insulating layer 826. The semiconductor layer 821 preferably includes a metal oxide (also referred to as an oxide semiconductor) film exhibiting semiconductor characteristics. A pair of conductive layers 825 is provided over and in contact with the semiconductor layer 821 and functions as a source electrode and a drain electrode.

[0183] An insulating layer 828 is provided to cover top surfaces and side surfaces of the pair of conductive layers 825 and side surfaces of the semiconductor layer 821, and an insulating layer 964 is provided over the insulating layer 828. The insulating layer 828 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 964 or the like to the semiconductor layer 821 and prevents oxygen from being released from the semiconductor layer 821. The insulating layer 828 can be an insulating film similar to the insulating layer 832.

[0184] An opening reaching the semiconductor layer 821 is provided in the insulating layer 828 and the insulating layer 964. An insulating layer 823 in contact with the top surface of the semiconductor layer 821 and a conductive layer 824 are buried in the opening. The conductive layer 824 functions as a second gate electrode, and the insulating layer 823 functions as a second gate insulating layer.

[0185] The top surface of the conductive layer 824, the top surface of the insulating layer 823, and the top surface of the insulating layer 964 are planarized so that their heights are the same or approximately the same, and insulating layers 829 and 965 are provided to cover them.

[0186] The insulating layers 964 and 965 function as interlayer insulating layers. The insulating layer 829 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 965 or the like to the transistor 820. The insulating layer 829 can be formed using an insulating film similar to the insulating layers 828 and 832.

[0187] A plug 974 electrically connected to one of the pair of conductive layers 825 is provided to be embedded in the insulating layer 965, the insulating layer 829, and the insulating layer 964. Here, the plug 974 is preferably configured such that the side surfaces of the openings in the insulating layer 965, the insulating layer 829, the insulating layer 964, and the insulating layer 828 and part of the top surface of the conductive layer 825 are covered with the conductive layer. In this case, the conductive layer covering the plug 974 is preferably made of a conductive material through which hydrogen and oxygen do not easily diffuse.

[0188] A capacitor 840 is provided on the insulating layer 965. The capacitor 840 and the transistor 820 are electrically connected by a plug 974.

[0189] The transistor 820 can be used as a transistor that forms a pixel circuit. The transistor 810 can be used as a transistor that forms a pixel circuit or a transistor that forms a driver circuit (gate line driver circuit, source line driver circuit) for driving the pixel circuit. The transistors 810 and 820 can be used as transistors that form various circuits such as memory cells.

[0190] The capacitor 840 has a conductive layer 941, a conductive layer 945, and an insulating layer 943 located therebetween. The conductive layer 941 functions as one electrode of the capacitor 840, the conductive layer 945 functions as the other electrode of the capacitor 840, and the insulating layer 943 functions as a dielectric of the capacitor 840.

[0191] The conductive layer 941 is provided over the insulating layer 965 and is buried in the insulating layer 954. The conductive layer 941 is electrically connected to one of the source and the drain of the transistor 820 by a plug 974 buried in the insulating layer 965. The insulating layer 943 is provided to cover the conductive layer 941. The conductive layer 945 is provided in a region overlapping with the conductive layer 941 with the insulating layer 943 interposed therebetween.

[0192] An insulating layer 955a is provided to cover the capacitor 840, an insulating layer 955b is provided over the insulating layer 955a, and an insulating layer 955c is provided over the insulating layer 955b.

[0193] An inorganic insulating film can be preferably used for each of the insulating layers 955a, 955b, and 955c. For example, it is preferable to use a silicon oxide film for the insulating layer 955a and the insulating layer 955c, and a silicon nitride film for the insulating layer 955b. This allows the insulating layer 955b to function as an etching protection film. In this embodiment, an example is shown in which part of the insulating layer 955c is etched to form a recess, but the insulating layer 955c does not necessarily have to have a recess.

[0194] The light emitting device 410R, the light emitting device 410G, and the light emitting device 410B are provided on the insulating layer 955c.

[0195] In the display device 200A, a separate light-emitting device is fabricated for each emitted color, resulting in minimal change in chromaticity between low-luminance and high-luminance emission. Furthermore, because the organic layers 412R, 412G, and 412B are spaced apart from one another, crosstalk between adjacent subpixels can be suppressed even in a high-resolution display panel. This allows for the realization of a high-resolution, high-quality display panel.

[0196] In the region between adjacent light emitting devices, an insulating layer 425, a resin layer 426, and a layer 428 are provided.

[0197] The pixel electrodes 411R, 411G, and 411B of the light-emitting device are electrically connected to one of the source and drain of the transistor 810 via a plug 956 embedded in insulating layers 955a, 955b, and 955c, a conductive layer 941 embedded in insulating layer 954, and a plug 971 embedded in insulating layer 961. The height of the top surface of the insulating layer 955c and the height of the top surface of the plug 956 are the same or approximately the same. Various conductive materials can be used for the plug.

[0198] A protective layer 421 is provided on the light-emitting devices 410R, 410G, and 410B. A substrate 470 is attached to the protective layer 421 with an adhesive layer 471.

[0199] No insulating layer covering the upper end of each pixel electrode 411 is provided between two adjacent pixel electrodes 411. This allows the distance between adjacent light-emitting devices to be extremely narrow, resulting in a high-definition or high-resolution display device.

[0200] With this configuration, not only pixel circuits but also driving circuits etc. can be formed directly below the light-emitting device, which makes it possible to make the display panel smaller than when driving circuits are provided around the periphery of the display area.

[0201] 23 has a stacked structure of a transistor 820A containing a metal oxide in a semiconductor layer in which a channel is formed and a transistor 820B containing a metal oxide in a semiconductor layer in which a channel is formed. This structure allows the use of transistors in which the metal oxide in the semiconductor layer has a different composition of constituent elements. Therefore, a display device using OS transistors with different transistor characteristics can be provided. For example, the upper transistor 820A can be used as a transistor in a pixel circuit that drives a light-emitting device, and the lower transistor 820B can be used as a transistor in a memory cell.

[0202] This configuration allows the circuits located directly below the light-emitting device to be arranged more densely, making it possible to make the display panel smaller than when the driving circuits are located around the periphery of the display area.

[0203] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes described in this specification.

[0204] Embodiment 4 In this embodiment, electronic devices to which a display device according to one embodiment of the present invention can be applied will be described.

[0205] A display device according to one embodiment of the present invention can be applied to a display portion of an electronic device. Therefore, an electronic device with high display quality, extremely high resolution, or high reliability can be realized.

[0206] Examples of electronic devices using a display device according to one embodiment of the present invention include display devices such as televisions and monitors, lighting devices, desktop or notebook personal computers, word processors, and DVD (Digital Versatile Examples of such equipment include image playback devices that play back still images or videos stored on recording media such as a CD (disc), portable CD players, radios, tape recorders, headphone stereos, stereos, table clocks, wall clocks, cordless telephone handsets, transceivers, car phones, mobile phones, personal digital assistants, tablet terminals, portable game machines, fixed game machines such as pachinko machines, calculators, electronic organizers, e-book terminals, electronic translators, voice input devices, video cameras, digital still cameras, electric shavers, high-frequency heating devices such as microwave ovens, air conditioning equipment such as electric rice cookers, electric washing machines, electric vacuum cleaners, hot water heaters, electric fans, hair dryers, air conditioners, humidifiers, and dehumidifiers, dishwashers, dish dryers, clothes dryers, futon dryers, electric refrigerators, electric freezers, electric refrigerator-freezers, DNA storage freezers, flashlights, and tools such as chainsaws, smoke detectors, and medical equipment such as dialysis machines. Further examples include industrial equipment such as emergency lights, traffic lights, conveyor belts, elevators, escalators, industrial robots, power storage systems, and power storage devices for power leveling and smart grids. Mobile bodies propelled by fuel-powered engines or electric motors powered by power from power storage devices may also be included in the category of electronic devices. Examples of such mobile bodies include electric vehicles (EVs), hybrid electric vehicles (HEVs) equipped with both internal combustion engines and electric motors, plug-in hybrid electric vehicles (PHEVs), tracked vehicles in which the tires and wheels of these vehicles are replaced with tracks, mopeds including electrically assisted bicycles, motorcycles, electric wheelchairs, golf carts, small or large ships, submarines, helicopters, aircraft, rockets, artificial satellites, space probes, planetary probes, and spaceships.

[0207] An electronic device according to one embodiment of the present invention may include a secondary battery (battery), and it is preferable that the secondary battery can be charged using contactless power transmission.

[0208] Examples of secondary batteries include lithium ion secondary batteries, nickel-metal hydride batteries, nickel-cadmium batteries, organic radical batteries, lead-acid batteries, air secondary batteries, nickel-zinc batteries, and silver-zinc batteries.

[0209] An electronic device according to one embodiment of the present invention may include an antenna. By receiving a signal through the antenna, images, information, and the like can be displayed on a display portion. When the electronic device includes an antenna and a secondary battery, the antenna may be used for contactless power transmission.

[0210] An electronic device according to one embodiment of the present invention may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0211] An electronic device according to one embodiment of the present invention can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read programs or data recorded on a recording medium, etc.

[0212] Furthermore, electronic devices having multiple display units can have a function of mainly displaying image information on one part of the display units and mainly displaying text information on another part, or a function of displaying a stereoscopic image by displaying an image taking into account parallax on the multiple display units. Furthermore, electronic devices having an image receiving unit can have a function of capturing a still image or a video, a function of automatically or manually correcting the captured image, a function of storing the captured image in a recording medium (external or built in the electronic device), a function of displaying the captured image on the display unit, etc. Note that the functions of the electronic device of one embodiment of the present invention are not limited to these, and can have various functions.

[0213] A display device according to one embodiment of the present invention can display high-resolution images. Therefore, the display device can be suitably used in portable electronic devices, wearable electronic devices, e-book readers, etc. For example, the display device can be suitably used in xR devices such as VR devices and AR devices.

[0214] 24A shows the appearance of a head-mounted display 710. The head-mounted display 710 includes a mounting portion 711, a lens 712, a main body 713, a display portion 714, a cable 715, and the like. A battery 716 is built into the mounting portion 711. A display device according to one embodiment of the present invention can be applied to the display portion 714.

[0215] A cable 715 supplies power from a battery 716 to the main body 713. The main body 713 is equipped with a wireless receiver and the like, and can display received video information such as image data on a display unit 714. In addition, a camera provided in the main body 713 captures the movement of the user's eyeballs and / or eyelids, and calculates the user's line of sight based on the information, thereby enabling the user's line of sight to be used as an input means.

[0216] The attachment unit 711 may also be provided with a plurality of electrodes at positions that come into contact with the user. The main body 713 may have a function of recognizing the user's line of sight by detecting current flowing through the electrodes in accordance with the movement of the user's eyeballs. The main body 713 may also have a function of monitoring the user's pulse by detecting the current flowing through the electrodes. The attachment unit 711 may also have various sensors such as a temperature sensor, a pressure sensor, an acceleration sensor, etc., and may have a function of displaying the user's biological information on the display unit 714. The attachment unit 711 may also detect the movement of the user's head, and change the image displayed on the display unit 714 in accordance with the movement.

[0217] 24B shows the appearance of the head-mounted display 720. The head-mounted display 720 is a goggle-type information processing device.

[0218] The head-mounted display 720 includes a housing 721, operation buttons 723, a band-shaped fixture 724, and two display units 722. The two display units 722 allow the user to view one display unit per eye. This allows high-resolution images to be displayed even when performing 3D display using parallax. The fixture 724 is also provided with a battery 725. While the battery 725 may be provided in the housing 721, providing the battery 725 in the fixture 724 is preferable because it allows the center of gravity of the head-mounted display 720 to be positioned rearward, improving the wearing comfort for the user. In addition to the battery 725, a drive circuit for operating the display units 722 may be provided in the fixture 724 to adjust the center of gravity of the head-mounted display 720.

[0219] The operation button 723 has a function of a power button, etc. In addition to the operation button 723, other buttons may be provided.

[0220] A display device according to one embodiment of the present invention can be applied to the display portion 722. The display device according to one embodiment of the present invention has extremely high definition, and therefore, pixels are less visible to a user, and more realistic images can be displayed.

[0221] FIG. 24C shows the exterior of camera 730 with viewfinder 740 .

[0222] The camera 730 includes a housing 731, a display portion 732, operation buttons 733, a shutter button 734, and the like. A detachable lens 736 is attached to the camera 730.

[0223] Here, the camera 730 has a structure in which the lens 736 can be detached from the housing 731 and replaced, but the lens 736 and the housing may be integrated.

[0224] The camera 730 can capture an image by pressing a shutter button 734. The display portion 732 also functions as a touch panel, and an image can be captured by touching the display portion 732.

[0225] The housing 731 of the camera 730 has a mount with electrodes, and can be connected to a finder 740 as well as a strobe device and the like.

[0226] The finder 740 includes a housing 741, a display portion 742, a button 743, and the like.

[0227] The housing 741 has a mount that engages with the mount of the camera 730, and the viewfinder 740 can be attached to the camera 730. The mount also has electrodes, and images received from the camera 730 can be displayed on the display unit 742 via the electrodes.

[0228] The button 743 functions as a power button, and can be used to switch the display of the display unit 742 on and off.

[0229] The display device according to one embodiment of the present invention can be applied to the display portion 732 of the camera 730 and the display portion 742 of the finder 740 .

[0230] Note that in FIG. 24C , the camera 730 and the finder 740 are separate electronic devices that are detachable; however, a finder including a display device according to one embodiment of the present invention may be built into the housing 731 of the camera 730.

[0231] 24D includes a housing 751, a display portion 752, a microphone 757, a speaker portion 754, a camera 753, an operation switch 755, and the like. A display device according to one embodiment of the present invention can be used for the display portion 752. The display portion 752 has a touch panel function. The information terminal 750 includes an antenna, a battery, and the like inside the housing 751. The information terminal 750 can be used as, for example, a smartphone, a mobile phone, a tablet information terminal, a tablet personal computer, an e-book reader, or the like.

[0232] 24E shows an example of a wristwatch-type information terminal. Information terminal 760 includes a housing 761, a display unit 762, a band 763, a buckle 764, operation switches 765, an input / output terminal 766, and the like. Information terminal 760 also includes an antenna, a battery, and the like inside housing 761. Information terminal 760 can execute various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, internet communication, and computer games.

[0233] The display unit 762 also has a touch sensor, allowing operation by touching the screen with a finger or a stylus. For example, an application can be started by touching an icon 767 displayed on the display unit 762. The operation switch 765 can have various functions, such as time setting, power on / off operation, wireless communication on / off operation, silent mode activation / deactivation, and power saving mode activation / deactivation. For example, the functions of the operation switch 765 can be set by an operating system incorporated in the information terminal 760.

[0234] The information terminal 760 is also capable of performing short-range wireless communication according to a communication standard. For example, hands-free conversation is also possible by mutual communication with a wirelessly enabled headset. The information terminal 760 is also provided with an input / output terminal 766, and can transmit and receive data to and from other information terminals via the input / output terminal 766. Charging can also be performed via the input / output terminal 766. Note that charging may be performed by wireless power supply without using the input / output terminal 766.

[0235] 24A to 24E , electronic devices to which the display device according to one embodiment of the present invention can be applied may be connected to an external server via a network. Alternatively, the electronic device may not perform processing requiring high computing power, but may instead perform the processing requiring high computing power on a server connected via a network. This type of processing is also referred to as a thin client. A user (client) terminal (the electronic device in this example) performs only limited processing, while the server performs advanced processing, such as application execution and management, on the server side, thereby reducing the scale of processing on the client side. This eliminates the need for a computing device with high computing performance in the electronic device, thereby facilitating cost reduction, weight reduction, and miniaturization. Furthermore, the electronic device according to one embodiment of the present invention may perform processing by combining the above-described thin client with processing requiring high computing power on the electronic device side.

[0236] The structure described in this embodiment mode can be used in appropriate combination with structures described in other embodiment modes or the like.

[0237] <Additional Notes Regarding the Description of the Present Specification, etc.> The following additional notes will be given regarding the above-described embodiments and the explanations of the respective configurations in the embodiments.

[0238] The configurations shown in each embodiment can be combined with the configurations shown in other embodiments as appropriate to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate.

[0239] In addition, the content (or even a part of the content) described in one embodiment can be applied to, combined with, or replaced with another content (or even a part of the content) described in that embodiment, and / or the content (or even a part of the content) described in one or more other embodiments.

[0240] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0241] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and / or a figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0242] In addition, in the present specification and the like, in the block diagrams, components are classified by function and shown as independent blocks. However, in actual circuits, etc., it is difficult to separate components by function, and there may be cases where one circuit is involved in multiple functions, or where one function is involved across multiple circuits. Therefore, the blocks in the block diagrams are not limited to the components described in the specification, but may be rephrased appropriately depending on the situation.

[0243] In addition, in the drawings, the size, layer thickness, or region is shown at an arbitrary size for convenience of explanation. Therefore, it is not necessarily limited to the scale. Note that the drawings are shown schematically for clarity, and are not limited to the shapes or values ​​shown in the drawings. For example, it is possible to include variations in signal, voltage, or current due to noise, or variations in signal, voltage, or current due to timing deviations.

[0244] In this specification and the like, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. This is because the source and drain of a transistor vary depending on the structure or operating conditions of the transistor. Note that the source and drain of a transistor can be appropriately referred to as source (drain) terminal, source (drain) electrode, or the like depending on the situation.

[0245] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0246] Furthermore, in this specification and the like, the terms voltage and potential can be interchanged as appropriate. Voltage refers to the potential difference from a reference potential. For example, if the reference potential is a ground voltage (earth voltage), then voltage can be interchanged with potential. Ground potential does not necessarily mean 0 V. Note that potential is relative, and the potential applied to wiring, etc. may change depending on the reference potential.

[0247] In this specification and the like, terms such as "film" and "layer" can be interchangeable depending on the circumstances. For example, the term "conductive layer" can be changed to the term "conductive film." Or, for example, the term "insulating film" can be changed to the term "insulating layer."

[0248] In this specification, a switch refers to a device that has a function of controlling whether a current flows by being in a conductive state (on state) or a non-conductive state (off state), or a device that has a function of selecting and switching a path for a current to flow.

[0249] In this specification, the channel length refers to, for example, in a top view of a transistor, a region where a semiconductor (or a portion in the semiconductor through which current flows when the transistor is on) and a gate overlap, or a distance between a source and a drain in a region where a channel is formed.

[0250] In this specification, the channel width refers to, for example, the length of the region where the semiconductor (or the portion in the semiconductor through which current flows when the transistor is on) and the gate electrode overlap, or the length of the portion where the source and drain face each other in the region where the channel is formed.

[0251] In this specification, "A and B are connected" includes not only a direct connection between A and B, but also an electrical connection between A and B. Here, "A and B are electrically connected" means that when an object having some kind of electrical effect exists between A and B, transmission of an electrical signal between A and B is possible.

[0252] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. Also, in this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as a device with an MML (metal maskless) structure.

[0253] In this specification and the like, a structure in which different light-emitting layers are formed or different light-emitting layers are painted for each color light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. In this specification and the like, a light-emitting device that can emit white light may be referred to as a white light-emitting device. In addition, a white light-emitting device can be combined with a colored layer (for example, a color filter) to realize a full-color display device.

[0254] Light-emitting devices can be broadly divided into single structures and tandem structures. A single-structure device has one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, two or more light-emitting layers can be selected so that the light emitted by each of the two or more light-emitting layers can produce white light. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration in which the light-emitting device as a whole emits white light can be obtained. Furthermore, when white light emission is obtained using three or more light-emitting layers, the light-emitting device as a whole can emit white light by combining the emission colors of the three or more light-emitting layers.

[0255] A tandem-structure device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light emission, light from the light-emitting layers of the light-emitting units may be combined to obtain white light emission. The configuration for obtaining white light emission is the same as that of the single-structure device. In a tandem-structure device, it is preferable to provide an intermediate layer such as a charge-generating layer between the light-emitting units.

[0256] Furthermore, when comparing the above-described white light-emitting device (single structure or tandem structure) with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. If it is desired to reduce power consumption, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, and therefore the manufacturing cost can be reduced or the manufacturing yield can be increased, making it preferable.

[0257] 10: Layer, 11: Memory section, 12: Memory cell, 20: Layer, 21: Control circuit, 23: Display section drive circuit, 24: Memory section drive circuit, 26: Sensor circuit, 27: Communication circuit, 28: Input / output circuit, 29: Terminal section, 30: Layer, 31: Display section, 40: Sealing substrate, 50: Pixel, 100A: Display device

Claims

1. 1. A display device having a first layer and a second layer on the first layer, the first layer has a functional circuit; the second layer has a display section including a plurality of pixels and a storage section including a plurality of memory cells; Each of the plurality of pixels includes a pixel circuit and a light-emitting element on the pixel circuit; the functional circuit includes a display unit drive circuit, the storage unit has a function of storing image data to be output to the display unit via the display unit drive circuit, The memory cell a first transistor for holding a potential according to the image data; a second transistor for reading out the potential; the first transistor is provided in the second layer, The second transistor is provided in the first layer.

2. In claim 1, At least one of the plurality of memory cells is provided in a region where the pixel circuit is provided.

3. In claim 1, At least one of the plurality of memory cells is provided in at least a part of an outer periphery of the display unit.

4. In claim 1, a semiconductor layer having a channel formation region of the first transistor includes a metal oxide; a semiconductor layer having a channel formation region of the second transistor, the semiconductor layer including silicon;

5. In any one of claims 1 to 4, The display device, wherein the display section drive circuit is provided in an area overlapping the display section.

6. In any one of claims 1 to 4, The display device, wherein the functional circuitry includes a control circuit, a sensor circuit, a communication circuit, and an input / output circuit.

7. In any one of claims 1 to 4, the display unit has a plurality of sub-display units, each of the sub-display units includes the display unit drive circuit; A display device, wherein the number of times image data is rewritten per unit time in any one of the sub-display sections is less than the number of times image data is rewritten per unit time in the other sub-display sections.

8. An electronic device having a display device according to any one of claims 1 to 4 and a housing.

9. 1. A display device having a first layer, a second layer on the first layer, and a third layer on the second layer, the first layer has a functional circuit; the second layer has a display portion including a plurality of pixels; the third layer has a storage unit including a plurality of memory cells; Each of the plurality of pixels includes a pixel circuit and a light-emitting element on the pixel circuit; the functional circuit includes a display unit drive circuit, The display device, wherein the storage unit has a function of storing image data to be output to the display unit via the display unit drive circuit.

10. In claim 9, The memory cell a first transistor for holding a potential according to the image data; a second transistor for reading out the potential; the first transistor is provided in the third layer, The second transistor is provided in the first layer.

11. In claim 10, a semiconductor layer having a channel formation region of the first transistor includes a metal oxide; a semiconductor layer having a channel formation region of the second transistor, the semiconductor layer including silicon;

12. In any one of claims 9 to 11, The display device, wherein the display section drive circuit is provided in an area overlapping the display section.

13. In any one of claims 9 to 11, The display device, wherein the functional circuitry includes a control circuit, a sensor circuit, a communication circuit, and an input / output circuit.

14. 12. An electronic device comprising: a display device according to claim 9; and a housing.