Display device

Abstract

Provided is a display device with little chromaticity variation and good gradation control characteristics. This is a display device capable of carrying out PAM and PWM control (pulse width control involving changes in amplitude) on light emitted by a light emitting device, and capable of improving control characteristics on the low-gradation side while minimizing the amount of variation in chromaticity. The display device has a pulse signal generation unit and a light emission control unit in each pixel, and after the light emission control unit has been charged to a signal potential, can cause the signal potential to be discharged in response to a pulse signal generated by the pulse signal generation unit. Consequently, a light emitting device can be caused to emit light for a desired period of time at a desired light emission intensity.

Description

Display devices and electronic devices

[0001] One aspect of the present invention relates to a display device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of one embodiment of the invention disclosed in this specification and the like relates to an object, a method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include a semiconductor device, a display device, a liquid crystal display device, a light-emitting device, a lighting device, a power storage device, a memory device, an imaging device, and an operation method thereof or a manufacturing method thereof.

[0003] Note that in this specification and the like, a semiconductor device refers to any device that can function by utilizing semiconductor characteristics. A transistor and a semiconductor circuit are examples of a semiconductor device. In addition, a memory device, a display device, an imaging device, and an electronic device may include a semiconductor device.

[0004] Display devices and lighting devices equipped with micro light-emitting diodes (hereinafter referred to as micro LEDs (LEDs: Light Emitting Diodes)) have been proposed (for example, Patent Document 1). Display devices equipped with micro LEDs are capable of displaying images with high brightness and are highly reliable, and are therefore promising as next-generation displays.

[0005] Furthermore, a technique for forming a transistor using a metal oxide formed on a substrate has attracted attention. For example, Patent Documents 2 and 3 disclose techniques for using a transistor using zinc oxide or an In—Ga—Zn-based oxide as a switching element for a pixel of a display device.

[0006] US Patent Application Publication No. 2014 / 0367705 JP 2007-123861 A JP 2007-96055 A

[0007] In a display device using a light-emitting device (also called a light-emitting element), the luminance can be changed by controlling the current flowing through the light-emitting device. However, LEDs, which are one type of light-emitting device, have the characteristic that their chromaticity tends to change depending on the current density.

[0008] Therefore, controlling the brightness of an LED using pulse amplitude modulation (PAM) can result in poor color reproducibility. Therefore, it is preferable to drive the LED using pulse width modulation (PWM), which controls brightness using a duty ratio. Using PWM control makes it possible to maintain a constant current density, allowing brightness to be adjusted without causing chromaticity deviation.

[0009] However, there is a lower limit to the duty ratio that can be stably controlled due to the response characteristics of the LED and the transistor that drives the LED, etc. Therefore, PWM control of LEDs has the problem that it is difficult to control the low gradation side where the duty ratio becomes small.

[0010] Therefore, an object of one embodiment of the present invention is to provide a display device with small chromaticity change and high gradation controllability. Another object is to provide a display device having a pixel circuit that generates a pulse signal. Another object is to provide a display device having a pixel circuit capable of PAM control and PWM control. Another object is to provide a display device with excellent display characteristics. Another object is to provide a display device with a narrow frame.

[0011] Another object is to provide a display device with low power consumption. Another object is to provide a display device with high reliability. Another object is to provide a novel display device or the like. Another object is to provide a method for operating the display device. Another object is to provide a novel semiconductor device or the like.

[0012] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these will become apparent from the description of the specification, drawings, claims, etc., and it is possible to extract other problems from the description of the specification, drawings, claims, etc.

[0013] One aspect of the present invention relates to a display device having a pixel circuit capable of PAM control and PWM control.

[0014] A first aspect of the present invention is a display device having a pulse signal generation unit and a light emission control unit in a pixel, the light emission control unit having a light emitting device, causing the light emitting device to emit light in accordance with a data potential charged in the light emission control unit, and discharging the data potential in accordance with a pulse signal generated by the pulse signal generation unit, thereby turning off the light emitting device.

[0015] A second aspect of the present invention is a display device having a pixel including a pulse signal generation unit, a first transistor, a second transistor, a third transistor, and a light-emitting device, wherein the gate of the first transistor is electrically connected to one of a source or a drain of the second transistor and one of a source or a drain of the third transistor, the one of the source or the drain of the first transistor is electrically connected to one electrode of the light-emitting device, and the gate of the third transistor is electrically connected to the pulse signal generation unit, and a first data potential is charged to the gate of the first transistor via the second transistor to cause the light-emitting device to emit light, and the third transistor is made conductive in response to a pulse signal generated by the pulse signal generation unit, and the first data potential charged to the gate of the first transistor is discharged to turn off the light-emitting device.

[0016] The pulse signal generating unit includes a fourth transistor, a fifth transistor, and a sixth transistor, and one of the source or drain of the fourth transistor can be electrically connected to one of the source or drain of the fifth transistor and the gate of the third transistor, and the gate of the fourth transistor can be electrically connected to one of the source or drain of the sixth transistor.

[0017] A slope-shaped signal potential can be input to the fourth transistor, a reset potential can be input to the fifth transistor, and a second data potential can be input to the sixth transistor.

[0018] A third aspect of the present invention is a display device having first to sixth transistors, a first capacitor, a second capacitor, and a light-emitting device, in which the gate of the first transistor is electrically connected to one of the source or drain of the second transistor, one of the source or drain of the third transistor, and one electrode of the first capacitor, the one of the source or drain of the first transistor is electrically connected to one electrode of the light-emitting device and the other electrode of the first capacitor, the gate of the third transistor is electrically connected to one of the source or drain of the fourth transistor and one of the source or drain of the fifth transistor, and the gate of the fourth transistor is electrically connected to one of the source or drain of the sixth transistor and one electrode of the second capacitor.

[0019] In the second and third aspects of the present invention, a seventh transistor may be provided, and one of the source or drain of the seventh transistor may be electrically connected to one of the source or drain of the first transistor.

[0020] The first to third transistors, the fifth transistor, and the sixth transistor can be n-channel transistors, and the fourth transistor can be a p-channel transistor.

[0021] In this case, it is preferable that the first transistor, the second transistor, the fifth transistor, and the sixth transistor each have a metal oxide in a channel formation region, and the third transistor and the fourth transistor each have silicon in a channel formation region.

[0022] Alternatively, the second transistor, the fourth transistor, and the sixth transistor can each be an n-channel transistor, and the first transistor, the third transistor, and the fifth transistor can each be a p-channel transistor.

[0023] In this case, it is preferable that the second transistor, the fourth transistor, and the sixth transistor each have a metal oxide in a channel formation region, and the first transistor, the third transistor, and the fifth transistor each have silicon in a channel formation region.

[0024] Preferably, the light emitting device is a mini LED or a micro LED.

[0025] By using one embodiment of the present invention, a display device with small chromaticity change and high gradation controllability can be provided. Alternatively, a display device having a pixel circuit that generates a pulse signal can be provided. Alternatively, a display device having a pixel circuit capable of PAM control and PWM control can be provided. Alternatively, a display device with excellent display characteristics can be provided. Alternatively, a display device with a narrow frame can be provided.

[0026] Alternatively, a display device with low power consumption can be provided. Alternatively, a display device with high reliability can be provided. Alternatively, a novel display device or the like can be provided. Alternatively, a method for operating the display device can be provided. Alternatively, a novel semiconductor device or the like can be provided.

[0027] FIG. 1 is a diagram illustrating a pixel circuit. FIGS. 2A and 2B are diagrams illustrating a display device. FIG. 3 is a timing chart illustrating the operation of a pixel. FIGS. 4A and 4B are diagrams illustrating the operation of a pixel circuit. FIGS. 5A and 5B are diagrams illustrating the operation of a pixel circuit. FIGS. 6A to 6C are diagrams illustrating modified pixel circuits. FIG. 7 is a diagram illustrating a pixel circuit. FIG. 8 is a timing chart illustrating the operation of a pixel circuit. FIGS. 9A and 9B are diagrams illustrating the operation of a pixel circuit. FIGS. 10A and 10B are diagrams illustrating the operation of a pixel circuit. FIGS. 11A to 11C are diagrams illustrating modified pixel circuits. FIG. 12A is a diagram illustrating the relationship between gray level and luminance. FIG. 12B is a diagram illustrating operation according to luminance in terms of the luminance intensity and luminance time of a light-emitting device. FIGS. 13A and 13B are diagrams illustrating the range of chromaticity deviation. FIGS. 14A and 14B are diagrams illustrating a pixel circuit. FIG. 15 is a block diagram illustrating a display device. FIG. 16 is a diagram illustrating a pixel circuit used in simulations. Fig. 17A and Fig. 17B are diagrams for explaining simulation results. Fig. 18A and Fig. 18B are diagrams for explaining a display device. Fig. 19 is a diagram for explaining a display device. Fig. 20 is a diagram for explaining a display device. Fig. 21A and Fig. 21B are diagrams for explaining a display device. Figs. 22A to 22D are diagrams for explaining an electronic device.

[0028] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various modifications in form and detail may be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be designated by the same reference numerals in different drawings, and repeated description thereof may be omitted. In addition, hatching of the same elements constituting the drawings may be omitted or changed as appropriate in different drawings.

[0029] Furthermore, even if a circuit diagram shows a single element, that element may be configured as multiple elements as long as there is no functional problem. For example, multiple transistors operating as switches may be connected in series or parallel. Also, a capacitor may be divided and placed in multiple locations.

[0030] Furthermore, a single conductor may have multiple functions, such as wiring, an electrode, and a terminal, and in this specification, multiple names may be used for the same element. Also, even when elements are shown as being directly connected to each other on a circuit diagram, in reality, the elements may be connected via one or more conductors, and in this specification, such a configuration is also included in the category of direct connection.

[0031] Embodiment 1 In this embodiment, a display device which is one embodiment of the present invention will be described with reference to drawings.

[0032] One embodiment of the present invention is a display device that can control the emission of a light-emitting device by PAM+PWM control (pulse width control with amplitude variation). The display device includes a pulse signal generation unit and a light-emission control unit in each pixel, and can charge a signal potential in the light-emission control unit and then discharge the signal potential in response to a pulse signal generated by the pulse signal generation unit. Therefore, the light-emitting device can emit light at a desired emission intensity for a desired period.

[0033] In this embodiment, PAM control refers to controlling brightness by changing the light emission intensity (corresponding to the current flowing through the light emitting device) while keeping the light emission time (corresponding to the width of the pulse signal generated by the pixel) constant, while PWM control refers to controlling brightness by changing the light emission time while keeping the light emission intensity constant.

[0034] An LED, which is a type of light-emitting device, has a characteristic that its chromaticity changes depending on the current density, and therefore PAM control may not be suitable. On the other hand, PWM control has a problem in that it is difficult to control low gradations due to the influence of the response characteristics of the drive transistor and the LED. In a display device according to one embodiment of the present invention, a display operation that combines PWM control and PWM control can be performed to alleviate these problems.

[0035] For example, the display operation can be performed by PAM control on the low gradation side and the high gradation side, and the display operation can be performed by PWM control on the intermediate gradation side. This operation can improve the controllability on the low gradation side while reducing the amount of change in chromaticity. Note that the display device of one embodiment of the present invention is not limited to this, and LED light emission can be performed by only PAM control or only PWM control over a wide range of gradations.

[0036] 1 is a circuit diagram of a pixel 10 a included in a display device of one embodiment of the present invention. The pixel 10 a can be roughly divided into a pulse signal generation unit 11 and a light-emission control unit 12.

[0037] The pulse signal generating unit 11 can include a transistor 101, a transistor 102, a transistor 103, and a capacitor 111. Here, the transistor 101 can be a p-channel transistor. Note that although an example in which n-channel transistors are used as the other transistors is shown in FIG. 1 , the transistor functioning as a switch may be a p-channel transistor.

[0038] The light-emitting control unit 12 has a transistor 104, a transistor 105, a transistor 106, a transistor 107, a capacitor 112, and a light-emitting device 110. While Fig. 1 shows an example in which n-channel transistors are used for the transistors 104 to 107, the transistor functioning as a switch may be a p-channel transistor. Furthermore, it is preferable to use an LED (e.g., a micro LED or a mini LED) for the light-emitting device 110, but an organic EL element may also be used.

[0039] In the pulse signal generating unit 11, one of the source and the drain of the transistor 101 is electrically connected to one of the source and the drain of the transistor 102 and the gate of the transistor 106 included in the light-emission control unit 12. The gate of the transistor 101 is electrically connected to one electrode of the capacitor 111 and one of the source and the drain of the transistor 103.

[0040] Here, a point (wiring or electrode, etc.) where the gate of the transistor 101, one electrode of the capacitor 111, and one of the source or drain of the transistor 103 are connected is referred to as a node N. Also, a point (wiring or electrode, etc.) where the source or drain of the transistor 101, one of the source or drain of the transistor 102, and the gate of the transistor 106 are connected is referred to as a node W.

[0041] In the light-emission control unit 12, the gate of the transistor 104 is electrically connected to one of the source or drain of the transistor 105, one electrode of the capacitor 112, and one of the source or drain of the transistor 106. The source or drain of the transistor 104 is electrically connected to one of the source or drain of the transistor 107, the other electrode of the capacitor 112, and one electrode (anode) of the light-emitting device 110.

[0042] Here, a point (such as a wiring or an electrode) where the gate of the transistor 104, one of the source and drain of the transistor 105, one electrode of the capacitor 112, and one of the source and drain of the transistor 106 are connected is referred to as a node A.

[0043] The connection relationship between each transistor and a wiring is as follows: The other of the source and the drain of the transistor 101 is electrically connected to a wiring 123. The other of the source and the drain of the transistor 102 is electrically connected to a wiring 124. The other of the source and the drain of the transistor 103 is electrically connected to a wiring 121. The other of the source and the drain of the transistor 104 is electrically connected to a wiring 125. The other of the source and the drain of the transistor 105 is electrically connected to a wiring 122. The other of the source and the drain of the transistor 106 is electrically connected to a wiring 128. The other of the source and the drain of the transistor 107 is electrically connected to a wiring 126. The other electrode of the capacitor 111 is electrically connected to a wiring 127. The other electrode (cathode) of the light-emitting device 110 is electrically connected to a wiring 129. The gate of the transistor 102 is electrically connected to a wiring 132. The gate of the transistor 103 is electrically connected to a wiring 131. A gate of the transistor 105 is electrically connected to a wiring 133. A gate of the transistor 107 is electrically connected to a wiring .

[0044] The wirings 121, 123, and 124 are wirings for supplying signal potentials for PWM control. The wiring 121 is a first source line that supplies a signal potential that determines a pulse width and can be electrically connected to a first source driver. The wiring 123 is a wiring for supplying a slope signal and can be electrically connected to a slope potential generating circuit. The wiring 124 is a wiring for supplying a reset potential to the node W.

[0045] In this specification, the term "sloping potential" refers to a type of ramp wave, which is a sloping signal potential that changes from high to low or from low to high.

[0046] The wiring 122 is a wiring for supplying a signal potential for PAM control. The wiring 122 is a second source line for supplying a signal potential for determining the amplitude (voltage), and can be electrically connected to a second source driver.

[0047] The wirings 131 to 134 are gate wirings for controlling the conduction or non-conduction of each transistor and can be electrically connected to a gate driver. Note that the wirings 131 to 134 may be a common wiring. The wirings 125 and 129 are power supply lines, and the wiring 125 can be a high-potential power supply line, and the wiring 129 can be a low-potential power supply line. The wiring 126 is a wiring for supplying a reset potential for fixing the source potential of the transistor 104. The wiring 128 is a fixed potential line and can be a wiring that supplies a potential lower than the smallest signal potential supplied from the wiring 122. The wiring 127 is a fixed potential line and can be, for example, a low-potential wiring. Note that any one of the wirings 124, 126, 127, 128, and 129 may be a common wiring with one or more of the others.

[0048] Here, the transistors 102, 103, 105, and 107 function as switches. The transistors 101 and 106 have a function of generating a pulse signal. The transistor 104 functions as a drive transistor for the light-emitting device 110 and performs switching operation in accordance with the generated pulse signal. Note that the amplitude of the pulse signal can be changed by the signal potential input from the wiring 122. The capacitors 111 and 112 function as storage capacitors.

[0049] The transistors 101 to 107 can be transistors having silicon in a channel formation region (hereinafter referred to as Si transistors), transistors having metal oxide in a channel formation region (hereinafter referred to as OS transistors), or the like. Alternatively, both Si transistors and OS transistors can be used.

[0050] 1, it is preferable to use Si transistors for the transistors 101 and 106 and OS transistors for the other transistors. Since the OS transistors can be provided in a process for providing a wiring layer over the Si transistors, the degree of integration can be increased.

[0051] The transistor 101 is a p-channel transistor, and therefore can be easily formed using a Si transistor. The transistor 106 preferably has fast charge / discharge characteristics and therefore preferably has a large transconductance (gm). Si transistors have relatively high mobility, so they can have a large gm. Note that an OS transistor may be used as the transistor 106.

[0052] An OS transistor is suitable for use as the driving transistor (transistor 104) of the light-emitting device 110 because it has favorable drain current saturation characteristics even when its channel length is shorter than that of a Si transistor.

[0053] Furthermore, because the energy gap of the semiconductor layer of an OS transistor is large, the OS transistor can exhibit extremely low off-state current of several yA / μm (current value per μm of channel width). The low off-state current can enhance the node potential retention capability, enabling appropriate image display even at a lower frame frequency. For example, the power consumption of a display device can be reduced by switching the frame frequency to a first frame frequency (e.g., 60 Hz or higher) for displaying moving images and a second frame frequency (e.g., approximately 1 to 10 Hz) lower than the first frame frequency for displaying still images.

[0054] As a semiconductor material for an OS transistor, a metal oxide having an energy gap of 2 eV or more, preferably 2.5 eV or more, more preferably 3 eV or more can be used. A typical example is an oxide semiconductor containing indium, such as CAAC-OS or CAC-OS, which will be described later. CAAC-OS has stable atoms constituting the crystal, making it suitable for transistors in which reliability is important. Furthermore, CAC-OS exhibits high mobility and is therefore suitable for transistors that operate at high speed.

[0055] An OS transistor has characteristics different from those of a transistor having silicon in a channel formation region (hereinafter referred to as a Si transistor), such as no impact ionization, no avalanche breakdown, and no short-channel effect, and can form a highly reliable circuit.

[0056] A semiconductor layer included in an OS transistor can be, for example, a film represented by an In-M-Zn-based oxide containing indium, zinc, and M (a metal such as aluminum, titanium, gallium, germanium, yttrium, zirconium, lanthanum, cerium, tin, neodymium, or hafnium). The In-M-Zn-based oxide can typically be formed by a sputtering method. Alternatively, it may be formed by an atomic layer deposition (ALD) method.

[0057] The atomic ratio of the metal elements in a sputtering target used to form an In-M-Zn-based oxide by a sputtering method preferably satisfies In≧M and Zn≧M. Preferred atomic ratios of the metal elements in such a sputtering target are In:M:Zn=1:1:1, In:M:Zn=1:1:1.2, In:M:Zn=3:1:2, In:M:Zn=4:2:3, In:M:Zn=4:2:4.1, In:M:Zn=5:1:6, In:M:Zn=5:1:7, In:M:Zn=5:1:8, etc. The atomic ratios of the semiconductor layer to be formed each include a variation of plus or minus 40% of the atomic ratio of the metal elements contained in the sputtering target.

[0058] The semiconductor layer is made of an oxide semiconductor having a low carrier concentration. For example, the semiconductor layer may have a carrier concentration of 1×10 １７ / cm ３ Below 1 × 10, preferably １５ / cm ３ More preferably, 1×10 １３ / cm ３ or less, more preferably 1 × 10 １１ / cm ３ More preferably, 1×10 １０ / cm ３ is less than 1×10 −９ / cm ３The above-described oxide semiconductors can be used. Such oxide semiconductors are called high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors. Such oxide semiconductors have a low density of defect states and stable characteristics.

[0059] Note that the present invention is not limited to these, and an oxide semiconductor having an appropriate composition may be used depending on the semiconductor characteristics and electrical characteristics (field-effect mobility, threshold voltage, etc.) of the transistor. In order to obtain the semiconductor characteristics of the transistor, it is preferable to appropriately set the carrier concentration, impurity concentration, defect density, atomic ratio of metal element to oxygen, interatomic distance, density, and the like of the semiconductor layer.

[0060] When silicon or carbon, which is one of the Group 14 elements, is contained in the oxide semiconductor constituting the semiconductor layer, oxygen vacancies increase, resulting in n-type conductivity. Therefore, the concentration of silicon or carbon in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 2×10 １８ atoms / cm ３ Below 2 × 10, preferably １７ atoms / cm ３ The following applies.

[0061] In addition, when an alkali metal or alkaline earth metal is bonded to an oxide semiconductor, carriers may be generated, which may increase the off-state current of a transistor. Therefore, the concentration of the alkali metal or alkaline earth metal in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is set to 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0062] Furthermore, when nitrogen is contained in the oxide semiconductor constituting the semiconductor layer, electrons serving as carriers are generated, increasing the carrier concentration and making the semiconductor layer more likely to be n-type. As a result, a transistor using an oxide semiconductor containing nitrogen is likely to have normally-on characteristics. Therefore, the nitrogen concentration in the semiconductor layer (concentration obtained by secondary ion mass spectrometry) is 5×10 １８ atoms / cm ３ It is preferable to do the following:

[0063] Furthermore, if hydrogen is contained in an oxide semiconductor constituting a semiconductor layer, it may react with oxygen bonded to metal atoms to form water, which may form oxygen vacancies in the oxide semiconductor. If oxygen vacancies are present in the channel formation region of an oxide semiconductor, the transistor may exhibit normally-on characteristics. Furthermore, defects in which hydrogen enters the oxygen vacancies may function as donors and generate electrons that serve as carriers. Furthermore, some of the hydrogen may bond with oxygen that is bonded to metal atoms to generate electrons that serve as carriers. Therefore, a transistor using an oxide semiconductor containing a large amount of hydrogen is likely to exhibit normally-on characteristics.

[0064] A defect in which hydrogen is introduced into an oxygen vacancy can function as a donor in an oxide semiconductor. However, it is difficult to quantitatively evaluate such defects. Therefore, oxide semiconductors are sometimes evaluated using carrier concentration instead of donor concentration. Therefore, in this specification and the like, a carrier concentration assuming a state in which no electric field is applied may be used as a parameter of an oxide semiconductor instead of donor concentration. In other words, the "carrier concentration" described in this specification and the like may be rephrased as "donor concentration."

[0065] Therefore, it is preferable that the hydrogen concentration in the oxide semiconductor be reduced as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by secondary ion mass spectrometry (SIMS) is set to 1×10 ２０ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ When an oxide semiconductor in which impurities such as hydrogen are sufficiently reduced is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0066] The semiconductor layer may have, for example, a non-single-crystal structure. Examples of the non-single-crystal structure include a c-axis aligned crystalline oxide semiconductor (CAAC-OS) having crystals oriented along the c-axis, a polycrystalline structure, a microcrystalline structure, and an amorphous structure. Among non-single-crystal structures, an amorphous structure has the highest density of defect states, and a CAAC-OS has the lowest density of defect states.

[0067] An amorphous oxide semiconductor film has, for example, a disordered atomic arrangement and does not contain any crystalline components, or an amorphous oxide film has, for example, a completely amorphous structure and does not contain any crystalline parts.

[0068] The semiconductor layer may be a mixed film including two or more of an amorphous region, a microcrystalline region, a polycrystalline region, a CAAC-OS region, and a single-crystal region. The mixed film may have a single layer structure or a stacked layer structure including two or more of the above-described regions.

[0069] The structure of a cloud-aligned composite (CAC)-OS, which is one mode of a non-single-crystal semiconductor layer, will be described below.

[0070] CAC-OS is a material in which, for example, elements constituting an oxide semiconductor are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in an oxide semiconductor and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 2 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0071] The oxide semiconductor preferably contains at least indium, particularly indium and zinc, and may further contain one or more elements selected from aluminum, gallium, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and the like.

[0072] For example, CAC-OS in In—Ga—Zn oxide (In—Ga—Zn oxide among CAC-OS may be particularly referred to as CAC-IGZO) is an indium oxide (hereinafter, InO Ｘ１ (X1 is a real number greater than 0).) or indium zinc oxide (hereinafter referred to as In Ｘ２ Zn Ｙ２ O Ｚ２ (X2, Y2, and Z2 are real numbers greater than 0.) and gallium oxide (hereinafter, GaO Ｘ３ (X3 is a real number greater than 0).) or gallium zinc oxide (hereinafter referred to as Ga Ｘ４ Zn Ｙ４ O Ｚ４ (X4, Y4, and Z4 are real numbers greater than 0).) The material is separated into a mosaic structure, and the mosaic structure of InO Ｘ１ , or In Ｘ２ Zn Ｙ２ O Ｚ２ However, the structure is such that the particles are uniformly distributed in the film (hereinafter also referred to as a cloud-like structure).

[0073] That is, CAC-OS is Ｘ３ The region where In is the main component and Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ In this specification, for example, when the atomic ratio of In to the element M in the first region is larger than the atomic ratio of In to the element M in the second region, the first region is said to have a higher In concentration than the second region.

[0074] IGZO is a common name and may refer to a compound of In, Ga, Zn, and O. A typical example is InGaO ３ (ZnO) ｍ１ (m1 is an integer of 1 or more), or In （１＋ｘ０） Ga （１−ｘ０） O ３ (ZnO) ｍ０ (-1≦x0≦1, m0 is an integer of 1 or more) can be mentioned.

[0075] The crystalline compound has a single crystal structure, a polycrystalline structure, or a CAAC structure. The CAAC structure is a crystal structure in which multiple IGZO nanocrystals have a c-axis orientation and are connected without being oriented in the a-b plane.

[0076] On the other hand, CAC-OS refers to a material structure of an oxide semiconductor. CAC-OS refers to a material structure containing In, Ga, Zn, and O, in which some regions observed as nanoparticles mainly composed of Ga and some regions observed as nanoparticles mainly composed of In are randomly dispersed in a mosaic pattern. Therefore, in CAC-OS, the crystal structure is a secondary element.

[0077] Note that the CAC-OS does not include a stacked structure of two or more films with different compositions, for example, a two-layer structure including a film containing In as the main component and a film containing Ga as the main component.

[0078] In addition, GaO Ｘ３ The region where In is the main component and Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ In some cases, a clear boundary between the region where the main component is the chromatic aberration and the region where the chromatic aberration is the main component may not be observed.

[0079] When one or more elements selected from aluminum, yttrium, copper, vanadium, beryllium, boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium are contained instead of gallium, the CAC-OS has a structure in which some regions observed to be nanoparticles containing the metal element as the main component and some regions observed to be nanoparticles containing In as the main component are randomly dispersed in a mosaic pattern.

[0080] The CAC-OS can be formed by sputtering, for example, under the condition that the substrate is not intentionally heated. When the CAC-OS is formed by sputtering, any one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate ratio of oxygen gas to the total flow rate of deposition gas during deposition, the more preferable it is. For example, the flow rate ratio of oxygen gas is preferably 0% or more and less than 30%, and more preferably 0% or more and 10% or less.

[0081] CAC-OS has a characteristic that no clear peak is observed when measured using θ / 2θ scanning by an out-of-plane method, which is one of the X-ray diffraction (XRD) measurement methods. That is, the X-ray diffraction measurement reveals that the orientation of the measurement region in the a-b plane direction and the c-axis direction is not observed.

[0082] In addition, in an electron beam diffraction pattern obtained by irradiating CAC-OS with an electron beam (also referred to as a nanobeam electron beam) with a probe diameter of 1 nm, a ring-shaped region with high brightness and multiple bright spots within the ring-shaped region are observed. Therefore, the electron beam diffraction pattern indicates that the crystal structure of CAC-OS has an nc (nano-crystal) structure that does not have orientation in the planar and cross-sectional directions.

[0083] For example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained by using energy dispersive X-ray spectroscopy (EDX) revealed that GaO Ｘ３ The region where In is the main component and Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ It can be seen that the region where the main component is the crystalline silicon is unevenly distributed and mixed.

[0084] CAC-OS has a structure different from that of an IGZO compound in which metal elements are uniformly distributed, and has properties different from those of an IGZO compound. Ｘ３ and In Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ The structure is such that the regions are separated into a mosaic of regions each containing one of the elements as the main component and a region each containing one of the elements as the main component.

[0085] Here, In Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ The region where is the main component is GaO Ｘ３ This region has higher conductivity than the region where the main component is In. Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ When carriers flow through the region where In is the main component, the conductivity of the oxide semiconductor is exhibited. Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ When the region containing the main component is distributed in a cloud-like shape in the oxide semiconductor, high field-effect mobility (μ) can be achieved.

[0086] On the other hand, GaO Ｘ３ The region where the main components are In Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１This region has higher insulating properties than the region where GaO is the main component. Ｘ３ When a region containing the above as a main component is distributed in the oxide semiconductor, leakage current can be suppressed and good switching operation can be achieved.

[0087] Therefore, when CAC-OS is used in a semiconductor device, GaO Ｘ３ Insulation due to Ｘ２ Zn Ｙ２ O Ｚ２ , or InO Ｘ１ The conductivity due to the high on-state current (I ｏｎ ), and high field-effect mobility (μ) can be achieved.

[0088] Furthermore, semiconductor devices using the CAC-OS have high reliability, making the CAC-OS suitable as a component material for various semiconductor devices.

[0089] The channel formation region of a Si transistor can be formed using amorphous silicon, microcrystalline silicon, polycrystalline silicon, single crystal silicon, etc. Note that when a transistor is provided on an insulating surface such as a glass substrate, polycrystalline silicon is preferably used.

[0090] High-quality polycrystalline silicon can be easily obtained by using a laser crystallization process or the like. High-quality polycrystalline silicon can also be obtained by a solid-phase growth method in which a metal catalyst such as nickel or palladium is added to amorphous silicon and the resulting material is heated. Furthermore, polycrystalline silicon formed by a solid-phase growth method using a metal catalyst may be irradiated with a laser to further enhance its crystallinity. Since the metal catalyst remains in the polycrystalline silicon and deteriorates the electrical characteristics of the transistor, it is preferable to provide a region to which phosphorus or a noble gas is added outside the channel formation region and capture the metal catalyst in that region.

[0091] Note that to obtain the effect of one embodiment of the present invention, the above structure is not limitative, and all the transistors included in the pixel may be formed using Si transistors. Alternatively, one or more of the transistors included in the pixel may be formed using p-channel transistors.

[0092] 2A is a diagram showing an example of a display device having a stacked structure, and FIG. 2B is a developed view and a partial enlarged view thereof. A display device having a stacked structure can have a structure in which a layer 310 having a silicon substrate or the like, a layer 320 having wiring or the like, and a layer 330 having a light-emitting device are stacked in this order. In this stacked structure, circuits can be formed by stacking them, so that the display device can have a narrow frame.

[0093] The layer 310 can have a Si transistor 311 and a functional circuit 312, which are components of a pixel circuit. The Si transistor 311 can be arranged in a region where it does not interfere with the functional circuit 312. The layer 320 can have an OS transistor 321, which is a component of a pixel circuit. The layer 330 can have an LED array 331.

[0094] The LED array 331 has a configuration in which LEDs are arranged in a matrix. As the LEDs, for example, micro LEDs formed with a diameter or a side length of 50 μm or less, or mini LEDs formed with a diameter or a side length of more than 50 μm and 200 μm or less can be used.

[0095] The functional circuit 312 can be, for example, one or more of a source driver, a gate driver, a memory circuit, an arithmetic circuit, and a power supply circuit. Note that part or all of the gate driver and the memory circuit can be formed using OS transistors. Details of the stacked structure will be described in Embodiment 2.

[0096] <Operation Method of Configuration Example 1> Next, the operation of the pixel 10a will be described using the timing chart shown in Fig. 3 and the diagrams illustrating the circuit operation shown in Figs. 4A to 5B. Note that dashed arrows in Figs. 4A to 5B indicate potentials supplied within the circuit, and dotted arrows indicate currents (I) flowing through the light-emitting device 110. ＬＥＤ ) are shown. In some timing charts, the switching of the supplied signal and the switching of the signal that controls the conduction and non-conduction of the switch (transistor) are shown to occur at the same time. In reality, these occur at different times, and the changes in the potential of each node follow the explanation below.

[0097] First, at time T1, when a low potential ("L") is supplied to the wirings 131, 133, and 134 and a high potential ("H") is supplied to the wiring 132, the transistor 102 becomes conductive, and the potential VRESW (low reset potential) of the wiring 124 is supplied to the node W (see FIG. 4A). This operation is a reset operation of the node W, and at this time, the transistor 106 becomes non-conductive.

[0098] At time T2, when a high potential ("H") is supplied to the wirings 131, 133, and 134 and a low potential ("L") is supplied to the wiring 132, the transistor 103 becomes conductive, and the potential DATAW of the wiring 121 (a data potential for determining the width of the pulse signal to be generated) is supplied to the node N. The transistor 105 also becomes conductive, and the potential DATAA (a data potential for determining the amplitude) is supplied to the node A (the gate of the transistor 104). At this time, the transistor 107 is also conductive, so the source potential of the transistor 104 becomes the reset potential supplied from the wiring 126, and an appropriate gate-source voltage (Vgs) can be written (see FIG. 4B ). At this time, the transistor 104 is conductive, but current flows through the wiring 126, so the light-emitting device 110 does not emit light.

[0099] At time T3, when a low potential ("L") is supplied to the wirings 131, 132, 133, and 134, the transistor 103 becomes non-conductive, and the potential DATAW is held at the node N. Furthermore, the transistor 105 becomes non-conductive, and the potential DATAA is held at the node A. Then, because the transistor 107 becomes non-conductive, a current corresponding to the potential DATAA flows from the transistor 104 to the light-emitting device 110, and the light-emitting device 110 emits light.

[0100] At time T3, a slope potential SLO, which increases over time, is supplied to the wiring 123. 5A illustrates a state in which Vgs = potential DATAW - slope potential SLO and |Vgs| < |Vth| (Vth is the threshold voltage) in the transistor 101, i.e., the transistor 101 is off. At this time, the potential of the node A does not change, and the light-emitting device 110 continues to emit light.

[0101] 5B , when the slope potential SLO further increases, for example, after time T6, |Vgs| > |Vth|. At this time, the transistor 101 is conductive, so the potential of the node W immediately increases to the slope potential SLO at that time, and the transistor 106 also becomes conductive. Then, the potential of the node A is quickly discharged from the potential DATAA to the potential VER of the wiring 128 (potential VER < potential DATAA). At this time, the transistor 104 is non-conductive, so the light-emitting device 110 is turned off.

[0102] As described above, the pixel 10a first emits light in accordance with the potential DATAA written to the node A. Then, the potential of the node A is discharged in accordance with the width of the pulse signal generated by the potential DATAW and the slope potential SLO, thereby ending the light emission.

[0103] That is, it is possible to perform PAM control, which keeps the light emission time constant and changes the light emission intensity, or PWM control, which keeps the light emission intensity constant and changes the light emission time.Furthermore, since the light emission time and light emission intensity can be set arbitrarily, it can also be said that PAM+PWM control (pulse width control with changing amplitude) is possible.

[0104] <Modifications of Configuration Example 1> FIGS. 6A to 6C show modifications of the circuit of the pixel 10a shown in FIG.

[0105] 6A illustrates an example in which a transistor 108 is added to the pixel 10a shown in FIG. One of the source and the drain of the transistor 108 is electrically connected to one of the source and the drain of the transistor 106, and the other of the source and the drain of the transistor 108 is electrically connected to the gate of the transistor 104. The gate of the transistor 108 is electrically connected to a wiring 135. The wiring 135 is a gate line that controls whether the transistor 108 is turned on or off.

[0106] As described above, a Si transistor with a large gm is suitable for the transistor 106 in order to quickly discharge the electric potential. On the other hand, a transistor with a small off-state current is preferable in terms of maintaining the electric potential of the node A. Since the off-state current of a Si transistor is relatively large, the electric potential of the node A may not be sufficiently maintained in the configuration of FIG. 1 depending on the operation method.

[0107] In such a case, it is preferable to provide the transistor 108 formed of an OS transistor. Because the off-state current of an OS transistor is extremely small, the potential of the node A can be maintained even when the off-state current (leakage current) of the transistor 106 is large. This is particularly effective for a display device that operates at a frame frequency of 10 Hz or less.

[0108] 6B shows an example in which the connection form of the light-emitting device 110 is different from that of the pixel 10a shown in Fig. 1. There are various types of LEDs used as the light-emitting device 110, and when the LED has a form that makes it easy to connect the cathode to the pixel electrode, it is preferable to electrically connect the cathode of the light-emitting device 110 to the other of the source or drain of the transistor 104, and to electrically connect the anode of the light-emitting device 110 to the wiring 125. In this configuration, the source of the transistor 104 can be connected to the wiring 129, which is a low-potential power supply line, so that the transistor 107 can be omitted.

[0109] 6C shows an example in which the connection of the transistor 105 is changed to form a circuit dedicated to PWM control. In the configuration shown in FIG. 1, any signal potential can be input to the node A through the transistor 105. However, in the configuration shown in FIG. 6C, the other of the source and the drain of the transistor 105 is electrically connected to the wiring 125, so that a high constant potential is input to the node A. Therefore, the node A is always charged to a constant potential and discharged in response to a pulse signal, so that the circuit can be dedicated to PWM control.

[0110] 7 is a circuit diagram of a pixel 10b different from that of configuration example 1. The pixel 10b differs from the pixel 10a shown in configuration example 1 in the conductivity types of the transistors 101 and 102 of the pulse signal generating unit 11 and the transistors 104 and 106 of the light-emission control unit 12. The pixel 10b also differs in that it does not have a transistor 107. Note that a description common to configuration example 1 will be omitted.

[0111] The pulse signal generating unit 11 can include a transistor 101, a transistor 102, a transistor 103, and a capacitor 111. Here, the transistor 102 can be a p-channel transistor. Note that although an example in which n-channel transistors are used as the other transistors is shown in FIG. 7, the transistor functioning as a switch may be a p-channel transistor.

[0112] The light-emission control unit 12 includes a transistor 104, a transistor 105, a transistor 106, a capacitor 112, and a light-emitting device 110. The transistors 104 and 106 can be p-channel transistors. Although Fig. 7 shows an example in which the transistor 105 is an n-channel transistor, it may also be a p-channel transistor.

[0113] The connection configuration of the transistors 101, 102, and 103 and the capacitor 111 in the pulse signal generating unit 11 is the same as that of the pixel 10a.

[0114] In the light-emission control unit 12, the gate of the transistor 104 is electrically connected to one of the source or drain of the transistor 105, one electrode of the capacitor 112, and one of the source or drain of the transistor 106. The one of the source or drain of the transistor 104 is electrically connected to one electrode (anode) of the light-emitting device 110. The other of the source or drain of the transistor 104 is electrically connected to the other electrode of the capacitor 112.

[0115] The connection relationship between each transistor and each wiring, and the function of each transistor are the same as those of pixel 10a. Wiring 128 is a fixed potential line and can be a wiring that supplies a potential higher than the largest signal potential supplied from wiring 122. Any one of wirings 124, 125, and 128 may be a wiring shared with one or more of the others. Furthermore, wirings 127 and 129 may be a common wiring.

[0116] Since the transistor 104 is a p-channel transistor, the source thereof is connected to the wiring 125, which is a high-potential power supply line. Therefore, the transistor 107 can be omitted.

[0117] The transistors 101 to 106 can be Si transistors, OS transistors, or the like. In particular, it is preferable to use a combination of Si transistors and OS transistors.

[0118] 7, it is preferable to use Si transistors as the transistors 102, 104, and 106 and OS transistors as the other transistors. The OS transistors can be provided in a process for providing wiring layers over the Si transistors.

[0119] <Operation Method of Configuration Example 2> Next, the operation of the pixel 10b will be described with reference to the timing chart shown in FIG. 8 and the diagrams illustrating the circuit operation in FIGS. 9A to 10B.

[0120] First, at time T1, when a low potential ("L") is supplied to the wirings 131, 132, and 133, the transistor 102 is turned on, and the potential VRESW (high reset potential) of the wiring 124 is supplied to the node W (see FIG. 9A). This operation is a reset operation of the node W, and at this time, the transistor 106 is turned off.

[0121] At time T2, when a high potential ("H") is supplied to wirings 131, 132, and 133, transistor 103 becomes conductive, and potential DATAW (a data potential for determining the width of the pulse signal to be generated) of wiring 121 is supplied to node N. Also, transistor 105 becomes conductive, and potential DATAA (a data potential for determining the amplitude) is supplied to node A (the gate of transistor 104). Then, a current corresponding to potential DATAA flows from transistor 104 to light-emitting device 110, causing light-emitting device 110 to emit light (see FIG. 9B).

[0122] Next, at time T3, when a low potential ("L") is supplied to the wirings 131 and 133 and a high potential ("H") is supplied to the wiring 132, the transistor 103 becomes non-conductive and the potential DATAW is held at the node N. In addition, the transistor 105 becomes non-conductive and the potential DATAA is held at the node A.

[0123] 10A illustrates a state in which Vgs=(potential DATAW−slope potential SLO) and |Vgs|<|Vth| (Vth is the threshold voltage) in the transistor 101, i.e., the transistor 101 is off. At this time, the potential of the node A does not change, and the light-emitting device 110 continues to emit light.

[0124] 10B , when the slope potential SLO further decreases, for example, after time T6, |Vgs|>|Vth|. At this time, the transistor 101 becomes conductive, so the potential of the node W immediately decreases to the slope potential SLO at that time, and the transistor 106 also becomes conductive. Then, the potential of the node A is quickly charged from the potential DATAA to the potential VER of the wiring 128 (potential VER>potential DATAA). At this time, the transistor 104 becomes non-conductive, so the light-emitting device 110 is turned off.

[0125] As described above, pixel 10b first emits light in accordance with the potential DATAA written to node A. Then, the potential of node A is charged in accordance with the width of the pulse signal generated by the potential DATAW and the slope potential SLO, and the light emission is terminated.

[0126] <Modifications of Configuration Example 2> FIGS. 11A to 11C show modifications of the circuit of the pixel 10b shown in FIG.

[0127] 11A illustrates an example in which a transistor 108 is added to the pixel 10b illustrated in FIG. 7. One of the source and the drain of the transistor 108 is electrically connected to the one of the source and the drain of the transistor 106, and the other of the source and the drain of the transistor 108 is electrically connected to the gate of the transistor 104. The gate of the transistor 108 is electrically connected to a wiring 135. The wiring 135 is a gate line that controls whether the transistor 108 is turned on or off.

[0128] As described above, a Si transistor with a large gm is suitable for the transistor 106 in order to quickly charge the transistor 106. On the other hand, a transistor with a small off-state current is preferable in terms of maintaining the potential of the node A. Since the off-state current of a Si transistor is relatively large, the potential of the node A may not be sufficiently maintained in the configuration of FIG. 7 depending on the operation method.

[0129] In such a case, it is preferable to provide the transistor 108 formed of an OS transistor. Because the off-state current of an OS transistor is extremely small, the potential of the node A can be maintained even when the off-state current (leakage current) of the transistor 106 is large. This is particularly effective for a display device that operates at a frame frequency of 10 Hz or less.

[0130] 11B shows an example in which the connection form of the light-emitting device 110 is different from that of the pixel 10b shown in Fig. 7. There are various types of LEDs used as the light-emitting device 110, and when the LED has a form that makes it easy to connect the cathode to the pixel electrode, it is preferable to electrically connect the cathode of the light-emitting device 110 to the other of the source or drain of the transistor 104, and to electrically connect the anode of the light-emitting device 110 to the wiring 125.

[0131] 11C shows an example in which the connection of the transistor 105 is changed to form a circuit dedicated to PWM control. In the configuration shown in FIG. 7, any signal potential can be input to the node A through the transistor 105. However, in the configuration shown in FIG. 11C, the other of the source and the drain of the transistor 105 is electrically connected to the wiring 129, so that a low constant potential is input to the node A. Therefore, the node A is always discharged at a constant potential and charged in response to a pulse signal, so that the circuit can be dedicated to PWM control.

[0132] 12A is a diagram showing the relationship between gray levels (input values ​​of 8 bits) and luminance (output values) according to a gamma curve (gamma value = 2). The pixels 10a and 10b according to one embodiment of the present invention can perform input and output shown in FIG. 12A and can switch their operation methods within a desired range of gray levels.

[0133] For example, the low brightness 32 gradations (luminance corresponding to 0 to 31 gradations) and the high brightness 128 gradations (luminance corresponding to 128 to 255 gradations) are operated under PAM control, and the intermediate 96 gradations (luminance corresponding to 32 to 127 gradations) are operated under PWM control. This operation makes it possible to display an image with little chromaticity deviation. However, this is not limiting, and the operation method and switching timing can be set arbitrarily. It is also possible to operate the entire range under either PAM control or PWM control.

[0134] 12B is a diagram illustrating the above operation in terms of the light emitting intensity and light emitting time of the light emitting device. The numerical values ​​shown inside the markers or through the arrows represent input values ​​of the gray levels.

[0135] For the low brightness 32 gradations, PAM control is performed with a relatively short first light emission time. PAM control can control the light emission intensity of the light-emitting device by controlling the amplitude, so it can accurately control even low brightness, which is difficult to control with PWM control.

[0136] The intermediate 96 gradations are achieved by varying the pulse signal width at a constant medium light intensity, thereby causing the light-emitting device to emit light. Because the intermediate 96 gradations do not require the use of extremely short light emission periods (pulse signals with extremely short widths), they can be controlled without any problems using PWM control.

[0137] For the high brightness 128 gradations, the PAM control operation is performed for a relatively long second light emission time, causing the light emitting device to emit light.

[0138] 13A is a diagram illustrating an example of the change in peak wavelength when the luminance of a light-emitting device is changed under PAM control. The difference between the minimum and maximum values ​​in such characteristics represents the range of chromaticity deviation (R1). When light is emitted under PAM control from low to high luminance, the chromaticity deviation is large, which can degrade display quality.

[0139] 13B is a diagram illustrating an example of a change in the peak wavelength of the luminance of a light-emitting device when the operation described with reference to FIGS. 12A and 12B is performed. Because PWM control is performed within a range near the minimum value in FIG. 13A, the peak wavelength within this range can be flattened. Therefore, the range of chromaticity deviation (R2) can be made smaller than R1. In other words, by using a display device according to one embodiment of the present invention and performing the above-described example operation, degradation of display quality can be alleviated.

[0140] In the configuration of the pixel 10a and the pixel 10b, when an OS transistor is used as the n-channel transistor, a back gate may be provided as shown in FIG. 14A or 14B . The on-state current can be increased by supplying the same potential as the front gate to the back gate. Alternatively, a constant potential may be supplied to the back gate. The threshold voltage can be controlled by supplying a constant potential to the back gate.

[0141] 15 is a block diagram illustrating a display device according to one embodiment of the present invention. The display device includes a pixel array 13, a first source driver 20a, a second source driver 20b, and a gate driver 30. The pixel array 13 includes pixels 10 arranged in the column and row directions. The pixel 10a or the pixel 10b described in this embodiment can be used as the pixel 10. Note that the wiring is illustrated simply, and wirings connected to elements included in the pixel 10 according to one embodiment of the present invention are provided.

[0142] Furthermore, a slope potential supply circuit 40 is provided and electrically connected to the pixel 10. The slope potential supply circuit 40 is electrically connected to a slope potential generation circuit 50.

[0143] A sequential circuit such as a shift register can be used for the first source driver 20a, the second source driver 20b, the gate driver 30, and the slope potential supply circuit 40. The first source driver 20a can supply a potential DATAW to the pixel 10. The second source driver 20b can supply a potential DATAA to the pixel 10.

[0144] The first source driver 20a, the second source driver 20b, the gate driver 30, and the slope potential supply circuit 40 can be formed on the layer 310 shown in Figures 2A and 2B. Alternatively, they can be provided on an IC chip connected by a COF (chip on film) method, a COG (chip on glass) method, a TCP (tape carrier package) method, or the like.

[0145] Although an example in which the gate driver 30 is arranged on one side of the pixel array 13 is shown, two gate drivers 30 may be arranged facing each other across the pixel array 13 to divide the driving rows.

[0146] <Simulation> Next, the results of a simulation of pixel operation will be described. Fig. 16 shows the configuration of a pixel PIX used in the simulation. The pixel PIX has a configuration similar to that of the pixel circuit shown in Fig. 1, with the transistor Tr1 being a p-channel Si transistor and the transistors Tr2 to Tr7 being n-channel OS transistors. Fig. 16 also shows the potentials supplied to the respective wirings.

[0147] The parameters in the simulation were as follows: The transistor sizes were W / L=3 μm / 3 μm (transistors Tr1, Tr2, Tr3, Tr5, and Tr7), and W / L=3 μm / 6 μm (transistors Tr4 and Tr6).

[0148] The capacitance of capacitors C1 and C2 was 20 fF, the potentials of the wiring connected to the gates of transistors Tr2, Tr3, Tr5, and Tr7 (RSTW, SCNW, SCNA, and RSTA) were +12 V for "H" and -7 V for "L," the power supply potential (LVDD) was +20 V, the power supply potential (LVSS) was -5 V, the potentials V0 and VB were 0 V, the potentials VER and VRESW were -5 V, the slope potential (SLO) was 0 to 10 V, and the light-emitting device was a red-emitting μLED with Vf = 1.3 V. SPICE was used as the circuit simulation software.

[0149] 17A shows the results of a simulation of the current flowing through the light-emitting device (LED) when the potential DATAW and the potential DATAA input to the pixel PIX within one frame period are set to +1 V to +8 V (in 1 V steps). The horizontal axis represents time (milliseconds), and it is assumed that the slope potential (SLO) changes from a minimum value to a maximum value within one frame period.

[0150] These results confirmed that as the values ​​of the potentials DATAW and DATAA increased, the current value increased and the light emission period became longer, confirming that PAM+PWM control (pulse width control accompanied by amplitude variation) was possible.

[0151] 17B is a graph plotting the current integral value against the digital input value. The digital input value corresponds to the gray level, and the current integral value corresponds to the brightness. The curve of the current integral value is proportional to the digital input value raised to the power γ (here, γ=3 because DATAW=DATAA), so it was confirmed that input and output can be performed according to the γ curve.

[0152] The above simulation results confirmed the effect of one aspect of the present invention.

[0153] This embodiment mode can be implemented in appropriate combination with any of the structures described in the other embodiment modes.

[0154] Embodiment 2 In this embodiment, a stacked structure of a display device according to one embodiment of the present invention, which is shown in FIGS. 2A and 2B, will be described.

[0155] 18A is a cross-sectional view of a display device 100A according to one embodiment of the present invention. The display device 100A includes a layer 310 including a transistor included in a driver circuit or the like of a pixel circuit, a layer 320 including a transistor, a wiring, or the like included in the pixel circuit, and a layer 330 including a light-emitting device such as an LED included in the pixel circuit, which are stacked in this order.

[0156] In this embodiment, for convenience, the display device is described as being divided into multiple layers, but the boundaries between the layers are not strictly defined. For example, even if an element is described as an element of layer 310, if the element is located near the boundary between layer 310 and layer 320, the element can also be considered an element of layer 320. Furthermore, as long as the function of the element is not impaired, the element may be located in a layer other than layer 310. Furthermore, in one embodiment of the present invention, in addition to the insulating layers and conductive layers of each layer, other insulating layers and other conductive layers may be provided as needed. Furthermore, some of the insulating layers and conductive layers of each layer may be omitted as needed.

[0157] The layer 310 includes, for example, a transistor 140, which is a component of a driver circuit (one or both of a gate driver and a source driver), a memory circuit, an arithmetic circuit, or the like of a pixel circuit. Because the transistor 140 is required to operate at high speed, it is preferable to use a transistor having silicon (single crystal silicon, polycrystalline silicon, amorphous silicon, or the like) in a channel formation region (hereinafter referred to as a Si transistor). Figure 18A shows an example in which single crystal silicon is used for the substrate 150, and the transistor 140 has a channel formation region in the substrate 150.

[0158] Note that a part of the driving circuit of the pixel circuit may be provided in an external IC chip connected to the pixel circuit.

[0159] The transistor 140 has a conductive layer 145, an insulating layer 144, an insulating layer 146, and a pair of low-resistance regions 143. The conductive layer 145 functions as a gate. The insulating layer 144 is located between the conductive layer 145 and a substrate 150 and functions as a gate insulating layer. The insulating layer 146 is provided to cover the side surfaces of the conductive layer 145 and functions as a sidewall. The pair of low-resistance regions 143 are regions in the substrate 150 doped with impurities, one of which functions as the source of the transistor and the other as the drain of the transistor. In addition, an element isolation layer 142 is provided around the transistor.

[0160] An insulating layer 149 is provided to cover the transistor 140, and a conductive layer 148 is provided over the insulating layer 149. A conductive layer 147 is embedded in an opening provided in the insulating layer 149. The conductive layer 148 is electrically connected to one of the pair of low-resistance regions 143 through the conductive layer 147. An insulating layer 151 is provided to cover the conductive layer 148. The conductive layer 148 functions as a wiring. The wiring can electrically connect another transistor, a pixel circuit, another circuit, or the like in a circuit including the transistor 140 as an element.

[0161] The layer 320 includes the transistor 160, insulating layer 152, insulating layer 162, insulating layer 163, insulating layer 181, insulating layer 182, insulating layer 183, conductive layer 184a, conductive layer 184b, insulating layer 185, insulating layer 186, insulating layer 187, conductive layer 192, conductive layer 195, conductive layer 196, and conductive layer 197, which are components of the pixel circuit. Although one or more of these elements may be considered as components of a transistor, in this embodiment, they will not be included in the components of a transistor. Note that each conductive layer and each insulating layer included in the layer 320 may have a stacked structure rather than a single-layer structure.

[0162] The insulating layer 152 is provided over the layer 310. The insulating layer 152 functions as a barrier layer that prevents impurities such as water and hydrogen from diffusing from the layer 310 to the transistor 160 and prevents oxygen from being released from the metal oxide layer 165 of the transistor 160 toward the layer 310. The insulating layer 152 can be, for example, a film through which hydrogen and oxygen are less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0163] The transistor 160 includes a conductive layer 161, an insulating layer 163, an insulating layer 164, a metal oxide layer 165, a pair of conductive layers 166, an insulating layer 167, a conductive layer 168, and the like.

[0164] The transistor 160 is preferably a transistor (OS transistor) having a channel formation region including a metal oxide layer 165. The metal oxide layer 165 includes a first region overlapping with one of the pair of conductive layers 166, a second region overlapping with the other of the pair of conductive layers 166, and a third region between the first and second regions.

[0165] The OS transistor can be formed in a region overlapping with a Si transistor via an insulating layer, without requiring a bonding process or the like. Therefore, a stacked device can be manufactured through a simple process, leading to reduced manufacturing costs.

[0166] Furthermore, compared to transistors using amorphous silicon, OS transistors have features such as high mobility, high-speed operation, and high reliability. Furthermore, metal oxides used in OS transistors can be formed in a film formation process, which eliminates the need for a laser device or the like that is required in a polycrystalline silicon crystallization process. Therefore, by using OS transistors, a display device with high reliability can be manufactured at low cost.

[0167] A conductive layer 161 and an insulating layer 162 are provided over the insulating layer 152, and an insulating layer 163 is provided to cover the conductive layer 161 and the insulating layer 162. An insulating layer 164 is provided over the insulating layer 163, and a metal oxide layer 165 is provided over the insulating layer 164.

[0168] The conductive layer 161 functions as a gate electrode, and the insulating layers 163 and 164 function as gate insulating layers. The conductive layer 161 has a region overlapping with the metal oxide layer 165 with the insulating layers 163 and 164 interposed therebetween. The insulating layer 163 is preferably formed using a material that functions as a barrier layer, similar to the insulating layer 152. The insulating layer 164 in contact with the metal oxide layer 165 is preferably an oxide insulating film such as a silicon oxide film.

[0169] A pair of conductive layers 166 are provided separately over the metal oxide layer 165. One of the pair of conductive layers 166 functions as a source of the transistor, and the other functions as a drain. An insulating layer 181 is provided to cover the metal oxide layer 165 and the pair of conductive layers 166, and an insulating layer 182 is provided over the insulating layer 181.

[0170] Openings reaching the metal oxide layer 165 are provided in the insulating layer 181 and the insulating layer 182, and the insulating layer 167 and the conductive layer 168 are embedded in the openings. The openings are provided at positions overlapping with the third region of the metal oxide layer 165. The insulating layer 167 has regions overlapping with side surfaces of the insulating layer 181 and the insulating layer 182. The conductive layer 168 has regions overlapping with side surfaces of the insulating layer 181 and the insulating layer 182, with the insulating layer 167 interposed therebetween.

[0171] The conductive layer 168 functions as a gate electrode, and the insulating layer 167 functions as a gate insulating layer. The conductive layer 168 has a region overlapping with the metal oxide layer 165 with the insulating layer 167 interposed therebetween.

[0172] An insulating layer 183 and an insulating layer 185 are provided to cover the upper surfaces of the insulating layer 182 , the insulating layer 167 , and the conductive layer 168 .

[0173] The insulating layers 181 and 183 are preferably formed using a material that functions as a barrier layer, similar to the insulating layer 152. Covering the pair of conductive layers 166 with the insulating layer 181 can prevent the pair of conductive layers 166 from being oxidized by oxygen contained in the insulating layer 182.

[0174] A plug electrically connected to one of the pair of conductive layers 166 and the conductive layer 195 is buried in an opening provided in the insulating layers 181, 182, 183, and 185. The plug can have a conductive layer 184b in contact with the side surface of the opening and the top surface of one of the pair of conductive layers 166, and a conductive layer 184a buried inward of the conductive layer 184b. The conductive layer 184b is preferably formed from a conductive material that is difficult for hydrogen and oxygen to diffuse into.

[0175] Conductive layer 192, conductive layer 195, and insulating layer 186 are provided on insulating layer 185. Furthermore, conductive layer 196, conductive layer 197, and insulating layer 187 are provided on insulating layer 186. Conductive layer 195 is electrically connected to conductive layer 196 via a plug. Conductive layer 192 is electrically connected to conductive layer 197 via a plug.

[0176] Here, the insulating layer 186 can have a planarization function. The insulating layer 187, the conductive layer 196, and the conductive layer 197 function as bonding layers. The conductive layer 196 and the conductive layer 197 have regions buried in the insulating layer 187.

[0177] Layer 330 has light-emitting device 110 provided on support layer 118. The side surface of light-emitting device 110 is sealed with insulating layer 189, and insulating layer 188, conductive layer 198, and conductive layer 199 are provided on the top surface of light-emitting device 110. Conductive layer 198 is electrically connected to one electrode of light-emitting device 110, and conductive layer 199 is electrically connected to the other electrode of light-emitting device 110. As insulating layer 189, it is preferable to use an insulating resin layer or the like.

[0178] Here, the insulating layer 188, the conductive layer 198, and the conductive layer 199 function as bonding layers. The conductive layer 198 and the conductive layer 199 have a region buried in the insulating layer 188.

[0179] The surfaces of layer 330 (insulating layer 188, conductive layer 198, and conductive layer 199) are bonded to the surfaces of layer 320 (insulating layer 187, conductive layer 196, and conductive layer 197). Here, insulating layer 188 is bonded to insulating layer 187 and joined. Conductive layer 198 is bonded to conductive layer 196 and joined, and the two are electrically connected. Conductive layer 199 is bonded to conductive layer 197 and joined, and the two are electrically connected.

[0180] Insulating layer 188 and insulating layer 187 are preferably made of the same component. Conductive layer 198 and conductive layer 196 are preferably made of the same metal as a main component. Conductive layer 199 and conductive layer 197 are preferably made of the same metal as a main component.

[0181] For example, the insulating layers 187 and 188 are preferably formed using a single layer or a stacked layer including one or more inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, hafnium oxide, or titanium nitride.

[0182] Copper, aluminum, tin, zinc, tungsten, silver, platinum, gold, or the like can be used for the conductive layers 196 to 199. In view of ease of bonding, copper, aluminum, tungsten, or gold is preferably used.

[0183] The transistor 160 can be used as a transistor that forms a pixel circuit. The transistor 140 can be used as a transistor that forms a driver circuit (such as a gate driver or a source driver, or both) for driving the pixel circuit. Note that the transistor 140 may also be a transistor that forms a pixel circuit. The transistors 140 and 160 can also be used as transistors that form various circuits such as an arithmetic circuit and a memory circuit.

[0184] With this configuration, not only elements such as transistors of the pixel circuit but also elements such as transistors of the driver circuit can be formed directly under the light-emitting device, which makes it possible to reduce the size of the display device compared to when the driver circuit is provided outside the display unit.Furthermore, it is possible to realize a display device with a narrow frame (a narrow non-display area).

[0185] The light-emitting device 110 has a semiconductor layer 113, a light-emitting layer 114, and a semiconductor layer 115, which are provided in this order on a support layer 118. A conductive layer 116 is provided on the semiconductor layer 113. The stack of the light-emitting layer 114 and the semiconductor layer 115 and the conductive layer 116 are covered with an insulating layer 117. The semiconductor layer 115 is electrically connected to a conductive layer 198 through a first opening provided in the insulating layer 117. The conductive layer 116 is electrically connected to a conductive layer 199 through a second opening provided in the insulating layer 117.

[0186] For example, gallium nitride formed by epitaxial growth on a sapphire substrate is used as support layer 118, and semiconductor layer 113, light-emitting layer 114, semiconductor layer 115, insulating layer 117, and conductive layer 116 formed on support layer 118 are processed to form multiple light-emitting devices 110. The multiple light-emitting devices formed in this process can be called a light-emitting device formed in a monolithic structure.

[0187] Then, an insulating layer 189 and a bonding layer are formed on the light-emitting devices 110, and a plurality of light-emitting devices 110 are bonded to the layer 320 in the same process. Then, a process of peeling off the sapphire substrate is performed, resulting in the structure shown in the display device 100A.

[0188] The light-emitting layer 114 is sandwiched between the semiconductor layer 113 and the semiconductor layer 115. In the light-emitting layer 114, electrons and holes combine to emit light. One of the semiconductor layer 113 and the semiconductor layer 115 can be an n-type semiconductor layer, and the other can be a p-type semiconductor layer. The light-emitting layer 114 can be an n-type, i-type, or p-type semiconductor layer.

[0189] The stacked layer structure including the semiconductor layer 113, the light-emitting layer 114, and the semiconductor layer 115 is formed to emit light of red, green, blue, blue-violet, purple, ultraviolet, or the like. For example, a compound including a Group 13 element and a Group 15 element (also referred to as a Group 3-5 compound) can be used for the stacked layer structure. Examples of Group 13 elements include aluminum, gallium, and indium. Examples of Group 15 elements include nitrogen, phosphorus, arsenic, and antimony.

[0190] For example, a pn junction or a pin junction can be formed using a gallium phosphide compound, a gallium arsenide compound, a gallium aluminum arsenide compound, an aluminum gallium indium phosphide compound, gallium nitride, an indium gallium nitride compound, a selenium zinc compound, etc., to fabricate a light-emitting device that emits the desired light. Note that compounds other than the above compounds may also be used.

[0191] Furthermore, the pn junction or pin junction of the light-emitting device 110 may be not only a homojunction but also a heterojunction or a double heterojunction. Alternatively, a light-emitting device having a quantum well junction or a light-emitting device using nanocolumns may be used.

[0192] For example, light-emitting devices that emit light in the ultraviolet to blue wavelength range can use materials such as gallium nitride. Light-emitting devices that emit light in the ultraviolet to green wavelength range can use materials such as indium gallium nitride compounds. Light-emitting devices that emit light in the green to red wavelength range can use materials such as aluminum gallium indium phosphide compounds or gallium arsenide compounds. Light-emitting devices that emit light in the infrared wavelength range can use materials such as gallium arsenide compounds.

[0193] If the plurality of light-emitting devices 110 provided on the same surface are configured to emit light of different colors, such as R (red), G (green), and B (blue), a color image can be displayed.

[0194] Alternatively, all the light-emitting devices 110 provided on the same surface may emit light of the same color. In this case, the light emitted from the light-emitting layer 114 is extracted to the outside of the display device via one or both of the color conversion layer and the colored layer. This configuration will be described in detail in embodiment 3.

[0195] The display device of this embodiment may also include a light-emitting device that emits infrared light, which can be used as a light source for an infrared light sensor, for example.

[0196] Note that while Figure 18A shows a form in which layer 330 is bonded to layer 320, a configuration in which a single light-emitting device 110 is mounted using a flip-chip bonder or the like and sealed with an insulating layer 189 may also be used, as in the display device 100B shown in Figure 18B.

[0197] This embodiment mode can be implemented in appropriate combination with any of the structures described in the other embodiment modes.

[0198] This embodiment describes a configuration in which a color conversion layer is provided on the light emission side of a light-emitting device in the display device described in Embodiment 2. Note that detailed description of components common to Embodiment 2 will be omitted.

[0199] 19 shows a cross-sectional view of a display device 100E. The display device 100E has a pixel 20R that emits red light, a pixel 20G that emits green light, and a pixel 20B that emits blue light. A layer 340 is provided on the layer 330 on which the light-emitting device is provided. A color conversion layer, a colored layer, a light-shielding layer, and the like are provided on the layer 340.

[0200] The pixel 20R has a light-emitting device 110R. The pixel 20G has a light-emitting device 110G. The pixel 20B has a light-emitting device 110B. The light-emitting devices 110R, 110G, and 110B each emit light of the same color. That is, the light-emitting devices 110R, 110G, and 110B can each have the same configuration.

[0201] Specifically, it is preferable that each of the light-emitting devices 110R, 110G, and 110B emit blue light. To construct a color image, pixels that emit light of the three primary colors of red (R), green (G), and blue (B) can be used. In the display device described in this embodiment, a color conversion layer is used in the pixels to convert light emitted by the light-emitting devices into light of the required color and emit it to the outside. Here, if a light-emitting device that emits blue light is used, there is no need to use a color conversion layer in the blue-emitting pixels, thereby reducing manufacturing costs.

[0202] The red pixel 20R is provided with a color conversion layer 360R and a coloring layer 361R in a region overlapping with the light-emitting device 110R. The light emitted by the light-emitting device 110R is converted from blue to red by the color conversion layer 360R, and the purity of the red light is increased by the coloring layer 361R before being emitted to the outside of the display device 100E. Note that the coloring layer 361R may be omitted.

[0203] The green pixel 20G is provided with a color conversion layer 360G and a coloring layer 361G in a region overlapping with the light-emitting device 110G. The light emitted by the light-emitting device 110G is converted from blue to green by the color conversion layer 360G, and the purity of the green light is increased by the coloring layer 361G before being emitted to the outside of the display device 100E. Note that the coloring layer 361G may be omitted.

[0204] The blue pixel 20B is provided with a coloring layer 361B in a region overlapping with the light-emitting device 110B. The purity of the blue light emitted by the light-emitting device 110B is increased by the coloring layer 361B, and the light is emitted to the outside of the display device 100E. Note that the coloring layer 361B may be omitted. As described above, the color conversion layer can be omitted from the blue pixel 20B.

[0205] In the display device 100E, it is only necessary to fabricate one type of light-emitting device on the substrate, and therefore the manufacturing equipment and process can be simplified compared to when a plurality of types of light-emitting devices are fabricated.

[0206] A light-shielding layer 350 is provided between the pixels of each color. The light-shielding layer 350 is provided at a position where it blocks at least the light emitted laterally by the light-emitting device 110. If necessary, it may also be provided at a position where it blocks the light emitted obliquely by the light-emitting device 110. In addition, a light-shielding layer 351 that covers the periphery of the pixels is provided on the support layer 118.

[0207] By providing the light-shielding layer 350 and the light-shielding layer 351, it is possible to prevent light emitted by the light-emitting device from entering adjacent pixel regions of other colors, thereby preventing color mixing. Therefore, it is possible to improve the display quality of the display device. Note that a configuration in which only one of the light-shielding layer 350 and the light-shielding layer 351 is provided may also be used.

[0208] The material constituting the light-shielding layer 350 and the light-shielding layer 351 is not particularly limited, and may be, for example, an inorganic material such as a metal material, or an organic material such as a resin containing a pigment (carbon black, etc.) or a dye. The light-shielding layer 351 may also be formed by laminating colored layers of each color. For example, it may be formed by laminating colored layers of three colors: red, green, and blue.

[0209] Furthermore, each of the light-emitting devices 110R, 110G, and 110B may be configured to emit light with a wavelength having a higher photon energy than blue light. For example, a light-emitting device capable of emitting blue-violet, purple, or ultraviolet light (UV light) may be used. Using light with high photon energy allows efficient color conversion in the color conversion layer.

[0210] 20, a color conversion layer 360B and a coloring layer 361B are provided in the blue pixel 20B in a region overlapping with the light-emitting device 110B. The light emitted by the light-emitting device 110B is converted from blue-violet, purple, or ultraviolet to blue by the color conversion layer 360B, and the purity of the blue light is increased by the coloring layer 361B before being emitted to the outside of the display device 100E. Note that the coloring layer 361B may be omitted.

[0211] It is preferable to use a phosphor or quantum dots (QD) for the color conversion layer. Quantum dots, in particular, have a narrow peak width in the emission spectrum, and can emit light with good color purity. This can improve the display quality of the display device.

[0212] The color conversion layer can be formed by a droplet ejection method (for example, an inkjet method), a coating method, an imprint method, various printing methods (screen printing, offset printing), etc. A color conversion film such as a quantum dot film may also be used.

[0213] Lithography can be used to process a film that will become a color conversion layer. For example, a method can be used in which a resist mask is formed on the thin film to be processed, the thin film is processed by etching or the like, and the resist mask is then removed. Alternatively, a method can be used in which a photosensitive thin film is formed, and then the thin film is processed into a desired shape by exposure and development. For example, an island-shaped color conversion layer can be formed by forming a thin film using a photosensitive material mixed with quantum dots and processing the thin film using lithography.

[0214] The material constituting the quantum dots is not particularly limited, and examples thereof include a Group 14 element, a Group 15 element, a Group 16 element, a compound consisting of multiple Group 14 elements, a compound of an element belonging to Groups 4 to 14 and a Group 16 element, a compound of a Group 2 element and a Group 16 element, a compound of a Group 13 element and a Group 15 element, a compound of a Group 13 element and a Group 17 element, a compound of a Group 14 element and a Group 15 element, a compound of a Group 11 element and a Group 17 element, iron oxides, titanium oxides, chalcogenide spinels, and various semiconductor clusters.

[0215] Specifically, cadmium selenide, cadmium sulfide, cadmium telluride, zinc selenide, zinc oxide, zinc sulfide, zinc telluride, mercury sulfide, mercury selenide, mercury telluride, indium arsenide, indium phosphide, gallium arsenide, gallium phosphide, indium nitride, gallium nitride, indium antimonide, gallium antimonide, aluminum phosphide, aluminum arsenide, aluminum antimonide, lead selenide, lead telluride, lead sulfide, indium selenide, and tellurium Indium sulfide, indium sulfide, gallium selenide, arsenic sulfide, arsenic selenide, arsenic telluride, antimony sulfide, antimony selenide, antimony telluride, bismuth sulfide, bismuth selenide, bismuth telluride, silicon, silicon carbide, germanium, tin, selenium, tellurium, boron, carbon, phosphorus, boron nitride, boron phosphide, boron arsenide, aluminum nitride, aluminum sulfide, barium sulfide, barium selenide, barium telluride, calcium sulfide, calcium selenide Calcium, calcium telluride, beryllium sulfide, beryllium selenide, beryllium telluride, magnesium sulfide, magnesium selenide, germanium sulfide, germanium selenide, germanium telluride, tin sulfide, tin selenide, tin telluride, lead oxide, copper fluoride, copper chloride, copper bromide, copper iodide, copper oxide, copper selenide, nickel oxide, cobalt oxide, cobalt sulfide, iron oxide, iron sulfide, manganese oxide, molybdenum sulfide, vanadium oxide, tungsten oxide, tantalum oxide Examples of the quantum dots include ZnO, titanium oxide, zirconium oxide, silicon nitride, germanium nitride, aluminum oxide, barium titanate, a compound of selenium, zinc, and cadmium, a compound of indium, arsenic, and phosphorus, a compound of cadmium, selenium, and sulfur, a compound of cadmium, selenium, and tellurium, a compound of indium, gallium, and arsenic, a compound of indium, gallium, and selenium, a compound of indium, selenium, and sulfur, a compound of copper, indium, and sulfur, and combinations thereof. Also, so-called alloy-type quantum dots, whose composition is expressed in any ratio, may be used.

[0216] Quantum dot structures include core, core-shell, and core-multishell types. Quantum dots have a high proportion of surface atoms, making them highly reactive and prone to aggregation. Therefore, to prevent quantum dot aggregation and improve their dispersibility in a dispersion medium, it is preferable that a protective agent be attached to the surface of the quantum dots or that protective groups be provided. This also reduces reactivity and improves electrical stability.

[0217] Since the band gap of quantum dots increases as their size decreases, their size can be adjusted appropriately to obtain light of the desired wavelength. As the crystal size decreases, the emission of quantum dots shifts toward the blue side, i.e., toward higher energy. Therefore, by changing the size of the quantum dots, the emission wavelength can be adjusted across the wavelength ranges of the ultraviolet, visible, and infrared spectral regions. The size (diameter) of the quantum dots is, for example, 0.5 nm or more and 20 nm or less, preferably 1 nm or more and 10 nm or less. The narrower the size distribution of quantum dots, the narrower the emission spectrum, and the more excellent the color purity of the light emitted. Furthermore, the shape of the quantum dots is not particularly limited and may be spherical, rod-shaped, disc-shaped, or other shapes. Quantum rods, which are rod-shaped quantum dots, have the function of emitting directional light.

[0218] The colored layer is a colored layer that transmits light in a specific wavelength range. For example, a color filter that transmits light in the red, green, blue, or yellow wavelength range can be used. Materials that can be used for the colored layer include metal materials, resin materials, and resin materials containing pigments or dyes.

[0219] Although the basic configuration of the display device 100E and the display device 100F has been exemplified using the configuration of the display device 100A, the display device 100B shown in the second embodiment can also be applied.

[0220] This embodiment mode can be implemented in appropriate combination with any of the structures described in the other embodiment modes.

[0221] Embodiment 4 In this embodiment, a display device of one embodiment of the present invention will be described with reference to FIGS. 21A and 21B.

[0222] The display device of the present embodiment can be a high-definition display device, and therefore can be used, for example, as a display unit of a wristwatch-type, bracelet-type, or other information terminal (wearable device), as well as a display unit of a wearable device that can be worn on the head, such as a head-mounted display (HMD) or other VR (Virtual Reality) device, or a glasses-type AR (Augmented Reality) device.

[0223] 21A shows a perspective view of a display module 280. The display module 280 includes the display device 100A described in the previous embodiment and an FPC 290. Note that the display device included in the display module 280 is not limited to the display device 100A, and may be any of the display devices 100B, 100E, and 100F.

[0224] The display module 280 has a substrate 291 and a substrate 292. The display module 280 has a display unit 281. The display unit 281 is a region that displays an image in the display module 280, and is a region where light from each pixel provided in a pixel unit 284 (described later) can be viewed.

[0225] 21B is a perspective view schematically illustrating the configuration on the substrate 291 side. A circuit portion 282, a pixel circuit portion 283 on the circuit portion 282, and a pixel portion 284 on the pixel circuit portion 283 are stacked on the substrate 291. A terminal portion 285 for connecting to the FPC 290 is provided in a portion of the substrate 291 that does not overlap with the pixel portion 284. The terminal portion 285 and the circuit portion 282 are electrically connected by a wiring portion 286 composed of a plurality of wirings.

[0226] The pixel section 284 has a plurality of periodically arranged pixels 284a. An enlarged view of one pixel 284a is shown on the right side of Fig. 21B. The pixel 284a has a plurality of sub-pixels (sub-pixels 10R, 10G, and 10B) that emit light of different colors. The pixel configurations described in the previous embodiments can be applied to these sub-pixels.

[0227] The pixel circuit section 283 has a plurality of pixel circuits 283a arranged periodically.

[0228] One pixel circuit 283a is a circuit that controls the driving of multiple elements included in one pixel 284a. One pixel circuit 283a can be configured to have three circuits that control the light emission of one light-emitting device. For example, the pixel circuit 283a can be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting device. In this case, a gate signal is input to the gate of the selection transistor, and a source signal is input to the source. This realizes an active matrix display device.

[0229] The circuit portion 282 includes a circuit for driving each pixel circuit 283 a of the pixel circuit portion 283. For example, it is preferable that the circuit portion 282 includes one or both of a gate line driver circuit and a source line driver circuit. In addition, the circuit portion 282 may include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like.

[0230] The FPC 290 functions as wiring for supplying a video signal, a power supply potential, or the like from the outside to the circuit portion 282. An IC may be mounted on the FPC 290.

[0231] The display module 280 can be configured such that one or both of the pixel circuit unit 283 and the circuit unit 282 are provided overlapping the pixel unit 284, thereby enabling the aperture ratio (effective display area ratio) of the display unit 281 to be extremely high. For example, the aperture ratio of the display unit 281 can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixels 284a can be arranged at an extremely high density, enabling the resolution of the display unit 281 to be extremely high. For example, it is preferable that the pixels 284a be arranged in the display unit 281 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20,000 ppi or less, or 30,000 ppi or less.

[0232] Because such a display module 280 has extremely high resolution, it can be suitably used in VR devices such as HMDs or eyeglass-type AR devices. For example, even in a configuration in which the display unit of the display module 280 is viewed through lenses, the display module 280 has an extremely high-resolution display unit 281, so even when the display unit is enlarged with lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 280 is not limited to this, and can be suitably used in electronic devices with relatively small displays. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0233] This embodiment mode can be implemented in appropriate combination with any of the structures described in the other embodiment modes.

[0234] Embodiment 5 In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS. 22A to 22D. FIG.

[0235] The electronic devices of this embodiment include the display device of one embodiment of the present invention in their display portions. The display device of one embodiment of the present invention can easily achieve high definition and high resolution. Therefore, the display device of one embodiment of the present invention can be used in the display portions of various electronic devices.

[0236] The display device of one embodiment of the present invention can have high resolution and can therefore be suitably used in electronic devices having a relatively small display area. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices such as head-mounted displays, AR glasses-type devices, and mixed reality (MR) devices.

[0237] The display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or higher, more preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display device having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth in electronic devices for portable or home use. Furthermore, the screen ratio (aspect ratio) of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, and 16:10.

[0238] The electronic device of this embodiment may have a sensor (including the function of detecting, detecting, or measuring force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0239] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

[0240] 22A to 22D , examples of wearable devices that can be worn on the head will be described. These wearable devices have at least one of the following functions: a function to display AR content, a function to display VR content, a function to display SR (Substitutional Reality) content, and a function to display MR content. By having an electronic device with the function to display at least one of AR, VR, SR, and MR content, it is possible to enhance the sense of immersion felt by the user.

[0241] The electronic device 700A shown in FIG. 22A and the electronic device 700B shown in FIG. 22B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0242] The display device of one embodiment of the present invention can be applied to the display panel 751. Therefore, the electronic device can provide an extremely high-definition display.

[0243] Furthermore, if the display device has a light-receiving device, the light-receiving device can capture an image of the user's pupils and perform iris authentication. The light-receiving device can also be used to track the user's gaze. By tracking the user's gaze, it is possible to identify what the user is looking at and where they are, allowing the user to select functions that the electronic device has and execute software.

[0244] Each of electronic devices 700A and 700B can project an image displayed on display panel 751 onto display area 756 of optical member 753. Because optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through optical member 753. Therefore, each of electronic devices 700A and 700B is an electronic device capable of AR display.

[0245] Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image of the front as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.

[0246] The communication unit has a wireless communication device, and can supply a video signal, etc. Instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential are supplied may be provided.

[0247] Furthermore, the electronic device 700A and the electronic device 700B are provided with batteries, which can be charged wirelessly and / or by wire.

[0248] The electronic device 800A shown in FIG. 22C and the electronic device 800B shown in FIG. 22D each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0249] The display device of one embodiment of the present invention can be applied to the display portion 820. Therefore, an electronic device capable of displaying images with extremely high definition can be provided. This allows a user to feel a high sense of immersion.

[0250] The display unit 820 is provided inside the housing 821 at a position that can be viewed through the lens 832. In addition, by displaying different images on the pair of display units 820, it is possible to perform three-dimensional display using parallax.

[0251] The electronic device 800A and the electronic device 800B can be said to be electronic devices for VR. A user wearing the electronic device 800A or the electronic device 800B can view an image displayed on the display unit 820 through the lens 832.

[0252] It is preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the left and right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the focus by changing the distance between lens 832 and display unit 820.

[0253] The mounting unit 823 allows the user to mount the electronic device 800A or the electronic device 800B on the head. Note that, in Fig. 22C and other figures, the mounting unit 823 is shaped like the temples of glasses, but is not limited to this. The mounting unit 823 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0254] The imaging unit 825 has a function of acquiring external information. Data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide-angle.

[0255] Although an example including the imaging unit 825 is shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object may be provided. That is, the imaging unit 825 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a range image sensor such as a LiDAR (Light Detection and Ranging) can be used. By using an image obtained by the camera and an image obtained by the range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0256] The electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of the display unit 820, the housing 821, and the wearing unit 823. This allows a user to enjoy video and audio simply by wearing the electronic device 800A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0257] The electronic device 800A and the electronic device 800B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device.

[0258] The electronic device of one embodiment of the present invention may have a function of wireless communication with an earphone 750. The earphone 750 includes a communication unit (not shown) and has a wireless communication function. The earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, the electronic device 700A shown in FIG. 22A has a function of transmitting information to the earphone 750 through the wireless communication function. Furthermore, for example, the electronic device 800A shown in FIG. 22C has a function of transmitting information to the earphone 750 through the wireless communication function.

[0259] The electronic device may also have an earphone unit. Electronic device 700B shown in Fig. 22B has earphone unit 727. For example, earphone unit 727 and the control unit may be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or wearing unit 723.

[0260] Similarly, electronic device 800B shown in Fig. 22D has earphone unit 827. For example, earphone unit 827 and control unit 824 can be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or wearing unit 823. Furthermore, earphone unit 827 and wearing unit 823 may have magnets. This allows earphone unit 827 to be fixed to wearing unit 823 by magnetic force, which is preferable as it makes storage easier.

[0261] The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

[0262] As such, as electronic devices of one embodiment of the present invention, both glasses-type devices (such as the electronic devices 700A and 700B) and goggle-type devices (such as the electronic devices 800A and 800B) are suitable.

[0263] Furthermore, the electronic device of one embodiment of the present invention can transmit information to the earphone by wire or wirelessly.

[0264] Furthermore, an electronic device to which a display device according to one embodiment of the present invention can be applied may be connected to an external server via a network. Furthermore, instead of performing processing requiring high computing power in the electronic device, the processing requiring high computing power may be performed by a server connected via a network. Such processing is also called a thin client, in which a user (client) terminal (electronic device in this case) performs only limited processing, and advanced processing such as application execution and management is performed by the server, thereby reducing the scale of processing required by the client terminal. This eliminates the need for a computing device with high computing performance in the electronic device, thereby facilitating cost reduction, weight reduction, and miniaturization. Furthermore, in the electronic device according to one embodiment of the present invention, the above-described thin client and processing requiring high computing power in the electronic device may be performed in combination.

[0265] This embodiment mode can be implemented in appropriate combination with any of the structures described in the other embodiment modes.

[0266] DATAA: potential, DATAW: potential, PIX: pixel, SLO: slope potential, VB: potential, VER: potential, VRESW: potential, 10a: pixel, 10B: sub-pixel, 10b: pixel, 10G: sub-pixel, 10R: sub-pixel, 10: pixel, 11: pulse signal generation unit, 12: light emission control unit, 13: pixel array, 20a: first source driver, 20B: pixel, 20b: second source driver, 20G: pixel, 20R: pixel, 30: gate driver, 40: slope potential supply circuit, 50: slope potential generation circuit, 100A: display device, 100B: display device, 100E: display Device, 100F: display device, 101: transistor, 102: transistor, 103: transistor, 104: transistor, 105: transistor, 106: transistor, 107: transistor, 108: transistor, 110B: light-emitting device, 110G: light-emitting device, 110R: light-emitting device, 110: light-emitting device, 111: capacitor, 112: capacitor, 113: semiconductor layer, 114: light-emitting layer, 115: semiconductor layer, 116: conductive layer, 117: insulating layer, 118: support layer, 121: wiring, 122: wiring, 123: wiring, 124: wiring, 125 : wiring, 126: wiring, 127: wiring, 128: wiring, 129: wiring, 131: wiring, 132: wiring, 133: wiring, 134: wiring, 135: wiring, 140: transistor, 142: element isolation layer, 143: low resistance region, 144: insulating layer, 145: conductive layer, 146: insulating layer, 147: conductive layer, 148: conductive layer, 149: insulating layer, 150: substrate, 151: insulating layer, 152: insulating layer, 160: transistor, 161: conductive layer, 162: insulating layer, 163: insulating layer, 164: insulating layer, 165: metal oxide layer, 166: conductive layer, 167: insulating layer, 168: conductive layer, 18 1: insulating layer, 182: insulating layer, 183: insulating layer, 184a: conductive layer, 184b: conductive layer, 185: insulating layer, 186: insulating layer, 187: insulating layer, 188: insulating layer, 189: insulating layer, 192: conductive layer, 195: conductive layer, 196: conductive layer, 197: conductive layer, 198: conductive layer, 199: conductive layer, 280: display module, 281: display section, 282: circuit section, 283a: pixel circuit, 283: pixel circuit section, 284a: pixel, 284: pixel section, 285: terminal section, 286: wiring section, 290: FPC, 291: substrate, 292: substrate, 310: layer, 311: Si transistor,312: functional circuit, 320: layer, 321: OS transistor, 330: layer, 331: LED array, 340: layer, 350: light-shielding layer, 351: light-shielding layer, 360B: color conversion layer, 360G: color conversion layer, 360R: color conversion layer, 361B: colored layer, 361G: colored layer, 361R: colored layer, 700A: electronic device, 700B: electronic device, 721: housing, 723: equipment Attachment part, 727: earphone part, 750: earphone, 751: display panel, 753: optical member, 756: display area, 757: frame, 758: nose pad, 800A: electronic device, 800B: electronic device, 820: display part, 821: housing, 822: communication part, 823: attachment part, 824: control part, 825: imaging part, 827: earphone part, 832: lens,

Claims

1. a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and a light emitting device; a gate of the first transistor is electrically connected to one of the source or the drain of the second transistor, one of the source or the drain of the third transistor, and one electrode of the first capacitor; one of a source and a drain of the first transistor is electrically connected to one electrode of the light-emitting device and the other electrode of the first capacitor; a gate of the third transistor is electrically connected to one of the source or the drain of the fourth transistor and one of the source or the drain of the fifth transistor; a gate of the fourth transistor is electrically connected to one of a source or a drain of the sixth transistor and one electrode of the second capacitor; the first transistor, the second transistor, the third transistor, the fifth transistor, and the sixth transistor are n-channel transistors, and the fourth transistor is a p-channel transistor; a display device in which the first transistor, the second transistor, the fifth transistor, and the sixth transistor each have a metal oxide in a channel formation region, and the third transistor and the fourth transistor each have silicon in a channel formation region;

2. a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a first capacitor, a second capacitor, and a light emitting device; a gate of the first transistor is electrically connected to one of the source or the drain of the second transistor, one of the source or the drain of the third transistor, and one electrode of the first capacitor; one of the source and the drain of the first transistor is electrically connected to one electrode of the light-emitting device; the other of the source and the drain of the first transistor is electrically connected to the other electrode of the first capacitor; a gate of the third transistor is electrically connected to one of the source or the drain of the fourth transistor and one of the source or the drain of the fifth transistor; a gate of the fourth transistor is electrically connected to one of a source or a drain of the sixth transistor and one electrode of the second capacitor; the second transistor, the fourth transistor, and the sixth transistor are n-channel transistors, and the first transistor, the third transistor, and the fifth transistor are p-channel transistors; a display device in which the second transistor, the fourth transistor, and the sixth transistor have metal oxide in a channel formation region, and the first transistor, the third transistor, and the fifth transistor have silicon in a channel formation region;