Analog-to-digital conversion circuit and current measuring circuit

Abstract

An analog-to-digital conversion circuit comprising: a first gain-variable amplifier (104) connected to an input terminal (2); a first AD converter (105) connected to the first gain-variable amplifier; a second gain-variable amplifier (204) connected to the input terminal (2); a second AD converter (205) connected to the second gain-variable amplifier (204); a selection circuit (6) to which an output of the first AD converter (105) and an output of the second AD converter (205) are input and which selects one of the outputs; and a control circuit (20) for relatively controlling the respective gain-change times of the first gain-variable amplifier (104) and the second gain-variable amplifier (204).

Description

Analog-to-digital conversion circuit and current measurement circuit

[0001] The present disclosure relates to analog-to-digital conversion circuits and current measurement circuits.

[0002] Patent Document 1 discloses an A / D converter that includes an ADC (Analog Digital Converter) that performs AD conversion of an analog signal and another ADC that performs AD conversion of a low-level analog signal, thereby improving conversion accuracy.

[0003] Patent Document 2 discloses a technology for performing gain control using an analog-to-digital conversion circuit that performs AD conversion of the voltage across a shunt resistor for detecting the battery current of a vehicle.

[0004] Furthermore, in electric vehicles, if an overcurrent that exceeds the allowable range flows through a lithium-ion battery pack, it can significantly reduce the battery's lifespan and even destroy it. Therefore, extremely high safety requirements are placed on the measurement of lithium-ion battery pack current in electric vehicles, and it must meet the requirements of ASIL-D (Automotive Safety Integrity Level D), the highest functional safety level based on ISO 26262. Therefore, current measurement AD converters in integrated circuits that measure current require redundancy, and by measuring the same current value with two or more AD converters, the accuracy of the measurement is guaranteed and redundancy is ensured.

[0005] Furthermore, in electric vehicles powered by lithium-ion battery packs, the output current value of the lithium-ion battery pack fluctuates rapidly and irregularly from a few mA to several hundred A when the vehicle is at full stop to maximum output. The range of this fluctuation is more than 100,000 times, so a dynamic range of 120 dB or more is required for current measurement.

[0006] For this reason, in such high dynamic range measurement circuits, it is common to install a variable gain amplifier (hereinafter referred to as VGA (Variable Gain Amplifier)) in the stage preceding the AD converter to expand the dynamic range of the AD converter and achieve both the dynamic range and resolution of the AD converter, which are in a trade-off relationship.

[0007] Furthermore, a system that allows the amplification factor of a VGA to be automatically changed in accordance with the input amplitude is called an automatic gain control (AGC).

[0008] U.S. Patent No. 6,172,653 U.S. Patent No. 9,397,690

[0009] However, since VGAs generally have frequency characteristics similar to those of a low-pass filter, which has a band-limited characteristic, as shown in Figure 7, the output signal immediately after the gain change begins changes gradually due to a frequency response caused by a phase delay, making it impossible for the AD converter to obtain an accurate measurement value during the gain change time until the output signal stabilizes. Furthermore, phase delays also occur in AD converters such as delta-sigma and integral types. Therefore, the waiting time from the start of the gain change until an accurate measurement value is obtained requires a time longer than the AD converter's sampling time.

[0010] The present disclosure aims to provide an analog-to-digital conversion circuit and a current measurement circuit that reduces the latency between the start of a gain change and obtaining a correct measurement.

[0011] In order to achieve the above object, an analog-to-digital conversion circuit according to one embodiment of the present disclosure comprises a first variable gain amplifier connected to an input terminal, a first AD converter connected to the first variable gain amplifier, a second variable gain amplifier connected to the input terminal, a second AD converter connected to the second variable gain amplifier, a selection circuit to which the output of the first AD converter and the output of the second AD converter are input, and a control circuit that relatively controls the gain change time of the first variable gain amplifier and the second variable gain amplifier.

[0012] Moreover, a current measurement circuit according to an aspect of the present disclosure includes the above analog-to-digital conversion circuit.

[0013] The analog-to-digital conversion circuit and current measurement circuit of the present disclosure can reduce the waiting time from when the gain change starts until a correct measurement value is obtained.

[0014] FIG. 1 is a diagram showing a configuration example of an analog-digital conversion circuit according to a first embodiment. FIG. 2A is a time chart showing an operation example of the analog-digital conversion circuit according to the first embodiment. FIG. 2B is a time chart showing another operation example of the analog-digital conversion circuit according to the first embodiment. FIG. 3 is a diagram showing a configuration example of an analog-digital conversion circuit according to a second embodiment. FIG. 4 is an explanatory diagram showing an example of AGC operation of the analog-digital conversion circuit according to the second embodiment. FIG. 5 is a diagram showing a configuration example of an analog-digital conversion circuit according to a third embodiment. FIG. 6 is a time chart showing an operation example of the analog-digital conversion circuit according to the third embodiment. FIG. 7 is a diagram showing the characteristics of a variable gain amplifier.

[0015] Hereinafter, an embodiment of an analog-to-digital converter circuit according to one aspect of the present disclosure will be specifically described with reference to the drawings.

[0016] It should be noted that the embodiments described below each illustrate a comprehensive or specific example of the present disclosure. The numerical values, shapes, materials, components, component placement and connection configurations, steps, and step order shown in the following embodiments are merely examples and are not intended to limit the present disclosure. Furthermore, among the components in the following embodiments, components that are not described in the independent claims that represent the highest concept are described as optional components.

[0017] 1 is a diagram showing an example of the configuration of an analog-to-digital conversion circuit 1 according to embodiment 1. In addition to the analog-to-digital conversion circuit 1, the diagram also shows an electric circuit that outputs an analog signal to be converted.

[0018] This electric circuit is, for example, a circuit mounted on an electric vehicle or a hybrid vehicle, and includes a motor M, a battery pack 17 and a shunt resistor 15 .

[0019] The motor M generates rotational driving force for running the vehicle using power supplied from the battery pack 17, and also generates regenerative power during deceleration to charge the battery pack 17.

[0020] The battery pack 17 is composed of one or more battery cells. The battery cells are, for example, lithium ion batteries. The battery cells may also be storage capacitor cells.

[0021] The shunt resistor 15 is a resistive element for detecting current and has a small resistance value. The voltage drop across the shunt resistor 15 is proportional to the current flowing through the battery pack 17. A magnetic circuit may be provided as a current sensor instead of the shunt resistor 15. The magnetic circuit may include a magnetic core and be of a magnetic proportional type (i.e., an open loop type). The magnetic circuit may also be of a magnetic balance type (i.e., a servo type) or a fluxgate type (i.e., a magnetic balance type) that includes a magnetic core and a coil.

[0022] The analog-to-digital conversion circuit 1 in FIG. 1 includes an input terminal 2, a first variable gain amplifier 104, a first AD converter 105, a first divider 106, a second variable gain amplifier 204, a second AD converter 205, a second divider 206, a control circuit 20, an averaging circuit 3, a selection circuit 6, and an error detection circuit 10.

[0023] Input terminal 2 is a pair of terminals connected to both ends of shunt resistor 15. The voltage appearing at this pair of terminals is the voltage drop across shunt resistor 15, and is an analog signal indicating the magnitude of the current flowing through battery pack 17. One of the pair of terminals is connected to one of the two input terminals of first variable gain amplifier 104 via input resistor 101. The other of the pair of terminals is connected to the other of the two input terminals of first variable gain amplifier 104 via input resistor 102. A capacitance element 103 for noise reduction is added between the two input terminals of first variable gain amplifier 104.

[0024] The first variable gain amplifier 104 is a variable gain amplifier having two input terminals, two output terminals, and a gain control terminal. A gain control signal G1 that indicates a gain is input to the gain control terminal. The first variable gain amplifier 104 amplifies the input analog signal with the gain indicated by the gain control signal G1 and outputs the amplified analog signal to the first AD converter 105.

[0025] The gain control signal G1 is assumed to be provided from a higher-level system external to the analog-to-digital conversion circuit 1. In Fig. 1, the gain control signal G1 shows an example in which the gain control signal G1 instructs the first variable gain amplifier 104 to have a gain of 1, 2, 4, or 8. Note that the gain indicated by the gain control signal G1 may be any other power of 2, or may not be a power of 2.

[0026] The first AD converter 105 converts the analog signal from the first variable gain amplifier 104 into a digital signal. The first AD converter 105 may be a delta-sigma type or an integral type. The combination of the first AD converter 105 and the first variable gain amplifier 104 can expand the dynamic range of the first AD converter 105 and improve the resolution, which is in a trade-off relationship.

[0027] The first divider 106 divides the digital signal from the first AD converter 105 by the gain indicated by the gain control signal G1. The weight of each bit of the digital signal resulting from the division remains unchanged before and after the gain indicated by the gain control signal G1 is changed. When the gain indicated by the gain control signal G1 is expressed as a power of 2, the first divider 106 performs division by bit shifting.

[0028] The circuit portion (hereinafter also referred to as the second system) of the second variable gain amplifier 204, the second AD converter 205, and the second divider 206 may have the same configuration as the circuit portion (hereinafter also referred to as the first system) of the first variable gain amplifier 104, the first AD converter 105, and the first divider 106. In other words, the above two circuit portions may have a redundantly duplicated configuration.

[0029] The control circuit 20 receives gain signals EG1 and EG2 that indicate the gains from an external device, and controls the gains of the first variable gain amplifier 104 and the second variable gain amplifier 204, as well as the divisors of the first divider 106 and the second divider 206. In this case, the control circuit 20 relatively controls the gain change times of the first variable gain amplifier 104 and the second variable gain amplifier 204. Here, the gain change time refers to the time from when the gain change starts until the output stabilizes. For example, the control circuit 20 controls the gain change so that the gain change time of the first variable gain amplifier 104 and the gain change time of the second variable gain amplifier 204 do not overlap. The control circuit 20 may also control between a normal operation mode in which the first variable gain amplifier 104 and the second variable gain amplifier 204 operate at the same gain, and a gain change mode in which the gains of the normal operation mode are changed to other gains and the normal operation mode is restored. In this normal operation mode, the gain signals EG1 and EG2 are changed almost simultaneously by the control circuit 20. For example, when one of the gain signals EG1 and EG2 is changed, the control circuit 20 first changes the gain of the first variable gain amplifier 104, waits for a lapse of time between gain changes, and then changes the gain of the second variable gain amplifier 204.

[0030] The control circuit 20 in FIG. 1 includes a timer 111, a timer 211, a timer 23, and a timing control circuit 24, and controls the gain change so that the gain change time of the first variable gain amplifier 104 and the gain change time of the second variable gain amplifier 204 do not overlap.

[0031] The timer 111 counts the gain change time of the first variable gain amplifier 104. That is, under the control of the timing control circuit 24, the timer 111 measures a fixed time from when the gain change of the first variable gain amplifier 104 starts until the output stabilizes.

[0032] The timer 211 counts the gain change time of the first variable gain amplifier 104. That is, under the control of the timing control circuit 24, the timer 211 measures a fixed time from when the gain change of the second variable gain amplifier 204 starts until the output stabilizes.

[0033] The timer 23 is an auxiliary timer for adjustment that adds an adjustment time to the counting times of the timers 111 and 211. The timer 23 may be omitted.

[0034] The timing control circuit 24 controls the timer 111, the timer 211, and the timer 23 based on the gain signals EG1 and EG2, and controls the timing of changing the gain control signals G1 and G2. For example, when one of the gain signals EG1 and EG2 is changed, the timing control circuit 24 first changes the gain control signal G1, and then changes the gain control signal G2 after the gain change time has elapsed. Alternatively, when the gain signal EG1 is changed, the timing control circuit 24 does not change the gain control signal G1 if the timer 211 is counting, and changes the gain control signal G1 after the timer 211 has finished counting. Furthermore, when the gain signal EG2 is changed, the timing control circuit 24 does not change the gain control signal G2 if the timer 111 is counting, and changes the gain control signal G2 after the timer 111 has finished counting.

[0035] The averaging circuit 3 calculates the average value of two measurement results obtained by redundantly measuring the first and second systems with the same gain.

[0036] The selection circuit 6 selects one of the measurement result of the first system, that is, the output value of the first divider 106 , the measurement result of the second system, that is, the output value of the second divider 206 , and the average value of the averaging circuit 3 .

[0037] The error detection circuit 10 detects a measurement error based on the difference or ratio between two measurement results obtained by redundantly measuring the first and second systems with the same gain. To this end, the error detection circuit 10 includes a comparison circuit 11 and an error determination circuit 12.

[0038] The comparator circuit 11 compares the output value of the first divider 106 with the output value of the second divider 206 and outputs the error.

[0039] If the error output from the comparison circuit 11 exceeds the allowable value, the error determination circuit 12 determines that an error has occurred and outputs an error signal.

[0040] The operation of the analog-to-digital conversion circuit 1 configured as above will now be described.

[0041] FIG. 2A is a time chart showing an example of the operation of the analog-to-digital converter circuit 1 according to the first embodiment.

[0042] The input signal column in FIG. 1A is an analog signal input to the input terminal 2, and shows a voltage waveform corresponding to the magnitude of the AC current resulting from the switching operation for driving the motor M.

[0043] (b) The Gain 1 column indicates the gain of the gain control signal G1. (c) The Timer 1 column indicates the operating state of the timer 111. That is, a high level indicates that the timer 111 is counting, and a low level indicates that the timer 111 is not counting. (d) The Output Signal 1 column indicates the output of the first variable gain amplifier 104.

[0044] (e) The Gain 2 column indicates the gain of the gain control signal G2. (f) The Timer 2 column indicates the operating state of the timer 211. That is, a high level indicates that the timer 211 is counting, and a low level indicates that it is not counting. (g) The Output Signal 2 column indicates the output of the first gain variable amplifier 204. (h) The Timer 3 column indicates the operating state of the timer 23. A high level indicates that the timer 211 is counting, and a low level indicates that it is not counting.

[0045] (i) The operating state column indicates the operating state of the analog-to-digital conversion circuit 1. "Normal" indicates normal operation in which the first variable gain amplifier 104 and the second variable gain amplifier 204 operate at the same gain. "VGA1 change" indicates operation of changing the gain of the first variable gain amplifier 104. "VGA2 change" indicates operation of changing the gain of the second variable gain amplifier 204. (j) Valid data indicates stable output values ​​unaffected by gain changes. "VGA1" indicates that the output value of the first system, i.e., the first divider 106, is valid. "VGA2" indicates that the output value of the second system, i.e., the second divider 206, is valid. VGA1 / 2 indicates that both the output value of the first divider 106 and the output value of the second divider 206 are valid.

[0046] The times t1 to t12 in FIG. 2A are not uniform time intervals, but merely indicate the change points in the operation.

[0047] From time t1 to time t2, the first variable gain amplifier 104 and the second variable gain amplifier 204 operate at the same gain, i.e., at a gain of gain control signal G1=G2=×2 (doubled), i.e., the analog-to-digital conversion circuit 1 operates in the normal operation mode.

[0048] At time t2, the amplitude of the input signal increases, causing both gain signals EG1 and EG2 to change from a gain of 2 to a gain of 1. In response to this, the control circuit 20 changes the gain control signal G1 from a gain of 2 to a gain of 1, maintains the gain of 2 indicated by the gain control signal G2, and starts counting time T1 with the timer 111. In response to the change in gain control signal G1, the first variable gain amplifier 104 changes its gain from 2 to 1. This gain change time corresponds to the shaded portion of (d) output signal 1. The time T1 counted by the timer 111 is equal to or longer than the gain change time of the first variable gain amplifier 104. In the figure, the time T1 is set to be the same as the gain change time.

[0049] The period from time t2 to time t3 corresponds to the gain change time of the first variable gain amplifier 104.

[0050] At time t3, the first variable gain amplifier 104 reaches a state in which it can output a stable digital value with the new gain of 1. If time T1 is set to the same time as the gain change time at this point, the gain change operation of the first variable gain amplifier 104 should be complete, and the output should be stable. However, the actual gain change time may be longer than time T1 due to the influence of temperature characteristics, etc. Therefore, the timer 23 starts counting time T3 when the timer 111 finishes counting time T1 (i.e., time t3). Time T3 is an adjustment time added to prevent time T1 from becoming shorter than the actual gain change time when the gain change time becomes longer due to the temperature characteristics, etc., of the first variable gain amplifier 104.

[0051] At time t4, a time (T1 + T3) exceeding the gain change time has elapsed since the start of the gain change of the first variable gain amplifier 104, and the output of the first variable gain amplifier 104 is completely free of the effects of the gain change and is stable. Furthermore, since the gain change of the first variable gain amplifier 104 is complete, the control circuit 20 then changes the gain control signal G2 from 2x to 1x, and starts counting time T2 with the timer 211. In response to the change in gain control signal G2, the second variable gain amplifier 204 changes its gain from 2x to 1x. This gain change time corresponds to the shaded portion of (g) output signal 2. The time T2 counted by the timer 211 is equal to or longer than the gain change time of the second variable gain amplifier 204. In the figure, time T2 is set to be the same as time T1 and the gain change time.

[0052] At time t5, the second variable gain amplifier 204 is ready to output a stable digital value with the new gain of 1. If time T2 is set to the same time as the gain change time at this point, the gain change operation of the second variable gain amplifier 204 should be complete, and the output should be stable. However, the actual gain change time may be longer than time T2 due to the influence of temperature characteristics, etc. Therefore, the timer 23 starts counting time T3 when the timer 211 finishes counting time T2 (i.e., time t5). Time T3 is an adjustment time added to prevent time T2 from becoming shorter than the actual gain change time when the gain change time becomes longer due to the temperature characteristics, etc., of the second variable gain amplifier 204.

[0053] At time t6, a time (T2 + T3) longer than the gain change time has passed since the start of the gain change of the second variable gain amplifier 204, and the output of the second variable gain amplifier 204 is now stable, with no effect from the gain change. The control circuit 20 completes the gain change operations of the first variable gain amplifier 104 and the second AD converter 205. This causes the analog-to-digital conversion circuit 1 to transition to a normal operation mode in which the first variable gain amplifier 104 and the second variable gain amplifier 204 operate at the same gain.

[0054] Furthermore, at time t7, the amplitude of the input signal decreases, and as a result, both gain signals EG1 and EG2 are changed from a gain of 1 to a gain of 2. In response to this, control circuit 20 changes gain control signal G1 from 1 to a gain of 2, maintains the gain of 1 indicated by gain control signal G2, and starts counting time T1 with timer 111. In response to the change in gain control signal G1, first variable gain amplifier 104 changes its gain from 1 to 2.

[0055] The period from time t7 to time t8 corresponds to the gain change time of the first variable gain amplifier 104.

[0056] At time t8, the first variable gain amplifier 104 is in a state where it can output a stable digital value with a gain that is twice the changed gain. Furthermore, the timer 23 starts counting the adjustment time T3 when the timer 111 finishes counting the time T1 (i.e., time t8).

[0057] At time t9, a time (T1 + T3) exceeding the gain change time has passed since the start of the gain change of the first variable gain amplifier 104, and therefore the output of the first variable gain amplifier 104 is completely free of the effects of the gain change and is stable. Furthermore, since the gain change of the first variable gain amplifier 104 has been completed, the control circuit 20 then changes the gain control signal G2 to indicate a gain of 1x to 2x, and starts counting time T2 with the timer 211. In response to the change in gain control signal G2, the second variable gain amplifier 204 changes its gain from 1x to 2x.

[0058] At time t10, the second variable gain amplifier 204 is in a state where it can output a stable digital value with a gain that is twice the changed gain. Furthermore, the timer 23 starts counting time T3 when the timer 211 finishes counting time T2 (i.e., time t10).

[0059] At time t11, a time (T2 + T3) exceeding the gain change time has passed since the start of the gain change of the second variable gain amplifier 204, and therefore the output of the second variable gain amplifier 204 is completely free of the effects of the gain change and is stable. The control circuit 20 ends the gain change operations of the first variable gain amplifier 104 and the second AD converter 205. This causes the analog-to-digital conversion circuit 1 to transition to a normal operation mode in which the first variable gain amplifier 104 and the second variable gain amplifier 204 operate at the same gain.

[0060] The analog-to-digital conversion circuit 1 has a normal operation mode in which the first variable gain amplifier 104 and the second variable gain amplifier 204 operate at the same gain, and a gain change mode in which the gain of the first variable gain amplifier 104 or the second variable gain amplifier 204 is changed.

[0061] 2A , to change the gain in the normal operation mode, that is, to change the gain of both the first variable gain amplifier 104 and the second variable gain amplifier 204, the control circuit 20 first starts changing the gain of the first variable gain amplifier 104 and prohibits changing the gain of the second variable gain amplifier 204 during the gain change time of the first variable gain amplifier 104. Next, the control circuit 20 starts changing the gain of the second variable gain amplifier 204 after the gain change time of the first variable gain amplifier 104 is completed and prohibits changing the gain of the first variable gain amplifier 104 during the gain change time of the second variable gain amplifier 204. In this way, the control circuit 20 controls the gain change time relative to the first variable gain amplifier 104 so that the gain change time of the second variable gain amplifier 204 does not overlap. As a result, even during the gain change time of one of the first variable gain amplifier 104 and the second variable gain amplifier 204, a correct output can be obtained from the AD converter corresponding to the other, thereby reducing or eliminating the latency due to the gain change. Furthermore, the analog-digital conversion circuit 1 serves as a current measurement circuit, making it possible to measure the current of the assembled battery 17, which fluctuates greatly, while achieving high functional safety performance with redundancy.

[0062] Next, another example of the operation of the analog-to-digital conversion circuit 1 will be described.

[0063] 2B is a time chart showing another example of the operation of the analog-to-digital conversion circuit 1 according to embodiment 1. Figure 2B differs from Figure 2A in that the time T1 counted by the timer 111 is changed to the time T1+T3 of Figure 2A, the time T2 counted by the timer 211 is changed to the time T2+T3 of Figure 2A, and the timer 23 is not used. Below, the following description will focus on the differences, avoiding duplication of explanation of the same points.

[0064] 2B is the total time of the gain change time and the adjustment time of the first variable gain amplifier 104. The adjustment time may be the same as time T3 in Fig. 2A, and is a time to prevent time T1 from being shorter than the actual gain change time even if the gain change time becomes longer due to the temperature characteristics of the second variable gain amplifier 204 or the like.

[0065] Time T2 in FIG. 2B is the total time of the gain change time of the second variable gain amplifier 204 and the adjustment time.

[0066] 2B , to change the gain in the normal operation mode, that is, to change the gain of both the first variable gain amplifier 104 and the second variable gain amplifier 204 from the first gain to the second gain, the control circuit 20 first starts changing the gain of the first variable gain amplifier 104 and prohibits changing the gain of the second variable gain amplifier 204 during the gain change time of the first variable gain amplifier 104. Next, after the gain change time of the first variable gain amplifier 104 is completed, the control circuit 20 starts changing the gain of the second variable gain amplifier 204 and prohibits changing the gain of the first variable gain amplifier 104 during the gain change time of the second variable gain amplifier 204. In this way, the control circuit 20 controls the gain change time relatively so that the gain change time of the first variable gain amplifier 104 and the gain change time of the second variable gain amplifier 204 do not overlap. This allows the correct output to be obtained from the AD converter corresponding to the other amplifier even during the gain change time of either the first variable gain amplifier 104 or the second variable gain amplifier 204, thereby reducing or eliminating the waiting time due to the gain change.

[0067] 1, instead of the first divider 106 and the second divider 206, a single divider may be provided in the subsequent stage of the selection circuit 6. This divider adjusts the bit weight of the digital signal selected by the selection circuit 6.

[0068] The two gain signals EG1 and EG2 may be signals that always indicate the same value.Also, one gain signal may be input instead of the two gain signals EG1 and EG2.

[0069] FIG. 1 shows an example in which the number of bits of the digital signals output by each of the first AD converter 105 and the second AD converter 205 is 14 bits, and the number of bits of the digital signals output by each of the first divider 106 and the second divider 206 is 17 bits, but the number of bits is not limited to this.

[0070] In the analog-to-digital converter circuit 1 according to the first embodiment, gain signals EG1 and EG2 that set the gains of the first variable gain amplifier 104 and the second variable gain amplifier 204 are input to a control circuit 20 that controls the gain change time. The two digital signals output from the first divider 106 and the second divider 206 can take digital values ​​with the same weight even when the gains of the first variable gain amplifier 104 and the second variable gain amplifier 204 are changed.

[0071] Therefore, when the gain signals EG1 and EG2 are changed, the control circuit 20 outputs one of the gain control signals G1 and G2 with priority, and temporarily prohibits the other gain control signal from being changed during the gain change time. During this time, the selection circuit 6 selects and outputs the output value of the signal whose gain has not been changed.

[0072] Furthermore, when the gain signals EG1 and EG2 are changed simultaneously, the control circuit 20 performs relative time control so that the gain of one of the gain control signals G1 and G2 is changed first, and then the other gain is changed after the gain change time has elapsed. During the gain change time for the other gain change, the selection circuit 6 selects the output value that was changed first.

[0073] Under normal circumstances when no gain change is made, the two systems function as redundant measurements, and the average value of the two measurement results can be used as the measurement value, or the two measurement results can be compared and an error signal output as a measurement error if the allowable error is exceeded.

[0074] This enables analog-to-digital conversion without interruption of the output value even during gain change times.

[0075] The analog-to-digital conversion circuit 1 is connected to a shunt resistor 15 for current detection, thereby enabling current measurement of a lithium-ion battery pack of an electric vehicle over a high dynamic range.

[0076] In FIG. 1, a shunt resistor is used for current detection, but a current sensor using a magnetic circuit can also be used to measure current over a wide dynamic range.

[0077] As described above, the analog-to-digital conversion circuit 1 according to the first embodiment comprises a first variable gain amplifier 104 connected to the input terminal 2, a first AD converter 105 connected to the first variable gain amplifier, a second variable gain amplifier 204 connected to the input terminal 2, a second AD converter 205 connected to the second variable gain amplifier, a selection circuit 6 to which the output of the first AD converter 105 and the output of the second AD converter 205 are input, and a control circuit 20 that relatively controls the gain change times of the first variable gain amplifier 104 and the second variable gain amplifier 204.

[0078] This makes it possible to reduce the waiting time from when the gain change starts until a correct measurement value is obtained.

[0079] Here, the gain change time is the time from when the gain of the first variable gain amplifier 104 starts to be changed until the output of the first variable gain amplifier 104 stabilizes, or the time from when the gain of the second variable gain amplifier 204 starts to be changed until the output of the second variable gain amplifier 204 stabilizes, and the control circuit 20 may control the gain change time of the first variable gain amplifier and the gain change time of the second variable gain amplifier so that they do not overlap.

[0080] With this, even during the gain change time of one of the first variable gain amplifier and the second variable gain amplifier, a correct output can be obtained from the AD converter corresponding to the other, thereby eliminating waiting time.

[0081] Here, the analog-to-digital conversion circuit 1 has a normal operation mode in which the first variable gain amplifier 104 and the second variable gain amplifier 204 operate at the same gain, and a gain change mode in which the gain of the first variable gain amplifier 104 or the second variable gain amplifier 204 is changed, and in the gain change mode, the control circuit 20 may perform control to change the gain of one of the first variable gain amplifier 104 and the second variable gain amplifier 204 from the first gain to the second gain, and then change the gain of the other from the first gain to the second gain.

[0082] This makes it possible to reduce the waiting time from when the gain change starts until a correct measurement value is obtained.

[0083] Here, the selection circuit 6 may select the output of the AD converter corresponding to the other of the first and second variable gain amplifiers, whose gain has not been changed, during the gain change time of either one of the first and second variable gain amplifiers.

[0084] This makes it possible to obtain a correct output from the selection circuit even during the gain change time of one of the first variable gain amplifier and the second variable gain amplifier, thereby eliminating waiting time.

[0085] Here, the analog-to-digital conversion circuit 1 may include a first divider 106 that divides the output of the first AD converter 105 by a value indicating the gain of the first variable gain amplifier 104 and outputs the divided result to the selection circuit 6, and a second divider 206 that divides the output of the second AD converter 205 by a value indicating the gain of the second variable gain amplifier 204 and outputs the divided result to the selection circuit 6.

[0086] This allows the weight of the digital value to be maintained without being changed even if the gain of the first or second variable gain amplifier is changed.

[0087] Here, the values ​​indicating the gains of the first variable gain amplifier 104 and the second variable gain amplifier 204 are expressed as powers of two, and the first divider 106 and the second divider 206 may each perform division by bit shifting.

[0088] This allows the weight of the digital value to be maintained without being changed even if the gain of the first or second variable gain amplifier is changed.

[0089] Here, an error detection circuit 10 may be provided that determines whether or not an error exists based on the outputs of the first AD converter 105 and the second AD converter 205, or the outputs of the first divider 106 and the second divider 206, during a period in which the first variable gain amplifier 104 and the second variable gain amplifier 204 are operating at the same gain.

[0090] According to this, even if the gain of the first or second variable gain amplifier 104 or 105 is changed, the division operation for maintaining the weight of the digital value can be realized by a simple bit shift.

[0091] The current measuring device according to the first embodiment also includes the analog-to-digital conversion circuit.

[0092] This makes it possible to reduce the waiting time from when the gain change starts until a correct measurement value is obtained.

[0093] Here, the current measurement circuit may include a shunt resistor for detecting the current.

[0094] This allows the current detection function to be realized with a simple circuit configuration.

[0095] Here, the current measurement circuit may include a magnetic circuit for detecting current.

[0096] This makes it possible to achieve a current detection function without contact and with low loss.

[0097] Here, the current measurement circuit may measure the current of a battery pack made up of one or more battery cells or storage capacitor cells.

[0098] This allows functional safety to be achieved for, for example, assembled batteries for electric vehicles, and current measurement with a high dynamic range to be made possible.

[0099] (Embodiment 2) In embodiment 2, in addition to the configuration of the analog-to-digital conversion circuit 1 of embodiment 1, an example configuration is described that includes an AGC (Auto Gain Control) circuit that automatically changes the gain of the first variable gain amplifier 104 and the second variable gain amplifier 204 depending on the amplitude of the input analog signal.

[0100] FIG. 3 is a diagram showing an example of the configuration of an analog-to-digital conversion circuit according to embodiment 2. FIG. 4 is an explanatory diagram showing an example of AGC operation of the analog-to-digital conversion circuit according to embodiment 2. The horizontal axis of FIG. 4 indicates the absolute value of the amplitude of the analog signal at input terminal 2. The vertical axis of FIG. 4 indicates gain. The analog-to-digital conversion circuit 1 in FIG. 3 differs from FIG. 1 in that the input of gain signals EG1 and EG2 is no longer provided and an AGC circuit 30 has been added. The following description will focus on the differences, avoiding duplication of explanation of the same points.

[0101] The AGC circuit 30 is a circuit that generates gain signals EG1 and EG2, i.e., an automatic gain control (AGC) circuit that controls the gains of the first variable gain amplifier 104 and the second variable gain amplifier 204 to optimal levels depending on the amplitude of the analog signal input to the input terminal 2. In FIG. 3 , the gain signal EG1 corresponds to the first instruction signal 115, and the gain signal EG2 corresponds to the second instruction signal 215. The control circuit 20 generates the first instruction signal 115 that instructs the gain to be increased or decreased depending on the amplitude of the analog signal (the output of the first AD converter 105 in FIG. 3 ), and the second instruction signal 215 that instructs the gain to be increased or decreased depending on the output of the second AD converter 205.

[0102] Specifically, the AGC circuit 30 generates the first instruction signal 115 and the second instruction signal 215 so that the smaller the amplitude of the analog signal, the larger the gain of the first variable gain amplifier 104 and the second variable gain amplifier 204. To this end, the AGC circuit 30 includes an absolute value circuit 107, an absolute value circuit 207, an upper reference value output unit 31, a lower reference value output unit 32, a comparison circuit 33, a UD counter 110, and a UD counter 210.

[0103] The absolute value circuit 107 is a circuit that outputs the absolute value of the digital signal output from the first AD converter 105. Here, when the digital signal output from the first AD converter 105 has a negative value, it is represented by a two's complement.

[0104] The absolute value circuit 207 is a circuit that outputs the absolute value of the digital signal output from the second AD converter 205. When the digital signal output from the second AD converter 205 has a negative value, it is represented by a two's complement.

[0105] The upper reference value output unit 31 is a circuit that outputs an upper reference value for reducing the gain when the amplitude of the analog signal input to the input terminal 2 increases. The upper reference value output unit 31 may be configured, for example, by a non-volatile memory, a register, or a fixed constant generating circuit. An example of the upper reference value is shown in FIG. 4.

[0106] The lower reference value output unit 32 is a circuit that outputs a lower reference value for reducing the gain when the amplitude of the analog signal input to the input terminal 2 becomes small. The lower reference value output unit 32 may be configured, for example, by any of a non-volatile memory, a register, and a fixed constant generating circuit. An example of the lower reference value is shown in FIG. 4.

[0107] The comparison circuit 33 is a circuit that compares the absolute values ​​output from the absolute value circuit 107 and the absolute value output from the absolute value circuit 207 with the upper reference value and the lower reference value.

[0108] The comparator 108 compares the output of the absolute value circuit 107, i.e., the absolute value of the digital signal from the first AD converter 105, with the upper reference value. The result of this comparison indicates whether the absolute value of the amplitude of the analog signal has become larger than the upper reference value, as shown in FIG.

[0109] The comparator 109 compares the output of the absolute value circuit 107, i.e., the absolute value of the digital signal from the first AD converter 105, with the lower reference value. The result of this comparison indicates whether the absolute value of the amplitude of the analog signal has become smaller than the lower reference value, as shown in FIG.

[0110] The output signals of the comparators 108 and 109 are transmitted as a first indication signal 115 to the UD counter 110 and the timing control circuit 24 .

[0111] The comparator 208 compares the output of the absolute value circuit 207, i.e., the absolute value of the digital signal from the second AD converter 205, with the upper reference value. The result of this comparison indicates whether the absolute value of the amplitude of the analog signal has become larger than the upper reference value, as shown in FIG.

[0112] The comparator 209 compares the output of the absolute value circuit 207, i.e., the absolute value of the digital signal from the second AD converter 205, with the lower reference value. The result of this comparison indicates whether the absolute value of the amplitude of the analog signal has become smaller than the lower reference value, as shown in FIG.

[0113] The output signals of the comparators 208 and 209 are transmitted as a second indication signal 215 to the UD counter 210 and the timing control circuit 24 .

[0114] The UD counter 110 is an up-down counter that holds a value corresponding to the gain to be set in the first variable gain amplifier 104 and counts up or down this value. The UD counter 110 outputs the value it holds to the control circuit 20 as the gain for the gain control signal G1. Specifically, the UD counter 110 counts down when the comparator 108 indicates that the absolute value of the amplitude of the analog signal is greater than the upper reference value (i.e., the gain indicated by the gain control signal G1 is decreased by one step). The UD counter 110 also counts up when the comparator 109 indicates that the absolute value of the amplitude of the analog signal is smaller than the lower reference value (i.e., the gain indicated by the gain control signal G1 is increased by one step).

[0115] The UD counter 210 is an up-down counter that holds a value corresponding to the gain to be set in the second variable gain amplifier 204 and counts up or down this value. The UD counter 210 outputs the value it holds to the control circuit 20 as the gain for the gain control signal G2. Specifically, the UD counter 210 counts down when the comparator 208 indicates that the absolute value of the amplitude of the analog signal is greater than the upper reference value (i.e., the gain indicated by the gain control signal G2 is decreased by one step). The UD counter 210 also counts up when the comparator 209 indicates that the absolute value of the amplitude of the analog signal is smaller than the lower reference value (i.e., the gain indicated by the gain control signal G2 is increased by one step).

[0116] 4, the gain transitions indicated by dotted lines correspond to count-downs of the UD counters 110 and 210 that decrease the gain by one step, and the gain transitions indicated by solid lines correspond to count-ups of the UD counters 110 and 210 that increase the gain by one step.

[0117] Furthermore, amplitude range R4 in FIG. 4 indicates an amplitude range of approximately 1 / 8 or less of the input range of the first variable gain amplifier 104 and the second variable gain amplifier 204. Amplitude range R3 indicates an amplitude range of approximately 1 / 8 to 1 / 4 of the input range. Amplitude range R2 indicates an amplitude range of approximately 1 / 4 to 1 / 2 of the input range. Amplitude range R1 indicates an amplitude range of approximately 1 / 2 or more of the input range. In the example shown in FIG. 4 , the AGC circuit 30 increases the gain indicated by the gain control signals G1 and G2 by 8 times when the absolute value of the amplitude of the analog signal is approximately within amplitude range R4. The AGC circuit 30 increases the gain indicated by the gain control signals G1 and G2 by 4 times when the absolute value of the amplitude of the analog signal is approximately within amplitude range R3. The AGC circuit 30 increases the gain indicated by the gain control signals G1 and G2 by 2 times when the absolute value of the amplitude of the analog signal is approximately within amplitude range R2. Furthermore, when the absolute value of the amplitude of the analog signal is approximately within the amplitude range R1, the AGC circuit 30 multiplies the gain indicated by the gain control signals G1 and G2 by 1.

[0118] In this way, the AGC circuit 30 can expand the dynamic range of the analog-to-digital conversion circuit 1 and improve the conversion accuracy (resolution) when the amplitude of the analog signal is relatively small. The thick lines parallel to the horizontal axis in Fig. 4 and corresponding to the amplitude ranges R1 to R4 indicate the correspondence relationship between gain and resolution in the analog-to-digital conversion circuit 1 of embodiment 2. In Fig. 4, the smaller the amplitude of the analog signal, the higher the resolution.

[0119] The upper and lower reference values ​​shown in FIG. 4 are merely examples and are not limiting.

[0120] As described above, in the second embodiment, the AGC circuit 30 is added. When the AGC automatically switches the gain, a waiting time for the AGC response is required, but the control circuit 20 exclusively changes the gain of two systems, and when one gain is changed, prohibits the other gain change during the waiting time for the AGC response, thereby reducing or eliminating interruptions in the output value and the occurrence of waiting times.

[0121] As described above, the analog-to-digital conversion circuit 1 according to the second embodiment includes an AGC circuit 30 that generates a first instruction signal 115 that instructs an increase or decrease in gain in accordance with the magnitude of the output of the first AD converter 105, and a second instruction signal 215 that instructs an increase or decrease in gain in accordance with the magnitude of the output of the second AD converter 205, and the control circuit 20 controls changes in the gain of the first variable gain amplifier 104 and the second variable gain amplifier 204 in accordance with the first instruction signal 115 and the second instruction signal 215.

[0122] This causes a waiting time for the response of the AGC circuit, but by controlling the gain variable times of the first and second variable gain amplifiers relatively, for example, by prohibiting the gain of one amplifier from being changed when the gain of the other amplifier is changed, the waiting time can be reduced or eliminated.

[0123] Here, the control circuit 20 may have a first timer 111 that counts the gain change time of the first variable gain amplifier 104, and may control the control circuit 20 so that the gain change of the second variable gain amplifier 204 does not start while the first timer 111 is counting.

[0124] According to this, when the gain of the first variable gain amplifier is changed, the waiting time can be reduced or eliminated by prohibiting the gain of the second variable gain amplifier from being changed.

[0125] Here, the control circuit 20 may have a second timer 211 that counts the gain change time of the second variable gain amplifier 204, and may control the control so that the gain change of the first variable gain amplifier 104 does not start while the second timer 211 is counting.

[0126] According to this, when the gain of the second variable gain amplifier is changed, the waiting time can be reduced or eliminated by prohibiting the gain of the first variable gain amplifier from being changed.

[0127] (Embodiment 3) In embodiment 3, in addition to the configuration of the analog-to-digital conversion circuit of embodiment 2, an example configuration will be described that includes a circuit that compares the values ​​of the two systems and corrects gain error and offset error when the gain settings of the two systems are different.

[0128] When the first variable gain amplifier 104 and the second variable gain amplifier 204 are configured as integrated circuits, they have gain errors and offset errors, and these errors change when the gain is varied. These gain errors and offset errors are often larger than the quantization errors of the first AD converter 105 and the second AD converter 205, and even with the same input value, there may be discrepancies in the digital values ​​after AD conversion before and after the gain is changed. Therefore, it is conceivable to measure the gain errors and offset errors each time the gains of the first variable gain amplifier 104 and the first AD converter 105 are changed, store the results in non-volatile memory, and correct the digital values. However, this method requires a process called trimming, in which the gain errors and offset errors are measured during shipping inspection of the integrated circuit and stored in non-volatile memory. Furthermore, gain errors and offset errors often vary with temperature and over time, and trimming may not be sufficient to correct them.

[0129] In the third embodiment, a configuration example will be described that eliminates the waiting time from the start of gain change until a correct measurement value is obtained, and also enables gain error and offset error to be corrected during operation (background correction).

[0130] Fig. 5 is a diagram showing an example of the configuration of an analog-to-digital conversion circuit according to embodiment 3. The analog-to-digital conversion circuit 1 in Fig. 5 differs from that in Fig. 3 in that a switch 5 and a VGA correction circuit 40 are added. Below, the following description will focus on the differences, avoiding duplication of explanation of the same points.

[0131] Switch 5 is a switch that shorts the terminal pair of input terminal 2. The purpose of shorting is to measure the offset error of the output values ​​of first variable gain amplifier 104 and second variable gain amplifier 204 by setting the input value of the analog signal to zero.

[0132] The VGA correction circuit 40 is a circuit that corrects gain errors and offset errors of the first variable gain amplifier 104 and the first AD converter 105. To this end, the VGA correction circuit 40 includes a multiplier 112, an adder 113, a multiplier 212, an adder 213, a comparison circuit 41, a correction value calculation unit 114, and a correction value calculation unit 214.

[0133] The multiplier 112 multiplies the output value of the first divider 106 by the correction coefficient from the correction value calculation section 114. The multiplier 112 corrects the gain error of the first variable gain amplifier 104 through this multiplication.

[0134] The adder 113 adds the output value of the multiplier 112 and the correction constant value from the correction value calculation unit 114. By this addition, the adder 113 corrects the offset error of the first variable gain amplifier 104. The adder 113 may be disposed in the preceding stage of the multiplier 112.

[0135] The multiplier 212 multiplies the output value of the second divider 206 by the correction coefficient from the correction value calculation section 214. The multiplier 212 corrects the gain error of the second variable gain amplifier 204 through this multiplication.

[0136] The adder 213 adds the output value of the multiplier 212 and the correction constant value from the correction value calculation unit 214. By this addition, the adder 213 corrects the offset error of the second variable gain amplifier 204. The adder 213 may be arranged in the previous stage of the multiplier 212.

[0137] The comparator circuit 41 compares the output value of the first divider 106 with the output value of the second divider 206 during a period when the gain of the first variable gain amplifier 104 is different from the gain of the second variable gain amplifier 204. Ideally, the comparison results should match, but in reality, gain errors and offset errors occur due to the difference in gain, changes over time, fluctuations due to temperature characteristics, etc.

[0138] When the gain of one of the first variable gain amplifier 104 and the second variable gain amplifier 204 operating in the normal operation mode is changed and a gain change time has elapsed, the correction value calculation units 114 and 214 calculate a gain error correction coefficient and an offset error correction constant value for one of the first variable gain amplifier 104 and the second variable gain amplifier 204 after the gain change, using the output of the other amplifier whose gain has not been changed as a reference. The offset error may be measured by temporarily turning on the switch 5, or a previously measured offset value may be stored.

[0139] The error detection circuit 10 is also connected to the VGA correction circuit 40, and judges it as an error if the tolerance range is exceeded during correction or if two output values ​​exceed the tolerance range during normal operation mode.

[0140] Next, an example of the operation of the analog-to-digital converter circuit 1 according to this embodiment will be described.

[0141] 6 is a time chart showing an example of the operation of the analog-to-digital conversion circuit according to the third embodiment. This figure differs from FIG. 2A in that an example of the correction operation by the VGA correction circuit 40 has been added to the (i) operating state column. The following description will focus on the differences.

[0142] Time T3 in FIG. 6 includes not only the time required for adjusting time T1 but also the time required for calculating the correction value and performing the correction operation.

[0143] From time t3 to t4, the VGA correction circuit 40 calculates a correction coefficient and a correction constant value for correcting the gain error and offset error of the first variable gain amplifier 104 based on the second variable gain amplifier 204 whose gain has not been changed, and corrects the output value of the first divider 106 corresponding to the changed gain using the multiplier 112 and the adder 113.

[0144] From time t5 to t6, the VGA correction circuit 40 calculates a correction coefficient and a correction constant value for correcting the gain error and offset error of the second variable gain amplifier 204 based on the first variable gain amplifier 104 whose gain has not been changed, and corrects the output value of the second divider 206 corresponding to the changed gain using the multiplier 212 and the adder 213.

[0145] From time t8 to t9, the VGA correction circuit 40 operates in the same manner as from time t3 to t4.

[0146] From time t11 to time t12, the VGA correction circuit 40 operates in the same manner as from time t5 to time t6.

[0147] In this way, during the period when the gains of the first variable gain amplifier 104 and the second variable gain amplifier 204 are different, the VGA correction circuit 40 corrects the gain error and offset error of the output value after the gain is changed, using the output value without the gain change as a reference, and performs correction so that the corrected output value approaches the same value. By performing similar correction when the other gain is then changed, it is possible to easily perform background correction during operation. Furthermore, by alternately correcting the analog-to-digital conversion of the two systems, the measurement error of the two systems becomes smaller, making this circuit ideal for current measurement circuits with redundancy.

[0148] As described above, in the third embodiment, the VGA correction circuit 40 compares the values ​​of the two systems when the gain settings of the two systems are different, and corrects the gain error and offset error.

[0149] When the gain of one of the first variable gain amplifier 104 and the second variable gain amplifier 204 is changed, the VGA correction circuit 40 corrects the gain error and offset error of the one gain amplifier whose gain has been changed, using the output of the other gain amplifier whose gain has not been changed as a reference, after the gain change time, so that the corrected output value approaches the same value. By performing the same correction when the gain of the other gain is subsequently changed, it is possible to easily perform background correction during operation. Furthermore, the VGA correction circuit 40 is ideal for current measurement circuits with redundancy, because the measurement errors of the two systems are further reduced by alternately correcting the two analog-to-digital conversion circuits.

[0150] As described above, the analog-to-digital conversion circuit 1 according to the third embodiment includes the VGA correction circuit 40 that corrects the first output value obtained from the first divider 106 or the second output value obtained from the second divider 206 so as to minimize the difference between the first output value or the second output value.

[0151] This reduces the difference between the first output value and the second output value, making it possible to correct the difference in characteristics that may occur between the two redundant systems.

[0152] Here, the VGA correction circuit 40 may include a multiplication circuit that multiplies the first output value or the second output value by a correction coefficient.

[0153] This makes it possible to correct the gain errors of the first variable gain amplifier and the second variable gain amplifier.

[0154] Here, the VGA correction circuit 40 may include an adder circuit that adds a correction constant value to the first output value or the second output value.

[0155] This makes it possible to correct the offset errors of the first variable gain amplifier and the second variable gain amplifier.

[0156] Here, the VGA correction circuit 40 may correct the gain of the first variable gain amplifier and the gain of the second variable gain amplifier at different times.

[0157] This is suitable for a circuit having two redundant systems.

[0158] As described above, the present disclosure is ideal for analog-to-digital conversion circuits that require redundancy and a high dynamic range.

[0159] In particular, in electric vehicles powered by lithium-ion battery packs, the output current value of the lithium-ion battery pack fluctuates rapidly and irregularly from a few milliamperes to several hundred amperes from a completely stopped state to maximum output. Because the fluctuation range is more than 100,000 times, a dynamic range of 120 dB or more is required for current measurement. However, even with a delta-sigma ADC capable of achieving a high dynamic range, it is difficult to achieve such a dynamic range. Meanwhile, current changes are irregular, and conventional AGCs cannot capture rapid current changes due to the response time of the AGC feedback loop. The present disclosure is ideal for measuring the current of lithium-ion battery packs in electric vehicles, which require a high dynamic range, uninterrupted measurement, redundancy, and high-level functional safety performance.

[0160] While the analog-to-digital conversion circuit 1 and the current measurement circuit according to one or more aspects of the present disclosure have been described above based on the embodiments, the present disclosure is not limited to these embodiments. As long as they do not deviate from the spirit of the present disclosure, various modifications conceivable by those skilled in the art to the present embodiments and configurations constructed by combining components of different embodiments may also be included within the scope of one or more aspects of the present disclosure.

[0161] The present disclosure is suitable for analog-to-digital conversion circuits and current measurement circuits.

[0162] REFERENCE SIGNS LIST 1 Analog-to-digital conversion circuit 2 Input terminal 3 Averaging circuit 5 Switch 6 Selection circuit 10 Error detection circuit 11, 33, 41 Comparison circuit 12 Error determination circuit 15 Shunt resistor 17 Assembled battery 20 Control circuit 23, 111, 211 Timer 24 Timing control circuit 30 AGC circuit 31 Upper reference value output section 32 Lower reference value output section 40 VGA correction circuit 101, 102, 201, 202 Input resistor 103, 203 Capacitor 104 First variable gain amplifier 105 First AD converter 106 First divider 107, 207 Absolute value circuit 108, 109, 208, 209 Comparator 110, 210 UD counter 112, 212 Multiplier 113, 213 Adder 114, 214 Correction value calculation unit 115 First instruction signal 204 Second variable gain amplifier 205 Second AD converter 206 Second divider 215 Second instruction signal G1, G2 Gain control signals EG1, EG2 Gain signals

Claims

1. A first gain variable amplifier connected to an input terminal; A first AD converter connected to the first gain variable amplifier; A second gain variable amplifier connected to the input terminal; A second AD converter connected to the second gain variable amplifier; A selection circuit to which the output of the first AD converter and the output of the second AD converter are input; A control circuit for relatively controlling the respective gain change times of the first gain variable amplifier and the second gain variable amplifier; and It has a normal operation mode in which the first gain variable amplifier and the second gain variable amplifier operate with the same gain, and a gain change mode for changing the gains of the first gain variable amplifier and the second gain variable amplifier; In the gain change mode, the control circuit performs control to change the gain of one of the first gain variable amplifier and the second gain variable amplifier from a first gain to a second gain and then change the gain of the other from the first gain to the second gain An analog-digital conversion circuit.

2. In the analog-digital conversion circuit according to Claim 1, The gain change time is the time from the start of the gain change of the first gain variable amplifier until the output of the first gain variable amplifier stabilizes, or the time from the start of the gain change of the second gain variable amplifier until the output of the second gain variable amplifier stabilizes, The control circuit Controls so that the gain change time of the first gain variable amplifier and the gain change time of the second gain variable amplifier do not overlap An analog-digital conversion circuit.

3. In the analog-digital conversion circuit according to Claim 1 or 2, The selection circuit selects the output of the AD converter corresponding to the other one whose gain has not been changed at the gain change time of either the first or second gain variable amplifier An analog-digital conversion circuit.

4. In the analog-digital conversion circuit according to Claim 1 or 2, A first divider that divides the output of the first AD converter by a value indicating the gain of the first gain variable amplifier and outputs the divided result to the selection circuit; A second divider that divides the output of the second AD converter by a value indicating the gain of the second gain variable amplifier and outputs the divided result to the selection circuit; and An analog-digital conversion circuit.

5. In the analog-digital conversion circuit according to Claim 4, The values indicating the gains of the first gain variable amplifier and the second gain variable amplifier are represented by powers of 2, each of the first divider and the second divider performs division by bit shift Analog-to-digital conversion circuit.

6. In the analog-to-digital conversion circuit according to claim 4, an error detection circuit that determines the presence or absence of an error based on the outputs of the first AD converter and the second AD converter, or the outputs of the first divider and the second divider, respectively, during a period in which the first gain variable amplifier and the second gain variable amplifier operate with the same gain Analog-to-digital conversion circuit.

7. In the analog-to-digital conversion circuit according to claim 1 or 2, an AGC circuit that generates a first instruction signal for instructing an increase or decrease in gain according to the magnitude of the output of the first AD converter and a second instruction signal for instructing an increase or decrease in gain according to the magnitude of the output of the second AD converter, the control circuit controls the gain change of the first gain variable amplifier and the second gain variable amplifier according to the first instruction signal and the second instruction signal Analog-to-digital conversion circuit.

8. In the analog-to-digital conversion circuit according to claim 7, the control circuit has a first timer that counts the gain change time of the first gain variable amplifier, and does not start the gain change of the second gain variable amplifier during the counting of the first timer Analog-to-digital conversion circuit.

9. In the analog-to-digital conversion circuit according to claim 7, the control circuit has a second timer that counts the gain change time of the second gain variable amplifier, and does not start the gain change of the first gain variable amplifier during the counting of the second timer Analog-to-digital conversion circuit.

10. In the analog-to-digital conversion circuit according to claim 4, a correction circuit that corrects the first output value or the second output value so as to minimize the difference between the first output value obtained from the first divider and the second output value obtained from the second divider Analog-to-digital conversion circuit.

11. In the analog-to-digital conversion circuit according to claim 10, the correction circuit includes a multiplication circuit that multiplies the first output value or the second output value by a correction coefficient Analog-to-digital conversion circuit.

12. In the analog-digital conversion circuit according to claim 10, the correction circuit includes an addition circuit that adds a correction constant value to the first output value or the second output value Analog-digital conversion circuit.

13. In the analog-digital conversion circuit according to claim 10, the correction circuit performs correction at a time when the gain of the first gain variable amplifier and the gain of the second gain variable amplifier are different Analog-digital conversion circuit.

14. Comprising the analog-digital conversion circuit according to claim 1 or 2 Current measurement circuit.

15. In the current measurement circuit according to claim 14, Comprising a shunt resistor for current detection Current measurement circuit.

16. In the current measurement circuit according to claim 14, Comprising a magnetic circuit for current detection Current measurement circuit.

17. In the current measurement circuit according to claim 14, Measuring the current of a battery pack composed of one or more battery cells or one or more capacitor cells Current measurement circuit.