Semiconductor device

Abstract

Provided are a semiconductor device that is able to perform authentication in a short time, and a method for driving the same. Provided are a semiconductor device having a light-emitting device and an imaging device, and a method for driving said semiconductor device. The imaging device has pixels arrayed in a matrix and a row driver circuit that has a shift register circuit. The method for driving has a first mode and a second mode. The first mode has a step for detecting the position of a finger of a user. The second mode has a step for reading an image of the fingerprint of the finger of the user one row at a time from the pixels in the first row to the row where the position of the finger of the user was detected in the first mode. When the first mode and the second mode are finished, the operation of the shift register circuit stops.

Description

Semiconductor device, electronic device, and method for driving semiconductor device

[0001] 1. Field of the Invention The present invention relates to a semiconductor device including a light-emitting device and an imaging device, an electronic device including the semiconductor device including the light-emitting device and the imaging device, and a method for driving the semiconductor device including the light-emitting device and the imaging device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include a semiconductor device, a display device, a light-emitting device, an imaging device, a power storage device, a memory device, an electronic device, a lighting device, an input device (e.g., a touch sensor), and a method for driving an input / output device (e.g., a touch panel). A semiconductor device refers to any device that can function by utilizing semiconductor characteristics.

[0003] While imaging devices have traditionally been installed in devices such as digital cameras, the widespread use of mobile information terminals such as smartphones and tablet devices has led to a demand for improved performance, smaller size, and lower cost. Furthermore, imaging devices are being used for a variety of purposes, including not only taking photographs or videos but also biometric authentication such as face authentication, fingerprint authentication, and vein authentication, and input devices such as touch sensors and motion sensors. Patent Document 1 discloses an electronic device such as a smartphone that is capable of fingerprint authentication.

[0004] JP 2019-79415 A

[0005] One method of fingerprint authentication, which is one form of authentication, is to irradiate light onto a finger from a light-emitting element and detect the light reflected by the finger with a light-receiving element. In this case, fingerprint authentication can be performed with high accuracy by obtaining a high-resolution fingerprint image. However, if it takes a long time to obtain a high-resolution fingerprint image, it can be stressful for the person being authenticated.

[0006] An object of one embodiment of the present invention is to provide a semiconductor device, an electronic device, and a method for driving the semiconductor device that can perform authentication in a short time.An object of one embodiment of the present invention is to provide a semiconductor device, an electronic device, and a method for driving the semiconductor device that can perform authentication with high accuracy.An object of one embodiment of the present invention is to provide a highly reliable semiconductor device, an electronic device, and a method for driving the semiconductor device.An object of one embodiment of the present invention is to provide a novel semiconductor device, an electronic device, and a method for driving the semiconductor device.

[0007] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily have to solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc.

[0008] One embodiment of the present invention is a semiconductor device including a light-emitting device and an imaging device. The imaging device includes a pixel portion in which pixels are arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 1) and a row driver circuit including a shift register circuit. The imaging device has a function of detecting that a detection target is located on pixels in p to q rows (p and q are integers greater than or equal to 1 and less than or equal to m, and p is smaller than q) in the pixel portion by detecting light emitted by the light-emitting device and reflected from the detection target, and a function of acquiring and reading out an image of the detection target from pixels in at least the 1st to qth rows in the pixel portion.

[0009] In the above, it is preferable that the pixels in the first row of the pixel unit are connected to the first stage of the shift register circuit, and the pixels in the mth row of the pixel unit are connected to the final stage from which the shift register circuit issues a selection signal.

[0010] In the above, the object to be detected is preferably a finger of a user of the semiconductor device.

[0011] In the above, it is preferable that the pixel portion and the shift register circuit each include a transistor, and that the transistor include a metal oxide in a channel formation region.

[0012] Another embodiment of the present invention is an electronic device including the above-described semiconductor device and a speaker, in which pixels in the first row of a pixel portion are pixels in a row farthest from the speaker, and pixels in the m-th row of the pixel portion are pixels in a row closest to the speaker.

[0013] Another embodiment of the present invention is an electronic device including the above-described semiconductor device and a camera, in which pixels in the first row of the pixel portion are pixels in the row farthest from the camera and pixels in the m-th row of the pixel portion are pixels in the row closest to the camera.

[0014] Another embodiment of the present invention is a semiconductor device including a light-emitting device and an imaging device. The imaging device includes a pixel portion in which pixels are arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 1) and a row driver circuit including a shift register circuit. The imaging device has a function of detecting that a detection target is located on pixels in p to q rows (p and q are integers greater than or equal to 1 and less than or equal to m, and p is smaller than q) in the pixel portion by detecting light emitted by the light-emitting device and reflected from the detection target; a function of skipping an imaging operation of the detection target in pixels in 1 to p−1 rows in the pixel portion; a function of acquiring and reading an image of the detection target in pixels in the p to q rows in the pixel portion; and a function of skipping an imaging operation of the detection target in pixels in q+1 to m rows in the pixel portion.

[0015] In the above, it is preferable that the object to be detected is a finger of a user of the semiconductor device, and the image is a fingerprint of the user.

[0016] In the above, it is preferable that the pixel portion and the shift register circuit each include a transistor, and that the transistor include a metal oxide in a channel formation region.

[0017] Another embodiment of the present invention is an electronic device including the above semiconductor device and a speaker.

[0018] Another embodiment of the present invention is an electronic device including the above semiconductor device and a camera.

[0019] Another embodiment of the present invention is a method for driving a semiconductor device including a light-emitting device and an imaging device. The imaging device has a pixel portion in which pixels are arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 1), and a row driver circuit including a shift register circuit. The method includes: a first mode in which a detection target is detected to be located on pixels in pth to qth rows (p and q are integers greater than or equal to 1 and less than m, and p is smaller than q) of the pixel portion; and a second mode in which the imaging device captures an image of the detection target that reflects light emitted from the light-emitting device, at pixels in the first to qth rows of the pixel portion, and reads the captured image. The second mode is executed after the first mode is executed, and operation of the shift register circuit is stopped when the second mode is completed.

[0020] In the above, the first mode is preferably executed on pixels every x rows and every y columns (x and y are integers between 1 and qp) of the m rows and n columns of pixels in the pixel section.

[0021] In the above, the second mode is preferably executed from the pixels in the first row to the pixels in the qth row of the pixel section.

[0022] In the above, it is preferable that the object to be detected is a finger of a user of the semiconductor device, and the image captured by the imaging device is an image of the user's fingerprint.

[0023] Another embodiment of the present invention is a method for driving a semiconductor device including a light-emitting device and an imaging device. The imaging device includes a pixel portion in which pixels are arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 1), and a row driver circuit including a shift register circuit. The driving method includes steps of capturing an image of a detection target that reflects light emitted from the light-emitting device in pixels in the first to rth rows (r is an integer greater than or equal to 1 and less than or equal to m) in the pixel portion, and reading out the captured image. When the steps are completed, operation of the shift register circuit is stopped.

[0024] In the above, it is preferable that the steps are performed from the pixels in the first row to the pixels in the rth row of the pixel section.

[0025] In the above, it is preferable that the object to be detected is a finger of a user of the semiconductor device, and the image captured by the imaging device is an image of the user's fingerprint.

[0026] Another embodiment of the present invention is a driving method for a semiconductor device including a light-emitting device and an imaging device, the imaging device including a first pixel portion in which pixels are arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 1), a second pixel portion provided in b to u rows (b and u are integers greater than or equal to 1 and less than m, and b is smaller than u) of the first pixel portion, and a row driver circuit including a shift register circuit, the driving method including: skipping an imaging operation of an object to be detected in one region of the first pixel portion that does not overlap with the second pixel portion; capturing an image of the object to be detected that reflects light emitted from the light-emitting device at pixels in the b to u rows of the pixel portion in the second pixel portion by the imaging device and reading out the captured image; and skipping an imaging operation of the object to be detected in the other region of the first pixel portion that does not overlap with the second pixel portion.

[0027] In the above, it is preferable that the object to be detected is a finger of a user of the semiconductor device, and the image captured by the imaging device is an image of the user's fingerprint.

[0028] Another embodiment of the present invention is a method for driving a semiconductor device including a light-emitting device and an imaging device, the imaging device including a pixel portion in which pixels are arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 1), and a row driver circuit including a shift register circuit, the method including: a first mode in which a detection target is detected to be located on pixels in p to q rows (p and q are integers greater than or equal to 1 and less than m, and p is smaller than q) of the pixel portion; and a second mode in which the imaging device captures an image of the detection target that reflects light emitted from the light-emitting device, at pixels in the p to q rows of the pixel portion, and reads the captured image; the method includes: performing a step of skipping an imaging operation of the detection target at pixels in the 1st to p−1th rows of the pixel portion after performing the step; performing a second mode after performing the step; and performing a step of skipping an imaging operation of the detection target at pixels in the q+1th to mth rows of the pixel portion after performing the second mode.

[0029] In the above, the first mode is preferably executed on pixels every x rows and every y columns (x and y are integers between 1 and qp) of the m rows and n columns of pixels in the pixel section.

[0030] In the above, it is preferable that the object to be detected is a finger of a user of the semiconductor device, and the image captured by the imaging device is an image of the user's fingerprint.

[0031] According to one embodiment of the present invention, a semiconductor device, an electronic device, and a method for driving the semiconductor device that can perform authentication in a short time can be provided. Alternatively, a semiconductor device, an electronic device, and a method for driving the semiconductor device that can perform authentication with high accuracy can be provided. Alternatively, a highly reliable semiconductor device, an electronic device, and a method for driving the semiconductor device can be provided. Alternatively, a novel semiconductor device, an electronic device, and a method for driving the semiconductor device can be provided.

[0032] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc.

[0033] 1A and 1B are schematic diagrams showing an example of the configuration of a semiconductor device. FIG. 2A is a block diagram showing an example of the configuration of an imaging device. FIG. 2B1 is a circuit diagram showing an example of the configuration of an imaging device. FIG. 2B2 is a timing chart showing an example of a method for driving an imaging device. FIG. 3 is a block diagram showing an example of the configuration of a row driver circuit. FIGS. 4A and 4B are circuit diagrams showing an example of the configuration of a register circuit. FIG. 5A is a circuit diagram showing an example of the configuration of a selection circuit. FIG. 5B is a circuit diagram showing an example of the configuration of a signal supply circuit. FIG. 6 is a schematic diagram showing an example of a method for driving a row driver circuit. FIG. 7 is a schematic diagram showing an example of a method for driving a row driver circuit. FIG. 8 is a flowchart showing an example of a method for driving a row driver circuit. FIG. 9 is a schematic diagram showing an example of a method for driving a row driver circuit. FIG. 10 is a timing chart showing an example of a method for driving a row driver circuit. FIG. 11 is a timing chart showing an example of a method for driving a row driver circuit. FIG. 12 is a timing chart showing an example of a method for driving a row driver circuit. FIG. 13 is a timing chart showing an example of a method for driving a row driver circuit. FIG. 14 is a flowchart showing an example of a method for driving a row driver circuit. FIG. 15 is a schematic diagram showing an example of a method for driving a row driver circuit. FIG. 16 is a flowchart showing an example of a method for driving a row driver circuit. FIG. 17 is a schematic diagram showing an example of a method for driving a row driver circuit. FIG. 18 is a timing chart showing an example of a method for driving a row driver circuit. FIG. 19 is a timing chart showing an example of a method for driving a row driver circuit. FIG. 20 is a flowchart showing an example of a method for driving a row driver circuit. FIG. 21 is a schematic diagram showing an example of a method for driving a row driver circuit. FIG. 22 is a block diagram showing an example of a configuration of a semiconductor device. FIG. 23 is a block diagram showing an example of a configuration of a semiconductor device. FIGS. 24A to 24C are circuit diagrams showing an example of a configuration of a pixel. FIG. 25 is a perspective view showing an example of a configuration of a semiconductor device. FIG. 26A is a cross-sectional view showing an example of a configuration of a semiconductor device. FIG. 26B is a cross-sectional view showing an example of a configuration of a transistor. FIG. 27A is a diagram explaining classification of IGZO crystal structures.Fig. 27B is a diagram illustrating an XRD spectrum of a quartz glass substrate. Fig. 27C is a diagram illustrating an XRD spectrum of a crystalline IGZO film. Fig. 27D is a diagram illustrating a micro-electron diffraction pattern of a quartz glass substrate. Fig. 27E is a diagram illustrating a micro-electron diffraction pattern of a crystalline IGZO film. Figs. 28A to 28D are diagrams illustrating examples of electronic devices.

[0034] The embodiments will be described in detail with reference to the drawings. However, the present invention is not limited to the following description, and it will be readily understood by those skilled in the art that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments shown below. In the configuration of the invention described below, the same parts or parts having similar functions will be denoted by the same reference numerals in different drawings, and repeated descriptions thereof will be omitted.

[0035] Furthermore, the position, size, range, etc. of each component shown in the drawings, etc. may not represent the actual position, size, range, etc. in order to facilitate understanding of the invention. Therefore, the disclosed invention is not necessarily limited to the position, size, range, etc. disclosed in the drawings, etc. For example, in an actual manufacturing process, a resist mask, etc., may be unintentionally eroded by processing such as etching, but this may not be reflected in the drawings in order to facilitate understanding.

[0036] Furthermore, the terms "electrode" and "wiring" used in this specification and the like do not limit the functionality of these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" also include cases where multiple "electrodes" or "wirings" are integrally formed.

[0037] In this specification and the like, the resistance value of a "resistor" may be determined by the length of the wiring, or by connecting a conductive layer having a different resistivity from the conductive layer used in the wiring, or by doping an impurity into a semiconductor layer.

[0038] In addition, in this specification, a "terminal" in an electric circuit refers to a portion where a current is input or output, a voltage is input or output, or a signal is received or transmitted. Therefore, a part of a wiring or an electrode may function as a terminal.

[0039] In this specification, the terms "above," "above," "below," or "below" do not limit the positional relationship of components to being directly above or below and in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude cases where other components are included between insulating layer A and electrode B. Furthermore, the expression "conductive layer D above conductive layer C" does not require that conductive layer D be formed in direct contact with conductive layer C, and does not exclude cases where other components are included between conductive layer C and conductive layer D. Furthermore, "above" or "below" does not exclude cases where components are arranged in an oblique direction.

[0040] In addition, the functions of the source and drain are interchangeable depending on operating conditions, such as when transistors of different polarities are used or when the direction of current changes during circuit operation, making it difficult to define which is the source and which is the drain. For this reason, the terms source and drain can be used interchangeably in this specification.

[0041] Furthermore, in this specification, "electrically connected" includes both direct connection and connection via "something that has some kind of electrical effect." Here, "something that has some kind of electrical effect" is not particularly limited as long as it allows for the exchange of electrical signals between the connected objects. Therefore, even when the term "electrically connected" is used, in an actual circuit, there may be no physical connection and only wiring may extend. Furthermore, even when the term "directly connected" is used, it includes cases where wiring is formed on different conductive layers via contacts.

[0042] In this specification, when referring to counting values ​​and measurement values, terms such as "same," "the same," "equal," or "uniform" are used, they are considered to include an error of plus or minus 20%, unless otherwise specified.

[0043] Furthermore, voltage often refers to the potential difference between a certain potential and a reference potential (for example, ground potential or source potential). Therefore, voltage and potential difference can often be interchangeable. In this specification and the like, unless otherwise specified, voltage and potential difference can be interchangeable.

[0044] It should be noted that even when written as a "semiconductor," if the conductivity is sufficiently low, it will have the properties of an "insulator." Therefore, it is also possible to use "semiconductor" instead of "insulator." In this case, the boundary between "semiconductor" and "insulator" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "insulator" described in this specification may be read interchangeably.

[0045] Furthermore, even when written as "semiconductor," if the conductivity is sufficiently high, it will have the properties of a "conductor." Therefore, it is also possible to use "semiconductor" instead of "conductor." In this case, the boundary between "semiconductor" and "conductor" is vague, and it is difficult to strictly distinguish between the two. Therefore, "semiconductor" and "conductor" described in this specification may be read interchangeably.

[0046] Note that ordinal numbers such as "first" and "second" used in this specification are used to avoid confusion between components, and do not indicate any order or ranking, such as the order of processes or stacking. Furthermore, even if a term does not have an ordinal number in this specification, an ordinal number may be added in the claims to avoid confusion between components. Furthermore, even if a term has an ordinal number in this specification, a different ordinal number may be added in the claims. Furthermore, even if a term has an ordinal number in this specification, the ordinal number may be omitted in the claims.

[0047] In this specification and the like, the "on state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically short-circuited (also referred to as a "conducting state"). The "off state" of a transistor refers to a state in which the source and drain of the transistor are considered to be electrically disconnected (also referred to as a "non-conducting state"). For example, a transistor in an on state can operate in a linear region.

[0048] In this specification, the term "on-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is on, and the term "off-state current" may refer to a current that flows between the source and drain of a transistor when the transistor is off.

[0049] In this specification and the like, a gate refers to a gate electrode and a part or the whole of a gate wiring. A gate wiring refers to a wiring for electrically connecting the gate electrode of at least one transistor to another electrode or another wiring.

[0050] In this specification, the term "source" refers to a source region, a source electrode, and part or all of a source wiring. The term "source region" refers to a region of a semiconductor layer having a resistivity equal to or lower than a certain value. The term "source electrode" refers to a conductive layer connected to a source region. The term "source wiring" refers to wiring for electrically connecting the source electrode of at least one transistor to another electrode or another wiring.

[0051] In this specification, the term "drain" refers to a drain region, a drain electrode, and part or all of a drain wiring. The term "drain region" refers to a region of a semiconductor layer whose resistivity is equal to or less than a certain value. The term "drain electrode" refers to a conductive layer connected to the drain region. The term "drain wiring" refers to wiring for electrically connecting the drain electrode of at least one transistor to another electrode or another wiring.

[0052] Embodiment 1 In this embodiment, a semiconductor device of one embodiment of the present invention will be described.

[0053] A semiconductor device according to one embodiment of the present invention includes a light-emitting device and an imaging device. The light-emitting device has a function of emitting, for example, infrared light or visible light. The imaging device has a function of detecting light. For example, a detection target can be irradiated with light emitted from the light-emitting device, and the imaging device can detect light reflected by the detection target. If the detection target is, for example, a finger of a user of the semiconductor device according to one embodiment of the present invention, the semiconductor device according to one embodiment of the present invention can perform fingerprint authentication or the like.

[0054] An imaging device included in a semiconductor device according to one embodiment of the present invention includes a pixel portion in which pixels are arranged in a matrix and a row driver circuit having a function of selecting, for each row, pixels from which image data is to be read.

[0055] For example, when fingerprint authentication is performed using a semiconductor device of one embodiment of the present invention, a row driver circuit first selects pixels in a specific row of the pixel portion (or a specified row within the pixel portion) and reads out first imaging data. This allows, for example, the position of a finger in contact with or close to the pixel portion to be detected. Next, the row driver circuit selects only pixels in the row in contact with or close to the finger and in rows surrounding the selected row, and reads out second imaging data, i.e., the user's fingerprint. In this way, the semiconductor device of one embodiment of the present invention performs fingerprint authentication.

[0056] Here, when reading out the first image data, it is only necessary to detect the position of the finger, and it is not necessary to read out the fingerprint image. Therefore, the first image data does not necessarily need to be read out from all the rows and columns of pixels in the pixel portion. For example, the first image data may be read out from a limited number of pixels, such as every few rows and every few columns. This shortens the readout period per pixel row compared to when the first image data is read out from all pixels in the pixel portion. On the other hand, when reading out the second image data, it is necessary to read out the fingerprint image from all pixels in a specified region, so the readout period per pixel row is longer than when the first image data is read out. In the semiconductor device according to one embodiment of the present invention, the second image data can be read out from only a portion of the pixels in the pixel portion for fingerprint authentication. Therefore, fingerprint authentication can be performed in a shorter time than when the second image data is read out from all pixels.

[0057] 1A is a diagram showing a configuration example of a semiconductor device 10. The semiconductor device 10 has a substrate 11 and a substrate 12, and a light emitting device 13 and an imaging device 15 are provided between the substrates 11 and 12. The light emitting device 13 and the imaging device 15 are provided on the same plane.

[0058] The light emitting device 13 has a function of emitting light 23. The light 23 can be infrared light or visible light.

[0059] The imaging device 15 has a function of detecting the irradiated light 25. Specifically, the imaging device 15 is provided with a light receiving element, and has a function of detecting the light 25 irradiated to the light receiving element.

[0060] In this specification, the term "element" can be appropriately replaced with "device." For example, a light-receiving element can be called a light-receiving device.

[0061] The light receiving element can be a photoelectric conversion element that detects incident light and generates an electric charge. The amount of electric charge generated by the light receiving element is determined based on the amount of incident light. For example, a pn-type or pin-type photodiode can be used as the light receiving element.

[0062] As the light-receiving element, it is preferable to use an organic photodiode having an organic compound in a photoelectric conversion layer. Organic photodiodes are easy to make thin, lightweight, and large-area. In addition, they have a high degree of freedom in shape and design, so they can be applied to various imaging devices. Alternatively, photodiodes using amorphous silicon, crystalline silicon (single crystal silicon, polycrystalline silicon, microcrystalline silicon, etc.), metal oxides, etc. can also be used as the light-receiving element.

[0063] When an organic compound is used in the photoelectric conversion layer of a photodiode, sensitivity from ultraviolet light to infrared light can be achieved by appropriately selecting the material. When amorphous silicon is used in the photoelectric conversion layer, sensitivity is mainly to visible light, and when crystalline silicon is used, sensitivity is mainly to visible light to infrared light. Because metal oxides have a large band gap, when a metal oxide is used in the photoelectric conversion layer, high sensitivity is mainly to light with higher energy than visible light. Note that, as the metal oxide, for example, In-M-Zn oxide (element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.) can be used.

[0064] The semiconductor device 10 can irradiate, for example, light 23 onto a detection object, and the imaging device 15 can detect the light reflected by the detection object as light 25 .

[0065] 1B is a diagram showing an example of the function of the semiconductor device 10. In Fig. 1B, the detection object is a finger 27. The finger 27 may be, for example, the finger of a user of the semiconductor device 10.

[0066] 1B, light 23 is irradiated onto a finger 27, and the light reflected by the finger 27 is detected as light 25 by the imaging device 15, thereby detecting a fingerprint 29 on the finger 27. This allows for authentication such as fingerprint authentication.

[0067] The light emitting device 13 and the imaging device 15 do not have to be provided on the same plane, and the light emitting device 13 may be arranged below the imaging device 15. For example, the light emitted from the light emitting device 13 may be reflected by the detection target through the imaging device 15, and the imaging device 15 may detect the reflected light.

[0068] <Configuration Example of Imaging Device> FIG. 2A is a block diagram showing a configuration example of the imaging device 15. The imaging device 15 includes a pixel section 30 in which m rows and n columns of pixels 31 (m and n are integers equal to or greater than 1) are arranged in a matrix, a control circuit 32, a row driver circuit 33, a CDS (Correlated Double Sampling) circuit 34, a readout circuit 36, and a detection circuit 37. Although not shown in FIG. 2A , the row driver circuit 33 includes a shift register circuit. A specific configuration example of the shift register circuit will be described later. Furthermore, a CDS circuit 34 can be provided for each column of pixels 31. FIG. 2A shows an example in which n CDS circuits 34 are provided.

[0069] In this specification and the like, when the same reference numeral is used for multiple elements, particularly when it is necessary to distinguish between them, an identification symbol such as "[ ]", "< >", "( )", or "_" may be added to the reference numeral. For example, the pixel 31 in the first row and first column will be referred to as pixel 31[1,1], and the pixel 31 in the mth row and nth column will be referred to as pixel 31[m,n]. Furthermore, the CDS circuit 34 in the first column will be referred to as CDS circuit 34[1], and the CDS circuit 34 in the nth column will be referred to as CDS circuit 34[n].

[0070] The row driver circuit 33 is electrically connected to the pixels 31 via wiring 43. The row driver circuit 33 is also electrically connected to the pixels 31 via wiring 44. Here, the wiring 43 is electrically connected to the terminal SL, and the wiring 44 is electrically connected to the terminal RS.

[0071] The CDS circuit 34 is electrically connected to the pixel 31 via a wiring 45. The CDS circuit 34 is also electrically connected to a readout circuit 36.

[0072] 2A illustrates a configuration in which pixels 31 in the same row are electrically connected to the same wiring 43 (terminal SL) and the same wiring 44 (terminal RS), and pixels 31 in the same column are electrically connected to the same wiring 45. In this specification, for example, the wiring 43 (terminal SL) electrically connected to the pixels 31 in the first row is referred to as wiring 43[1] (terminal SL[1]), and the wiring 43 (terminal SL) electrically connected to the pixels 31 in the mth row is referred to as wiring 43[m] (terminal SL[m]). Furthermore, for example, the wiring 44 (terminal RS) electrically connected to the pixels 31 in the first row is referred to as wiring 44[1] (terminal RS[1]), and the wiring 44 (terminal RS) electrically connected to the pixels 31 in the mth row is referred to as wiring 44[m] (terminal RS[m]). Furthermore, for example, the wiring 45 electrically connected to the pixels 31 in the first column is referred to as wiring 45[1], and the wiring 45 electrically connected to the pixels 31 in the nth column is referred to as wiring 45[n].

[0073] The control circuit 32 has a function of generating signals for controlling the driving of the row driver circuit 33. The control circuit 32 has a function of generating, for example, a start pulse signal, a clock signal, etc., and supplying them to the row driver circuit 33. Details of the signals that the control circuit 32 can generate will be described later.

[0074] The row driver circuit 33 has a function of selecting a pixel 31 from which imaging data is to be read. Specifically, by supplying a signal to a wiring 43 (terminal SL), the pixel 31 from which acquired imaging data is to be read can be selected. The row driver circuit 33 also has a function of selecting a pixel 31 from which imaging data is to be reset. Specifically, by supplying a signal to a wiring 44 (terminal RS), the pixel 31 from which acquired imaging data is to be reset can be selected. The row driver circuit is also referred to as a gate driver circuit or a scan driver circuit.

[0075] In this specification and the like, for example, a high-potential signal may be simply referred to as a “signal.” For example, supplying a high-potential signal may be simply referred to as “supplying a signal,” and supplying a low-potential signal may be simply referred to as “stopping the supply of a signal.”

[0076] The CDS circuit 34 has a function of performing correlated double sampling on the imaging data read out from the pixels 31. Correlated double sampling refers to taking the difference between the potential output from the pixels 31 when the imaging data is read out and the potential output from the pixels 31 when the imaging data is reset. By performing correlated double sampling, it is possible to reduce noise contained in the read imaging data.

[0077] The readout circuit 36 ​​has a function of sequentially outputting the imaging data output from the CDS circuits 34[1] to 34[n] to the detection circuit 37 and the like.

[0078] The detection circuit 37 has a function of detecting an object or the like based on the data output from the readout circuit 36. For example, when the semiconductor device 10 is driven as shown in FIG. 1B , the detection circuit 37 has a function of detecting the position of the finger 27. The detection circuit 37 also has a function of detecting a fingerprint 29 on the finger 27 and performing authentication.

[0079] The detection result by the detection circuit 37 is supplied to the control circuit 32. This allows the row driver circuit 33 to perform driving in accordance with the detection result by the detection circuit 37.

[0080] 2A do not necessarily have to be provided in the imaging device 15. For example, the control circuit 32 and the detection circuit 37 may be provided outside the imaging device 15.

[0081] <Pixel Configuration Example 1> FIG. 2B1 is a circuit diagram showing a configuration example of a pixel 31. The pixel 31 shown in FIG. 2B1 includes a light-receiving element 50, a transistor 51, a transistor 52, a transistor 53, a transistor 54, a capacitor 56, and a capacitor 57. The capacitor 56 may be omitted if the parasitic capacitance between the connected transistor and the wiring 49 can ensure a sufficient capacitance value for operation. The capacitor 57 may be omitted if the parasitic capacitance of the connected light-receiving element 50 can ensure a sufficient capacitance value for operation. In the following description, the transistors 51 to 54 are n-channel transistors. However, the following description can be referred to even if p-channel transistors are included by appropriately reversing the potential magnitude relationship. The light-receiving element 50 can also be connected by reversing the connection direction by appropriately adjusting the potential magnitude relationship.

[0082] One electrode of the light-receiving element 50 is electrically connected to one electrode of a capacitor 57. One electrode of the capacitor 57 is electrically connected to one of the source and drain of a transistor 51. The other of the source and drain of the transistor 51 is electrically connected to the gate of a transistor 52. One of the source and drain of the transistor 52 is electrically connected to one of the source and drain of a transistor 53. The gate of the transistor 52 is electrically connected to one of the source and drain of a transistor 54. One of the source and drain of the transistor 54 is electrically connected to one electrode of a capacitor 56. Note that a node to which the other of the source and drain of the transistor 51, the gate of the transistor 52, the one of the source and drain of the transistor 54, and one electrode of the capacitor 56 are electrically connected is referred to as a node FD.

[0083] The gate of the transistor 51 is electrically connected to the wiring 41. The gate of the transistor 53 is electrically connected to the wiring 43 (terminal SL). The gate of the transistor 54 is electrically connected to the wiring 44 (terminal RS). The other of the source and the drain of the transistor 53 is electrically connected to the wiring 45. The other electrode of the light-receiving element 50 and the other electrode of the capacitor 57 are electrically connected to the wiring 46. The other of the source and the drain of the transistor 52 is electrically connected to the wiring 47. The other of the source and the drain of the transistor 54 is electrically connected to the wiring 48. The other electrode of the capacitor 56 is electrically connected to the wiring 49.

[0084] A power supply potential can be supplied to the wirings 46 to 49. Therefore, the wirings 46 to 49 can be said to function as power supply lines. For example, a high potential can be supplied to the wiring 47, and a low potential can be supplied to the wiring 49. Furthermore, as shown in FIG. 2B1 , when the cathode of the light-receiving element 50 is electrically connected to the wiring 46, the wiring 46 can be at a high potential and the wiring 48 can be at a low potential. On the other hand, when the anode of the light-receiving element 50 is electrically connected to the wiring 46, the wiring 46 can be at a low potential and the wiring 48 can be at a high potential.

[0085] 2B2 is a timing chart illustrating an example of a method for driving the pixel 31 having the configuration shown in FIG. 2B1. Here, the potential of the wiring 46 is high, and the potential of the wiring 48 is low. Note that in FIG. 2B2, "H" indicates high potential, and "L" indicates low potential. The same notation is used in other timing charts. In FIG. 2B2, periods T1 to T5 are shown as periods during which the pixel 31 is driven.

[0086] In the period T1, the potentials of the wiring 41 and the wiring 44 (terminal RS) are set to high potential, and the potential of the wiring 43 (terminal SL) is set to low potential. As a result, the transistors 51 and 54 are turned on, and the transistor 53 is turned off. When the transistor 54 is turned on, the potential of the node FD becomes low, which is the potential of the wiring 48. Furthermore, when the transistor 51 and the transistor 54 are turned on, the potential of one electrode of the light-receiving element 50 also becomes low, which is the potential of the wiring 48, although not shown in FIG. 2B2. As a result, the charges accumulated in the capacitors 56 and 57 are reset. Therefore, the period T1 is a reset period, and the operation performed in the period T1 can be considered to be a reset operation.

[0087] In the period T2, the potentials of the wiring 41 and the wiring 44 (terminal RS) are set to low. As a result, the transistors 51 and 54 are turned off. When the light-receiving element 50 is irradiated with light in this state, charge corresponding to the energy of the light incident on the light-receiving element 50 is accumulated in the capacitor 57. Therefore, the period T2 can be considered an exposure period, and the operation performed in the period T2 can be considered an exposure operation.

[0088] In the period T3, the potential of the wiring 41 is set to a high potential. As a result, the transistor 51 is turned on, and the charge accumulated in the capacitor 57 is transferred to the node FD. As a result, the potential of the node FD increases. Therefore, the period T3 is a transfer period, and the operation performed in the period T3 can be considered a transfer operation.

[0089] In the period T4, the potential of the wiring 41 is set to low, which turns off the transistor 51 and stops the transfer of charge from the capacitor 57 to the node FD.

[0090] In this way, the image data is acquired by the pixel 31. Specifically, the potential of the node FD becomes a potential corresponding to the image data. Therefore, it can be said that the periods T1 to T4 are acquisition periods, and the operations performed in the periods T1 to T4 are acquisition operations.

[0091] Next, an example of a driving method in the period T5 will be described. During the period T5, the potential of the wiring 43 (terminal SL) is set to a high potential. This turns on the transistor 53, and a signal representing image data acquired by the pixel 31 is output to the wiring 45. Specifically, the potential of the wiring 45 corresponds to the potential of the node FD. This allows the image data acquired by the pixel 31 to be read.

[0092] As described above, by supplying a high-potential signal to the wiring 43 (terminal SL), imaging data acquired by the pixel 31 is read out. That is, the pixel 31 from which imaging data is to be read can be selected by the signal supplied to the wiring 43 (terminal SL). Therefore, the signal supplied to the wiring 43 (terminal SL) can be said to be a selection signal.

[0093] After the image data is read, the potential of the wiring 44 (terminal RS) is set to high. This turns on the transistor 54, and the image data acquired by the pixel 31 is reset. Specifically, the potential of the node FD becomes low, which is the potential of the wiring 48. Here, because the transistor 53 is on, the potential of the wiring 45 also changes in response to the change in the potential of the node FD. As described above, correlated double sampling can be performed by the CDS circuit 34 electrically connected to the wiring 45.

[0094] As described above, supplying a high-potential signal to the wiring 44 (terminal RS) resets the imaging data acquired by the pixel 31. Therefore, the signal supplied to the wiring 44 (terminal RS) can be said to be a reset signal.

[0095] After the correlated double sampling, the potential of the wiring 44 (terminal RS) is set to low to turn off the transistor 54, and the potential of the wiring 43 (terminal SL) is set to low to turn off the transistor 53.

[0096] The above is an example of a driving method in the period T5. In the period T5, the imaging data acquired by the pixels 31 is read out. Therefore, the period T5 is a readout period, and the operation performed in the period T5 can be said to be a readout operation.

[0097] It is preferable that the acquisition of imaging data by pixels 31[1,1] to 31[m,n] be performed by a global shutter system. Here, the global shutter system refers to a system in which imaging data is acquired simultaneously by all pixels. By acquiring imaging data by the global shutter system, it is possible to ensure the simultaneity of imaging, and therefore it is possible to easily obtain an image with little distortion even when the subject is moving at high speed.

[0098] On the other hand, the reading of imaging data from the pixels 31[1,1] to 31[m,n] is performed, for example, row by row. Therefore, when imaging data is acquired by the global shutter system, there are pixels 31 in which the period from acquisition to reading of imaging data becomes long. Therefore, when imaging data is acquired by the global shutter system, it is preferable to be able to hold the charge transferred from the capacitor 57 to the node FD for a long period of time.

[0099] To hold charge in the node FD for a long period of time, a transistor electrically connected to the node FD may have low off-state current. An example of a transistor with low off-state current is a transistor having a metal oxide in a channel formation region (hereinafter referred to as an OS transistor). Therefore, the transistors 51 and 54 are preferably OS transistors.

[0100] The OS transistor preferably has a metal oxide in a channel formation region. The metal oxide preferably contains at least indium or zinc. In particular, it is preferable to contain indium and zinc. Furthermore, it is preferable to contain aluminum, gallium, yttrium, tin, or the like in addition to these. Furthermore, the metal oxide may contain one or more elements selected from the group consisting of boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0101] The OS transistor has an off-state current of 1 yA / μm (y; yocto, 10 −２４ ) or more than 1zA / μm (z; Zepto, 10 −２１) or less.

[0102] Further, it is preferable to use a C-Axis-Aligned Crystalline (CAAC)-OS or a Cloud-Aligned Composite (CAC)-OS for the OS transistor. The details of the CAAC-OS and the CAC-OS will be described in later embodiments.

[0103] As long as the off-state current is low, OS transistors do not have to be used as the transistors 51 and 54. For example, transistors including a semiconductor with a wide band gap may be used. A wide band gap semiconductor may refer to a semiconductor with a band gap of 2.2 eV or more. Examples of such semiconductors include silicon carbide, gallium nitride, and diamond.

[0104] Note that the transistors 51 and 54 may be transistors having silicon in their channel formation regions (hereinafter referred to as Si transistors), or the like. Si transistors have a higher off-state current than OS transistors. However, even if the off-state currents of the transistors 51 and 54 are high, by increasing the capacitance value of the capacitor 56, for example, image data can be acquired by the pixels 31[1,1] to 31[m,n] using a global shutter system. Note that image data can also be acquired by the pixels 31[1,1] to 31[m,n] using a rolling shutter system. In this case, even if the transistors 51 and 54 are transistors with a high off-state current, the capacitance value of the capacitor 56 does not need to be increased.

[0105] The transistors 52 and 53 may be Si transistors or OS transistors. For example, when transistors including crystalline silicon (typically, low-temperature polysilicon (also referred to as LTPS), single-crystal silicon, or the like) are used as the transistors 52 and 53, the on-state current of the transistors 52 and 53 can be increased. Therefore, image data can be read at high speed. On the other hand, when the transistors 51 to 54 are all OS transistors, all the transistors included in the pixel 31 can be formed in the same layer. Furthermore, when all the transistors included in the semiconductor device 10, including the transistors 51 to 54, are OS transistors, all the transistors included in the semiconductor device 10 can be formed in the same layer. Thus, the manufacturing process of the semiconductor device 10 can be simplified. Note that the transistors 51 to 54 may be transistors including amorphous silicon in their channel formation regions. Note that the transistors 51 to 54 may be a combination of Si transistors (typically, LTPS transistors) and OS transistors. Note that a structure in which an LTPS transistor and an OS transistor are combined may be referred to as LTPO. For example, when an OS transistor is used as a transistor that functions as a switch for controlling conduction or non-conduction between wirings and an LTPS transistor is used as a transistor for controlling current, a display device with high display quality can be obtained.

[0106] <Configuration Example of Shift Register Circuit> FIG. 3 is a diagram showing a configuration example of the row driver circuit 33. Specifically, it is a diagram showing a configuration example of the shift register circuit included in the row driver circuit 33. The shift register circuit includes a register circuit F, a register circuit S, a selection circuit M, and a signal supply circuit B. Here, the shift register circuit may be provided with, for example, m register circuits F, m selection circuits M, and m signal supply circuits B. That is, the number of selection circuits M, register circuits F, and m signal supply circuits B may be the same as the number of rows of pixels 31 in the pixel unit 30 described in FIG. 2A with m rows and n columns. Furthermore, t register circuits S (where t is an integer greater than or equal to 1) may be provided. Here, the relationship between m and t may be m = t × 50. That is, a register circuit S may be provided for every 50th row of pixels 31 included in the pixel unit 30.

[0107] The register circuit F, the register circuit S, the selection circuit M, and the signal supply circuit B are electrically connected to input terminals for inputting signals and output terminals for outputting signals, respectively.

[0108] In this specification and the like, an input terminal electrically connected to a register circuit F may be referred to as an input terminal of the register circuit F or an input terminal of the register circuit F. Also, an output terminal electrically connected to a register circuit F may be referred to as an output terminal of the register circuit F or an output terminal of the register circuit F. The same applies to other circuits and the like.

[0109] The terminal SP1 is electrically connected to the input terminal of the register circuit F[1]. The signal output from the register circuit F[1] is input to the register circuit F[2] via the terminal FOUT[1]. Note that the terminal SP1 may also be referred to as the terminal FOUT[0].

[0110] The register circuit F[1] has two output terminals between it and the selection circuit M[1]. One output terminal is electrically connected to a different input terminal of the selection circuit M[1] via a terminal FO1[1], and the other output terminal is electrically connected to a different input terminal of the selection circuit M[1] via a terminal FFN[1].

[0111] Similarly, the register circuit F[2] has two output terminals between it and the selection circuit M[2], one of which is electrically connected to a different input terminal of the selection circuit M[2] via a terminal FO1[2] and the other via a terminal FFN[2]. The register circuit F[3] has two output terminals between it and the selection circuit M[3], one of which is electrically connected to a different input terminal of the selection circuit M[3] via a terminal FO1[3] and the other via a terminal FFN[3]. The register circuit F[4] has two output terminals between it and the selection circuit M[4], one of which is electrically connected to a different input terminal of the selection circuit M[4] via a terminal FO1[4] and the other via a terminal FFN[4].

[0112] That is, the register circuits F[1] to F[m] each have two output terminals between them and the selection circuits M[1] to M[m], and one output terminal is electrically connected to a different input terminal of the selection circuits M[1] to M[m] via the terminal FO1, and the other output terminal is electrically connected to a different input terminal of the selection circuits M[1] to M[m] via the terminal FFN (register circuit F[m] and selection circuit M[m] are not shown in Figure 3).

[0113] As described above, the signal output from register circuit F[1] is input to register circuit F[2] via terminal FOUT[1] electrically connected to register circuit F[1]. Similarly, the signal output from register circuit F[2] is input to register circuit F[3] via terminal FOUT[2] electrically connected to register circuit F[2]. Furthermore, the signal output from register circuit F[3] is input to register circuit F[4] via terminal FOUT[3] electrically connected to register circuit F[3]. Furthermore, the signal output from register circuit F[4] is input to register circuit F[5] via terminal FOUT[4] electrically connected to register circuit F[4].

[0114] That is, the signals output by register circuits F[1] to F[m-1] are input to the subsequent register circuits F[2] to F[m] via terminals FOUT[1] to FOUT[m-1] (not shown in Figure 3) that are electrically connected to register circuits F[1] to F[m-1], respectively.

[0115] The signal output by register circuit F[3] is input to register circuit F[1] via terminal FOUT[3]. The signal output by register circuit F[4] is input to register circuit F[2] via terminal FOUT[4]. The signal output by register circuit F[5] is input to register circuit F[3] via terminal FOUT[5].

[0116] That is, the signals output from register circuits F[3] to F[m] are input to the register circuits F[1] to F[m-2] in the previous stage via terminals FOUT[3] to FOUT[m], respectively.

[0117] 3, the register circuit F[1] is electrically connected to the terminals CLK1[1] to CLK1[4], for example, three terminals CLK1. The terminals CLK1[1] to CLK1[4] are electrically connected to the input terminals of the register circuits F[1] to F[m]. For example, as shown in FIG. 3, the register circuit F[1] is electrically connected to the terminals CLK1[1], CLK1[2], and CLK1[3], the register circuit F[2] is electrically connected to the terminals CLK1[2], CLK1[3], and CLK1[4], the register circuit F[3] is electrically connected to the terminals CLK1[3], CLK1[4], and CLK1[1], and the register circuit F[4] is electrically connected to the terminals CLK1[4], CLK1[1], and CLK1[2]. The number of terminals CLK1 that the row driver circuit 33 has is not limited to four, and the number of terminals CLK1 electrically connected to one register circuit F is not limited to three.

[0118] Furthermore, the register circuits F[1] to F[m] are all electrically connected to the terminal RES1.

[0119] The input terminal of the register circuit S[1] is electrically connected to the terminal SP2. The signal output from the register circuit S[1] is input to the register circuit S[2] (not shown in FIG. 3) via the terminal SOUT[1]. Note that the terminal SP2 may also be referred to as the terminal SOUT[0].

[0120] The register circuit S[1] has two output terminals between the selection circuits M[5] and M[6]. One output terminal is electrically connected to different input terminals of the selection circuits M[5] and M[6] via terminal SO1[1], and the other output terminal is electrically connected to different input terminals of the selection circuits M[5] and M[6] via terminal SFN[1].

[0121] 3, the signal output from the register circuit S[2] immediately following the register circuit S[1] is input to the register circuit S[1] via the terminal SOUT[2] electrically connected to the register circuit S[2]. Similarly, the signals output from the register circuits S[3] to S[t] are input to the preceding register circuits S[2] to S[t-1] via the terminals SOUT[3] to SOUT[t] electrically connected to the register circuits S[3] to S[t-1].

[0122] Furthermore, for example, two terminals CLK2 out of the terminals CLK2[1] to CLK2[4] are electrically connected to the input terminals of the register circuits S[1] to S[t]. For example, as shown in FIG. 3, the terminals CLK2[1] and CLK2[2] are electrically connected to the register circuit S[1]. Although not shown in FIG. 3, the terminals CLK2[2] and CLK2[3] are electrically connected to the register circuit S[2], the terminals CLK2[3] and CLK2[4] are electrically connected to the register circuit S[3], and the terminals CLK2[4] and CLK2[1] are electrically connected to the register circuit S[t]. Note that the number of terminals CLK2 included in the row driver circuit 33 is not limited to four, and the number of terminals CLK2 electrically connected to one register circuit S is not limited to two.

[0123] The register circuits S[1] to S[t] are all electrically connected to a terminal RES2. The register circuits S[1] to S[t] are all electrically connected to a terminal RD2_VDD. Here, the terminal RD2_VDD is a terminal that supplies a potential from a high-potential power supply.

[0124] As described above, the register circuit S[1] has two output terminals between the selection circuits M[5] and M[6], one output terminal is electrically connected to a different input terminal of the selection circuits M[5] and M[6] via the terminal SO1[1], and the other output terminal is electrically connected to a different input terminal of the selection circuits M[5] and M[6] via the terminal SFN[1]. Also, although not shown in FIG. 3, the register circuit S[2] has two output terminals between the selection circuits M

[10] and M

[11] , one output terminal is electrically connected to a different input terminal of the selection circuits M

[10] and M

[11] via the terminal SO1[2], and the other output terminal is electrically connected to a different input terminal of the selection circuits M

[10] and M

[11] via the terminal SFN[2]. Furthermore, the register circuit S[3] has two output terminals between the selection circuits M

[15] and M

[16] , one output terminal is electrically connected to different input terminals of the selection circuits M

[15] and M

[16] via terminal SO1[3] and the other output terminal is electrically connected to different input terminals of the selection circuits M

[15] and M

[16] via terminal SFN[3]. That is, in the case of the register circuit S[t], it has two output terminals between the selection circuits M[5t] and M[5t+1], one output terminal is electrically connected to different input terminals of the selection circuits M[5t] and M[5t+1] via terminal SO1[t] and the other output terminal is electrically connected to different input terminals of the selection circuits M[5t] and M[5t+1] via terminal SFN[t]. In this way, all the register circuits S are electrically connected to the selection circuits M according to the above rules.

[0125] 3, all of the selection circuits M except for the selection circuits M[5] and M[6], i.e., the selection circuits M not electrically connected to the register circuit S[1], are electrically connected to the terminal RD_VDD. Here, the terminal RD_VDD is a terminal that supplies a potential from a high-potential power supply. Also, all of the selection circuits M except for the selection circuits M[5] and M[6] are electrically connected to the terminal RD_VSS. Here, the terminal RD_VSS is a terminal that supplies a potential from a low-potential power supply.

[0126] 3 shows only the selection circuits M[1] to M[7], the selection circuits M that are not electrically connected to the register circuit S among all the selection circuits M (selection circuits M[1] to M[m]) included in the row driver circuit 33 are electrically connected to the terminal RD_VDD as described above and are also electrically connected to the terminal RD_VSS.

[0127] The selection circuit M[1] has two output terminals between it and the signal supply circuit B[1]. One output terminal is electrically connected to a different input terminal of the signal supply circuit B[1] via a terminal O1[1], and the other output terminal is electrically connected to a different input terminal of the signal supply circuit B[1] via a terminal FN[1].

[0128] Similarly, the selection circuit M[2] has two output terminals between it and the signal supply circuit B[2], one output terminal electrically connected to a different input terminal of the signal supply circuit B[2] via terminal O1[2] and the other output terminal electrically connected to a different input terminal of the signal supply circuit B[2] via terminal FN[2]. The selection circuit M[3] has two output terminals between it and the signal supply circuit B[3], one output terminal electrically connected to a different input terminal of the signal supply circuit B[3] via terminal O1[3] and the other output terminal electrically connected to a different input terminal of the signal supply circuit B[3] via terminal FN[3]. The selection circuit M[4] has two output terminals between it and the signal supply circuit B[4], one output terminal electrically connected to a different input terminal of the signal supply circuit B[4] via terminal O1[4] and the other output terminal electrically connected to a different input terminal of the signal supply circuit B[4] via terminal FN[4].

[0129] That is, the selection circuits M[1] to M[m] have two output terminals between the signal supply circuits B[1] to M[m], respectively, and one output terminal is electrically connected to a different input terminal of the signal supply circuits B[1] to B[m] via terminal O1, and the other output terminal is electrically connected to a different input terminal of the signal supply circuits B[1] to B[m] via terminal FN (the selection circuit M[m] and the signal supply circuit B[m] are not shown in Figure 3).

[0130] The selection circuits M[1] to M[m] are electrically connected to the terminals SEL1 and SEL2, respectively. Here, the terminals SEL1 and SEL2 are circuit selection signal terminals.

[0131] 3, for example, selection circuits M[5] and M[6] select either the output signal supplied from register circuit F[5] and register circuit F[6] or the output signal supplied from register circuit S[1]. In this case, depending on the selection signals supplied from terminals SEL1 and SEL2, either terminal FO1[5] and terminal FO1[6] or terminal SO1[1] is selected, and one of the output signals described above is input to selection circuits M[5] and selection circuits M[6]. The input signal is then supplied to signal supply circuits B[5] and signal supply circuits B[6] via terminals O1[5] and O1[6], respectively.

[0132] Similarly, although not shown in FIG. 3 , selection circuits M

[10] and M

[11] select either the output signal supplied from register circuit F

[10] and register circuit F

[11] or the output signal supplied from register circuit S[2], respectively, in response to selection signals supplied from terminals SEL1 and SEL2. The input signals are supplied to signal supply circuits B

[10] and B

[11] , respectively, via terminals O1

[10] and O1

[11] . Selection circuits M

[15] and M

[16] also select either the output signal supplied from register circuit F

[15] and register circuit F

[16] or the output signal supplied from register circuit S[3], respectively, in response to selection signals supplied from terminals SEL1 and SEL2. The input signals are supplied to signal supply circuits B

[15] and B

[16] , respectively, via terminals O1

[15] and O1

[16] . That is, in the case of the selection circuits M[5t] and M[5t+1], the output signal supplied from the register circuit F[5t] and the register circuit F[5t+1], or the output signal supplied from the register circuit S[t], is selected according to the selection signals supplied from the terminals SEL1 and SEL2. The input signals are then supplied to the signal supply circuits B[5t] and B[5t+1] via the terminals O1[5t] and O1[5t+1], respectively.

[0133] Furthermore, among the selection circuits M[1] to M[m], the selection circuits M that do not fall under the above description, i.e., the selection circuits M that are not electrically connected to the register circuit S, select whether to input a signal supplied from the terminal FO1[1] to the terminal FO1[m] or a signal (low potential) supplied from the terminal RD_VSS. At this time, one of the two types of signals described above is selected according to the selection signals supplied from the terminals SEL1 and SEL2, and the selected signal is output to the terminals O1[1] to O1[m], respectively. Furthermore, among the selection circuits M[1] to M[m], the selection circuits M that do not fall under the above description, i.e., the selection circuits M that are not electrically connected to the register circuit S, also select whether to input a signal supplied from the terminals FFN[1] to FFN[m] or a signal (low potential) supplied from the terminal RD_VSS, respectively. At this time, one of the two types of signals described above is selected depending on the selection signals supplied from terminals SEL1 and SEL2, and the selected signal is output to terminals FN[1] to FN[m], respectively.

[0134] 3, each of the signal supply circuits B is electrically connected to a terminal RD_VDD. Here, the terminal RD_VDD is a terminal that supplies a potential from a high-potential power supply. Each of the signal supply circuits B is also electrically connected to a terminal RD_VSS. Here, the terminal RD_VSS is a terminal that supplies a potential from a low-potential power supply. Furthermore, each of the signal supply circuits B is also electrically connected to a terminal RS_VSS.

[0135] 3, the signal supply circuit B[1] is electrically connected to the terminal SL_PWC1, the signal supply circuit B[2] is electrically connected to the terminal SL_PWC2, the signal supply circuit B[3] is electrically connected to the terminal SL_PWC3, and the signal supply circuit B[4] is electrically connected to the terminal SL_PWC4. Note that the number of terminals SL_PWC of the row driver circuit 33 is not limited to four.

[0136] 3, the signal supply circuit B is electrically connected to one terminal RS_PWC among the terminals RS_PWC1 to RS_PWC4. For example, as shown in FIG. 3, the signal supply circuit B[1] is electrically connected to the terminal RS_PWC1, the signal supply circuit B[2] is electrically connected to the terminal RS_PWC2, the signal supply circuit B[3] is electrically connected to the terminal RS_PWC3, and the signal supply circuit B[4] is electrically connected to the terminal RS_PWC4. The number of terminals RS_PWC of the row driver circuit 33 is not limited to four.

[0137] Terminals SL[1] to SL[m] and terminals RS[1] to RS[m] are electrically connected to the output terminals of the signal supply circuits B[1] to B[m], respectively. As described in FIG. 2, the signal output to the terminal SL can be a selection signal, and the signal output to the terminal RS can be a reset signal. Therefore, the terminal SL can be referred to as a selection signal output terminal, and the terminal RS can be referred to as a reset signal output terminal.

[0138] A start pulse signal is input to terminals SP1 and SP2. Thus, terminals SP1 and SP2 are start pulse signal input terminals. By inputting a start pulse signal to terminal SP1 or terminal SP2, the shift register circuit shown in FIG. 3 can start operating.

[0139] A clock signal is input to the terminals CLK1[1] to CLK1[4]. Therefore, the terminals CLK1[1] to CLK1[4] are clock signal input terminals. For example, the clock signals input to the terminals CLK1[1] to CLK1[4] can be signals with different phases, and the register circuits F[1] to F[m] can be driven in response to the clock signals.

[0140] Specifically, by inputting a start pulse signal to terminal SP1, any one of register circuits F[1] to F[m] outputs a signal to terminal FO1 and terminal FFN. The signal output to terminal FOUT can be input to the register circuit F in the next stage, which allows the register circuit F in the next stage to output a signal. Therefore, the signal output by register circuit F to terminal FOUT and the signal input to register circuit F via terminal FOUT can be called a scanning signal.

[0141] Furthermore, by inputting a start pulse signal to terminal SP2, any one of register circuits S[1] to S[t] outputs a signal to terminal SO1 and terminal SFN. The signal output to terminal SOUT can be input to the register circuit S in the next stage, which allows the register circuit S in the next stage to output a signal. Therefore, the signal output by register circuit S to terminal SOUT and the signal input to register circuit S via terminal SOUT can be called a scanning signal.

[0142] As described above, the signal output by the register circuit F to the terminal FO1 and the signal output by the register circuit F to the terminal FFN are input to the selection circuit M. In addition, the signal output by the register circuit S to the terminal SO1 and the signal output to the terminal SFN are input to the selection circuit M. In response to inputs from the terminals SEL1 and SEL2, the selection circuit M outputs one of the input signals from the terminal FO1 or the terminal SO1 to the signal supply circuit B via the terminal O1. In response to inputs from the terminals SEL1 and SEL2, the selection circuit M outputs one of the input signals from the terminal FFN or the terminal SFN to the signal supply circuit B via the terminal FN. In response to inputs from the terminals O1 and FN, the signal supply circuit B outputs a selection signal to the pixel 31 via the terminal SL and outputs a reset signal to the pixel 31 via the terminal RS.

[0143] 4A is a circuit diagram showing an example configuration of a register circuit F. The register circuit F includes transistors Tr11, Tr13, Tr14, Tr15, Tr17, Tr19, Tr20, Tr21, Tr22, Tr23, Tr24, Tr25, and capacitors C11 and C21. In FIG. 4A and other figures, the transistors Tr19, Tr20, and capacitor C11 constitute a circuit 60.

[0144] 4A and other figures, the terminal CLK1[k1], the terminal CLK1[k2], and the terminal CLK1[k3] may be any of the multiple terminals CLK1 described above. For example, the register circuit F included in the row driver circuit 33 may have terminals CLK1[1] to CLK1[4]. In this case, the terminal CLK1[k1] may be any one of the terminals CLK1[1] to CLK1[4], the terminal CLK1[k2] may be any one of the terminals CLK1[1] to CLK1[4], excluding the terminal CLK1 that is the same as the terminal CLK1[k1], and the terminal CLK1[k3] may be any one of the terminals CLK1[1] to CLK1[4], excluding the terminal CLK1 that is the same as the terminal CLK1[k1] and the terminal CLK1[k2].

[0145] Specifically, for example, in the register circuit F[1], the terminal CLK1[k1] can be the terminal CLK1[1], the terminal CLK1[k2] can be the terminal CLK1[2], and the terminal CLK1[k3] can be the terminal CLK1[3]. In the register circuit F[2], the terminal CLK1[k1] can be the terminal CLK1[2], the terminal CLK1[k2] can be the terminal CLK1[3], and the terminal CLK1[k3] can be the terminal CLK1[4]. In the register circuit F[3], the terminal CLK1[k1] can be the terminal CLK1[3], the terminal CLK1[k2] can be the terminal CLK1[4], and the terminal CLK1[k3] can be the terminal CLK1[1].

[0146] In the register circuit F having the configuration shown in FIG. 4A , the terminal CLK1[k1] is electrically connected to one of the source and drain of the transistor Tr20. The terminal CLK1[k2] is electrically connected to the gate of the transistor Tr14. The terminal CLK1[k3] is electrically connected to the gate of the transistor Tr13. The terminal RIN is electrically connected to the gate of the transistor Tr15. Here, the terminal RIN refers to the terminal FOUT that inputs to the register circuit F in the second previous stage among all the terminals FOUT electrically connected to the register circuit F described in FIG. 3 . That is, among the terminals FOUT[1] to FOUT[m], the terminals FOUT[3] to FOUT[m] correspond to the terminal RIN. For example, the terminal FOUT[3] corresponds to the terminal RIN[1]. The terminal FOUT[4] corresponds to the terminal RIN[2]. Furthermore, the terminal FOUT[5] corresponds to the terminal RIN[3]. The terminal RES1 is electrically connected to the gate of transistor Tr17. The terminal RD_VDD is electrically connected to one of the source or drain of transistor Tr11, one of the source or drain of transistor Tr13, one of the source or drain of transistor Tr15, one of the source or drain of transistor Tr17, and the gate of transistor Tr19. The terminal LIN is electrically connected to the gate of transistor Tr11, the gate of transistor Tr23, and the gate of transistor Tr24. Here, the terminal LIN refers to the terminal FOUT, which is located three stages behind the above-mentioned terminal RIN. For example, FOUT[3] corresponds to terminal LIN[4]. Furthermore, terminal FOUT[4] corresponds to terminal LIN[5]. Furthermore, terminal FOUT[5] corresponds to terminal LIN[6]. The terminal RD_VSS is electrically connected to one of the source or drain of the transistor Tr22, one electrode of the capacitor C21, one of the source or drain of the transistor Tr24, and one of the source or drain of the transistor Tr25. The terminal FO1 is electrically connected to the other of the source or drain of the transistor Tr11, one of the source or drain of the transistor Tr21, and one of the source and drain of the transistor Tr19.The terminal FFN is electrically connected to the gate of transistor Tr21, the gate of transistor Tr22, one of the source or drain of transistor Tr14, the other electrode of capacitor C21, the other of the source or drain of transistor Tr15, one of the source or drain of transistor Tr23, the other of the source or drain of transistor Tr17, and the gate of transistor Tr25. The terminal FOUT is electrically connected to the other of the source or drain of transistor Tr20, the other of the source or drain of transistor Tr25, and one electrode of capacitor C11.

[0147] If the gate capacitance of the transistor Tr21 and the gate capacitance of the transistor Tr25 are sufficiently large, the register circuit F does not need to have the capacitor C21.

[0148] The other of the source or drain of transistor Tr13 is electrically connected to the other of the source or drain of transistor Tr14. The other of the source or drain of transistor Tr21 is electrically connected to the other of the source or drain of transistor Tr22. The other of the source or drain of transistor Tr23 is electrically connected to the other of the source or drain of transistor Tr24.

[0149] The other of the source and drain of the transistor Tr19, the gate of the transistor Tr20, and the other electrode of the capacitor C11 are electrically connected to one another. By providing the transistor Tr19 in the register circuit F, the circuit 60 can be configured as a bootstrap circuit. Note that the register circuit F does not necessarily have to include the transistor Tr19. In this case, the capacitor C11 may also be omitted.

[0150] In the following explanation, transistor Tr11, transistor Tr13, transistor Tr14, transistor Tr15, transistor Tr17, transistor Tr19, transistor Tr20, transistor Tr21, transistor Tr22, transistor Tr23, transistor Tr24, and transistor Tr25 are assumed to be n-channel transistors, but the following explanation can be referred to even if p-channel transistors are included by appropriately reversing the magnitude relationship of the potentials, for example.

[0151] A high potential can be supplied to one of the source or drain of transistor Tr11, one of the source or drain of transistor Tr13, one of the source or drain of transistor Tr15, one of the source or drain of transistor Tr17, and the gate of transistor Tr19. A low potential can be supplied to one of the source or drain of transistor Tr22, one of the source or drain of transistor Tr24, one of the source or drain of transistor Tr25, and one electrode of capacitor C21.

[0152] When a high-potential signal is input to the terminal LIN, the transistors Tr11, Tr23, and Tr24 are turned on. With the transistor Tr11 turned on, if the transistors Tr21 and Tr22 are turned off, a high-potential signal is output from the terminal FO1, and the potential of the gate of the transistor Tr20 becomes high. With the potential of the gate of the transistor Tr20 becoming high, the transistor Tr20 is turned on. Therefore, the signal input to the terminal CLK1[k1] can be output to the terminal FOUT.

[0153] On the other hand, when a high-potential signal is input to terminal CLK1[k2] and terminal CLK1[k3], transistors Tr14 and Tr13 are turned on. This causes the potentials of the gates of transistors Tr21, Tr22, and Tr25 to be high. Since the potentials of the gates of transistors Tr21 and Tr22 are high, transistors Tr21 and Tr22 are turned on. Therefore, if transistor Tr11 is off, the potential of terminal FO1 is low. Furthermore, since the potential of the gate of transistor Tr25 is high, transistor Tr25 is turned on. Since transistors Tr21 and Tr25 are on, the potential of terminal FOUT is low. Similarly, when a high-potential signal is input to terminal RIN or terminal RES1, the potentials of terminals FO1 and FOUT are low.

[0154] Here, the transistor Tr19 is preferably a transistor with low off-state current, such as an OS transistor. This allows the gate potential of the transistor Tr20 to be held at a low potential even after the terminal LIN is set to a low potential and the transistor Tr11 is turned off. Therefore, a signal input to the terminal CLK1[k1] can be continuously output to the terminal FOUT until the terminal CLK1[k2], the terminal RIN, or the terminal RES1 is set to a high potential.

[0155] The transistors Tr11, Tr13, Tr14, Tr15, Tr17, Tr20, Tr21, Tr22, Tr23, Tr24, and Tr25 may also be OS transistors. By using OS transistors as all the transistors included in the register circuit F, all the transistors included in the register circuit F can be manufactured in the same process.

[0156] Furthermore, Si transistors can be used for transistors Tr11, Tr13, Tr14, Tr15, Tr17, Tr19, Tr20, Tr21, Tr22, Tr23, Tr24, and Tr25. In particular, using transistors having crystalline silicon in their channel formation regions as these transistors can increase the on-state current. This allows the register circuit F to operate at high speed. Furthermore, transistors having amorphous silicon in their channel formation regions can be used for transistors Tr11, Tr13, Tr14, Tr15, Tr17, Tr19, Tr20, Tr21, Tr22, Tr23, Tr24, and Tr25.

[0157] 4B is a circuit diagram showing a configuration example of a register circuit S. The register circuit S differs from the register circuit F in that it does not include a transistor Tr13. The register circuit S also differs from the register circuit F in that the gate of the transistor Tr17 is electrically connected to the terminal RES2. The register circuit S also differs from the register circuit F in that one of the source or drain of the transistor Tr11, one of the source or drain of the transistor Tr14, one of the source or drain of the transistor Tr15, one of the source or drain of the transistor Tr17, and the gate of the transistor Tr19 are electrically connected to the terminal RD2_VDD. The register circuit S also differs from the register circuit F in that the other of the source or drain of the transistor Tr11, one of the source or drain of the transistor Tr21, and one of the source or drain of the transistor Tr19 are electrically connected to the terminal SO1. Also, the register circuit F differs in that the gate of transistor Tr21, the gate of transistor Tr22, the other of the source or drain of transistor Tr14, the other electrode of capacitor C21, the other of the source or drain of transistor Tr15, one of the source or drain of transistor Tr23, the other of the source or drain of transistor Tr17, and the gate of transistor Tr25 are electrically connected to the terminal SFN. Also, the register circuit F differs in that the other of the source or drain of transistor Tr20, the other of the source or drain of transistor Tr25, and one electrode of capacitor C11 are electrically connected to the terminal SOUT.

[0158] 5A is a circuit diagram showing an example of the configuration of the selection circuit M. The selection circuit M includes a transistor Tr31, a transistor Tr32, a transistor Tr41, and a transistor Tr42.

[0159] In the selection circuit M having the configuration shown in FIG. 5A , the terminal SEL1 is electrically connected to the gate of the transistor Tr31 and the gate of the transistor Tr41. The terminal SEL2 is electrically connected to the gates of the transistors Tr32 and Tr42. The terminal O11 is electrically connected to one of the source or drain of the transistor Tr31. The terminal O12 is electrically connected to one of the source or drain of the transistor Tr32. The terminal FN1 is electrically connected to one of the source or drain of the transistor Tr41. The terminal FN2 is electrically connected to one of the source or drain of the transistor Tr42. The terminal O1 is electrically connected to the other of the source or drain of the transistor Tr31 and the other of the source or drain of the transistor Tr32. The terminal FN is electrically connected to the other of the source or drain of the transistor Tr41 and the other of the source or drain of the transistor Tr42.

[0160] 5B is a circuit diagram showing an example of the configuration of the signal supply circuit B. The signal supply circuit B includes a transistor Tr51, a transistor Tr52, a transistor Tr53, a transistor Tr54, a transistor Tr61, a transistor Tr62, a transistor Tr64, a capacitor C51, a capacitor C52, and a capacitor C61.

[0161] In the signal supply circuit B shown in FIG. 5B , the terminal SL_PWC is electrically connected to one of the source or drain of the transistor Tr54. The terminal RS_PWC is electrically connected to one of the source or drain of the transistor Tr52. The terminal RD_VDD is electrically connected to the gate of the transistor Tr61, the gate of the transistor Tr51, and the gate of the transistor Tr53. The terminal O1 is electrically connected to one of the source or drain of the transistor Tr51 and one of the source or drain of the transistor Tr53. The terminal FN is electrically connected to one of the source or drain of the transistor Tr61 and the gate of the transistor Tr64. The terminal RS_VSS is electrically connected to one electrode of the capacitor C61 and one of the source or drain of the transistor Tr62. The terminal RD_VSS is electrically connected to one of the source or drain of the transistor Tr64. The terminal RS is electrically connected to one electrode of the capacitor C51, the other of the source or drain of the transistor Tr52, and the other of the source or drain of the transistor Tr62. The terminal SL is electrically connected to one electrode of the capacitor C52, the other of the source or drain of the transistor Tr54, and the other of the source or drain of the transistor Tr64.

[0162] The other of the source or drain of transistor Tr51, the gate of transistor Tr52, and the other electrode of capacitor C51 are electrically connected to each other. The other of the source or drain of transistor Tr53, the gate of transistor Tr54, and the other electrode of capacitor C52 are electrically connected to each other. The other of the source or drain of transistor Tr61, the gate of transistor Tr62, and the other electrode of capacitor C61 are electrically connected to each other.

[0163] An example of a method for driving the row driver circuit 33 will be described below. Specifically, an example of a method for driving the shift register circuit included in the row driver circuit 33 in the period T5, which is the readout period, shown in FIG. 2B2 will be described. By using the driving method described below, the semiconductor device of one embodiment of the present invention can perform authentication such as fingerprint authentication, for example.

[0164] 6 and 7 are schematic diagrams illustrating an example of a method for driving the row driver circuit 33 during the readout period. In Fig. 6 and Fig. 7, the area of ​​the pixel section 30 that includes the pixels 31 from which image data is read out is indicated by hatching. Similar notations may be used in other figures.

[0165] In this specification, the driving method shown in Fig. 6 may be referred to as a first mode, and the driving method shown in Fig. 7 may be referred to as a second mode.

[0166] For example, when fingerprint authentication is performed, the row driver circuit 33 first scans specific pixels 31 of the pixel unit 30. At this time, the zth stage (z is an integer between 1 and m) of the shift register circuit included in the row driver circuit 33 operates the pixels 31 in the zth row. As a result, image data is read out from the specific pixels 31. FIG. 6 shows an example in which image data is read out from the hatched pixels 31 in every other row and every other column. The read-out image data is supplied to, for example, the detection circuit 37 shown in FIG. 2A. The detection circuit 37 detects the position of the finger 70 on the pixel unit 30 based on the image data.

[0167] Here, the pixel unit 30 is composed of pixels arranged in a matrix of m rows and n columns, as explained in <Configuration Example of Imaging Device>. Therefore, detecting the position of the finger 70 on the pixel unit 30 can be said to be detecting that the finger 70 is located on pixels in the pth to qth rows (p and q are integers between 1 and m) of the pixel unit 30, as shown in FIG.

[0168] 2A, for example, the control circuit 32 or the like determines the row of the pixel unit 30 from which image data is to be read for fingerprint detection based on the detected position of the finger 70. After the determination, for example, the control circuit 32 generates data indicating the row from which the row driver circuit 33 starts scanning when reading image data for fingerprint detection.

[0169] 7, the row driver circuit 33 scans a portion of the pixel unit 30 based on the above-mentioned determination result. This makes it possible to read out imaging data only from the pixels 31 in the row in contact with or close to the finger 70, for example. Alternatively, it is possible to read out imaging data only from the pixels 31 in the row in contact with or close to the finger 70 and the rows surrounding that row. In FIG. 7, the region of the pixel unit 30 that includes the pixels 31 from which imaging data is to be read out is designated as pixel unit 30R.

[0170] 7 is supplied to, for example, the detection circuit 37 shown in FIG. 2A. The detection circuit 37 authenticates a fingerprint 71 of a finger 70 based on the image data. In this way, the semiconductor device of one embodiment of the present invention can perform fingerprint authentication.

[0171] Here, during the period in which the driving method shown in FIG. 6 is applied, it is sufficient to detect the position of the finger 70, and it is not necessary to read out a fingerprint image. Therefore, as described above, the position of the finger 70 may be detected using only a limited number of pixels, arranged every several rows and every several columns, among the pixels 31 included in the pixel portion 30. This allows the readout period per pixel row in the pixel portion 30 to be shorter than when a fingerprint image is read out. Meanwhile, during the period in which the driving method shown in FIG. 7 is applied, the fingerprint image needs to be read out, so the readout period per pixel row in the pixel portion 30 is longer than when the driving method shown in FIG. 6 is applied. However, in the semiconductor device of one embodiment of the present invention, as shown in FIG. 7 , the pixels 31 from which image data is read out for fingerprint authentication can be limited to only pixels near the position where the finger is detected, i.e., only some of the pixels 31 provided in the pixel portion 30. Therefore, fingerprint authentication can be performed in a shorter time than when image data for fingerprint authentication is read out from all the pixels 31 included in the pixel portion 30.

[0172] Note that, in the above description, a case has been described in which the driving method shown in Fig. 7 is applied after the driving method shown in Fig. 6 has been applied, but this is not a limitation of one embodiment of the present invention. In one embodiment of the present invention, fingerprint authentication may be performed by limiting the area from which a fingerprint image is read out to a designated area in the pixel unit 30 in advance, without applying the driving method shown in Fig. 6, and applying only the driving method shown in Fig. 7 to that area.

[0173] An example of a driving method for the row driver circuit 33 that combines the first and second modes described above will be described below with reference to a flowchart and the like.

[0174] 8 is a flowchart illustrating an example of a driving method of one embodiment of the present invention for the row driver circuit 33. By using this driving method, the semiconductor device of one embodiment of the present invention can perform fingerprint authentication of a user in a short time.

[0175] First, in step S1, the position of the user's finger is detected. For example, in Fig. 6, the position of the user's finger 70 on the pixel unit 30 is detected. That is, step S1 is the driving method shown in Fig. 6, which is the first mode.

[0176] As described above, in step S1, it is not necessary to perform the process of detecting the position of the user's finger on all pixels 31 in the pixel unit 30. For example, the process may be performed on only limited pixels, that is, every several rows and every several columns, among the pixels 31 in the pixel unit 30. For example, if the pixel unit has 2560 rows and 1440 columns of pixels, the first imaging data may be read out on pixels of 2 rows and 36 columns, that is, every 50 rows. This allows the position of the user's finger to be detected in a shorter time than when all pixels 31 in the pixel unit 30 are targeted.

[0177] As explained in <Configuration Example of Imaging Device>, the pixel unit 30 is composed of pixels arranged in a matrix of m rows and n columns. Therefore, detecting the position of the finger 70 on the pixel unit 30 can be said to mean detecting that the finger 70 is located on pixels in the pth to qth rows (p and q are integers between 1 and m) of the pixel unit 30.

[0178] It is preferable that the pixels in the pth to qth rows of the pixel section 30 described above are included in the pixels in the 1st to m / 2th rows.

[0179] Here, the pixels in the first row of the pixel unit 30 refer to the pixels in the bottom row of the pixel unit 30 shown in FIG. 6 . For example, if the schematic diagram shown in FIG. 6 is a smartphone having the pixel unit 30, the speaker 38 or camera 39 may be provided outside the pixel unit 30, as shown in FIG. 6 . In this case, the pixels in the row farthest from the speaker 38 or camera 39 are the pixels in the first row (bottom row), and the pixels in the row closest to the speaker 38 or camera 39 are the pixels in the mth row (top row). The pixels in the first row of the pixel unit 30 can also be referred to as the pixels in the row to which the first stage of the shift register circuit is connected. The pixels in the mth row of the pixel unit 30 can also be referred to as the pixels in the row to which the final stage, from which the shift register circuit emits a selection signal, is connected. The schematic diagram shown in FIG. 6 is not limited to smartphones.

[0180] Next, in step S2, a process of reading out a fingerprint image row by row is performed from the pixels in the first row of the pixel portion 30 described above to the region where the finger was detected in step S1 (the pixels in the qth row of the pixel portion 30). As described in FIG. 1 , the semiconductor device 10 of one embodiment of the present invention includes a light-emitting device and an imaging device, and light emitted from the light-emitting device is reflected by a finger or the like and the light is detected by the imaging device. Therefore, in step S2, it can be said that a pixel that detects light reflected by the finger, among the light emitted from the light-emitting device, captures an image of the fingerprint on the finger and reads out the image data.

[0181] Step S2 is the driving method shown in FIG. 7, which is the second mode.

[0182] In other words, in FIG. 7, the process of detecting fingerprint 71 is performed by shifting up one row at a time, from the bottom row (first row) of pixel section 30 to the top row (qth row) of pixel section 30R where user's finger 70 is detected.

[0183] For example, when step S1 is performed on limited pixels, every x rows and every y columns (x and y are integers greater than or equal to 1 and less than or equal to q-p), among the pixels 31 included in the pixel unit 30, step S2 may be performed on pixels in the 1st to q+xth rows of the pixel unit 30. By performing step S2 on pixels in an extra number of rows (x rows) beyond the pixels in the top row (q row) where the position of the finger is detected, it is possible to reliably capture an image of the user's fingerprint.

[0184] Here, shifting up row by row from the first row of pixels in the pixel unit 30 refers to selecting, by the shift register circuit, one row at a time from the pixels in the first row described above toward, for example, the pixels in the qth row. That is, in the case of the smartphone described above as an example, this refers to selecting, by the shift register circuit, one row at a time from the pixels in the row (first row) farthest from the speaker 38 or camera 39 toward the pixels in the row (qth row) closest to the speaker 38 or camera 39 among the rows in which the finger 70 is detected.

[0185] In step S2, when the reading of the fingerprint images from the pixels in all the target rows (the first to qth rows of the pixel section 30) is completed, the operation of the shift register circuit is stopped (step S3).

[0186] As described above, in the driving method according to one embodiment of the present invention, the position of a user's finger is detected in the first mode (step S1), and in the second mode (step S2), a fingerprint image is read out only from a partial region of the pixel unit 30. The fingerprint image is not read out from regions other than the partial region of the pixel unit 30. That is, in the driving method according to one embodiment of the present invention, an image captured only in the region where a finger is detected on the pixel unit 30 is extracted and fingerprint authentication is performed.

[0187] FIG. 9 is a schematic diagram showing an example of the driving method of the row driver circuit 33 described using the flowchart of FIG.

[0188] 9, the pixel section 30R is located at the lower side within the pixel section 30. The pixel section 30R is an area including the pixels of the first to qth rows of the pixel section 30.

[0189] 9, the pixel section 30U is an area above the pixel section 30R in the pixel section 30. That is, it is an area including the pixels in the q+1th to mth rows of the pixel section 30.

[0190] As described above, when the reading of the fingerprint image in the pixel unit 30R (the area including the pixels in the first to qth rows of the pixel unit 30) is completed in step S2, the operation of the shift register circuit is stopped in step S3. Therefore, no processing related to imaging is performed in the pixel unit 30U.

[0191] That is, in the driving method of one embodiment of the present invention, the first mode is performed on the pixel portion 30, and then the second mode is performed on only the pixel portion 30R. By limiting the area where the fingerprint image is read out to a part of the pixel portion 30 in this way, the frame frequency for reading out the fingerprint image by the row driver circuit 33 can be made faster than when the fingerprint image is read out from the entire pixel portion 30. This enables fingerprint authentication to be performed in a short time.

[0192] For example, consider a case where the schematic diagram shown in FIG. 9 is a smartphone having a pixel portion 30. For example, when a user tries to operate a smartphone with one hand, the user often holds the vicinity of the lower side of the smartphone and touches a lower region of the pixel portion 30 (a region of the pixel portion 30 that includes pixels in the first to m / 2th rows). Therefore, it is preferable that the position of the finger 70 be detected in the lower region of the pixel portion 30. In this case, fingerprint authentication only needs to be performed on the lower region where the finger 70 touches, and the driving method of one embodiment of the present invention is preferable. Note that the schematic diagram shown in FIG. 9 is not limited to a smartphone.

[0193] A detailed example of the driving method shown in Figures 6 and 7 will be described with reference to Figures 10 to 13. Figures 10 and 11 are timing charts showing a detailed example of the driving method shown in Figure 6, in which an example of the driving method of the row driver circuit 33 is divided into periods T10 to T39.

[0194] In the periods T12 to T39 (FIG. 11), the potential of the terminal SEL2 is high, and the potential of the terminal SEL1 is low. In the periods T12 to T39 (FIG. 11), the potential of the terminal SP1 is low. In the periods T12 to T39 (FIG. 10), the potentials of the terminals CLK1[1] to CLK1[4] are low.

[0195] During period T12 (FIG. 11), a high-potential signal is input to terminal SP2 as a start pulse signal, causing the register circuit S[1] to output a high-potential signal to terminal SO1[1]. Also, a low-potential signal is output from register circuit S[1] to terminal SFN[1]. At this time, the potential of terminal SEL2, which is an input terminal of selection circuits M[5] and M[6], is high, and the potential of terminal SEL1, another input terminal of selection circuits M[5] and M[6], is low. Therefore, the signal from terminal SO1[1] is output to terminals O1[5] and O1[6] by selection circuits M[5] and M[6]. Therefore, the potentials of terminals O1[5] and O1[6] are high. Also, the signal from terminal SFN[1] is output to terminals FN[5] and FN[6]. Therefore, the potentials of the terminals FN[5] and FN[6] are low. Note that in the period T12 (FIG. 10), the potentials of the terminals CLK2[1] to CLK2[4] are all low.

[0196] Next, in the periods T13 and T14 (FIG. 10), the potentials of the terminals SL_PWC1 and SL_PWC2 are high. Following the period T12, the potentials of the terminals O1[5] and O1[6] are high and the potentials of the terminals FN[5] and FN[6] are low. Therefore, the potentials of the terminals SL[5] and SL[6] are high due to the outputs from the signal supply circuits B[5] and B[6]. That is, selection signals are output to the terminals SL[5] and SL[6]. Subsequently, in the period T15 (FIG. 10), the potentials of the terminals SL_PWC1 and SL_PWC2 are low. Therefore, the potentials of the terminals SL[5] and SL[6] are low due to the outputs from the signal supply circuits B[5] and B[6]. Note that in the periods T13 and T14 (FIG. 10), the potentials of the terminals SL_PWC3 and SL_PWC4 are both low.

[0197] Furthermore, during period T14 (FIG. 10), the potentials of terminals RS_PWC1 and RS_PWC2 become high. Following on from period T12, the potentials of terminals O1[5] and O1[6] remain high, and the potentials of terminals FN[5] and FN[6] remain low. Therefore, the output from signal supply circuit B[5] and signal supply circuit B[6] causes the potentials of terminals RS[5] and RS[6] to become high. That is, a reset signal is output to terminals RS[5] and RS[6]. Subsequently, during period T15 (FIG. 10), the potentials of terminals RS_PWC1 and RS_PWC2 become low. Therefore, the output from signal supply circuit B[5] and signal supply circuit B[6] causes the potentials of terminals RS[5] and RS[6] to become low. Note that during a period T14 (FIG. 10), the potentials of the terminals RS_PWC3 and RS_PWC4 are both low.

[0198] Furthermore, in the periods T13 to T14 (FIG. 10), the potential of the terminal CLK2[1] is high. Therefore, in the periods T13 to T14, the potential of the terminal SOUT[1] output from the register circuit S[1] is high. As described above, the signal output from the register circuit S[1] is input to the register circuit S[2] (not shown in FIG. 3) via the terminal SOUT[1], and therefore a high-potential signal is output from the register circuit S[2] to the terminal SO1[2]. In addition, a low-potential signal is output from the register circuit S[2] to the terminal SFN[2]. Here, in the periods T13 to T14 (FIG. 11), the potential of the terminal SEL1 is low, and the potential of the terminal SEL2 is high. As described above, the terminals SEL1 and SEL2 are electrically connected to the selection circuits M[1] to M[m], respectively. Therefore, although not shown in FIG. 3, the selection circuit M

[55] and the selection circuit M

[56] electrically connected to the terminals SEL1 and SEL2 output the signal output from the register circuit S[2] to the terminal SO1[2] to the terminal O1

[55] and the terminal O1

[56] . Therefore, the potentials of the terminals O1

[55] and O1

[56] become high. Furthermore, the signal output from the register circuit S[2] to the terminal SFN[2] is output to the terminals FN

[55] and FN

[56] . Therefore, the potentials of the terminals FN

[55] and FN

[56] become low. Note that during the periods T13 to T14 (FIG. 10), the potentials of the terminals CLK2[2] to CLK2[4] remain low, as they were during the period T12.

[0199] Next, in the periods T15 and T16 (FIG. 10), the potentials of the terminals SL_PWC3 and SL_PWC4 are set to high potential. Following the period T14, the potentials of the terminals O

[55] and O

[56] are set to high potential, and the potentials of the terminals FN

[55] and FN

[56] are set to low potential. Therefore, although not shown in FIG. 3, the potentials of the terminals SL

[55] and SL

[56] are set to high potential by the outputs from the signal supply circuits M

[55] and M

[56] . That is, selection signals are output to the terminals SL

[55] and SL

[56] . Subsequently, in the period T17, the potentials of the terminals SL_PWC3 and SL_PWC4 are set to low potential. Therefore, the potentials of the terminals SL

[55] and SL

[56] are set to low potential by the outputs from the signal supply circuit B

[55] and the signal supply circuit B

[56] . Note that in the periods T15 and T16 (FIG. 10), the potentials of the terminals SL_PWC1 and SL_PWC2 are both set to low potential.

[0200] Also, in period T16 (FIG. 10), the potentials of the terminals RS_PWC3 and RS_PWC4 become high. Following period T14, the potentials of the terminals O

[55] and O

[56] described above are high, and the potentials of the terminals FN

[55] and FN

[56] described above are low. Therefore, although not shown in FIG. 3, the potentials of the terminals RS

[55] and RS

[56] become high due to the outputs from the signal supply circuits B

[55] and B

[56] . That is, a reset signal is output to the terminals RS

[55] and RS

[56] . Subsequently, in period T17, the potentials of the terminals RS_PWC3 and RS_PWC4 become low. Therefore, the potentials of the terminals RS

[55] and RS

[56] become low due to the outputs from the signal supply circuits B

[55] and B

[56] . Note that during the period T16 (FIG. 10), the potentials of the terminal RS_PWC1 and the terminal RS_PWC2 are both low.

[0201] In addition, in the periods T15 and T16 (FIG. 10), the potential of the terminal CLK2[2] is high. Therefore, in the periods T15 and T16, the potential of the terminal SOUT[1] output from the register circuit S[1] is high. In addition, due to the output from the register circuit S[1], the potential of the terminal SO1[1] is low and the potential of the terminal SFN[1] is high.

[0202] As described above, the potential of the terminal CLK2[2] is high during the periods T15 and T16 (FIG. 10). As described above, the signal output from the register circuit S[1] is input to the register circuit S[2] (not shown in FIG. 3) via the terminal SOUT[1]. The signal output from the register circuit S[2] is input to the terminal SOUT[2] (not shown in FIG. 3). Therefore, during the periods T15 and T16, the potential of the terminal SOUT[2] is also high. Similarly, the signal output from the register circuit S[2] is input to the register circuit S[3] (not shown in FIG. 3) via the terminal SOUT[2]. The signal output from the register circuit S[3] is input to the terminal SOUT[3] (not shown in FIG. 3). Therefore, a high-potential signal is output from the register circuit S[3] to the terminal SO1[3]. Furthermore, a low-potential signal is output from the register circuit S[3] to the terminal SFN[3]. Here, during the periods T15 to T16 (FIG. 11), the potential of the terminal SEL1 is low, and the potential of the terminal SEL2 is high. As described above, the selection circuits M[1] to M[m] are electrically connected to the terminals SEL1 and SEL2, respectively. Therefore, although not shown in FIG. 3, the selection circuits M

[105] and M

[106] , which are electrically connected to the terminals SEL1 and SEL2, output the signal output from the register circuit S[3] to the terminal SO1[3] to the terminal O1

[105] and the terminal O1

[106] . Furthermore, the signal output from the register circuit S[3] to the terminal SFN[3] is output to the terminal FN

[105] and the terminal FN

[106] . Note that in the periods T15 and T16 (FIG. 10), the potentials of the terminals CLK2[1], CLK2[3], and CLK2[4] are low.

[0203] 10 and 11, by repeating the above-described operations, scanning signals can be sequentially supplied to the pixels 31. That is, when a start pulse signal is input to the terminal SP2 in the period T12 (FIG. 11), the start pulse signal is supplied to the register circuit S[1]. Subsequently, the start pulse signal is sequentially supplied to the selection circuits M[5] and M[6], and the signal supply circuits B[5] and B[6], and a selection signal is sequentially output to the terminals SL[5] and SL[6], and a reset signal is sequentially output to the terminals RS[5] and RS[6] in response to the scanning signal.

[0204] 3, the start pulse signal input to the register circuit S[1] is output to the terminal SOUT[1] and input to the register circuit S[2] electrically connected to the terminal SOUT[1]. The input signal is then sequentially supplied to the selection circuit M

[55] and the selection circuit M

[56] , and the signal supply circuit B

[55] and the signal supply circuit B

[56] . In response to the scanning signal, a selection signal is sequentially output to the terminal SL

[55] and the terminal SL

[56] , and a reset signal is sequentially output to the terminal RS

[55] and the terminal RS

[56] . The signal input to the register circuit S[2] is also output to the terminal SOUT[2] and input to the register circuit S[3] electrically connected to the terminal SOUT[2]. The input signal is then sequentially supplied to the selection circuit M

[105] and the selection circuit M

[106] , and the signal supply circuit B

[105] and the signal supply circuit B

[106] , and in response to the scanning signal, the selection signal is sequentially output to the terminal SL

[105] and the terminal SL

[106] , and the reset signal is sequentially output to the terminal RS

[105] and the terminal RS

[106] . Furthermore, the signal input to the register circuit S[3] is output to the terminal SOUT[3] and input to the register circuit S[4] electrically connected to the terminal SOUT[3]. The input signal is then sequentially supplied to the selection circuit M

[155] and the selection circuit M

[156] , and the signal supply circuit B

[155] and the signal supply circuit B

[156] , and in response to the scanning signal, the selection signal is sequentially output to the terminal SL

[155] and the terminal SL

[156] , and the reset signal is sequentially output to the terminal RS

[155] and the terminal RS

[156] . That is, the signal input to the register circuit S[t] is output to the terminal SOUT[t+1] and input to the register circuit S[t+1] electrically connected to the terminal SOUT[t]. The input signal is then sequentially supplied to the selection circuits M[5+50t] and M[6+50t], and the signal supply circuits B[5+50t] and B[6+50t], and in response to the scanning signal, a selection signal is sequentially output to the terminals SL[5+50t] and SL[6+50t], and a reset signal is sequentially output to the terminals RS[5+50t] and RS[6+50t]. This allows image data to be sequentially read out from the pixels 31 in every 50 rows, from the 5th and 6th rows to the 5+50t and 6+50t rows in the pixel section 30.In the driving method shown in FIG. 6, no start pulse signal is input to the terminal SP1.

[0205] 12 and 13 are timing charts showing a detailed example of the driving method shown in FIG. 7 (FIG. 9), and show an example of the driving method of the row driver circuit 33 divided into periods T40 to T68.

[0206] In the periods T42 to T68 (FIG. 13), the potential of the terminal SEL1 is high, and the potential of the terminal SEL2 is low. In the periods T42 to T68 (FIG. 13), the potential of the terminal SP2 is low. In the periods T42 to T68 (FIG. 12), the potentials of the terminals CLK2[1] to CLK2[4] are low.

[0207] During the period T42 (FIG. 13), a high-potential signal is input to the terminal SP1 as a start pulse signal, causing the register circuit F[1] to output a high-potential signal to the terminal FO1[1]. Also, a low-potential signal is output from the register circuit F[1] to the terminal FFN[1]. At this time, the potential of the terminal SEL1, which is an input terminal of the selection circuit M[1], is high, and the potential of the terminal SEL2, which is another input terminal of the selection circuit M[1], is low. Therefore, the signal from the terminal FO1[1] is output to the terminal O1[1] by the selection circuit M[1]. Therefore, the potential of the terminal O1[1] becomes high. Also, the signal from the terminal FFN[1] is output to the terminal FN[1]. Therefore, the potential of the terminal FN[1] becomes low. Note that during the period T42 (FIG. 12), the potentials of the terminals CLK1[1] to CLK1[4] are all low.

[0208] Next, in a period T43 (FIG. 12), the potential of the terminal CLK1[1] becomes high. Therefore, in the period T43, the potential of the terminal FOUT[1] output from the register circuit F[1] becomes high. Note that the potentials of the terminals CLK1[2] to CLK1[4] remain low as in the period T42.

[0209] Furthermore, in the periods T43 and T44 (FIG. 12), the potential of the terminal SL_PWC1 is high. Since the potential of the terminal O1[1] is high and the potential of the terminal FN[1] is low, as in the period T42, the potential of the terminal SL[1] is high due to the output from the signal supply circuit B[1]. That is, a selection signal is output to the terminal SL[1]. Subsequently, in the period T45 (FIG. 12), the potential of the terminal SL_PWC1 is low, and therefore the potential of the terminal SL[1] is low due to the output from the signal supply circuit B[1]. Note that in the periods T43 and T44 (FIG. 12), the potentials of the terminals SL_PWC2 to SL_PWC4 are all low.

[0210] Furthermore, in the period T44 (FIG. 12), the potential of the terminal RS_PWC1 becomes high. Since the potential of the terminal O1[1] is high and the potential of the terminal FN[1] is low, continuing from the period T42 described above, the potential of the terminal RS[1] becomes high due to the output from the signal supply circuit B[1]. That is, a reset signal is output to the terminal RS[1]. Subsequently, in the period T45 (FIG. 12), the potential of the terminal RS_PWC1 becomes low. Therefore, the potential of the terminal RS[1] becomes low due to the output from the signal supply circuit B[1]. Note that in the period T44 (FIG. 12), the potentials of the terminals RS_PWC2 to RS_PWC4 are all low.

[0211] Also, during period T45 (FIG. 12), the potentials of terminals CLK1[1] and CLK1[2] are high. Therefore, during period T45, the potential of terminal FOUT[1] output from register circuit F[1] is high. As described above, the signal output from register circuit F[1] is input to register circuit F[2] via terminal FOUT[1], so a high-potential signal is output from register circuit F[2] to terminal FO1[2]. Furthermore, a low-potential signal is output from register circuit F[2] to terminal FFN[2]. Here, during period T45 (FIG. 13), the potential of terminal SEL1 is high, and the potential of terminal SEL2 is low. Therefore, the selection circuit M[2], which is electrically connected to terminals SEL1 and SEL2, outputs the signal output from register circuit F[2] to terminal FO1[2] to terminal O1[2]. Therefore, the potential of the terminal O1[2] becomes high. Also, the signal output from the register circuit F[2] to the terminal FFN[2] is output to the terminal FN[2]. Therefore, the potential of the terminal FN[2] becomes low.

[0212] Furthermore, in the periods T45 to T46 (FIG. 12), the potential of the terminal SL_PWC2 is high. Since the potential of the terminal O1[2] is high and the potential of the terminal FN[2] is low following the period T43, the potential of the terminal SL[2] is high due to the output from the signal supply circuit B[2]. That is, a selection signal is output to the terminal SL[2]. Subsequently, in the period T47 (FIG. 12), the potential of the terminal SL_PWC2 is low, and the potential of the terminal SL[2] is low due to the output from the signal supply circuit B[2]. Note that in the periods T45 to T46 (FIG. 12), the potentials of the terminals SL_PWC1, SL_PWC3, and SL_PWC4 are all low.

[0213] Furthermore, in period T46 (FIG. 12), the potential of terminal RS_PWC2 becomes high. Here, continuing from the aforementioned period T43, the potential of terminal O1[2] is high and the potential of terminal FN[2] is low, so that the output from signal supply circuit B[2] causes the potential of terminal RS[2] to become high. That is, a reset signal is output to terminal RS[2]. Subsequently, in period T47 (FIG. 12), the potential of terminal RS_PWC2 becomes low. Therefore, the output from signal supply circuit B[2] causes the potential of terminal RS[2] to become low. Note that in period T46 (FIG. 12), the potentials of terminals RS_PWC1, RS_PWC3, and RS_PWC4 are all low.

[0214] As described above, during period T45, the potential of terminal FOUT[1] output from register circuit F[1] is high. As described above, the signal output from register circuit F[1] is input to register circuit F[2] via terminal FOUT[1]. The signal output from register circuit F[2] is input to terminal FOUT[2]. Therefore, during period T45, the potential of terminal FOUT[2] is also high. Similarly, the signal output from register circuit F[2] is input to register circuit F[3] via terminal FOUT[2]. Therefore, a high-potential signal is output from register circuit F[3] to terminal FO1[3]. Furthermore, a low-potential signal is output from register circuit F[3] to terminal FFN[3]. Here, during period T45 ( FIG. 13 ), the potential of terminal SEL1 is high, and the potential of terminal SEL2 is low. Therefore, the selection circuit M[3], which is electrically connected to the terminals SEL1 and SEL2, outputs the signal output from the register circuit F[3] to the terminal FO1[3] to the terminal O1[3]. As a result, the potential of the terminal O1[3] becomes high. Also, the selection circuit M[3] outputs the signal output from the register circuit F[3] to the terminal FFN[3] to the terminal FN[3]. As a result, the potential of the terminal FN[3] becomes low.

[0215] Next, from period T47 to period T50 (FIG. 12), the potential of the terminal CLK1[3] becomes high. Therefore, from period T47 to period T50, the potential of the terminal FOUT[3] output from the register circuit F[3] becomes high. Here, as described above, the signal output from the register circuit F[3] is input to the register circuit F[1] in the stage before the previous stage via the terminal FOUT[3]. Therefore, from period T47 to period T50, a high-potential signal is input to the register circuit F[1]. Therefore, the output from the register circuit F[1] causes the potential of the terminal FO1[1] to become low. Furthermore, the output from the register circuit F[1] causes the potential of the terminal FFN[1] to become high.

[0216] 12 and 13, by repeating the above-described operations, scanning signals can be sequentially supplied to the pixels 31. That is, when a start pulse signal is input to the terminal SP1 in the period T42 (FIG. 13), the start pulse signal is supplied to the register circuit F[1]. At the same time, scanning signals are supplied to the selection circuit M[1] and the signal supply circuit B[1]. After that, scanning signals are sequentially supplied to the register circuits F[2] to F[m], the selection circuits M[2] to M[m], and the signal supply circuits B[2] to B[m]. Then, in response to the scanning signals, selection signals are sequentially output to the terminals SL[1] to SL[m], and reset signals are sequentially output to the terminals RS[1] to RS[m]. This allows image data to be sequentially read from the pixels 31 in the first to m-th rows in the pixel portion 30. Note that in the driving method shown in FIG. 7, a start pulse signal is not input to the terminal SP2.

[0217] Below, we will explain another example of the details of the driving method shown in Figure 7, specifically, an example of a driving method that stops the operation of the shift register circuit (resets the data held by the pixels 31) shown in step S3 of the flowchart in Figure 8.

[0218] In the periods T40 to T68 (FIG. 13), the potential of the terminal SEL2 is low, and the potential of the terminal SEL1 is high. In the periods T40 to T68 (FIG. 13), the terminal RES2 is high. In the periods T40 to T68 (FIG. 13), the terminal SP2 is low. In the periods T40 to T68 (FIG. 12), the terminals CLK2[1] to CLK2[4] are low.

[0219] During the period T40 (FIG. 13), a high-potential signal is input to the terminal RES1, causing the register circuits F[1] to F[m] to output low-potential signals to the terminals FO1[1] to FO1[m]. The terminal SEL1, which is an input terminal of the selection circuits M[1] to M[m], is at high potential, and the terminal SEL2, which is another input terminal of the selection circuits M[1] to M[m], is at low potential. Therefore, the selection circuits M[1] to M[m] output the signals from the terminals FO1[1] to FO1[m] to the terminals O1[1] to O1[m]. Therefore, the terminals O1[1] to O1[m] are at high potential. Furthermore, the signals from the terminals FFN[1] to FFN[m] are output to the terminals FN[1] to FN[m]. Therefore, the terminals FN[1] to FN[m] are at low potential.

[0220] In the next period T41 ( FIG. 13 ), continuing from the period T40 described above, the terminals O1[1] to O1[m] are at high potential, and the terminals FN[1] to FN[m] are at low potential. Therefore, by inputting a high-potential signal to the terminal RS_VSS, the signal supply circuits B[1] to B[m] output high potentials to the terminals RS[1] to RS[m]. Therefore, data held by the pixels in the first to m-th rows in the pixel portion 30 (i.e., all the pixels 31) can be reset.

[0221] 10 to 13 during the read period, the semiconductor device of one embodiment of the present invention can perform authentication such as fingerprint authentication. Note that in this specification and the like, the driving method shown in FIGS. 10 and 11 may be referred to as a first mode. The driving method shown in FIGS. 12 and 13 may be referred to as a second mode.

[0222] 14 is a flowchart illustrating an example of a driving method of the row driver circuit 33 according to one embodiment of the present invention, which is different from the flowchart illustrated in FIG. 8. By using this driving method, the semiconductor device according to one embodiment of the present invention can perform fingerprint authentication of a user in a short time.

[0223] First, in step T1, a process of reading out a fingerprint image is performed row by row from the pixels in the first row to the pixels in the rth row in a designated region of the pixel portion 30, for example, in a region including pixels in the first to rth rows (r is an integer greater than or equal to 1 and less than or equal to m) of the pixel portion 30. As described with reference to FIG. 1 , the semiconductor device 10 of one embodiment of the present invention includes a light-emitting device and an imaging device. Light emitted from the light-emitting device is reflected by a finger or the like, and the reflected light is detected by the imaging device. Therefore, in step T1, the pixels that detect the light reflected by the finger among the light emitted from the light-emitting device capture an image of the fingerprint on the finger and read the image data. As described above, the pixels in the first row of the pixel portion 30 refer to the bottom row of the pixel portion 30 shown in FIG. 6 . Also, the pixels in the first row of the pixel portion 30R refer to the bottom row of the pixel portion 30R shown in FIG. 9 . For example, if the schematic diagrams shown in FIGS. 6 , 7 , and 9 are of a smartphone including the pixel portion 30, a speaker 38 or a camera 39 may be provided outside the pixel portion 30 as shown. In this case, the pixel in the row farthest from the speaker 38 or camera 39 becomes the pixel in the first row (bottom row), and the pixel in the row closest to the speaker 38 or camera 39 becomes the pixel in the mth row (top row).

[0224] Here, the number of rows r of the pixel unit 30 can be set arbitrarily within the range of 1 to m. For example, if the schematic diagrams shown in Figures 6, 7, and 9 are of an electronic device such as a smartphone, the manufacturer or user of the electronic device can set the value of r arbitrarily in advance. It is preferable that the pixel in the rth row of the pixel unit 30 is included in the pixels in the 1st to m / 2th rows.

[0225] Therefore, it can be said that the pixels in the rth row and below (1st to rth rows) of the pixel section 30 correspond to the pixels in the rows from which the fingerprint image is read out.

[0226] That is, in the driving method of one aspect of the present invention, in step T1, a process of detecting fingerprint 71 is performed by shifting up one row at a time, from the bottom row (first row) of pixel section 30 to the rth row of pixels.

[0227] Here, shifting up by one row from the pixels in the first row of the pixel unit 30 refers to shifting by one row from the pixels in the first row described above toward the pixels in the rth row. That is, in the case of the smartphone described above as an example, this refers to shifting by one row from the pixels in the row (first row) farthest from the speaker 38 or camera 39 toward the pixels in the rth row that are closer to the speaker 38 or camera 39 than the pixels in the first row.

[0228] Here, step T1 in Fig. 14 is a driving method that corresponds to step S2 in Fig. 8, that is, the second mode. Therefore, step T1 in Fig. 14 can be said to be the second mode.

[0229] In step T2, when the reading of the fingerprint images from the pixels in all the target rows (the first to rth rows of the pixel section 30) is completed, the operation of the shift register circuit is stopped (step T2).

[0230] Incidentally, the flowchart shown in Fig. 14 does not include processing corresponding to the first mode in the flowchart shown in Fig. 8. That is, the driving method according to one aspect of the present invention shown in the flowchart in Fig. 14 does not perform processing for detecting the position of the user's finger.

[0231] As described above, in the driving method of one embodiment of the present invention, the number of pixel rows (the first to r-th rows) from which a fingerprint image is read in the pixel portion 30 can be set arbitrarily. Therefore, by setting the value of r in advance to a number greater than the number of pixel rows expected to be touched by a user's finger, it is possible to reliably read out a fingerprint image even without the first mode. Note that an image or a comment specifying that the area is an area where the user's finger will touch or approach may be displayed in an area including pixels in the first to r-th rows of the pixel portion 30.

[0232] As described above, in the driving method of one embodiment of the present invention, the first mode is not performed, and a fingerprint image is read out only in the second mode (step T2) from a partial region of the pixel unit 30. A fingerprint image is not read out from regions other than the partial region of the pixel unit 30. That is, in the driving method of one embodiment of the present invention, fingerprint authentication is performed only in a region of the pixel unit 30 where a finger is expected to be detected.

[0233] FIG. 15 is a schematic diagram showing an example of the driving method of the row driver circuit 33 described using the flowchart of FIG.

[0234] In FIG. 15, the pixel section 30R is an area in the pixel section 30 where a fingerprint image is read out, and is an area including pixels in the first to r-th rows of the pixel section 30.

[0235] 15, the pixel section 30U is an area above the pixel section 30R in the pixel section 30. That is, it is an area including the pixels in the r+1th to mth rows of the pixel section 30.

[0236] As described above, when the reading of the fingerprint image in the pixel unit 30R (the area including the pixels in the first to rth rows of the pixel unit 30) is completed in step T1, the operation of the shift register circuit is stopped in step T2. Therefore, no processing related to imaging is performed in the pixel unit 30U.

[0237] 9, the upper end of pixel unit 30R (the boundary between pixel unit 30R and pixel unit 30U) and the position of the tip of the user's finger 70 are approximately aligned. That is, in the schematic diagram shown in FIG. 9, the upper end of pixel unit 30R and the tip of finger 70 are positioned at the pixel in the qth row of pixel unit 30.

[0238] 15, the upper end of pixel unit 30R is located above the tip of the user's finger 70. In other words, in the schematic diagram shown in Fig. 15, the pixels in the row (r-th row) of pixel unit 30 from which the fingerprint image is last read out in the above-mentioned step T1 are located above the pixels in the row (q-th row) of pixel unit 30 on which the tip of finger 70 is placed.

[0239] Therefore, in the driving methods shown in FIGS. 14 and 15, the number of pixel rows in the pixel section 30 from which a fingerprint image is read may be greater than in the driving methods shown in FIGS.

[0240] However, the driving methods shown in Figures 14 and 15 do not require the first mode. That is, they do not require time to detect the position of the user's finger. Therefore, the overall processing time may be shorter than the driving methods shown in Figures 8 and 9 that perform the first mode.

[0241] As described above, in the driving method of one embodiment of the present invention, the first mode is not performed, and the second mode is performed only on the pixel portion 30R. By not performing the first mode in this way, the overall processing time can be shortened. Furthermore, by limiting the area from which the fingerprint image is read to only a part of the pixel portion 30, the frame frequency required for reading the fingerprint image by the row driver circuit 33 can be increased compared to when the fingerprint image is read from the entire pixel portion 30. This allows fingerprint authentication to be performed in a short time.

[0242] For example, consider a case where the schematic diagram shown in FIG. 15 is a smartphone having a pixel portion 30. For example, when a user tries to operate a smartphone with one hand, the user often holds the vicinity of the lower side of the smartphone and touches a lower region of the pixel portion 30 (a region of the pixel portion 30 including pixels in the first to m / 2th rows). Therefore, in this case, fingerprint authentication only needs to be performed on the lower region touched by the finger 70, and the driving method of one embodiment of the present invention is preferable. Note that the schematic diagram shown in FIG. 15 is not limited to a smartphone.

[0243] Below, we will explain, using a flowchart, another example of a driving method for the row driver circuit 33 that combines the first mode and the second mode, which is different from the contents described in Figures 8, 9, 14, and 15.

[0244] 16 is a flowchart illustrating another example of a driving method of one embodiment of the present invention for the row driver circuit 33. By using this driving method, the semiconductor device of one embodiment of the present invention can perform fingerprint authentication of a user in a short time.

[0245] First, in step X1, a process is performed to skip fingerprint imaging in one region of the pixel unit 30 where a finger is not detected. For example, in FIG. 7 , the region from which a fingerprint image is read is the region including pixels in rows p to q of the pixel unit 30 where the finger position was detected in FIG. 6 . However, in one aspect of the present invention, a region including pixels in rows p to q of the pixel unit 30 is designated in advance as a region where a finger is to be in contact with or approach the pixel unit 30. Therefore, in step X1, a process is performed to skip fingerprint imaging from the pixels in the first row (m row) to the pixels in the p-1th row (q+1th row) of the pixel unit 30 in FIG. 7 . Note that in FIG. 7 , the region including pixels in rows 1 to p-1 of the pixel unit 30 is designated as one region, and the region including pixels in rows q+1 to m of the pixel unit 30 is designated as the other region. However, the reverse may be true. That is, the region including pixels in rows m to q+1 of the pixel unit 30 may be designated as one region, and the region including pixels in rows p-1 to 1 of the pixel unit 30 may be designated as the other region.

[0246] Furthermore, the pixels in the first row of the pixel unit 30 refer to the pixels in the topmost or bottommost row of the pixel unit 30 shown in FIG. 6 . For example, if the schematic diagram shown in FIG. 6 is a smartphone having the pixel unit 30, the speaker 38 or camera 39 may be provided outside the pixel unit 30 as shown. In this case, the pixels in the row closest (farthest) from the speaker 38 or camera 39 are the pixels in the first row, and the pixels in the row farthest (closest) from the speaker 38 or camera 39 are the pixels in the mth row. Furthermore, the pixels in the first row of the pixel unit 30 can also be referred to as the pixels in the row to which the first stage of the shift register circuit is connected. Furthermore, the pixels in the mth row of the pixel unit 30 can also be referred to as the pixels in the row to which the final stage, from which the shift register circuit emits a selection signal, is connected. Note that the schematic diagram shown in FIG. 6 is not limited to smartphones.

[0247] Next, in step X2, a process of reading out the fingerprint image row by row from the pixel in the pth row (qth row) to the pixel in the qth row (pth row) of the pixel portion 30, which is the designated region, is performed. As described with reference to FIG. 1 , the semiconductor device 10 of one embodiment of the present invention includes a light-emitting device and an imaging device, and light emitted from the light-emitting device is reflected by a finger or the like, and the light is detected by the imaging device. Therefore, in step X2, it can be said that the pixel that detects the light reflected by the finger, out of the light emitted from the light-emitting device, captures an image of the fingerprint on the finger and reads out the image data.

[0248] Step X2 is the driving method shown in FIG. 7, which is the second mode.

[0249] Next, in step X3, a process is performed to skip fingerprint imaging operations in the other area of ​​the pixel unit 30 where a finger is not detected, i.e., from the pixels in the q+1th row (p-1th row) of the pixel unit 30 to the pixels in the mth row (1st row).

[0250] As described above, in the driving method according to one aspect of the present invention, the first mode is not performed, and the fingerprint image is read out in the pre-specified area in the second mode (step X2).For the non-specified area, the fingerprint image is not read out, and only the process of shifting the rows of the pixels included in the area is performed (steps X1 and X3).

[0251] FIG. 17 is a schematic diagram showing an example of the driving method of the row driver circuit 33 described using the flowchart of FIG.

[0252] 17, the pixel section 30 includes a pixel section 30B, a pixel section 30R, and a pixel section 30U. Also, in FIG. 17, the pixel section 30R includes a pixel section 30F.

[0253] Pixel unit 30F is the designated area where the user's fingerprint image is read in step X2, and is an area including pixels in rows b to u (b is an integer between 1 and p, and u is an integer between q and m) of pixel unit 30. Pixel unit 30F is provided within pixel unit 30R.

[0254] In this specification, the pixel unit 30 may be referred to as a first pixel unit, and a specified region of the pixel unit 30 (first pixel unit) (a region including pixels in rows b to u) may be referred to as a second pixel unit.

[0255] 17 is a smartphone. For example, when a user attempts to operate the smartphone with one hand, the user holds the smartphone near its lower side, and the finger 70 often touches the lower region of the pixel unit 30 (the region of the pixel unit 30 that includes the pixels in the 1st to m / 2th rows or the m / 2+1st to mth rows). In this case, therefore, the fingerprint image only needs to be read from the lower region that the finger 70 touches, and it is preferable that the pixel unit 30F be provided in the lower region of the pixel unit 30.

[0256] Note that the pixel unit 30F is not limited to being provided in the region below the pixel unit 30. The schematic diagram shown in Fig. 17 is not limited to a smartphone.

[0257] The pixel section 30B is one of the regions of the pixel section 30 adjacent to the pixel section 30R, and is a region including pixels in the 1st to (b-1)th rows of the pixel section 30.

[0258] The pixel section 30U is the other region of the pixel section 30 adjacent to the pixel section 30R, and is a region including pixels in the u+1th to mth rows of the pixel section 30.

[0259] As described above, in step X1, a process is performed to skip fingerprint imaging within one region of pixel unit 30 where a finger is not detected (this can also be said to be one region of the first pixel unit that does not overlap with the second pixel unit), i.e., from the pixels in the first row (m-th row) to the pixels in the b-1st row (u+1st row) of pixel unit 30. That is, in pixel unit 30B (pixel unit 30U), the fingerprint image is not read out, and only the process of moving from one row to the next is performed by skipping the imaging operation.

[0260] As described above, after reading out the user's fingerprint image in pixel unit 30F in the second mode (step X2), step X3 performs processing to skip fingerprint imaging operation in the other region of pixel unit 30 where a finger is not detected (which can also be said to be the other region of the first pixel unit that does not overlap with the second pixel unit), i.e., from the pixels in row u+1 (row b-1) of pixel unit 30 to the pixels in row m (row 1). That is, in pixel unit 30U (pixel unit 30B), the fingerprint image is not read out, but the imaging operation is skipped and only processing to move from one row to the next is performed.

[0261] That is, in the driving method of one embodiment of the present invention, the first mode is not performed, and the second mode is performed only for the pixel portion 30F. By specifying the area where the user's fingerprint is to be read in advance, it is not necessary to detect the position of the user's finger, and the overall processing time can be shortened. Furthermore, by limiting the area where the fingerprint image is to be read to a portion of the pixel portion 30, the frame frequency required for the row driver circuit 33 to read the fingerprint image can be increased compared to when the fingerprint image is read from the entire pixel portion. This allows fingerprint authentication to be performed in a short time.

[0262] An example of the details of the driving method shown in FIGS. 16 and 17 will be described below with reference to FIGS. 18 and 19. FIG.

[0263] 18 and 19 are timing charts showing an example of the details of the driving method shown in FIG. 7 (FIG. 17), and show an example of the driving method of the row driver circuit 33 divided into periods T40 to T73.

[0264] As described above, in step X1 of the flowchart in FIG. 16 , a process is performed to skip fingerprint imaging in one region of the pixel unit 30 where a finger is not detected. That is, a process is performed to skip fingerprint imaging from the pixels in the first row (the mth row) to the pixels in the p-1th row (the q+1th row) of the pixel unit 30 shown in FIG. 7 . The period during this process in FIGS. 18 and 19 corresponds to periods T40 to T47. During this period, the row driver circuit 33 does not perform fingerprint imaging, but only performs row shifting from the pixels in the first row (the mth row) to the pixels in the p-1th row (the q+1th row) of the pixel unit 30 described above. Therefore, the overall processing time in this region can be set shorter than when a fingerprint imaging operation is performed.

[0265] Next, in step X2 shown in the flowchart of FIG. 16 , a process (second mode) is performed in which a fingerprint image is read row by row from the pixel in the pth row (qth row) to the pixel in the qth row (pth row) of the pixel unit 30, which is the designated region. The period during this process in FIGS. 18 and 19 corresponds to periods T48 to T68. During this period, the row driver circuit 33 performs both an operation of shifting between rows from the pixel in the pth row (qth row) to the pixel in the qth row (pth row) of the pixel unit 30 described above, and an operation of capturing an image of a fingerprint in each row. Therefore, the processing time for this region is set to a time width that takes into account the above-mentioned image capturing operation.

[0266] As described above, in step X3 of the flowchart in FIG. 16 , a process is performed to skip fingerprint imaging in the other region of the pixel unit 30 where a finger is not detected. That is, a process is performed to skip fingerprint imaging from the pixels in the q+1th row (p-1th row) to the pixels in the mth row (1st row) of the pixel unit 30 shown in FIG. 7 . The period during this process in FIGS. 18 and 19 corresponds to periods T69 to T73. During this period, the row driver circuit 33 does not perform fingerprint imaging, but only performs row shifting from the pixels in the q+1th row (p-1th row) to the pixels in the mth row (1st row) of the pixel unit 30 described above. Therefore, the overall processing time in this region can be set shorter than when a fingerprint imaging operation is performed.

[0267] In the periods T40 to T73 (FIG. 19), the potential of the terminal SEL1 is high, and the potential of the terminal SEL2 is low. In the periods T40 to T73 (FIG. 19), the potential of the terminal SP2 is low. In the periods T40 to T73 (FIG. 18), the potentials of the terminals CLK2[1] to CLK2[4] are low.

[0268] During the period T40 (FIG. 19), a high-potential signal is input to the terminal SP1 as a start pulse signal, causing the register circuit F[1] to output a high-potential signal to the terminal FO1[1]. Also, a low-potential signal is output from the register circuit F[1] to the terminal FFN[1]. At this time, the potential of the terminal SEL1, which is an input terminal of the selection circuit M[1], is high, and the potential of the terminal SEL2, which is another input terminal of the selection circuit M[1], is low. Therefore, the signal from the terminal FO1[1] is output to the terminal O1[1] by the selection circuit M[1]. Therefore, the potential of the terminal O1[1] becomes high. Also, the signal from the terminal FFN[1] is output to the terminal FN[1]. Therefore, the potential of the terminal FN[1] becomes low. Note that during the period T40 (FIG. 18), the potentials of the terminals CLK1[1] to CLK1[4] are all low.

[0269] Next, in a period T41 (FIG. 18), the potential of the terminal CLK1[1] becomes high. Therefore, in the period T41, the potential of the terminal FOUT[1] output from the register circuit F[1] becomes high. Note that the potentials of the terminals CLK1[2] to CLK1[4] remain low, as in the period T40.

[0270] Periods T41 to T47 are periods during which processing corresponding to step X1 in the flowchart of Fig. 16 is performed. That is, these are periods during which the fingerprint imaging operation is skipped in one region of the pixel unit 30 where a finger is not detected, and during these periods, output signals are sequentially sent from terminals CLK1[1] to CLK1[4]. During this period, the potentials of terminals SL_PWC1 to SL_PWC4 and terminals RS_PWC1 to RS_PWC4 are low, and the potentials of terminal SL[1] and terminal RS[1] are low.

[0271] Furthermore, during period T42 (FIG. 18), the potential of the terminal CLK1[2] becomes high. Therefore, during period T42, the potential of the terminal FOUT[1] output from the register circuit F[1] becomes high. As described above, the signal output from the register circuit F[1] is input to the register circuit F[2] via the terminal FOUT[1], and therefore a high-potential signal is output from the register circuit F[2] to the terminal FO1[2]. However, during this period, the potentials of the terminals SL_PWC1 to SL_PWC4 and the terminals RS_PWC1 to RS_PWC4 are low, and the potential of the terminal SL[2] and the terminal RS[2] are low.

[0272] Furthermore, during period T43 (FIG. 18), the potential of the terminal CLK1[3] becomes high. Therefore, during period T43, the potential of the terminal FOUT[2] output from the register circuit F[2] becomes high. As described above, the signal output from the register circuit F[2] is input to the register circuit F[3] via the terminal FOUT[2], and therefore a high-potential signal is output from the register circuit F[3] to the terminal FO1[3]. However, during this period, the potentials of the terminals SL_PWC1 to SL_PWC4 and the terminals RS_PWC1 to RS_PWC4 are low, and the potential of the terminal SL[3] and the terminal RS[3] are low.

[0273] Furthermore, during period T44 (FIG. 18), the potential of the terminal CLK1[4] becomes high. Therefore, during period T44, the potential of the terminal FOUT[3] output from the register circuit F[3] becomes high. As described above, the signal output from the register circuit F[3] is input to the register circuit F[4] via the terminal FOUT[3], and therefore a high-potential signal is output from the register circuit F[4] to the terminal FO1[4]. However, during this period, the potentials of the terminals SL_PWC1 to SL_PWC4 and the terminals RS_PWC1 to RS_PWC4 are low, and the potential of the terminal SL[4] and the terminal RS[4] are low.

[0274] Next, during period T46 (FIG. 18), the potential of terminal CLK1[3] becomes high. Therefore, during period T46, the potential of terminal FOUT[3] output from register circuit F[3] becomes high. Here, as described above, the signal output from register circuit F[3] is input to the register circuit F[1] in the stage before the previous stage via terminal FOUT[3]. Therefore, during period T46, a high-potential signal is input to register circuit F[1]. Therefore, the output from register circuit F[1] causes the potential of terminal FO1[1] to become low. Furthermore, the output from register circuit F[1] causes the potential of terminal FFN[1] to become high.

[0275] 16, the register circuit F performs only the operation of shifting between rows by repeatedly performing the operation described above in Fig. 18 and Fig. 19 from the pixels in the first row (the mth row) to the p-1th row (the q+1th row) of the pixel unit 30. During this time, the potentials of the terminals SL_PWC1 to SL_PWC4 and the terminals RS_PWC1 to RS_PWC4 are low, all potentials of the terminal SL and all potentials of the terminal RS are low, and no imaging operation is performed.

[0276] Next, we will explain the periods T48 to T68, which are the periods for performing the processing of step X2 shown in the flowchart of Figure 16. As mentioned above, during these periods, processing is performed to read out the fingerprint image row by row, from the pixel in the pth row (qth row) to the pixel in the qth row (pth row) of the pixel unit 30, which is the designated area. For convenience of explanation, we will explain this as if the terminal SL[5] in the configuration example of the row driver circuit 33 shown in Figure 3 is electrically connected to the pixel 31 in the qth row of the pixel unit 30.

[0277] First, in a period T48 (FIG. 18), the potential of the terminal CLK1[1] becomes high. Therefore, in the period T48, the potential of the terminal FOUT[5] output from the register circuit F[5] becomes high.

[0278] Furthermore, in the periods T48 to T49 (FIG. 18), the potential of the terminal SL_PWC1 is high. Since the potential of the terminal O1[5] is high and the potential of the terminal FN[5] is low, as in the period T47, the potential of the terminal SL[5] is high due to the output from the signal supply circuit B[5]. That is, a selection signal is output to the terminal SL[5]. Subsequently, in the period T50 (FIG. 18), the potential of the terminal SL_PWC1 is low, and the potential of the terminal SL[5] is low due to the output from the signal supply circuit B[5]. Note that in the periods T48 to T49 (FIG. 18), the potentials of the terminals SL_PWCS2 to SL_PWC4 are all low.

[0279] Furthermore, in the period T49 (FIG. 18), the potential of the terminal RS_PWC1 becomes high. Here, continuing from the period T47 described above, the potential of the terminal O1[5] is high and the potential of the terminal FN[1] is low, so that the potential of the terminal RS[5] becomes high due to the output from the signal supply circuit B[5]. That is, a reset signal is output to the terminal RS[5]. Subsequently, in the period T50 (FIG. 18), the potential of the terminal RS_PWC1 becomes low. Therefore, the potential of the terminal RS[5] becomes low due to the output from the signal supply circuit B[5]. Note that in the period T49 (FIG. 18), the potentials of the terminals RS_PWC2 to RS_PWC4 are all low.

[0280] Also, during period T50 (FIG. 18), the potentials of terminals CLK1[1] and CLK1[2] are high. Therefore, during period T50, the potential of terminal FOUT[5] output from register circuit F[5] is high. As described above, the signal output from register circuit F[5] is input to register circuit F[6] via terminal FOUT[5], so a high-potential signal is output from register circuit F[6] to terminal FO1[6]. Furthermore, a low-potential signal is output from register circuit F[6] to terminal FFN[6]. Here, during period T50 (FIG. 19), the potential of terminal SEL1 is high, and the potential of terminal SEL2 is low. Therefore, selection circuit M[6], electrically connected to terminals SEL1 and SEL2, outputs the signal output from register circuit F[6] to terminal FO1[6] to terminal O1[6]. Therefore, the potential of the terminal O1[6] becomes high. Also, the signal output from the register circuit F[6] to the terminal FFN[6] is output to the terminal FN[6]. Therefore, the potential of the terminal FN[6] becomes low.

[0281] Furthermore, in the periods T50 to T51 (FIG. 18), the potential of the terminal SL_PWC2 is high. Since the potential of the terminal O1[6] is high and the potential of the terminal FN[6] is low following the period T48, the potential of the terminal SL[6] is high due to the output from the signal supply circuit B[6]. That is, a selection signal is output to the terminal SL[6]. Subsequently, in the period T52 (FIG. 18), the potential of the terminal SL_PWC2 is low, and the potential of the terminal SL[6] is low due to the output from the signal supply circuit B[6]. Note that in the periods T50 to T51 (FIG. 18), the potentials of the terminals SL_PWC1, SL_PWC3, and SL_PWC4 are all low.

[0282] Furthermore, in period T51 (FIG. 18), the potential of terminal RS_PWC2 becomes high. Here, continuing from period T48 described above, the potential of terminal O1[6] is high and the potential of terminal FN[6] is low, so that the output from signal supply circuit B[6] causes the potential of terminal RS[6] to become high. That is, a reset signal is output to terminal RS[6]. Subsequently, in period T52 (FIG. 18), the potential of terminal RS_PWC2 becomes low. Therefore, the output from signal supply circuit B[6] causes the potential of terminal RS[6] to become low. Note that in period T51 (FIG. 18), the potentials of terminals RS_PWC1, RS_PWC3, and RS_PWC4 are all low.

[0283] As described above, during period T50, the potential of terminal FOUT[5] output from register circuit F[5] is high. As described above, the signal output from register circuit F[5] is input to register circuit F[6] via terminal FOUT[5]. The signal output from register circuit F[6] is then input to terminal FOUT[6]. Therefore, during period T50, the potential of terminal FOUT[6] is also high. Similarly, the signal output from register circuit F[6] is input to register circuit F[7] via terminal FOUT[6]. Therefore, a high-potential signal is output from register circuit F[7] to terminal FO1[7]. Furthermore, a low-potential signal is output from register circuit F[7] to terminal FFN[7]. Here, during period T50 (FIG. 19), the potential of terminal SEL1 is high, and the potential of terminal SEL2 is low. Therefore, the selection circuit M[7], which is electrically connected to the terminals SEL1 and SEL2, outputs the signal output from the register circuit F[7] to the terminal FO1[7] to the terminal O1[7]. As a result, the potential of the terminal O1[7] becomes high. Also, the selection circuit M[7] outputs the signal output from the register circuit F[7] to the terminal FFN[7] to the terminal FN[7]. As a result, the potential of the terminal FN[7] becomes low.

[0284] Next, from period T52 to period T55 (FIG. 18), the potential of terminal CLK1[3] becomes high. Therefore, from period T52 to period T55, the potential of terminal FOUT[7] output from register circuit F[7] becomes high. Here, as described above, the signal output from register circuit F[7] is input to the register circuit F[5] in the second previous stage via terminal FOUT[7]. Therefore, from period T52 to period T55, a high-potential signal is input to register circuit F[5]. Therefore, the output from register circuit F[5] causes the potential of terminal FO1[5] to become low. Furthermore, the output from register circuit F[5] causes the potential of terminal FFN[5] to become high.

[0285] As described above, by repeatedly performing the process corresponding to step X2 shown in the flowchart of FIG. 16 , i.e., the above-described fingerprint image readout operation in a specified region of the pixel unit 30 (a region including pixels in the pth row (qth row) to the qth row (pth row) of the pixel unit 30), scan signals can be sequentially supplied to the pixels 31. That is, in the period T47, when a high potential is input to the register circuit F[p] from the register circuit F[p-1] in the preceding stage of the register circuit F[p] via the terminal FOUT[p-1], a scan signal is supplied to the selection circuit M[p] and the signal supply circuit B[p]. Thereafter, scan signals are sequentially supplied to the register circuits F[p] to F[q], the selection circuits M[p] to M[q], and the signal supply circuits B[p] to B[q]. Then, in response to the scan signals, selection signals are sequentially output to the terminals SL[p] to SL[q], and reset signals are sequentially output to the terminals RS[p] to RS[q], respectively. This allows the imaging data to be read out sequentially from the pixels 31 in the pth to qth rows in the pixel section 30. In the driving method shown in Fig. 7 (Fig. 17), no start pulse signal is input to the terminal SP2.

[0286] Below, we will explain the process corresponding to step X3 shown in the flowchart of FIG. 16, i.e., the process of skipping the imaging operation in the other region of the pixel unit 30 where a finger is not detected (the region including the pixels in the q+1th row (the p-1th row) to the mth row (the 1st row) of the pixel unit 30).

[0287] During a period T69 (FIG. 18), the potential of the terminal CLK1[1] becomes high. Therefore, during the period T69, the high potential of the terminal FOUT[q] output from the register circuit F[q] is input to the register circuit F[q+1], and the potential of the terminal FOUT[1] output from the register circuit F[q+1] becomes high.

[0288] 16. That is, the period from T69 to T73 is a period during which the process corresponding to step X3 shown in the flowchart of FIG. 16 is performed. In other words, this is a period during which the fingerprint imaging operation is skipped in the other region of the pixel unit 30 where a finger is not detected, and during this period, output signals are sequentially sent from terminals CLK1[1] to CLK1[4]. During this period, the potentials of terminals SL_PWC1 to SL_PWC4 and terminals RS_PWC1 to RS_PWC4 are low, and the potentials of terminal SL[q+1] and terminal RS[q+1] are low.

[0289] Furthermore, during the period T70 (FIG. 18), the potential of the terminal CLK1[2] becomes high. Therefore, during the period T70, the potential of the terminal FOUT[q+1] output from the register circuit F[q+1] becomes high. As described above, the signal output from the register circuit F[q+1] is input to the register circuit F[q+2] via the terminal FOUT[q+1], and therefore a high-potential signal is output from the register circuit F[q+2] to the terminal FO1[q+2]. However, during this period, the potentials of the terminals SL_PWC1 to SL_PWC4 and the terminals RS_PWC1 to RS_PWC4 are low, and therefore the potentials of the terminal SL[q+2] and the terminal RS[q+2] become low.

[0290] Furthermore, during the period T71 (FIG. 18), the potential of the terminal CLK1[3] becomes high. Therefore, during the period T71, the potential of the terminal FOUT[q+2] output from the register circuit F[q+2] becomes high. As described above, the signal output from the register circuit F[q+2] is input to the register circuit F[q+3] via the terminal FOUT[q+2], and therefore a high-potential signal is output from the register circuit F[q+3] to the terminal FO1[q+3]. However, during this period, the potentials of the terminals SL_PWC1 to SL_PWC4 and the terminals RS_PWC1 to RS_PWC4 are low, and therefore the potentials of the terminal SL[q+3] and the terminal RS[q+3] become low.

[0291] Furthermore, during the period T72 (FIG. 18), the potential of the terminal CLK1[4] becomes high. Therefore, during the period T72, the potential of the terminal FOUT[q+3] output from the register circuit F[q+3] becomes high. As described above, the signal output from the register circuit F[q+3] is input to the register circuit F[q+4] via the terminal FOUT[q+3], and therefore a high-potential signal is output from the register circuit F[q+4] to the terminal FO1[q+4]. However, during this period, the potentials of the terminals SL_PWC1 to SL_PWC4 and the terminals RS_PWC1 to RS_PWC4 are low, and therefore the potentials of the terminal SL[q+4] and the terminal RS[q+4] become low.

[0292] 16, the operation described above in FIGS. 18 and 19 (similar to the operation in step X1 in the flowchart of FIG. 16) is repeatedly performed from the q+1th row (the p-1th row) to the mth row (the 1st row) of the pixel section 30, so that the register circuit F only performs the operation of shifting between the rows. During this time, the potentials of the terminals SL_PWC1 to SL_PWC4 and the terminals RS_PWC1 to RS_PWC4 are low, so that all potentials of the terminal SL and all potentials of the terminal RS are low, and no imaging operation is performed.

[0293] As described above, the row driver circuit 33 performs the operations shown in FIGS. 18 and 19 in the read period, whereby the semiconductor device of one embodiment of the present invention can perform authentication such as fingerprint authentication.

[0294] 20 is a flowchart illustrating another example of a driving method of the row driver circuit 33 according to one embodiment of the present invention, which is different from the flowchart illustrated in FIG. 16. By using this driving method, the semiconductor device according to one embodiment of the present invention can perform fingerprint authentication of a user in a short time.

[0295] First, in step Y1, the position of the user's finger is detected. For example, in Fig. 6, it is detected where the user's finger 70 is located on the pixel unit 30. That is, step Y1 is the driving method shown in Fig. 6, which is the first mode.

[0296] As explained in <Configuration Example of Imaging Device>, the pixel unit 30 is composed of pixels arranged in a matrix of m rows and n columns. Therefore, detecting the position of the finger 70 on the pixel unit 30 can be said to mean detecting that the finger 70 is located on pixels in the pth to qth rows (p and q are integers between 1 and m) of the pixel unit 30.

[0297] As mentioned above, in step Y1, it is not necessary to perform the process of detecting the position of the user's finger on all pixels 31 in the pixel unit 30. For example, it is preferable to perform the process on limited pixels, that is, every x rows and every y columns (x and y are integers greater than or equal to 1 and less than or equal to q-p), among the pixels 31 in the pixel unit 30. This allows the position of the user's finger to be detected in a shorter time than when all pixels 31 in the pixel unit 30 are targeted.

[0298] Next, in step Y2, a process is performed to skip fingerprint imaging within one region of the pixel unit 30 where a finger is not detected (which can also be said to be one region of the first pixel unit that does not overlap with the second pixel unit). For example, in Fig. 7, the region where a finger is not detected is the region including pixels in the 1st to p-1th rows of the pixel unit 30 and the region including pixels in the q+1st to mth rows of the pixel unit 30. Therefore, in step Y2, a process is performed to skip fingerprint imaging from the pixels in the 1st row (mth row) to the pixels in the p-1th row (q+1th row) of the pixel unit 30.

[0299] Next, in step Y3, a process of reading out the fingerprint image row by row from the pixel in the pth row (qth row) to the pixel in the qth row (pth row) of the pixel unit 30, which is the designated region, is performed. As described with reference to FIG. 1 , the semiconductor device 10 of one embodiment of the present invention includes a light-emitting device and an imaging device, and light emitted from the light-emitting device is reflected by a finger or the like, and the light is detected by the imaging device. Therefore, in step Y2, it can be said that the pixel that detects the light reflected by the finger, out of the light emitted from the light-emitting device, captures an image of the fingerprint on the finger and reads out the image data.

[0300] Step Y3 is the driving method shown in FIG. 7, which is the second mode.

[0301] Next, in step Y4, a process is performed to skip fingerprint imaging within the other area of ​​the pixel unit 30 where a finger is not detected (which can also be said to be the other area of ​​the first pixel unit that does not overlap with the second pixel unit), i.e., from the pixels in the q+1th row (p-1th row) of the pixel unit 30 to the pixels in the mth row (1st row).

[0302] As described above, in the driving method of one aspect of the present invention, the position of a user's finger is detected in the first mode (step Y1), and a fingerprint image is read out only from a partial region of the pixel unit 30 in the second mode (step Y3). For regions where a finger is not detected, the fingerprint image is not read out, and only the process of shifting the rows of pixels included in those regions is performed (steps Y2 and Y4). That is, the flowchart shown in FIG. 20 differs from the flowchart shown in FIG. 16 in that the first mode is performed first.

[0303] FIG. 21 is a schematic diagram showing an example of the driving method of the row driver circuit 33 described using the flowchart of FIG.

[0304] In FIG. 21, the pixel section 30 includes a pixel section 30B, a pixel section 30R, and a pixel section 30U.

[0305] The pixel section 30B is one of the regions of the pixel section 30 adjacent to the pixel section 30R, and is a region including pixels in the 1st to p-1th rows of the pixel section 30.

[0306] The pixel section 30U is the other region of the pixel section 30 adjacent to the pixel section 30R, and is a region including pixels in the q+1th to mth rows of the pixel section 30.

[0307] 21 does not show a designated area for detecting the position of a finger, which corresponds to pixel unit 30F in FIG. 17, but this is not a limitation of one aspect of the present invention. In one aspect of the present invention, pixel unit 30 in FIG. 21 may have a designated area for detecting the position of a finger, and the first mode may be performed within the designated area.

[0308] As described above, after detecting the position of the user's finger in the first mode (step Y1), in step Y2, a process is performed to skip fingerprint imaging within one region of the pixel unit 30 where a finger is not detected, i.e., from the pixels in the first row (the mth row) to the pixels in the p-1th row (the q+1th row) of the pixel unit 30. That is, in the pixel unit 30B (pixel unit 30U), the fingerprint image is not read out, but the imaging operation is skipped and only the process of moving from one row to the next is performed.

[0309] As described above, after the user's fingerprint image is read out in pixel unit 30R in the second mode (step Y3), step Y4 is performed to skip the fingerprint imaging operation in the other region of pixel unit 30 where a finger is not detected, i.e., from the pixels in row q+1 (row p-1) of pixel unit 30 to the pixels in row m (row 1). That is, in pixel unit 30U (pixel unit 30B), the fingerprint image is not read out, but the imaging operation is skipped and only the process of moving from one row to the next is performed.

[0310] That is, in the driving method of one embodiment of the present invention, the first mode is performed on limited pixels, that is, pixels every x rows and every y columns, among the pixels 31 included in the pixel portion 30, and then the second mode is performed on only the pixel portion 30R. By limiting the area from which a fingerprint image is read out to a part of the pixel portion 30 in this way, the frame frequency for reading out the fingerprint image by the row driver circuit 33 can be made faster than when the fingerprint image is read out from the entire pixel portion. This enables fingerprint authentication to be performed in a short time.

[0311] <Configuration Example 2 of Semiconductor Device> Fig. 22 is a block diagram showing a configuration example of the semiconductor device 10. As shown in Fig. 1A, the semiconductor device 10 has a light-emitting device 13 and an imaging device 15. Note that although the boundary between the light-emitting device 13 and the imaging device 15 is not shown in Fig. 22, the semiconductor device 10 shown in Fig. 22 has the imaging device 15 shown in Fig. 2A. Therefore, the description of the configuration described in Fig. 2A will be omitted as appropriate.

[0312] The semiconductor device 10 has a pixel section 84 in which pixel sections 30 are arranged in a matrix. The semiconductor device 10 also has a control circuit 32, a row driver circuit 33, a CDS circuit 34, a readout circuit 36, a detection circuit 37, a gate driver circuit 83, and a data driver circuit 86.

[0313] The pixel unit 30 can be configured to include a pixel 81 and a pixel 82 in addition to the pixel 31. For example, the pixel 81 has a function of emitting light for displaying an image in the pixel unit 84. The pixel 82 has a function of emitting light for irradiating an object to be detected. In other words, the pixel 82 has a function of emitting light 23 shown in FIGS. 1A and 1B, etc. Here, the pixel 81, the pixel 82, and the pixel 31 can be referred to as sub-pixels.

[0314] The pixel 31 has a light-emitting element (also called a light-emitting device) that emits visible light, for example, and the pixel 82 has a light-emitting element that emits infrared light.

[0315] As the light-emitting element, it is preferable to use an EL element such as an OLED (organic light-emitting diode) or a QLED (quantum-dot light-emitting diode). Examples of light-emitting materials that the EL element has include fluorescent materials (fluorescent materials), phosphorescent materials (phosphorescent materials), materials that exhibit thermally activated delayed fluorescence (thermally activated delayed fluorescence (TADF) materials), inorganic compounds (quantum dot materials, etc.). Furthermore, LEDs such as micro LEDs (light-emitting diodes) can also be used as the light-emitting element.

[0316] The gate driver circuit 83 is electrically connected to the pixels 81 and 82 via gate lines. The data driver circuit 86 is electrically connected to the pixels 81 and 82 via data lines.

[0317] The gate driver circuit 83 has a function of selecting the pixel 81 and the pixel 82 to which data representing the light emission intensity of the light-emitting element is written. The data driver circuit 86 has a function of generating data representing the light emission intensity of the light-emitting element of the pixel 81 and data representing the light emission intensity of the light-emitting element of the pixel 82. The gate driver circuit 83 and the data driver circuit 86 are drive circuits for driving the pixels 81 and 82.

[0318] The drive circuit for driving the pixel 81 and the drive circuit for driving the pixel 82 may be separate. The main function of the pixel 82 is to emit light to irradiate the detection target. Therefore, for example, all the pixels 82 may emit light of the same brightness. In this case, the drive circuit for driving the pixel 82 may have a simplified configuration that does not include a highly functional sequential circuit or the like.

[0319] Fig. 23 is a block diagram showing a configuration example of the semiconductor device 10, which is a modified example of the semiconductor device 10 shown in Fig. 22. The semiconductor device 10 shown in Fig. 23 differs from the semiconductor device 10 shown in Fig. 22 in that the pixel section 30 does not have pixels 82.

[0320] 23, a light source 82E that emits light to irradiate an object to be detected is provided outside a pixel unit 84. An LED that emits high-intensity near-infrared light or the like can be used as the light source 82E. Because the light source 82E is provided outside the pixel unit 84, it can also be turned on by a control separate from that of the semiconductor device 10.

[0321] 23 are merely examples and are not intended to be limiting. The light source 82E may be an element of a device in which the semiconductor device 10 is installed. Alternatively, the light source 82E may be a device separate from the semiconductor device 10.

[0322] The configuration of the pixel section 30 is not limited to the configuration shown in FIGS. 22 and 23, and various arrangements can be adopted.

[0323] 24A is a circuit diagram showing a configuration example of a pixel circuit PIX1 that can be used for pixel 81 and pixel 82. The pixel circuit PIX1 has a light-emitting element EL1, transistors M1, M2, and M3, and a capacitor C101. Here, an example is shown in which a light-emitting diode is used as the light-emitting element EL1. It is preferable to use an organic EL element that emits visible light or an organic EL element that emits infrared light as the light-emitting element EL1.

[0324] One of the source and drain of transistor M1 is electrically connected to wiring S1. The other of the source and drain of transistor M1 is electrically connected to the gate of transistor M2 and one electrode of capacitor C101. The gate of transistor M1 is electrically connected to wiring G1. One of the source and drain of transistor M2 is electrically connected to wiring V2. The other of the source and drain of transistor M2 is electrically connected to the anode of light-emitting element EL1, the other electrode of capacitor C101, and one of the source and drain of transistor M3. The other of the source and drain of transistor M3 is electrically connected to wiring V0. The gate of transistor M3 is electrically connected to wiring G2. The cathode of light-emitting element EL1 is electrically connected to wiring V1.

[0325] The wiring G1 and the wiring G2 can be electrically connected to the gate driver circuit 83 shown in Figures 22 and 23. The wiring S1 can be electrically connected to the data driver circuit 86 shown in Figures 22 and 23.

[0326] A constant potential is supplied to the wiring V1 and the wiring V2. The light-emitting element EL1 can emit light by setting the anode side of the light-emitting element EL1 at a high potential and the cathode side at a low potential. The transistor M1 is controlled by a signal supplied to the wiring G1 and functions as a selection transistor for controlling the selection state of the pixel circuit PIX1. The transistor M2 also functions as a drive transistor for controlling the current flowing through the light-emitting element EL1 in accordance with the potential supplied to its gate.

[0327] When the transistor M1 is in a conductive state, the potential supplied to the wiring S1 is supplied to the gate of the transistor M2, and the light emission luminance of the light-emitting element EL1 can be controlled according to the potential. The transistor M3 is controlled by a signal supplied to the wiring G2. By turning on the transistor M3, the potential between the transistor M3 and the light-emitting element EL1 can be reset to a constant potential supplied from the wiring V0. This allows a potential to be written to the gate of the transistor M2 while the source potential of the transistor M2 is stabilized.

[0328] 24B shows an example of a pixel circuit PIX2 that is different from the pixel circuit PIX1. The pixel circuit PIX2 has a boosting function. The pixel circuit PIX2 includes a light-emitting element EL2, transistors M4, M5, M6, and M7, and capacitors C102 and C103. Here, an example is shown in which a light-emitting diode is used as the light-emitting element EL2.

[0329] One of the source and drain of transistor M4 is electrically connected to wiring S4. The other of the source and drain of transistor M4 is electrically connected to the gate of transistor M6, one electrode of capacitor C102, and one electrode of capacitor C103. The gate of transistor M4 is electrically connected to wiring G1. One of the source and drain of transistor M5 is electrically connected to wiring S5. The other of the source and drain of transistor M5 is electrically connected to the other electrode of capacitor C103. The gate of transistor M5 is electrically connected to wiring G3.

[0330] One of the source and drain of transistor M6 is electrically connected to wiring V2. The other of the source and drain of transistor M6 is electrically connected to one of the source and drain of transistor M7, the other electrode of capacitor C102, and the anode of light-emitting element EL2. The other of the source and drain of transistor M7 is electrically connected to wiring V0. The gate of transistor M7 is electrically connected to wiring G2. The cathode of light-emitting element EL2 is electrically connected to wiring V1.

[0331] The wirings G1 to G3 can be electrically connected to the gate driver circuit 83 shown in Figures 22 and 23. The wirings S4 and S5 can be electrically connected to the data driver circuit 86 shown in Figures 22 and 23.

[0332] The transistor M4 is controlled by a signal supplied to the wiring G1, and the transistor M5 is controlled by a signal supplied to the wiring G3. The transistor M6 functions as a drive transistor that controls the current flowing through the light-emitting element EL2 in accordance with the potential supplied to the gate.

[0333] The light emission luminance of the light-emitting element EL2 can be controlled according to the potential supplied to the gate of the transistor M6. The transistor M7 is controlled by a signal supplied to the wiring G2. By turning on the transistor M7, the potential between the transistor M6 and the light-emitting element EL2 can be reset to a constant potential supplied from the wiring V0. This allows a potential to be written to the gate of the transistor M6 while the source potential of the transistor M6 is stabilized. Furthermore, by setting the potential supplied from the wiring V0 to the same potential as or lower than the wiring V1, the light emission of the light-emitting element EL2 can be suppressed.

[0334] The boosting function of the pixel circuit PIX2 will be described below.

[0335] First, the potential "D1" of the wiring S4 is supplied to the gate of the transistor M6 via the transistor M4, and at the same timing, the reference potential "V ｒｅｆ At this time, the capacitor C103 is supplied with "D1-V ｒｅｆ Next, the gate of the transistor M6 is set to a floating state, and the potential "D2" of the wiring S5 is supplied to the other electrode of the capacitor C103 via the transistor M5. Here, the potential "D2" is a potential for addition.

[0336] At this time, the capacitance value of the capacitor C103 is C ３ , the capacitance value of the capacitor C102 is C ２ , the capacitance value of the gate of the transistor M6 is C Ｍ６ Then, the potential of the gate of the transistor M6 is D1+((C ３ / (C ３ +C ２ +C Ｍ６ ) × (D2 − V ｒｅｆ )) where C ３ The value of C ２ +C Ｍ６ If we assume that the value is sufficiently larger than the value of C ３ / (C ３ +C ２ +C Ｍ６ ) is close to 1. Therefore, the potential of the gate of the transistor M6 is "D1 + (D2 - Vｒｅｆ )" and D1 = D2, and V ｒｅｆ = 0, then "D1 + (D2 - V ｒｅｆ ))" = "2D1".

[0337] In other words, if the circuit is designed appropriately, a potential that is approximately twice the potential that can be input from the wiring S4 or S5 can be supplied to the gate of the transistor M6.

[0338] This effect makes it possible to generate a high voltage even when using a general-purpose driver IC, thereby lowering the input voltage and reducing power consumption.

[0339] The pixel circuit PIX2 may also have the configuration shown in FIG. 24C . The pixel circuit PIX2 shown in FIG. 24C differs from the pixel circuit PIX2 shown in FIG. 24B in that it includes a transistor M8. In the pixel circuit PIX2 shown in FIG. 24C , one of the source or drain of the transistor M8 is electrically connected to the other of the source or drain of the transistor M5 and the other electrode of the capacitor C103. The other of the source or drain of the transistor M8 is electrically connected to a wiring V0. The gate of the transistor M8 is electrically connected to a wiring G1. In addition, one of the source or drain of the transistor M5 is electrically connected to a wiring S4.

[0340] 24B, as described above, the pixel circuit PIX2 performs the operation of supplying the reference potential and the potential for addition to the other electrode of the capacitor C103 via the transistor M5. In this case, two wirings S4 and S5 are required, and the reference potential and the potential for addition must be rewritten alternately on the wiring S5.

[0341] 24C , the number of transistors M8 is increased, but a dedicated path for supplying the reference potential is provided, allowing the number of wirings S5 to be reduced. Furthermore, the gate of transistor M8 can be connected to wiring G1, and wiring V0 can be used as the wiring for supplying the reference potential, so the number of wirings connected to transistor M8 does not increase. Furthermore, the reference potential and the potential for addition are not alternately rewritten on a single wiring, allowing for low power consumption and high-speed operation.

[0342] 24B and 24C, the reference potential "V ｒｅｆ In this case, a potential about three times the potential that can be input from the wiring S4 or the wiring S5 can be supplied to the gate of the transistor M6. Note that the inverted potential means a potential whose absolute value of the difference from a certain reference potential is the same (or approximately the same) but which is different from the original potential. The original potential is "D1", the inverted potential is "D1B", and the reference potential is V ０ When V ０ = (D1+D1B) / 2.

[0343] In the semiconductor device of one embodiment of the present invention, an image may be displayed by emitting pulsed light from a light-emitting element. By shortening the driving time of the light-emitting element, the power consumption and heat generation of the semiconductor device can be reduced. Organic EL elements are particularly suitable because of their excellent frequency characteristics. The frequency can be, for example, from 1 kHz to 100 MHz.

[0344] <Configuration Example 3 of Semiconductor Device> FIG. 25 shows a perspective view of the semiconductor device 10, and FIG. 26A shows a cross-sectional view of the semiconductor device 10. As shown in FIG.

[0345] The semiconductor device 10 has a configuration in which a substrate 452 and a substrate 451 are bonded together. In Fig. 25, the substrate 452 is clearly indicated by a dashed line.

[0346] The semiconductor device 10 includes a display portion 462, a circuit 464, wiring 465, and the like. Fig. 25 shows an example in which an IC 473 and an FPC 472 are mounted on the semiconductor device 10. Therefore, the structure shown in Fig. 25 can also be said to be a display module including the semiconductor device 10, an IC (integrated circuit), and an FPC.

[0347] The circuit 464 can be, for example, a scanning line driver circuit.

[0348] The wiring 465 has a function of supplying signals and power to the display portion 462 and the circuit 464. The signals and power are input to the wiring 465 from the outside via the FPC 472 or input to the wiring 465 from the IC 473.

[0349] 25 shows an example in which an IC 473 is provided on a substrate 451 by a chip-on-glass (COG) method, a chip-on-film (COF) method, or the like. The IC 473 can be, for example, an IC including a scan line driver circuit or a signal line driver circuit. Note that the semiconductor device 10 and the display module may not necessarily include an IC. Alternatively, the IC may be mounted on an FPC by a COF method or the like.

[0350] 26A shows an example of a cross section of the semiconductor device 10, which is obtained by cutting a part of a region including the FPC 472, a part of the circuit 464, a part of the display portion 462, and a part of a region including a connecting portion. In FIG. 26A, an example of a cross section of the display portion 462 is shown, in particular, by cutting a region including the light-emitting element 430b that emits green light (G) and the light-receiving element 440 that receives reflected light (L).

[0351] The semiconductor device 10 shown in FIG. 26A includes a transistor 252, a transistor 260, a transistor 258, a light-emitting element 430b, a light-receiving element 440, and the like between a substrate 453 and a substrate 454.

[0352] The light-emitting element 430b and the light-receiving element 440 can be any of the light-emitting elements or light-receiving elements exemplified above.

[0353] Here, when a pixel of a display device has three types of subpixels having light-emitting elements that emit different colors, the three subpixels include subpixels of three colors: red (R), green (G), and blue (B), or subpixels of three colors: yellow (Y), cyan (C), and magenta (M). When a pixel of a display device has four subpixels, the four subpixels include subpixels of four colors: R, G, B, and white (W), or subpixels of four colors: R, G, B, and Y. Alternatively, the subpixels may be equipped with light-emitting elements that emit infrared light.

[0354] The light receiving element 440 may be a photoelectric conversion element sensitive to light in the red, green, or blue wavelength range, or a photoelectric conversion element sensitive to light in the infrared wavelength range.

[0355] The substrate 454 and the protective layer 416 are bonded together via an adhesive layer 442. The adhesive layer 442 is provided to overlap the light-emitting element 430b and the light-receiving element 440, respectively, and a solid sealing structure is applied to the semiconductor device 10. A light-shielding layer 417 is provided on the substrate 454.

[0356] The light-emitting element 430b and the light-receiving element 440 each have a conductive layer 411a, a conductive layer 411b, and a conductive layer 411c as pixel electrodes. The conductive layer 411b is reflective to visible light and functions as a reflective electrode. The conductive layer 411c is transparent to visible light and functions as an optical adjustment layer.

[0357] A conductive layer 411a included in the light-emitting element 430b is connected to a conductive layer 272b included in the transistor 260 through an opening provided in the insulating layer 264. The transistor 260 has a function of controlling driving of the light-emitting element. On the other hand, the conductive layer 411a included in the light-receiving element 440 is electrically connected to a conductive layer 272b included in the transistor 258. The transistor 258 has a function of controlling the timing of exposure using the light-receiving element 440, etc.

[0358] An EL layer 412G or a photoelectric conversion layer 412S is provided to cover the pixel electrode. An insulating layer 421 is provided in contact with the side surface of the EL layer 412G and the side surface of the photoelectric conversion layer 412S, and a resin layer 422 is provided to fill the recessed portion of the insulating layer 421. An organic layer 414, a common electrode 413, and a protective layer 416 are provided to cover the EL layer 412G and the photoelectric conversion layer 412S. By providing the protective layer 416 to cover the light-emitting element, impurities such as water can be prevented from entering the light-emitting element, thereby improving the reliability of the light-emitting element.

[0359] Light G emitted by the light-emitting element 430b is emitted toward the substrate 454. The light-receiving element 440 receives light L incident thereon through the substrate 454 and converts it into an electrical signal. The substrate 454 is preferably made of a material that is highly transparent to visible light.

[0360] The transistor 252, the transistor 260, and the transistor 258 are all formed over a substrate 453. These transistors can be manufactured using the same material and through the same process.

[0361] Note that the transistor 252, the transistor 260, and the transistor 258 may be fabricated to have different structures. For example, transistors may be fabricated with or without a back gate, or transistors may be fabricated with different materials and / or thicknesses of semiconductors, gate electrodes, gate insulating layers, source electrodes, and drain electrodes.

[0362] The substrate 453 and the insulating layer 262 are bonded together by an adhesive layer 455 .

[0363] In a method for manufacturing the semiconductor device 10, first, a formation substrate provided with the insulating layer 262, the transistors, the light-emitting elements, the light-receiving elements, and the like is bonded to a substrate 454 provided with a light-shielding layer 417 by an adhesive layer 442. Then, the formation substrate is peeled off, and a substrate 453 is attached to the exposed surface, thereby transferring each component formed on the formation substrate to the substrate 453. The substrate 453 and the substrate 454 are preferably flexible. This can increase the flexibility of the semiconductor device 10.

[0364] In the semiconductor device 10, the EL layer and the photoelectric conversion layer can be formed using a fine metal mask (FMM), or can be formed using a photolithography method instead of an FMM. When using photolithography, the EL layer and the photoelectric conversion layer are formed by depositing a film that will become the EL layer and the photoelectric conversion layer on one surface and then processing the film, so that the island-shaped EL layer and the photoelectric conversion layer can be formed with a uniform thickness.

[0365] In this specification, a device fabricated using a metal mask or FMM may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, a device fabricated without using a metal mask or FMM may be referred to as a device with an MML (metal maskless) structure.

[0366] In this specification, the term "island-like" refers to a state in which two or more layers made of the same material and formed in the same process are physically separated. For example, an island-like light-emitting layer refers to a state in which the light-emitting layer is physically separated from an adjacent light-emitting layer.

[0367] A connection portion 254 is provided in a region of the substrate 453 where the substrate 454 does not overlap. In the connection portion 254, the wiring 465 is electrically connected to the FPC 472 via a conductive layer 466 and a connection layer 292. The conductive layer 466 can be obtained by processing the same conductive film as the pixel electrode. This allows the connection portion 254 and the FPC 472 to be electrically connected via the connection layer 292.

[0368] The transistor 252, the transistor 260, and the transistor 258 each include a conductive layer 271 functioning as a gate, an insulating layer 261 functioning as a gate insulating layer, a semiconductor layer 281 including a channel formation region 281i and a pair of low-resistance regions 281n, a conductive layer 272a connected to one of the pair of low-resistance regions 281n, a conductive layer 272b connected to the other of the pair of low-resistance regions 281n, an insulating layer 275 functioning as a gate insulating layer, a conductive layer 273 functioning as a gate, and an insulating layer 265 covering the conductive layer 273. The insulating layer 261 is located between the conductive layer 271 and the channel formation region 281i. The insulating layer 275 is located between the conductive layer 273 and the channel formation region 281i.

[0369] The conductive layer 272a and the conductive layer 272b are connected to the low-resistance region 281n through openings provided in the insulating layer 275 and the insulating layer 265, respectively. One of the conductive layer 272a and the conductive layer 272b functions as a source, and the other functions as a drain.

[0370] 26A shows an example in which the top surface and side surfaces of the semiconductor layer are covered with an insulating layer 275. The conductive layer 272a and the conductive layer 272b are connected to the low-resistance region 281n through openings provided in the insulating layer 275 and the insulating layer 265, respectively.

[0371] 26B , the insulating layer 275 overlaps with the channel formation region 281i of the semiconductor layer 281 but does not overlap with the low-resistance region 281n. For example, the insulating layer 275 is processed using the conductive layer 273 as a mask, thereby manufacturing the structure shown in FIG. 26B . In FIG. 26B , the insulating layer 265 is provided to cover the insulating layer 275 and the conductive layer 273, and the conductive layer 272a and the conductive layer 272b are connected to the low-resistance region 281n through openings in the insulating layer 265. Furthermore, an insulating layer 268 may be provided to cover the transistor.

[0372] The structure of the transistor included in the display device of this embodiment is not particularly limited. For example, a planar transistor, a staggered transistor, an inverted staggered transistor, or the like can be used. Furthermore, either a top-gate transistor or a bottom-gate transistor structure may be used. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0373] The transistor 252, the transistor 260, and the transistor 258 each have a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and the same signal may be supplied to drive the transistor. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving the other.

[0374] The crystallinity of a semiconductor material used for a semiconductor layer of a transistor is not particularly limited, and any of an amorphous semiconductor, a single-crystal semiconductor, and a semiconductor having crystallinity other than single crystal (a microcrystalline semiconductor, a polycrystalline semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a single-crystal semiconductor or a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0375] The semiconductor layer of the transistor preferably includes a metal oxide (also referred to as an oxide semiconductor). That is, the display device of this embodiment preferably includes a transistor using a metal oxide for a channel formation region (hereinafter referred to as an OS transistor).

[0376] The band gap of the metal oxide used for the semiconductor layer of the transistor is preferably 2 eV or more, more preferably 2.5 eV or more. Use of a metal oxide with a wide band gap can reduce the off-state current of the OS transistor.

[0377] The metal oxide preferably contains at least indium or zinc, and more preferably contains indium and zinc. For example, the metal oxide preferably contains indium, M (wherein M is one or more selected from gallium, aluminum, yttrium, tin, silicon, boron, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt), and zinc. In particular, M is preferably one or more selected from gallium, aluminum, yttrium, and tin, and more preferably gallium. Note that a metal oxide containing indium, M, and zinc may be referred to as In-M-Zn oxide hereinafter.

[0378] When the metal oxide is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include a composition in which In:M:Zn = 1:1:1 or thereabouts, a composition in which In:M:Zn = 1:1:1.2 or thereabouts, a composition in which In:M:Zn = 2:1:3 or thereabouts, a composition in which In:M:Zn = 3:1:2 or thereabouts, a composition in which In:M:Zn = 4:2:3 or thereabouts, a composition in which In:M:Zn = 4:2:4.1 or thereabouts, a composition in which In:M:Zn = 5:1:3 or thereabouts, a composition in which In:M:Zn = 5:1:6 or thereabouts, a composition in which In:M:Zn = 5:1:7 or thereabouts, a composition in which In:M:Zn = 5:1:8 or thereabouts, a composition in which In:M:Zn = 6:1:6 or thereabouts, and a composition in which In:M:Zn = 5:2:5 or thereabouts. Note that the term "nearby composition" includes a range of ±30% of the desired atomic ratio. By increasing the atomic ratio of indium in the metal oxide, the on-state current, field-effect mobility, and the like of the transistor can be increased.

[0379] For example, when describing a composition having an atomic ratio of In:Ga:Zn = 4:2:3 or thereabout, this includes a case where, when the atomic ratio of In is 4, the atomic ratio of Ga is 1 or more and 3 or less, and the atomic ratio of Zn is 2 or more and 4 or less. Furthermore, when describing a composition having an atomic ratio of In:Ga:Zn = 5:1:6 or thereabout, this includes a case where, when the atomic ratio of In is 5, the atomic ratio of Ga is more than 0.1 and 2 or less, and the atomic ratio of Zn is 5 or more and 7 or less. Furthermore, when describing a composition having an atomic ratio of In:Ga:Zn = 1:1:1 or thereabout, this includes a case where, when the atomic ratio of In is 1, the atomic ratio of Ga is more than 0.1 and 2 or less, and the atomic ratio of Zn is more than 0.1 and 2 or less.

[0380] Furthermore, the atomic ratio of In in the In-M-Zn oxide may be less than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxide include a composition of In:M:Zn = 1:3:2 or thereabouts, a composition of In:M:Zn = 1:3:3 or thereabouts, and a composition of In:M:Zn = 1:3:4 or thereabouts. Increasing the atomic ratio of M in the metal oxide can increase the band gap of the In-M-Zn oxide and improve its resistance to a negative bias stress test due to light irradiation. Specifically, the amount of change in threshold voltage or the amount of change in shift voltage (Vsh) measured in a negative bias temperature illumination stress (NBTIS) test of a transistor can be reduced. The shift voltage (Vsh) is defined as the Vg at which the tangent to the maximum slope of the drain current (Id)-gate voltage (Vg) curve of the transistor intersects with the line of Id=1 pA.

[0381] Alternatively, the semiconductor layer of the transistor may contain silicon, such as amorphous silicon or crystalline silicon (such as low-temperature polysilicon or single-crystal silicon).

[0382] In particular, low-temperature polysilicon has a relatively high mobility and can be formed over a glass substrate, and therefore can be suitably used in display devices. For example, a transistor using low-temperature polysilicon for a semiconductor layer can be applied to the transistor 252 in the driver circuit, and a transistor using an oxide semiconductor for a semiconductor layer can be applied to the transistor 260 and the transistor 258 provided in the pixel.

[0383] Alternatively, the semiconductor layer of the transistor may include a layered material that functions as a semiconductor. A layered material is a general term for a group of materials having a layered crystal structure. A layered crystal structure is a structure in which layers formed by covalent bonds or ionic bonds are stacked via bonds weaker than covalent bonds or ionic bonds, such as van der Waals forces. A layered material has high electrical conductivity within a unit layer, that is, high two-dimensional electrical conductivity. By using a material that functions as a semiconductor and has high two-dimensional electrical conductivity in the channel formation region, a transistor with a large on-state current can be provided.

[0384] Examples of the layered material include graphene, silicene, and chalcogenides. Chalcogenides are compounds containing chalcogen (an element belonging to Group 16). Examples of chalcogenides include transition metal chalcogenides and Group 13 chalcogenides. Specific examples of transition metal chalcogenides that can be used as semiconductor layers of transistors include molybdenum sulfide (typically MoS ２ ), molybdenum selenide (typically MoSe ２ ), molybdenum telluride (typically MoTe ２ ), tungsten sulfide (typically WS ２ ), tungsten selenide (typically WSe ２ ), tungsten tellurium (typically WTe ２ ), hafnium sulfide (typically HfS ２ ), hafnium selenide (typically HfSe ２ ), zirconium sulfide (typically ZrS ２ ), zirconium selenide (typically ZrSe ２ ) etc.

[0385] The transistors included in the circuit 464 may have the same structure as or different from the transistors included in the display portion 462. The transistors included in the circuit 464 may all have the same structure or may have two or more types of structures. Similarly, the transistors included in the display portion 462 may all have the same structure or may have two or more types of structures.

[0386] At least one insulating layer covering the transistor is preferably made of a material that is resistant to the diffusion of impurities such as water and hydrogen. This allows the insulating layer to function as a barrier layer. With this structure, it is possible to effectively prevent impurities from diffusing into the transistor from the outside, thereby improving the reliability of the display device.

[0387] It is preferable to use an inorganic insulating film for each of the insulating layers 261, 262, 265, 268, and 275. Examples of the inorganic insulating film that can be used include a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, and an aluminum nitride film. Alternatively, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film may also be used. Two or more of the above-described inorganic insulating films may be stacked.

[0388] Here, organic insulating films often have lower barrier properties than inorganic insulating films. Therefore, it is preferable that the organic insulating film has an opening near the edge of the semiconductor device 10. This makes it possible to prevent impurities from entering from the edge of the semiconductor device 10 through the organic insulating film. Alternatively, the organic insulating film may be formed so that the edge of the organic insulating film is located inside the edge of the semiconductor device 10, so that the organic insulating film is not exposed at the edge of the semiconductor device 10.

[0389] An organic insulating film is suitable for the insulating layer 264 that functions as a planarizing layer. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins.

[0390] It is preferable to provide a light-shielding layer 417 on the surface of substrate 454 facing substrate 453. Various optical members can be arranged on the outside of substrate 454. Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. The outside of substrate 454 may also be arranged with an antistatic film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, an impact absorbing layer, or the like.

[0391] 26A, the common electrode 413 and the wiring are electrically connected to each other at the connection portion 278. In FIG. 26A, an example is shown in which the same laminated structure as that of the pixel electrode is applied to the wiring.

[0392] The substrate 453 and the substrate 454 can each be made of glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. When a flexible material is used for the substrate 453 and the substrate 454, the flexibility of the display device can be increased. Alternatively, a polarizing plate may be used for the substrate 453 or the substrate 454.

[0393] The substrates 453 and 454 may each be made of a polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), a polyacrylonitrile resin, an acrylic resin, a polyimide resin, a polymethyl methacrylate resin, a polycarbonate (PC) resin, a polyethersulfone (PES) resin, a polyamide resin (nylon, aramid, etc.), a polysiloxane resin, a cycloolefin resin, a polystyrene resin, a polyamideimide resin, a polyurethane resin, a polyvinyl chloride resin, a polyvinylidene chloride resin, a polypropylene resin, a polytetrafluoroethylene (PTFE) resin, an ABS resin, or a cellulose nanofiber. One or both of the substrates 453 and 454 may be made of glass having a thickness sufficient to provide flexibility.

[0394] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. A substrate with high optical isotropy has small birefringence (or a small amount of birefringence).

[0395] The absolute value of the retardation (phase difference) of a substrate having high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0396] Examples of films with high optical isotropy include triacetyl cellulose (TAC, also called cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0397] Furthermore, when a film is used as a substrate, the film may absorb water, causing deformation such as wrinkles in the display panel. Therefore, it is preferable to use a film with low water absorption for the substrate. For example, it is preferable to use a film with a water absorption rate of 1% or less, more preferably 0.1% or less, and even more preferably 0.01% or less.

[0398] The adhesive layer can be made of various curable adhesives, such as photocurable adhesives (e.g., ultraviolet curable), reactive curable adhesives, thermosetting adhesives, and anaerobic adhesives. Examples of such adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. Materials with low moisture permeability, such as epoxy resin, are particularly preferred. Two-component resins may also be used. Adhesive sheets, etc., may also be used.

[0399] The connection layer 292 may be made of an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0400] Materials that can be used for the gate, source, and drain of a transistor, as well as conductive layers such as various wirings and electrodes that constitute a display device, include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, and alloys containing these metals as main components, etc. Films containing these materials can be used as a single layer or a stacked layer structure.

[0401] Examples of light-transmitting conductive materials include conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide containing gallium, or graphene. Alternatively, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, or alloy materials containing such metal materials, can be used. Alternatively, nitrides of such metal materials (e.g., titanium nitride) can be used. When using metal materials or alloy materials (or their nitrides), it is preferable to thin them sufficiently to ensure light-transmitting properties. A stacked film of the above materials can also be used as the conductive layer. For example, a stacked film of an alloy of silver and magnesium and indium tin oxide is preferable because it can increase conductivity. These can also be used for conductive layers such as various wirings and electrodes constituting a display device, and for conductive layers (conductive layers functioning as pixel electrodes or common electrodes) of light-emitting elements.

[0402] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0403] The structures shown in this embodiment mode can be combined as appropriate. For example, structures shown in different drawings can be combined as appropriate.

[0404] This embodiment mode can be appropriately combined with other embodiment modes shown in this specification and the like.

[0405] Embodiment 2 In this embodiment, a metal oxide that can be used for the OS transistor described in the above embodiment will be described.

[0406] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. In addition to these, it is preferable that it contains aluminum, gallium, yttrium, tin, etc. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc.

[0407] <Classification of Crystal Structures> First, classification of crystal structures in oxide semiconductors will be described with reference to Fig. 27A. Fig. 27A is a diagram illustrating classification of crystal structures of oxide semiconductors, typically IGZO (metal oxide containing In, Ga, and Zn).

[0408] As shown in FIG. 27A , oxide semiconductors are broadly classified into "amorphous," "crystalline," and "crystal." Furthermore, "amorphous" includes completely amorphous. Furthermore, "crystalline" includes CAAC, nc (nanocrystalline), and CAC. The "crystalline" classification excludes single crystal, poly crystal, and completely amorphous (excluding single crystal and poly crystal). Furthermore, "Crystal" includes single crystal and poly crystal.

[0409] The structure within the bold frame shown in Figure 27A is an intermediate state between "Amorphous" and "Crystal" and belongs to a new boundary region (New crystalline phase). In other words, this structure can be said to be a structure that is completely different from the energetically unstable "Amorphous" and "Crystal."

[0410] The crystalline structure of a film or substrate can be evaluated using an X-ray diffraction (XRD) spectrum. Here, XRD spectra obtained by GIXD (Grazing-Incident XRD) measurement of a quartz glass substrate and an IGZO (also called crystalline IGZO) film having a crystal structure classified as "crystalline" are shown in FIGS. 27B and 27C, respectively. The GIXD method is also called the thin film method or the Seemann-Bohlin method. Hereinafter, the XRD spectra obtained by GIXD measurement shown in FIGS. 27B and 27C will be simply referred to as XRD spectra. In FIGS. 27B and 27C, the vertical axis represents X-ray intensity, and the horizontal axis represents the diffraction angle (2θ) of the X-rays. Fig. 27B shows the XRD spectrum of the quartz glass substrate, and Fig. 27C shows the XRD spectrum of the crystalline IGZO film. The composition of the crystalline IGZO film shown in Fig. 27C is approximately In:Ga:Zn = 4:2:3 [atomic ratio]. The thickness of the crystalline IGZO film shown in Fig. 27C is 500 nm.

[0411] As shown by the arrows in FIG. 27B, the peak shape of the XRD spectrum is nearly symmetrical for a quartz glass substrate. On the other hand, as shown by the arrows in FIG. 27C, the peak shape of the XRD spectrum for a crystalline IGZO film is asymmetrical. The asymmetrical peak shape of the XRD spectrum clearly indicates the presence of crystals in the film or substrate. In other words, if the peak shape of the XRD spectrum is not symmetrical, it cannot be said that the film or substrate is in an amorphous state. Note that FIG. 27C clearly shows the crystalline phase (IGZO crystal phase) at or near 2θ = 31°. It is presumed that the asymmetric peak shape in the XRD spectrum is due to the diffraction peak of the crystalline phase (microcrystals).

[0412] Specifically, it is presumed that interference of X-rays scattered by atoms contained in IGZO contributes to the peak at or near 2θ=34°. It is also presumed that minute crystals contribute to the peak at or near 2θ=31°. In the XRD spectrum of the crystalline IGZO film shown in FIG. 27C, the peak width on the low-angle side is broadened at or near 2θ=34°. This suggests that minute crystals resulting from the peak at or near 2θ=31° are present in the crystalline IGZO film.

[0413] The crystalline structure of the film or substrate can be evaluated by a diffraction pattern (also referred to as a nanobeam electron diffraction pattern) observed by nanobeam electron diffraction (NBED). The diffraction patterns of a quartz glass substrate and an IGZO film formed at room temperature are shown in FIGS. 27D and 27E, respectively. FIG. 27D shows the diffraction pattern of the quartz glass substrate, and FIG. 27E shows the diffraction pattern of the IGZO film. The IGZO film shown in FIG. 27E is formed by sputtering using an oxide target with an In:Ga:Zn=1:1:1 [atomic ratio]. In nanobeam electron diffraction, electron diffraction is performed with a probe diameter of 1 nm.

[0414] As shown in Figure 27D, a halo is observed in the diffraction pattern of the quartz glass substrate, confirming that the quartz glass is in an amorphous state. Furthermore, as shown in Figure 27E, a spot-like pattern is observed in the diffraction pattern of the IGZO film formed at room temperature, rather than a halo. Therefore, it is estimated that the IGZO film formed at room temperature is in an intermediate state, neither crystalline nor amorphous, and cannot be concluded to be in an amorphous state.

[0415] <<Structure of Oxide Semiconductor>> Note that oxide semiconductors may be classified differently from those shown in FIG. 27A when focusing on their crystal structures. For example, oxide semiconductors are classified into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-described CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, pseudo-amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0416] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0417] [CAAC-OS] A CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction refers to the thickness direction of the CAAC-OS film, the normal direction to the surface where the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region having periodic atomic arrangement. If the atomic arrangement is considered as a lattice arrangement, a crystalline region is also a region with a uniform lattice arrangement. Furthermore, a CAAC-OS has a region where multiple crystalline regions are connected in the a-b plane direction, and the region may have distortion. Note that distortion refers to a portion where the lattice arrangement changes between a region with a uniform lattice arrangement and a region with another uniform lattice arrangement in a region where multiple crystalline regions are connected. In other words, a CAAC-OS is an oxide semiconductor whose c-axes are aligned and whose orientation is not clearly aligned in the a-b plane direction.

[0418] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nanometers.

[0419] In an In-M-Zn oxide (wherein the element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, and the like), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing the element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and the element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. The In layer may contain the element M. The In layer may contain Zn. The layered structure is observed as a lattice image in a high-resolution TEM image, for example.

[0420] When a CAAC-OS film is subjected to structural analysis using an XRD apparatus, for example, a peak indicating c-axis orientation is detected at or near 2θ = 31° in out-of-plane XRD measurement using θ / 2θ scanning. Note that the position of the peak indicating c-axis orientation (the value of 2θ) may vary depending on the type, composition, and the like of the metal elements constituting the CAAC-OS.

[0421] For example, multiple bright spots are observed in the electron diffraction pattern of a CAAC-OS film, and the observed spots are at positions that are point-symmetric with respect to a spot of an incident electron beam that has passed through the sample (also referred to as a direct spot).

[0422] When a crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be a non-regular hexagon. The distortion may have a pentagonal, heptagonal, or other lattice arrangement. In the CAAC-OS, no clear grain boundary can be identified even near the distortion. This indicates that the distortion in the lattice arrangement suppresses the formation of grain boundaries. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of a dense arrangement of oxygen atoms in the a-b plane direction or the change in interatomic bond distance caused by metal atom substitution.

[0423] Note that a crystal structure in which clear grain boundaries are observed is called polycrystalline. The grain boundaries act as recombination centers, and are likely to trap carriers, resulting in a decrease in the on-state current of a transistor and a decrease in field-effect mobility. Therefore, CAAC-OS, in which clear grain boundaries are not observed, is one of the crystalline oxides having a crystal structure suitable for a semiconductor layer of a transistor. Note that a structure containing Zn is preferable for forming a CAAC-OS. For example, In—Zn oxide and In—Ga—Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0424] CAAC-OS is an oxide semiconductor with high crystallinity and no clear crystal grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to crystal grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by the inclusion of impurities, the formation of defects, or the like, the CAAC-OS can also be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, an oxide semiconductor having a CAAC-OS has stable physical properties. Therefore, an oxide semiconductor having a CAAC-OS is heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even against high temperatures (so-called thermal budget) in the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0425] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, in the nc-OS, no regularity is observed in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analysis method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peak indicating crystallinity is detected in out-of-plane XRD measurement using θ / 2θ scanning. When an nc-OS film is subjected to electron diffraction (also referred to as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of a nanocrystal (e.g., 50 nm or more), a diffraction pattern resembling a halo pattern is observed. On the other hand, when an nc-OS film is subjected to electron diffraction (also referred to as nanobeam electron diffraction) using an electron beam with a probe diameter close to or smaller than that of a nanocrystal (e.g., 1 nm to 30 nm), an electron diffraction pattern in which multiple spots are observed within a ring-shaped region centered on a direct spot may be obtained.

[0426] [a-Like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and an amorphous oxide semiconductor. The a-like OS has pores or low-density regions. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0427] <<Structure of Oxide Semiconductor>> Next, the above-described CAC-OS will be described in detail. Note that the CAC-OS relates to a material structure.

[0428] [CAC-OS] CAC-OS is, for example, a material in which elements constituting a metal oxide are unevenly distributed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that hereinafter, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed in a size of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0429] Furthermore, the CAC-OS has a mosaic structure in which a material is separated into a first region and a second region, and the first region is distributed throughout the film (hereinafter also referred to as a cloud structure). That is, the CAC-OS is a composite metal oxide having a structure in which the first region and the second region are mixed.

[0430] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In—Ga—Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In—Ga—Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0431] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0432] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0433] Furthermore, CAC-OS in In—Ga—Zn oxide refers to a structure in which a mosaic of regions containing Ga as the main component and regions containing In as the main component are randomly arranged in a material composition containing In, Ga, Zn, and O. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed nonuniformly.

[0434] The CAC-OS can be formed by sputtering without heating the substrate. When the CAC-OS is formed by sputtering, one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition, the more preferable it is. For example, the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition is preferably 0% or more and less than 30%, and more preferably 0% or more and 10% or less.

[0435] Furthermore, for example, in the case of CAC-OS in an In—Ga—Zn oxide, EDX mapping obtained using energy dispersive X-ray spectroscopy (EDX) can confirm that the CAC-OS has a structure in which a region containing In as a main component (first region) and a region containing Ga as a main component (second region) are unevenly distributed and mixed.

[0436] Here, the first region has higher conductivity than the second region. That is, the flow of carriers through the first region causes the metal oxide to exhibit conductivity. Therefore, the first region is distributed in a cloud-like manner in the metal oxide, thereby achieving high field-effect mobility (μ).

[0437] On the other hand, the second region has higher insulating properties than the first region. That is, the second region is distributed in the metal oxide, thereby suppressing leakage current.

[0438] Therefore, when a CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (a function of turning on / off). That is, a CAC-OS has a conductive function in a part of the material and an insulating function in a part of the material, and the entire material functions as a semiconductor. By separating the conductive function and the insulating function, both functions can be maximized. Therefore, by using a CAC-OS in a transistor, a high on-current (I ｏｎ ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0439] Furthermore, a transistor using the CAC-OS has high reliability, and therefore, the CAC-OS is suitable for use in various semiconductor devices such as displays.

[0440] Oxide semiconductors have a variety of structures, each of which has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0441] <Transistor Having Oxide Semiconductor> Next, a case where the oxide semiconductor is used for a transistor will be described.

[0442] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0443] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 １７ cm −３ Below 1 × 10, preferably １５ cm −３ More preferably, 1×10 １３ cm −３ or less, more preferably 1 × 10 １１ cm −３More preferably, 1×10 １０ cm −３ is less than 1×10 −９ cm −３ The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0444] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0445] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to disappear and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0446] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0447] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0448] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are less than 2×10 １８ atoms / cm ３ Below 2 × 10, preferably１７ atoms / cm ３ The following applies.

[0449] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect levels are formed and carriers are generated in some cases. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 １８ atoms / cm ３ Below 2 × 10, preferably １６ atoms / cm ３ Do the following:

[0450] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 １９ atoms / cm ３ Less than 5×10 １８ atoms / cm ３ or less, more preferably 1 × 10 １８ atoms / cm ３ or less, more preferably 5 × 10 １７ atoms / cm ３ Do the following:

[0451] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, thereby forming an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. Therefore, it is preferable to reduce hydrogen in the oxide semiconductor as much as possible. Specifically, the hydrogen concentration in the oxide semiconductor measured by SIMS is 1×10 ２０ atoms / cm ３ less than 1×10 １９ atoms / cm ３ less than 5×10 １８ atoms / cm ３ less than 1×10 １８ atoms / cm ３ Make it less than.

[0452] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0453] This embodiment mode can be appropriately combined with other embodiment modes shown in this specification and the like.

[0454] Embodiment 3 In this embodiment, an electronic device including a semiconductor device according to one embodiment of the present invention will be described.

[0455] The semiconductor device of one embodiment of the present invention can be provided in various electronic devices. For example, the semiconductor device of one embodiment of the present invention can be provided in electronic devices with relatively large screens, such as television devices, desktop or notebook computers, tablet computers, computer monitors, digital signage, and large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, portable game machines, personal digital assistants, sound players, etc. Structural examples of electronic devices in which the semiconductor device of one embodiment of the present invention can be provided are described with reference to FIGS. 28A to 28D .

[0456] 28A is a diagram showing an example of a portable data terminal 9100. The portable data terminal 9100 includes a display unit 9110, a housing 9101, keys 9102, a speaker 9103, and the like. The portable data terminal 9100 may be, for example, a tablet. Here, keys such as the key 9102 may be keys for turning the power on and off, for example. That is, the keys such as the key 9102 may be, for example, power switches. Furthermore, the keys such as the key 9102 may be, for example, operation keys used to cause an electronic device to perform a desired operation.

[0457] The display portion 9110 can display information 9104, operation buttons (also referred to as operation icons or simply as icons) 9105, and the like.

[0458] By providing the semiconductor device of one embodiment of the present invention in the portable data terminal 9100, the portable data terminal 9100 can perform authentication such as fingerprint authentication with high accuracy in a short time.

[0459] 28B is a diagram illustrating an example of a digital signage 9200. The digital signage 9200 can have a configuration in which a display unit 9210 is attached to a pillar 9201.

[0460] By providing the semiconductor device of one embodiment of the present invention in the digital signage 9200, the digital signage 9200 can perform authentication such as fingerprint authentication with high accuracy in a short time.

[0461] FIG. 28C illustrates an example of a portable information terminal 9300. The portable information terminal 9300 includes a display unit 9310, a housing 9301, a speaker 9302, a camera 9303, keys 9304, a connection terminal 9305, a connection terminal 9306, and the like. The portable information terminal 9300 may be, for example, a smartphone. The speaker 9302 in FIG. 28C corresponds to the speaker 38 in the schematic diagram shown in FIG. 6 and the like of Embodiment 1. The camera 9303 in FIG. 28C corresponds to the camera 39 in the schematic diagram shown in FIG. 6 and the like of Embodiment 1. The display unit 9310 in FIG. 28C corresponds to the pixel unit 30 in the schematic diagram shown in FIG. 6 and the like of Embodiment 1. Therefore, in FIG. 28C , among the pixels arranged in m rows and n columns in the display unit 9310, the pixel in the row farthest from the speaker 9302 corresponds to the pixel in the first row, and the pixel in the closest row corresponds to the pixel in the m-th row. Similarly, among the pixels in m rows and n columns of the display portion 9310, the pixels in the row farthest from the camera 9303 correspond to the pixels in the first row, and the pixels in the row closest to the camera 9303 correspond to the pixels in the mth row. Note that the connection terminal 9305 can be, for example, a micro USB, lighting, or Type-C. The connection terminal 9306 can be, for example, an earphone jack.

[0462] The display portion 9310 can display, for example, operation buttons 9307. The display portion 9310 can also display information 9308. Examples of the information 9308 include an indication of an incoming email, SNS (social networking service), or phone call, a title of the email or SNS, a sender name of the email or SNS, a date and time, a remaining battery level, and an antenna reception strength.

[0463] By providing the semiconductor device of one embodiment of the present invention in the portable information terminal 9300, the portable information terminal 9300 can perform authentication such as fingerprint authentication in a short time with high accuracy.

[0464] 28D is a diagram showing an example of a wristwatch-type portable information terminal 9400. The portable information terminal 9400 includes a display portion 9410, a housing 9401, a wristband 9402, keys 9403, and a connection terminal 9404. Note that the connection terminal 9404 can be, for example, a micro USB, a lighting, or a Type-C, similar to the connection terminal 9305 in the portable information terminal 9300 shown in FIG.

[0465] Information 9406, operation buttons 9407, and the like can be displayed on the display portion 9410. In FIG. 28D, time is displayed on the display portion 9410 as the information 9406.

[0466] By providing the semiconductor device of one embodiment of the present invention in the portable information terminal 9400, the portable information terminal 9400 can perform authentication such as fingerprint authentication in a short time with high accuracy.

[0467] This embodiment mode can be appropriately combined with other embodiment modes shown in this specification and the like.

[0468] 10: semiconductor device, 11: substrate, 12: substrate, 13: light-emitting device, 15: imaging device, 23: light, 25: light, 27: finger, 29: fingerprint, 30: pixel unit, 30R: pixel unit, 30U: pixel unit, 31: pixel, 32: control circuit, 33: row driver circuit, 34: CDS circuit, 36: readout circuit, 37: detection circuit, 38: speaker, 39: camera, 41: wiring, 43: wiring, 44: wiring, 45: wiring, 46: wiring, 47: wiring, 48: wiring, 49: wiring, 50: light-receiving element, 51: transistor, 52: transistor, 53: transistor, 54: transistor , 56: capacitor, 57: capacitor, 60: circuit, 70: finger, 71: fingerprint, 81: pixel, 82: pixel, 82E: light source, 83: gate driver circuit, 84: pixel portion, 86: data driver circuit, 252: transistor, 254: connection portion, 258: transistor, 259: transistor, 260: transistor, 261: insulating layer, 262: insulating layer, 264: insulating layer, 265: insulating layer, 268: insulating layer, 271: conductive layer, 272a: conductive layer, 272b: conductive layer, 273: conductive layer, 275: insulating layer, 278: connection portion, 281i: channel formation region, 281n : low resistance region, 281: semiconductor layer, 292: connection layer, 411a: conductive layer, 411b: conductive layer, 411c: conductive layer, 412G: EL layer, 412S: photoelectric conversion layer, 413: common electrode, 414: organic layer, 416: protective layer, 417: light-shielding layer, 421: insulating layer, 422: resin layer, 430b: light-emitting element, 440: light-receiving element, 442: adhesive layer, 451: substrate, 452: substrate, 453: substrate, 454: substrate, 455: adhesive layer, 462: display unit, 464: circuit, 465: wiring, 466: conductive layer, 472: FPC, 473: IC, 9100: portable data terminal, 91 01: Housing, 9102: Keys, 9103: Speaker, 9104: Information, 9110: Display unit, 9200: Digital signage, 9201: Pillar, 9210: Display unit, 9300: Mobile information terminal, 9301: Housing, 9302: Speaker, 9303: Camera, 9304: Keys, 9305: Connection terminal, 9306: Connection terminal, 9307: Operation buttons, 9308: Information, 9310: Display unit, 9400: Mobile information terminal, 9401: Housing, 9402: Wristband, 9403: Keys, 9404: Connection terminal, 9406: Information, 9407: Operation buttons, 9410: Display unit

Claims

1. A semiconductor device having a light-emitting device and an imaging device, The imaging device includes a pixel portion in which pixels of m rows and n columns (m and n are integers of 1 or more) are arranged in a matrix, and a load driver circuit having a shift register circuit, The imaging device has a function of detecting that the detection target is on the pixels of the p-th to q-th rows (p and q are integers of 1 or more and m or less, and p is smaller than q) in the pixel portion by detecting the light emitted by the light-emitting device and reflected by the detection target, and a function of acquiring and reading out an image of the detection target in at least the pixels of the 1st to q-th rows in the pixel portion. The shift register circuit has a plurality of register circuits, At least one of the plurality of register circuits has a first transistor to a tenth transistor, One of the source or drain of the first transistor is electrically connected to a first wiring, The other of the source or drain of the first transistor is electrically connected to a second wiring, One of the source or drain of the second transistor is electrically connected to a third wiring, The other of the source or drain of the second transistor is electrically connected to the first wiring, One of the source or drain of the third transistor is electrically connected to the gate of the first transistor, The other of the source or drain of the third transistor is electrically connected to a fourth wiring, The gate of the third transistor is electrically connected to a fifth wiring, One of the source or drain of the fourth transistor is electrically connected to a sixth wiring, The other of the source or drain of the fourth transistor is electrically connected to the fifth wiring, The gate of the fourth transistor is electrically connected to a seventh wiring, One of the source or drain of the fifth transistor is electrically connected to the sixth wiring. The other of the source or drain of the fifth transistor is electrically connected to the fifth wiring. The gate of the fifth transistor is electrically connected to the eighth wiring. One of the source or drain of the sixth transistor is electrically connected to the sixth wiring. The other of the source or drain of the sixth transistor is electrically connected to one of the source or drain of the seventh transistor. The gate of the sixth transistor is electrically connected to the ninth wiring. The other of the source or drain of the seventh transistor is electrically connected to the fifth wiring. The gate of the seventh transistor is electrically connected to the tenth wiring. One of the source or drain of the eighth transistor is electrically connected to the fourth wiring. The other of the source or drain of the eighth transistor is electrically connected to the fifth wiring. The gate of the eighth transistor is electrically connected to the eleventh wiring. One of the source or drain of the ninth transistor is electrically connected to the third wiring. The other of the source or drain of the ninth transistor is electrically connected to the sixth wiring. The gate of the ninth transistor is electrically connected to the eleventh wiring. One of the source or drain of the tenth transistor is electrically connected to the third wiring. The other of the source or drain of the tenth transistor is electrically connected to the fourth wiring. The gate of the tenth transistor is electrically connected to the sixth wiring. Semiconductor device.

2. In claim 1, Each of the first transistor to the tenth transistor has a metal oxide in a channel formation region. Semiconductor device.

3. In claim 2, The metal oxide has indium or zinc. Semiconductor device.

4. A semiconductor device having a light emitting device and an imaging device, The imaging device includes a pixel portion in which pixels of m rows and n columns (m and n are integers of 1 or more) are arranged in a matrix, and a load driver circuit having a shift register circuit. The imaging device detects light emitted by the light emitting device and reflected by a detection object, and thereby detects that the detection object is on the pixels of the p-th to q-th rows (p and q are integers of 1 or more and m or less, and p is smaller than q) in the pixel portion. A function of skipping an imaging operation of the detection object in the pixels of the first to p-1 rows in the pixel portion, a function of acquiring and reading an image of the detection object in the pixels of the p-th to q-th rows in the pixel portion, and a function of skipping an imaging operation of the detection object in the pixels of the q + 1-th to m-th rows in the pixel portion. The shift register circuit has a plurality of register circuits. At least one of the plurality of register circuits has a first transistor to a tenth transistor. One of the source or drain of the first transistor is electrically connected to a first wiring. The other of the source or drain of the first transistor is electrically connected to a second wiring. One of the source or drain of the second transistor is electrically connected to a third wiring. The other of the source or drain of the second transistor is electrically connected to the first wiring. One of the source or drain of the third transistor is electrically connected to the gate of the first transistor. The other of the source or drain of the third transistor is electrically connected to a fourth wiring. The gate of the third transistor is electrically connected to a fifth wiring. One of the source or drain of the fourth transistor is electrically connected to a sixth wiring. The other of the source or drain of the fourth transistor is electrically connected to the fifth wiring. The gate of the fourth transistor is electrically connected to a seventh wiring. One of the source or drain of the fifth transistor is electrically connected to the sixth wiring. The other of the source or drain of the fifth transistor is electrically connected to the fifth wiring. The gate of the fifth transistor is electrically connected to an eighth wiring. One of the source or drain of the sixth transistor is electrically connected to the sixth wiring. The other of the source or drain of the sixth transistor is electrically connected to one of the source or drain of the seventh transistor. The gate of the sixth transistor is electrically connected to a ninth wiring. The other of the source or drain of the seventh transistor is electrically connected to the fifth wiring. The gate of the seventh transistor is electrically connected to a tenth wiring. One of the source or drain of the eighth transistor is electrically connected to the fourth wiring. The other of the source or drain of the eighth transistor is electrically connected to the fifth wiring. The gate of the eighth transistor is electrically connected to an eleventh wiring. One of the source or drain of the ninth transistor is electrically connected to the third wiring. The other of the source or drain of the ninth transistor is electrically connected to the sixth wiring. The gate of the ninth transistor is electrically connected to the eleventh wiring. One of the source or drain of the tenth transistor is electrically connected to the third wiring. The other of the source or drain of the tenth transistor is electrically connected to the fourth wiring. The gate of the tenth transistor is electrically connected to the sixth wiring. Semiconductor device.

5. In claim 4, Each of the first transistor to the tenth transistor has a metal oxide in a channel formation region. Semiconductor device.

6. In claim 5, The metal oxide contains indium or zinc. Semiconductor device.