Information processing device and information processing method

Abstract

An information processing device (1) comprises an acquisition unit (11) that acquires a netlist of an electric circuit and a processing unit (12) that: extracts a part name list and a connection name list from the netlist; creates a part name list updated by adding part names indicating a ground terminal, an input terminal, and an output terminal, a connection name list updated by removing connection names indicating a ground connection, an input connection, and an output connection, and a combined list that includes part names extracted from part names in the updated part name list and corresponding to connection names in the updated connection name list; and outputs the updated part name list and the combined list.

Description

Information processing device and information processing method

[0001] The present disclosure relates to an information processing device and an information processing method.

[0002] Circuit diagram data showing an electric circuit designed using CAD (Computer-Aided Design) is data that includes component information about the components and connection information about the wiring between the components. For example, Patent Document 1 describes a technology that uses a circuit matrix that represents an electric circuit as a matrix to search for circuit diagram data of an electric circuit with a similar configuration from a database in which circuit diagram data is registered.

[0003] Japanese Patent Application Laid-Open No. 2007-128383

[0004] A graph network, which represents an electric circuit with nodes and edges, is created using list information extracted from the netlist of the electric circuit. The list information is information about the components and wiring included in the electric circuit, and includes a component name list and a wiring name list. The component name list contains the names of the components included in the electric circuit. The wiring name list contains the names of the wiring connecting the components.

[0005] The wiring names set in the wiring name list include ground wiring, input wiring, and output wiring in an electric circuit. On the other hand, the component name list sets only the component names of circuit components with structural features, and does not include elements indicating ground, input, or output, which do not have structural features. For this reason, conventional list information requires that various types of ground, multiple inputs, and multiple outputs be defined by wiring.

[0006] On the other hand, with conventional list information, if a circuit has its own ground or its own inputs and outputs, it is impossible to distinguish the ground or inputs and outputs as different circuit information unless a special mechanism is provided for each circuit. For example, the inputs of a circuit component include the power supply to the circuit component as well as the input of an external signal. As such, the inputs of circuit components are diverse, and defining them only by the wiring name can lead to confusion between them. For this reason, after converting an electrical circuit into a graph network, it is difficult to separate the two using the graph network alone.

[0007] To separate the two, it is necessary to decide on the number of components or the order of their listing in the graph network, and this can only be used when the number of input terminals is predetermined. If a graph network is created without the above agreement and using list information in which the ground, input, and output definitions of circuit components are inappropriate, information degradation may occur in the graph network. If information degradation occurs, it may be impossible to restore the original circuit diagram from the graph network.

[0008] However, in the conventional technology described in Patent Document 1, if a circuit matrix is ​​created using list information in which the ground, input, and output definitions are inappropriate, it is expected that the information in the circuit matrix will be degraded as described above. In this case, even if the circuit matrix is ​​used, it may not be possible to accurately search for circuit diagram data of similar electrical circuits.

[0009] The present disclosure aims to solve the above-mentioned problem, and aims to provide an information processing device and an information processing method that can provide list information that can suppress information degradation that occurs when converting an electrical circuit into a graph network.

[0010] The information processing device according to the present disclosure includes an acquisition unit that acquires a netlist of an electric circuit, and a processing unit that extracts a component name list and a wiring name list from the netlist, updates the component name list by adding component names indicating ground terminals, input terminals, and output terminals, updates the wiring name list by removing wiring names indicating ground wiring, input wiring, and output wiring, extracts component names corresponding to wiring names in the updated wiring name list from the component names in the updated component name list, creates a combination list including the extracted component names, and outputs the updated component name list and combination list.

[0011] According to the present disclosure, a component name list and a wiring name list are extracted from a netlist of an electric circuit, and the component name list is updated by adding component names indicating ground terminals, input terminals, and output terminals, and the wiring name list is updated by removing wiring names indicating ground wiring, input wiring, and output wiring, and component names corresponding to the wiring names in the updated wiring name list are extracted from the component names in the updated component name list, a combination list including the extracted component names is created, and the updated component name list and combination list are output. In this way, an information processing device according to the present disclosure outputs list information in which the ground, input, and output in an electric circuit are defined as circuit components, and therefore it is possible to provide list information that can suppress information degradation that occurs when the electric circuit is converted into a graph network.

[0012] 4A and 4B are block diagrams showing a hardware configuration for realizing the functions of the information processing device according to the first embodiment. FIG. 4A is a circuit diagram showing an example (1) of an electric circuit and a graph network according to the first embodiment. FIG. 4B is a circuit diagram showing an example (2) of an electric circuit and a graph network according to the first embodiment. FIG. 4B is a block diagram showing a hardware configuration for realizing the functions of the information processing device according to the first embodiment. FIG. 4B is a flowchart showing an information processing method according to the first embodiment. FIG. 4A is a circuit diagram showing an example (1) of an electric circuit. FIG. 4B is a circuit diagram showing an example (2) of an electric circuit. FIG. 4B is a circuit diagram showing an example (3) of an electric circuit. FIG. 4B is a schematic diagram showing a graph network in which nodes are connected by edges. FIG. 4B is a schematic diagram showing a graph network in which nodes are connected via wiring nodes. FIG. 4B is a flowchart showing a data input process (1) to a graph network according to the first embodiment. FIG. 4C is a flowchart showing a data input process (2) to a graph network according to the first embodiment. FIG. 4D is a graph showing an example (1) of a calculation result of inference accuracy by the information processing device according to the first embodiment. FIG. 4D is a graph showing an example (2) of a calculation result of inference accuracy by the information processing device according to the first embodiment. FIG. 4C is a block diagram showing a configuration example of an information processing device according to the second embodiment. FIG. 4D is a flowchart showing an information processing method according to the second embodiment. 1 is a circuit diagram showing an example (4) of an electric circuit; FIG. 2 is a circuit diagram showing an example (5) of an electric circuit; FIG. 3 is a schematic diagram showing an example (1) of an electric circuit and a graph network in embodiment 2; FIG. 4 is a schematic diagram showing an example (2) of an electric circuit and a graph network in embodiment 2; FIG. 5 is a schematic diagram showing an example (3) of an electric circuit and a graph network in embodiment 2; and FIG. 6 is a graph showing an example of a calculation result of inference accuracy by an information processing device according to embodiment 2.

[0013] First Embodiment. Fig. 1 is a block diagram showing an example configuration of an information processing device 1 according to a first embodiment. In Fig. 1, the information processing device 1 acquires a netlist of an electric circuit and uses the acquired netlist to provide list information capable of suppressing information degradation in a graph network of the electric circuit. The graph network of an electric circuit is information that represents the electric circuit using nodes representing components and edges representing wiring. The graph network also includes information indicating the feature amounts of the nodes and the feature amounts of the edges.

[0014] In creating an electric circuit, a circuit diagram of the electric circuit is designed using a circuit design CAD, information representing the circuit diagram is transferred to a board design CAD, and a board circuit pattern is designed using the board design CAD. The information representing the circuit diagram transferred from the circuit design CAD to the board design CAD is a netlist of the electric circuit. For example, the information processing device 1 acquires a netlist from the circuit design CAD and outputs a netlist including list information created using the acquired netlist to a computer equipped with the board design CAD. The computer uses the board design CAD to design a board circuit pattern for the circuit diagram represented by the input netlist.

[0015] The circuit diagram represented by the netlist includes information indicating the passive components, active components, I / O components, and wiring in the electrical circuit. Passive components are, for example, coils, capacitors, resistors, or diodes. Active components are, for example, power supplies, processors, memories, or FPGAs (Field Programmable Gate Arrays). I / O components include, for example, board-to-board connectors, power connectors, and communication connectors. Wiring is used to connect the above components.

[0016] A circuit diagram shows an electrical circuit that operates by receiving an external power supply, a control signal such as Ethernet (registered trademark), or an analog signal obtained from a sensor. Therefore, the power supply itself is not included in the circuit diagram. The power supply can be a battery or a commercial power source. Hereinafter, in circuit diagrams, at least the ground wiring, input wiring, and output wiring are assumed to be connected to one or more circuit components. Furthermore, the circuit diagram shown in the netlist does not necessarily have to be operational; it can be a design in progress, or it can be an extracted circuit portion that realizes a partial function of the entire circuit.

[0017] Dozens of different representation methods for netlists are known, such as the TELESIS format, the PADS format, and the SCICARDS format. All of these formats include information indicating the components included in an electrical circuit and the wiring connecting the components. Circuit diagrams generally include ground wiring, input wiring, and output wiring. However, circuit diagrams that handle electromagnetic waves or heat that are input or output without wiring may not have input or output wiring. In addition, when electromagnetic waves or heat are converted into electrical signals and the electrical signals are converted into electromagnetic waves or heat, the circuit diagram includes input wiring through which the electrical signals converted from the electromagnetic waves or heat propagate, and output signals through which the electrical signals converted into electromagnetic waves or heat propagate. Netlists also include information about such wiring.

[0018] The netlist also includes a component name list and a wiring name list. The component name list contains the names of all components in the netlist. The wiring name list contains the names of all wiring in the netlist. The wiring name list also contains names of wiring indicating ground wiring, input wiring, and output wiring in an electric circuit, but the component name list does not contain information indicating ground, input, or output, and only contains circuit components with structural characteristics such as semiconductor elements (hereinafter simply referred to as semiconductors) or capacitors. Therefore, even if an electric circuit has multiple types of grounds, inputs, and outputs, it is not possible to distinguish between them from the component name list.

[0019] In this case, the wiring name list must further classify and define the ground wiring, input wiring, and output wiring according to the type of ground, input, and output. For example, if a component has multiple types of ground, input, and output, multiple types of wiring classified according to the type of ground, input, and output must also be defined between this component and the components connected to it, which makes the wiring name list complex. If an electrical circuit is converted into a graph network using list information including a complex wiring name list, there is a high possibility that information degradation will occur in the graph network.

[0020] In response to this, the information processing device 1 adds component names indicating ground terminals, input terminals, and output terminals to the component name list, and removes wiring names indicating ground wiring, input wiring, and output wiring from the wiring name list. The information processing device 1 then extracts component names corresponding to wiring names in the wiring name list from the component names in the component name list, creates a combination list including the extracted component names, and outputs list information including the component name list and the combination list. This allows the information processing device 1 to define multiple types of grounds, inputs, and outputs in an electrical circuit as individual components. Therefore, the list information does not become complicated as would occur if multiple types of wiring were defined, and it is possible to provide list information that can suppress information degradation in the graph network of the electrical circuit.

[0021] As shown in FIG. 1 , the information processing device 1 includes an acquisition unit 11 and a processing unit 12. The acquisition unit 11 executes a first process of acquiring a netlist of an electric circuit. For example, the information processing device 1 is connected to a computer equipped with a circuit design CAD, and the acquisition unit 11 acquires a netlist created using the circuit design CAD from the computer. The acquisition unit 11 may also acquire a circuit diagram model of the electric circuit that operates on a circuit simulator and convert the circuit diagram represented by this circuit diagram model into a netlist. In other words, acquiring a netlist by the acquisition unit 11 also includes converting a circuit diagram to acquire a netlist.

[0022] The processing unit 12 extracts a component name list and a wiring name list from the netlist, creates an updated component name list by adding component names indicating ground terminals, input terminals, and output terminals, an updated wiring name list by removing wiring names indicating ground wiring, input wiring, and output wiring, and extracts component names corresponding to wiring names in the updated wiring name list from the component names in the updated component name list, and creates a combination list including the extracted component names, and outputs the updated component name list and combination list.The processing unit 12 also outputs an updated component name list and combination list in which component names have been replaced with unique identification numbers common to each component feature.

[0023] Specifically, the processing unit 12 executes the second to sixth processes. The second process is a process of extracting a component name list and a wiring name list from the netlist acquired by the acquisition unit 11. The third process is a process of adding component names indicating ground terminals, input terminals, and output terminals to the component name list. The fourth process is a process of removing wiring names indicating ground wiring, input wiring, and output wiring from the wiring name list. The fifth process is a process of extracting component names corresponding to wiring names in the wiring name list obtained by the fourth process from component names in the component name list obtained by the third process, and creating a combination list including the extracted component names. The sixth process is a process of replacing component names in the component name list obtained by the third process with component names in the combination list obtained by the fifth process by unique identification numbers common to each component feature, and outputting list information including the component name list and the combination list in which the component names have been replaced with the identification numbers.

[0024] Figure 2 is a schematic diagram showing an example (1) of an electric circuit and a graph network, where the diagram on the left side of Figure 2 shows an example of an electric circuit, and the diagrams on the top and bottom right side show the graph network of the electric circuit on the left. The electric circuit shown in Figure 2 is a circuit having a power supply V, a semiconductor X, an inductor L, a capacitor C, and a resistor R. In this electric circuit, the power supply V, one terminal of the semiconductor X, the capacitor C, and the resistor R are connected to ground GND.

[0025] A circuit diagram of an electric circuit that operates using power supplied (input) from a power source V does not include the power source V itself. Therefore, the netlist representing the circuit diagram does not include input terminals to which power is supplied from the power source as circuit components. Furthermore, the component name list included in this netlist includes electric circuit components that have functional structures, such as a semiconductor X, an inductor L, a capacitor C, and a resistor R, but does not include power inputs or grounds GND that do not have functional structures.

[0026] If a component name list for which power supply input and ground GND are not set is used, the graph network shown in the lower right corner is created. The graph network in the lower right corner has a node for semiconductor X, a node for inductor L, a node for capacitor C, and a node for resistor R, but does not have a node for power supply input from power supply V or a node for ground GND. In the graph network in the lower right corner, the power supply input from power supply V and ground GND are defined as wiring.

[0027] For example, in the electric circuit on the left, power is supplied (input) from a power source V to one terminal of a semiconductor X. Therefore, in the graph network on the lower right, the thick wire connected to the node of the semiconductor X is an input wire related to the power input from the power source V. Also, in the electric circuit on the left, the semiconductor X, the capacitor C, and the resistor R are each connected to ground GND.

[0028] For example, as shown by the white lines, ground GND is defined as the ground wiring between semiconductor X and capacitor C, the ground wiring between semiconductor X and resistor R, and the ground wiring between capacitor C and resistor R. In other words, if the power supply input and ground GND are not set in the component name list, four types of wiring indicating the power supply input from power supply V and ground GND are defined in the netlist.

[0029] If a netlist of an electrical circuit is converted into a graph network and then the converted graph network is converted back into a netlist, and the original electrical circuit can be identified using the converted netlist, it is determined that there is no information degradation in the graph network. Generally, there is no reversibility between the conversion from a netlist to a graph network and the reverse conversion from the graph network to a netlist, and the netlist after the reverse conversion may not be a netlist that can be calculated by a circuit simulator.

[0030] For this reason, the determination of information degradation of a graph network is performed by inputting the graph network into a graph neural network and training the graph neural network to infer the original electrical circuit, without performing a reverse conversion from the graph network to a netlist. Determining information degradation using a graph neural network has the advantage of avoiding the above-mentioned problem because it does not involve a process of reverse conversion from the graph network to a netlist. However, graph neural networks can suffer from the problem of variability in inference results. In this case, by training a graph neural network with a common network structure multiple times and checking the variability in inference results by the trained graph neural network, the impact of variability in inference results can be minimized. In this way, determining information degradation using a graph neural network is an excellent determination method that obtains more stable results than performing a reverse conversion from a graph network to a netlist. Here, the graph neural network is a machine learning model (AI) that, when a graph network is input, infers an electrical circuit corresponding to the graph network. If the graph neural network has high accuracy in inferring the original electrical circuit, it is determined that there will be little information degradation when the netlist of this electrical circuit is converted into a graph network.

[0031] When an electric circuit has multiple types of grounds, inputs, and outputs, the graph network converted from the netlist of this electric circuit has the wiring indicating the grounds, inputs, and outputs classified and defined according to the type of ground, input, and output. These wirings are defined under complex conditions including information indicating the classified type as well as relationships with connected components. For this reason, the graph neural network must learn by taking into account the complex conditions for each wiring, which reduces the accuracy of the graph neural network's inference of the original electric circuit.

[0032] In response to this, the information processing device 1 adds component names indicating the ground terminal, input terminal, and output terminal to the component name list included in the netlist of the electric circuit on the left, and removes the wiring names indicating the ground wiring, input wiring, and output wiring from the wiring name list included in the netlist.The information processing device 1 then extracts component names corresponding to wiring names in the wiring name list from the component names in the component name list, creates a combination list including the extracted component names, and outputs the component name list and the combination list.

[0033] In the component name list and combination list, the power supply input of the power supply V and the ground GND in the electric circuit on the left are set as components. Therefore, the netlist including the component name list and combination list is converted into the graph network on the right. In the graph network on the right, in addition to a node for the semiconductor X, a node for the inductor L, a node for the capacitor C, and a node for the resistor R, a node for the power supply input from the power supply V and a node for the ground GND are set.

[0034] Because the power supply input from the power supply V and the ground GND are defined as components, in the graph network on the right, the wiring related to the power supply input from the power supply V to the semiconductor X does not need to be classified as an input wiring type, and is defined as a connection between nodes. There is also no need to classify the ground wiring type for the ground GND, and it is defined as a connection between nodes. In other words, in the graph network on the right, all wiring in the original electric circuit is defined as a single type of wiring that connects nodes.

[0035] Therefore, the multiple types of grounds GND, inputs, and outputs of the electric circuit are distinguished as components, which means that the graph neural network can learn the grounds GND, inputs, and outputs of the electric circuit as components, improving the accuracy with which the graph neural network infers the original electric circuit.

[0036] Figure 3 is a schematic diagram showing an example (2) of an electric circuit and graph network, where the left diagram in Figure 3 shows an example of an electric circuit, and the top and bottom diagrams on the right show the graph network of the left electric circuit. The electric circuit shown in Figure 3 is a circuit having a power supply V, a semiconductor X, an inductor L, a capacitor C, and a resistor R. When using a component name list in which a ground GND is not set in the electric circuit on the left, the electric circuit is converted into the graph network shown on the bottom right.

[0037] The graph network on the lower right shows a power supply input node from the power supply V, a node for the semiconductor X, a node for the inductor L, a node for the capacitor C, and a node for the resistor R. The ground GND is defined as the ground wiring set between the nodes, as shown by the white lines. Generally, many components included in an electrical circuit are connected to the ground GND, so depending on the circuit size, it may be necessary to define a huge number of ground wirings for the ground GND. The output node is the voltage across the resistor R. For ease of explanation, the circuit diagram shown in Figure 3 shows the power supply V, which serves as the input node, and the resistor R, which represents the load on the output node. However, in typical circuit diagrams used in electrical design, the power supply V or resistor R are not shown and are represented as open ends.

[0038] In the graph network on the lower right, six ground wires are set for the ground GND, but five more wires are set to connect nodes other than the ground GND, meaning that a total of 11 wires must be defined in the netlist.

[0039] In response, the information processing device 1 provides list information in which ground GND is set as a component. This list information can be converted into a graph network on the right. As shown in FIG. 3 , the graph network on the right includes a power supply input node from power supply V, a node for semiconductor X, a node for inductor L, a node for capacitor C, and a node for resistor R, as well as a node for ground GND. Semiconductors include not only single-function semiconductors such as transistors, diodes, MOS FETs (Metal-Oxide-Semiconductor Field-Effect Transistors), or IGBTs (Insulated Gate Bipolar Transistors), but also large-scale integrated circuits such as ICs or LSIs, for example, CPUs, GPUs, memories, or ASICs. In the first embodiment, large-scale integrated circuits whose internal circuit elements are unknown (black boxes) can be defined as nodes, so all semiconductors can be treated in the same way. Even when the internal circuit elements are known, circuits that handle high-frequency signals or signals in frequency bands other than those targeted by the semiconductor often have discrepancies between circuit calculation results and actual measurements due to influences such as parasitic capacitance, residual inductance, and residual resistance, i.e., do not form equivalent circuits. For this reason, even if the internal circuit elements can be identified, it is often useless. Therefore, this embodiment, which allows the circuit elements to be treated as a black box, has a special effect. However, even when the internal circuit elements of an integrated circuit are unknown, attribute information possessed by the integrated circuit itself, such as a CPU or memory, can often be grasped. Therefore, it is desirable to input the attribute information possessed by the integrated circuit as attribute information for the semiconductor node. Note that attribute information is a combination of various information contained in specifications (also called spec sheets), such as the manufacturer, component type, component model number, production lot, number of component terminals, input signal frequency, input signal voltage, input signal current, input signal power, output signal frequency, output signal voltage, output signal current, output signal power, or dimensions from the component.

[0040] By defining ground GND as a component, it is only necessary to set nine wires connecting each of the nine nodes in the graph network on the upper right. Therefore, only a total of nine wires need to be defined in the netlist, which makes it possible to reduce the number of wires that need to be defined in the netlist compared to when ground GND is not defined as a component. Reducing the number of wires reduces the amount of calculation, making it possible to handle large-scale circuits even with computers that do not have high computational performance or edge computing.

[0041] Next, a hardware configuration for realizing the functions of the information processing device 1 will be described. The information processing device 1 is, for example, a computer connected to an information network. The computer may be a server or client that can connect to the cloud or the like via the information network, or a standalone computer that is not connected to an information network. It may also be a computer used in a closed network environment within a factory, known as edge computing. The information processing device 1 may also be a smartphone, a tablet terminal, a PC (Personal Computer), or a microcomputer.

[0042] The information processing device 1 may be a device that uses an information processing service provided in the form of SaaS (Software as a Service). That is, a dedicated application for providing the information processing service in the first embodiment is executed by a server to which the information processing device 1 is connected via an information network, and the information processing device 1 can receive the information processing service on a web browser without installing the dedicated application.

[0043] The functions of the acquisition unit 11 and the processing unit 12 included in the information processing device 1 are realized by a processing circuit. That is, the information processing device 1 includes a processing circuit for executing the processes of steps ST1 to ST9 shown in Fig. 5, which will be described later. The processing circuit may be dedicated hardware, or may be a CPU (Central Processing Unit) that executes a program stored in a memory.

[0044] FIG. 4A is a block diagram showing a hardware configuration that realizes the functions of the information processing device 1. In FIG. 4A, the input interface 100, the output interface 101, and the processing circuit 102 are interconnected via a bus. FIG. 4B is a block diagram showing a hardware configuration that executes software that realizes the functions of the information processing device 1. In FIG. 4B, the input interface 100, the output interface 101, the processor 103, and the memory 104 are interconnected via a bus. In FIGS. 4A and 4B, the input interface 100 is an interface that relays, for example, a netlist acquired by the information processing device 1. The output interface 101 is an interface that relays list information output from the information processing device 1 to an external device.

[0045] 4A, the processing circuit 102 may be, for example, a single circuit, a composite circuit, a programmed processor, a parallel programmed processor, an ASIC (Application Specific Integrated Circuit), an FPGA (Field-Programmable Gate Array), or a combination thereof. The functions of the acquisition unit 11 and the processing unit 12 included in the information processing device 1 may be realized by separate processing circuits, or these functions may be realized together by a single processing circuit.

[0046] 4B , the functions of the acquisition unit 11 and the processing unit 12 included in the information processing device 1 are realized by software, firmware, or a combination of software and firmware. The software or firmware is written as a program and stored in the memory 104.

[0047] The processor 103 reads and executes programs stored in the memory 104 to realize the functions of the acquisition unit 11 and the processing unit 12 included in the information processing device 1. For example, the information processing device 1 includes the memory 104 for storing programs that, when executed by the processor 103, result in the processing of steps ST1 to ST9 shown in FIG. 5 being executed. These programs cause a computer to execute the procedures or methods of the processing performed by the acquisition unit 11 and the processing unit 12. The memory 104 may be a computer-readable storage medium that stores programs for causing a computer to function as the acquisition unit 11 and the processing unit 12.

[0048] The memory 104 may be, for example, a non-volatile or volatile semiconductor memory such as a RAM (Random Access Memory), a ROM (Read Only Memory), a flash memory, an EPROM (Erasable Programmable Read Only Memory), or an EEPROM (Electrically-EPROM), a magnetic disk, a flexible disk, an optical disk, a compact disk, a mini disk, or a DVD.

[0049] Some of the functions of the acquisition unit 11 and processing unit 12 included in the information processing device 1 may be realized by dedicated hardware, and some may be realized by software or firmware. For example, the functions of the acquisition unit 11 may be realized by a processing circuit 102 that is dedicated hardware, and the functions of the processing unit 12 may be realized by the processor 103 reading and executing a program stored in memory 104. In this way, the processing circuit can realize the above functions by hardware, software, firmware, or a combination of these.

[0050] The program executed by the processor 103 may be received from a system (comport) such as the World Wide Web (WWW) that connects multiple pieces of hardware via wired and / or wireless connections. Furthermore, when the information processing device 1 performs learning of a graph neural network (described later), parameters obtained by learning, particularly a weight matrix in the case of a neural network, may be transmitted and received in the system.

[0051] The information processing device 1 may function as a learning device that performs machine learning. Note that the learning device may be a device that has general-purpose hardware that excels in parallel operations, such as a GPU (Graphics Processing Unit), in addition to a CPU. The information processing device 1 may also be configured with multiple computers connected via communication ports.

[0052] In the following description, the information processing device 1 is assumed to perform both learning and inference, but learning and inference may be performed by separate devices that operate independently of each other. In this case, one of these devices may be the information processing device 1, or both may be the information processing device 1. Furthermore, the information processing device 1 may be a device that provides multiple virtual hardware environments within a single piece of hardware, and each virtual hardware is virtually treated as a separate piece of hardware.

[0053] Next, the operation of the information processing device 1 according to the first embodiment will be described. FIG. 5 is a flowchart showing an information processing method according to the first embodiment, illustrating a series of operations performed by the information processing device 1. First, the acquisition unit 11 acquires a netlist (step ST1). For example, the acquisition unit 11 reads a circuit diagram model from the memory 104 shown in FIG. 4B and converts the circuit diagram represented by the circuit diagram model into a netlist. Some netlist notation formats include listing component names followed by wiring names. Examples of such formats include Telesis, PADS, Allegro, Express PCB, Intergraph, and Scicards.

[0054] In addition, there are netlist notation formats in which the wiring names are written first, followed by the component names. Examples include Calay, Mentor, and Vectoron. Furthermore, there are netlist notation formats in which the component names and wiring names are written simultaneously. Examples include ComputerVision, Algorex, and Multiwire.

[0055] In both notation methods, ground, input, and output are defined as wires. The netlist below is a Telesis representation of the netlist for the electrical circuit that operates the switching power supply: $PACKAGES lt3489! LT3489; U1 ind! 2.2u; L1 schottky! 1N5818; D1 cap! 20u; C1 res! 28.7K; R1 res! 5.23K; R2 cap! . 001u; C2 $NETS N002; U1.1 U1.7 N003; U1.2 R1.2 R2.1 IN; U1.3 U1.6 L1.1 0; U1.4 C1.2 R2.2 C2.2 N001; U1.5 L1.2 D1.1 N004; U1.8 C2.1 OUT; D1.2 C1.1 R1.1 $END

[0056] The processing unit 12 extracts a component name list from the netlist (step ST2-1) and extracts a wiring name list from the netlist (step ST2-2). For example, the processing unit 12 stores all component names included in the netlist in the component name list, and stores all wiring names included in the netlist in the wiring name list. Note that the processing of step ST2-1 and the processing of step ST2-2 may be performed either first or simultaneously.

[0057] The component name list stores components with structural characteristics, such as semiconductors or capacitors, and does not include ground terminals, input terminals, or output terminals. On the other hand, the wiring name list includes ground wiring, input wiring, and output wiring, which are part of the wiring. The processing unit 12 adds the ground wiring, input wiring, and output wiring included in the netlist to the component name list as ground terminals, input terminals, and output terminals (step ST3-1). The processing unit 12 removes the ground wiring, input wiring, and output wiring from the wiring name list (step ST3-2). This leaves information indicating the ground terminals, input terminals, and output terminals as component information in the component name list, thereby suppressing information degradation when converting an electrical circuit into a graph network using list information including the component name list. Note that the processing of step ST3-1 and the processing of step ST3-2 may be performed first, or may be performed simultaneously.

[0058] In the above netlist, the lines following "$PACKAGES" represent component names, and the lines following "$NETS" represent wiring names. The component names "U1, L1, D1, C1, R1, R2, C2" extracted from this netlist constitute the component name list. The wiring names "N002, N003, IN, 0, N001, N004, OUT" extracted from the netlist constitute the wiring name list. Input wiring is defined as "IN," and output wiring is defined as "OUT." While some netlists do not define names for inputs and outputs, all netlists include wiring corresponding to the inputs and outputs of electrical circuits. "0" is the wiring name indicating ground wiring, which is always present, for example, on a board on which a semiconductor is mounted. In this case, N001, N002, N003, and N004 are wiring names mechanically assigned by the CAD system to wiring that the designer did not intentionally assign wiring names to.

[0059] The processing unit 12 adds ground (GND), input (IN), and output (OUT) to the component name list. For example, the component name list to which ground (GND), input (IN), and output (OUT) have been added is "U1, L1, D1, C1, R1, R2, C2, GND, IN, OUT." Unlike circuit components, ground (GND), input (IN), and output (OUT) do not have structural characteristics and are therefore not set in the component name list. However, the processing unit 12 processes ground (GND), input (IN), and output (OUT) as circuit components.

[0060] In a netlist, there does not need to be one ground (GND), input (IN), and output (OUT) and there can be multiple grounds. For example, grounds can be divided into system ground and frame ground, and depending on the electrical circuit, the two can be connected by a capacitor, resistor, inductor, etc. These grounds can be defined as different grounds.

[0061] An electric circuit has multiple types of input terminals, such as a power supply terminal connected to a commercial power source or a battery, an input terminal for an external signal, etc. Also, an electric circuit has multiple output terminals, such as an output terminal for outputting a signal connected to a rotating machine such as a motor, and an output terminal for outputting a signal indicating the rotation speed of the rotating machine.

[0062] The processing unit 12 removes the ground wire (0), input wire (IN), and output wire (OUT) from the wire name list. The wire name list becomes "N002, N003, N001, N004." This defines the ground, input, and output as components rather than wires, thereby reducing information degradation when converting from an electrical circuit to a graph network.

[0063] For example, if the same electrical circuit is represented using "PADS," another netlist notation format, it will look like this, and in this case too, a component name list and a wiring name list can be created. Note that no matter which netlist notation format is used, an electrical circuit cannot be formed without components and wiring, so a component name list and a wiring name list can always be created. *PART* U1 LT3489 L1 2.2u D1 1N5818 C1 20u R1 28.7K R2 5.23K C2 . 001u *NET* *SIGNAL*N002 U1.1 U1.7 *SIGNAL*N003 U1.2 R1.2 R2.1 *SIGNAL*IN U1.3 U1.6 L1.1 *SIGNAL*0 U1.4 C1.2 R2.2 C2.2 *SIGNAL*N001 U1.5 L1.2 D1.1 *SIGNAL*N004 U1.8 C2.1 *SIGNAL*OUT D1.2 C1.1 R1.1 *END*

[0064] Next, the processing unit 12 extracts, from the component names in the component name list, component names corresponding to the wiring names in the wiring name list, and creates a combination list including the extracted component names (step ST4). For example, the processing unit 12 extracts, from the netlist, component names in the component name list that correspond to the wiring names in the wiring name list in the listed order, and creates a combination list including the extracted component names. Here, the processing unit 12 includes in the combination list the ground terminals, input terminals, and output terminals added to the component name list. Note that the "component names corresponding to the wiring names" are component names that indicate the components to which the wiring indicated by the wiring names is connected.

[0065] By including a ground terminal in the combination list, the amount of information in the combination list can be reduced. Generally, many components in an electric circuit are connected to ground GND. For example, if N components are connected to ground GND, the combination list will include N combinations of ground GND and components. If ground GND is not defined, it is necessary to create a number of combinations of ground GND and components proportional to the square of N.

[0066] Since an electric circuit cannot be established unless components are connected by wires, it is always possible to create a combination list for any electric circuit that functions normally. Figure 6 is a circuit diagram showing an example of an electric circuit (1). The netlist for the electric circuit shown in Figure 6 is as follows: # Components A B C D # Wiring (1); IN, A (2); A, B (3); B, C, D (4); D, OUT GND; A, B, C

[0067] The component name list extracted from the above netlist becomes "A, B, C, D, IN, OUT, GND" by adding "IN", "OUT", and "GND". The wiring name list becomes "(1), (2), (3), (4)" by removing "IN", "OUT", and "GND".

[0068] In netlists where wiring connected to ground terminals is not defined, wiring is provided between the ground and components, and names are assigned to the wiring. That is, from the "GND; A, B, C" in the netlist of the electric circuit shown in Figure 6, for example, ground is represented by "G," and the component names are connected to assign wiring names such as "G-A," "G-B," and "G-C." As a result, the wiring name list becomes "(1), (2), (3), (4), G-A, G-B, G-C."

[0069] The following combination list is obtained by extracting the component names corresponding to the wiring names in the wiring name list "(1), (2), (3), (4), G-A, G-B, G-C" from the netlist in the component name list "A, B, C, D, IN, OUT, GND" in order: (1): IN, A (2): A, B (3): B, C, D (4): D, OUT G-A: GND, A G-B: GND, B G-C: GND, C

[0070] Next, the processing unit 12 determines whether or not there are three or more component names corresponding to one wiring name among the component names in the combination list (step ST5). If it is determined that there are less than three component names corresponding to one wiring name in the combination list (step ST5; NO), the processing unit 12 replaces the component names in the combination list with identification numbers (step ST6).

[0071] On the other hand, if it is determined that the combination list contains three or more component names corresponding to one wiring name (step ST5; YES), the processing unit 12 breaks it down into combinations of two component names (step ST7). For example, if the component name held by a certain wiring name, i.e., the component name corresponding to one wiring name, is [capacitor, coil, resistor], the processing unit 12 breaks it down into three combinations: [capacitor, coil], [coil, resistor], and [resistor, capacitor]. Similarly, if the component name is [capacitor, coil, resistor, semiconductor], the processing unit 12 breaks it down into six combinations: [capacitor, coil], [capacitor, resistor], [capacitor, semiconductor], [coil, resistor], [coil, semiconductor], and [resistor, semiconductor].

[0072] The processing unit 12 adds the decomposition into pairs of part names to the combination list, and removes from the combination list any combinations that have three or more part names before the decomposition. However, this process is for creating an adjacency matrix in the graph network, and if an adjacency matrix can be created directly from the combination list, decomposition is not necessary.

[0073] For example, in the above netlist, since (3); B, C, D corresponds to a combination of three or more component names, the processing unit 12 breaks it down into (B, C), (C, D), and (D, B). As a result, the following combination list is obtained for the circuit diagram shown in Figure 6: (1); (IN, A) (2); (A, B) (3); (B, C), (C, D), (D, B) (4); (D, OUT) G-A; (GND, A) G-B; (GND, B) G-C; (GND, C)

[0074] 7 is a circuit diagram showing an example (2) of an electric circuit. The circuit diagram shown in FIG. 7 has the following netlist: #Components A C D E F #Wiring '; IN, A'; A, D'; C, D, E (4A); E, F (5A); F, OUT GND; A, C, E

[0075] The component name list included in the above netlist is "A, C, D, E, F, GND, IN, OUT," and the wiring name list is "(1A), (2A), (3A), (4A), (5A), G-A, G-C, G-E." The processing unit 12 extracts, from the netlist, component names corresponding to each wiring name in the wiring name list, to create the following combination list: (1A); IN, A (2A); A, D (3A); C, D, E (4A); E, F (5A); F, OUT G-A; GND, A G-C; GND, B G-E; GND, E

[0076] Next, if each combination list has three or more component names, the processing unit 12 breaks it down. For example, the processing unit 12 breaks down the combination "(3A); C, D, E" into combinations of two component names each, to create the following combination lists: (1A); (IN, A) (2A); (A, D) (3A); (C, D), (D, E), (E, C) (4A); (E, F) (5A); (F, OUT) G-A; (GND, A) G-C; (GND, B) G-E; (GND, E)

[0077] The above explanation has been based on the assumption that component names do not match unless they are identical components, but if the same component name is used for circuit components with different functions, the processing unit 12 changes the component name. Conversely, if different component names are used for the same circuit component, the processing unit 12 changes the component name. If there are a large number of component names and it is difficult to unify them, using the model numbers of each component manufacturer makes unification easier.

[0078] The processing unit 12 defines a unique identification number common to each type of part or each model number of each part indicated by each part name in the part name list (step ST8), and replaces each part number in the part name list with the identification number (step ST9). The processing unit 12 replaces each part name included in the part name list and the combination list with the identification number. The part name list and the combination list obtained in this way are output as list information.

[0079] By using list information including a component name list in which component names are replaced with identification numbers and a combination list, circuit information can be expressed numerically, and as described above, information degradation in the graph network is reduced, so the original electrical circuit can be created by using this graph network.

[0080] Furthermore, an identification number may be defined for each type of component, which is a characteristic of the component. The type of component can be expressed by information such as a capacitor, coil, power supply IC, or diode. The number of component types is generally less than 100, depending on how they are classified. Thus, the number of component types is relatively small. For example, the processing unit 12 uses a serial number set for each component type as an identification number to replace the component name.

[0081] Furthermore, identification numbers may be defined for each part model number. If the number of parts used in an electric circuit is limited, the number of identification numbers for each part model number will be relatively small. In this case, by using identification numbers defined by part model numbers, it is possible to prevent information degradation when converting list information into a graph network.

[0082] In step ST8, the processing unit 12 defines identification numbers by the following method and assigns the defined identification numbers to the component names. As described above, the component name list for the electric circuit shown in Figure 6 is "A, B, C, D, IN, OUT, GND," and the component name list for the electric circuit shown in Figure 7 is "A, C, D, E, F, GND, IN, OUT."

[0083] The processing unit 12 combines these component name lists to create a component name list of "A, A, B, C, C, D, D, E, F, GND, GND, IN, IN, OUT, OUT." This component name list contains multiple identical component names. The processing unit 12 removes duplicate component names to create a component name list of "A, B, C, D, E, F, GND, IN, OUT." Next, the processing unit 12 assigns identification numbers to each component in the component name list so that each component has a different identification number. If natural numbers are used as the identification numbers, the component name list in which the component names have been replaced with identification numbers will look like the following. Note that the identification numbers do not need to be consecutive numbers and may use letters or symbols. A → 1 B → 2 C → 3 D → 4 E → 5 F → 6 GND → 7 IN → 8 OUT → 9

[0084] The identification number for a component with the name "GND" can be "0," the identification number for a component with the name "IN" can be "1," and the identification number for a component with the name "OUT" can be "2," and the order can be changed as desired. The identification number can also be a number based on the circuit constant, model number, manufacturer, or voltage resistance of the component. For example, components with the same function, such as a power supply, memory, and CPU, are assigned the same identification number.

[0085] For example, when a switching power supply is divided into isolated power supplies and non-isolated power supplies, the same identification number is assigned to the isolated power supplies and the same identification number is assigned to the non-isolated power supplies. The same identification number may also be assigned to operations such as voltage step-up, voltage step-down, or step-up / down. Furthermore, identification numbers may be assigned according to the circuit constants of passive elements. For example, the same identification number may be assigned to a capacitor with a capacitance of 1.0 μF, and the same identification number may be assigned to capacitors with capacitances ranging from 1.0 μF to 3.3 μF. Furthermore, the definition of identification numbers may be changed according to user requirements. Furthermore, identification numbers may be assigned for each model number assigned to a component by a component manufacturer. The method of defining identification numbers may be changed according to the electrical circuit being handled.

[0086] For example, if the component names are replaced with identification numbers for each type of component (capacitor, coil, resistor, semiconductor, etc.), the component name list for the electrical circuit shown in Figure 6 would be "1, 2, 3, 4, 7, 8, 9," and the combination list would be "(8, 1), (1, 2), (2, 3), (3, 4), (4, 2), (4, 9), (7, 1), (7, 2), (7, 3)." Similarly, the component name list for the electrical circuit shown in Figure 7 would be "1, 3, 4, 5, 6, 7, 8, 9," and the combination list would be "(8, 1), (1, 4), (3, 4), (4, 5), (5, 3), (5, 6), (6, 9), (7, 1), (7, 2), (7, 5)."

[0087] By repeating the above-described series of processes, the processing unit 12 creates component name lists and combination lists for all circuit diagrams. Because the definition of the identification number is arbitrary, by determining an identification number according to the characteristics of the component of interest, the usage of the circuit can be changed according to the intended use of the circuit. For example, in a problem of predicting the type of component, the model number is redundant information to use as the identification number, while using the component manufacturer as the identification number may provide insufficient information and may result in an inaccurate prediction. Therefore, it is necessary to select an identification number according to the intended use. If the identification number is selected correctly, the amount of calculation required to predict the component type can be reduced and the prediction accuracy can be improved.

[0088] Furthermore, multiple identification numbers may be assigned to a single component name. For example, identification numbers may be assigned corresponding to the component model number, component type, and component circuit constants. In this case, for example, the component name list for the electrical circuit shown in Figure 7 would be "(1,3,0), (3,3,7), (4,5,3), (5,2,0), (6,8,1), (7,1,0), (8,1,0), (9,1,0)." The component types "IN," "OUT," and "GND" are all wiring, so the identification number is defined as "1." The identification number "1" assigned to a semiconductor, the identification number "5" assigned to another semiconductor, and the components indicated by the component names "IN," "OUT," and "GND" are input terminals, output terminals, and grounds, and have no circuit constants. In this case, for example, the identification number is defined as "0." For example, circuit constants may be set for semiconductors in consideration of their internal characteristics, or different identification numbers may be assigned to the types of components indicated by "IN," "OUT," and "GND." The method of assigning identification numbers may be arbitrary as long as it is based on a common rule between circuits.

[0089] The identification number can be a real number and does not necessarily have to be a natural number. The circuit constants of the component can be entered as the identification number. For example, the range of circuit constants used in a typical circuit is from a maximum of f (femto) to several hundred G (gigabits), approximately 10 to the 20th power. Therefore, if the circuit constants are used as identification numbers in their raw form, the larger numbers will dominate. Furthermore, small values ​​may be rounded or changed to different values ​​due to calculation errors. To avoid this, a function including logarithms can be used for the circuit constants. For example, the function f(x) = log10(x) + 15. In this case, +15 is -log10 (f = 1 femto). This allows f(x) to be converted to a real number greater than or equal to 0. To avoid the problem of 1f becoming 0 and making it impossible to determine which component is included, it is acceptable to use log10(x) + 16 or log10(x) + 15 + (a small amount greater than 0 but less than 1). For simplicity of explanation, the case where the logarithm has a base of 10 has been described, but it does not have to be 10.

[0090] There are many cases where component constants are sufficient with an accuracy of one digit or less, so in such cases, the identification numbers can be defined by rounding the values ​​as follows: 1f → 1, 10f → 2, 100f → 3, 1n → 4, 10n → 5, 100n → 6, 1u → 7, 10u → 8, 100u → 9, 1m → 10, 10m → 11, 100m → 12, 1 → 13, 10 → 14, 100 → 15, 1k → 16, 10k → 17, 100k → 18, 1M → 19, 10M → 20, 100M → 21, 1G → 22, 10G → 23, 100G → 24.

[0091] By using the above-described series of processes, a circuit diagram can be converted into a netlist, and the netlist can be converted into a component name list and a combination list. Using the component name list and the combination list, a graph network in graph theory can be created. The graph network can be used to search for similar circuits, which is difficult to do using a netlist.

[0092] For example, the processing unit 12 can search for a loop path consisting of a semiconductor, a capacitor, a coil, a ground, and another semiconductor by sequentially searching the adjacency matrix created using the combination list. In particular, in an electric circuit using a specific circuit component, the processing unit 12 sequentially searches for the identification numbers of each component that makes up the circuit.

[0093] For example, the processing unit 12 references a database containing the semiconductors that are noise sources and their terminal numbers, and performs a search process in which, starting from a terminal corresponding to the terminal number in the electrical circuit, the search continuously searches for adjacent components under the condition that the same component is not passed through more than twice, extracting a current loop representing the semiconductor and completing the search process. Specifically, the processing unit 12 uses the terminal of the semiconductor being searched as the starting point for the search, searches for one or more adjacent components from the starting point, and continuously searches for one or more circuit components adjacent to those components. However, the search is performed under the condition that components other than the semiconductor that was the starting point for the search are not passed through more than twice. This makes it possible to avoid searches that contradict physical phenomena, such as the current returning to its original state or stopping midway.

[0094] The processing unit 12 ends the search process when a current terminates at any terminal of the semiconductor that was the search starting point, excluding the terminal that was the search starting point. The path created by this search process is called the "current loop." In other words, the above process is equivalent to the process of extracting a current loop path in Kirchhoff's current law (Kirchhoff's First Law). The termination can be any terminal. For example, a ground terminal is the most common, but in a differential line, one of the differential signal terminals is the starting point and the opposite terminal is the end point. This makes it possible to, for example, extract noise filters based on an algorithm, or to estimate the impedance of a propagation path through which current can flow and predict which current loop is most likely to flow from a circuit. This allows the processing unit 12 to extract characteristics of the semiconductor being searched and characteristics of a current loop that indicate the semiconductor from one or more electrical circuits containing one or more semiconductors, and then use the extracted characteristics of the semiconductor and the current loop to search for semiconductors similar to the semiconductor being searched for.

[0095] The processing unit 12 may also determine whether a current loop contains a component that indicates a noise filter. As an example, a case will be described in which a path is detected that runs from a semiconductor's power input terminal through a ground-to-ground capacitor (Y capacitor) and ground, and then returns to the semiconductor's ground terminal. In this embodiment, the ground-to-ground capacitor and ground are defined as nodes in a graph network. Therefore, the path can be detected by determining whether or not there is a path from a starting node (semiconductor) through two nodes and then back to the same node. To achieve this detection, all current loops that pass through two nodes are extracted, and by extracting current loops in which one node is a capacitor and the other node is ground, current loops containing noise filters can be identified. Furthermore, a database containing model numbers of noise suppression components is created in advance in the information processing device 1. The processing unit 12 checks whether the extracted capacitor is included in the database, and if so, can determine that the current loop contains a noise filter. Furthermore, to limit nodes that could be noise sources and reduce the amount of calculations, a database containing model numbers of circuit components that could be noise sources is created in advance in the information processing device 1. The processing unit 12 can reduce the number of search targets by starting the search only from the applicable node. While the above explanation uses an example of a ground capacitor, similar extraction can be performed for T-type filters, π-type filters, etc. The presence or absence of connections between any components can also be confirmed in a similar manner. Furthermore, by using the attribute information of each node, it is possible to predict frequency characteristics or time waveforms such as impedance, current flow, or voltage drop between components. The processing unit 12 can extract similar circuits by creating a current loop for each semiconductor terminal and analyzing the circuit components through which the current loop passes. Through the above search process, the processing unit 12 can search for noise filter circuits or similar circuits regardless of the number of components or wiring, grounds, or input / output ports in the electrical circuit.This makes it possible to reduce search errors by searching for a path adjacent to a semiconductor, input connector, or output connector that is a noise source for which a noise filter is provided.

[0096] For semiconductors that are noise sources, the part model numbers can be extracted as text data from the netlist. Also, in circuit diagrams, inputs and outputs are often written as input and output symbols, but they may also be written as input connectors and output connectors with the connector model numbers attached. For this reason, by preparing the database described above in which semiconductors that are noise sources, noise suppression components, and input or output connectors are registered, and then referencing this database to extract only the text data, it is possible to prevent overlooking search results.

[0097] In addition to searching for noise sources or noise filters, by giving nodes and edges resistance components or delay components, the processing unit 12 can calculate the impedance between two components and estimate the path through which the most current will flow or the path through which the pulse signal will arrive earliest.

[0098] When an electric circuit has multiple components connected in parallel to a single wiring, the processing described above results in an increase in the number of component combinations in the combination list. Fig. 8 is a circuit diagram showing an example (3) of an electric circuit. The electric circuit shown in Fig. 8 is a circuit in which a single wiring Line 1 is connected between an input terminal IN and an output terminal OUT, and a capacitor C1, a capacitor C2, and a resistor R are connected in parallel to this wiring Line 1. The information processing device 1, which treats the ground, input, and output as components, creates list information that converts the electric circuit into a graph network shown in Fig. 9 below.

[0099] FIG. 9 is a schematic diagram showing a graph network in which nodes are connected by edges. The graph network shown in FIG. 9 represents the components in the electric circuit shown in FIG. 8 as nodes, and these components are connected by edges. The information processing device 1 creates list information that treats ground, input, and output as components. Therefore, the list information created by the information processing device 1 is converted into a graph network in which, for example, semiconductor X, capacitor C1, capacitor C2, resistor R, and output terminal OUT are each represented as nodes, and all of these nodes are connected by edges. For simplicity of explanation, the node representing the input terminal IN and the node representing the ground are omitted in FIG. 9 . Note that this graph network has the feature that component names are nodes, and the node adjacent to any node is a node with the component name.

[0100] When an electrical circuit has multiple components connected in parallel to a single wiring, the number of corresponding component combinations in the combination list increases approximately in proportion to the square of the number of components connected in parallel to the wiring. In Figure 9, three components (capacitor C1, capacitor C2, and resistor R) are connected in parallel to a single wiring, Line 1, resulting in nine combinations, which is the square of three. For example, some large-scale circuits have ten or more bypass capacitors connected in parallel to a single wiring. In such circuits, the number of combinations increases significantly. As a result, the amount of calculation required to search for current loops increases exponentially, and the search time also increases.

[0101] In the graph network shown in Figure 9, when searching for all current loops starting from a specific component name node, it is possible to comprehensively search for nodes so as to satisfy the condition that a node that has been passed through once is not passed through twice. However, when component name nodes are adjacent, as described above, it is necessary to include a number of components proportional to approximately the square of the number of components connected in parallel to a single wiring. For example, as shown in Figure 9, if there are three components connected in parallel, it is difficult to calculate a path that passes through nodes corresponding to the component names of the three components and returns to the node with the same component name as the starting point.

[0102] Therefore, the information processing device 1 may create a combination list including wiring names and component names so as to suppress an increase in the number of combinations of component names for a large-scale circuit in which multiple components are connected in parallel to a single wiring, as described above. For example, the processing unit 12 extracts a component name list and a wiring name list from the netlist of the above-mentioned electric circuit, updates the component name list by adding component names indicating ground terminals, input terminals, and output terminals, updates the wiring name list by removing wiring names indicating ground wiring, input wiring, and output wiring, extracts component names corresponding to the wiring names in the updated wiring name list from the component names in the updated component name list, and creates a combination list including the extracted component names and the corresponding wiring names, and outputs the updated component name list and combination list.

[0103] 10 is a schematic diagram showing a graph network in which nodes are connected via wiring nodes. As shown in FIG. 10, the processing unit 12 extracts, as a combination list, combinations of each wiring name and a component name corresponding to a component connected by a wiring indicated by each wiring name in the wiring name list. The graph network converted from this list information has a feature in which component names and wiring names are represented by nodes, and a node adjacent to a node with any component name becomes a node with the wiring name. This makes it possible to make the number of combinations proportional to the first power of the number of components.

[0104] In the graph network shown in Figure 10, when searching for all current loops starting from a specific component name node, it is possible to comprehensively search for nodes so as to satisfy the condition that a node that has been passed through once is not passed through twice. Meanwhile, in this graph network, the component name node and the wiring name node are adjacent, and instead of a node consisting of three circuit components (capacitor C1, capacitor C2, and resistor R), a path returning to the starting point via four wiring name nodes and three component name nodes is searched for. However, because the wiring connected to each node is linearly proportional, the amount of calculation required for the search does not increase exponentially.

[0105] As an example of an experiment, when a current loop search was performed on a large-scale circuit with over 1,000 components in the same computer environment, it took 10 minutes when component name nodes were adjacent in the graph network, but when the component name nodes and wiring name nodes were adjacent, the search was completed in less than one second. This example shows that a particularly significant effect can be obtained in current loop search.

[0106] However, compared to when component name nodes are adjacent, when component name nodes and wire name nodes are adjacent is advantageous when there are many components connected in parallel to a single wire, but because the number of wire name nodes increases, it becomes disadvantageous when there are only a few components connected in parallel. Therefore, it is desirable to use the two methods depending on the size of the circuit or the number of components connected in parallel to a single wire. For example, when searching for current loops in a circuit with approximately 100 components, it is often better to use a graph network with adjacent component name nodes. Note that, regardless of whether wire name nodes are included or not, both of the above methods obtain the same loop path but with opposite directions. Therefore, in post-processing, it is possible to keep only one path and remove the other. However, if the current direction is known and the graph is directed, only one path is extracted, so the above post-processing is not necessary.

[0107] The processing unit 12 may replace elements corresponding to passive circuits in the feature matrix with function values ​​calculated by substituting the circuit constants of the components into a function including a logarithm. For components having circuit constants, the circuit constants can be converted into a graph network by changing elements corresponding to passive circuits in the feature matrix with function values ​​obtained by applying a function including a logarithm to the circuit constants. Components having circuit constants are resistors, capacitors, or coils, but may also be small-signal circuits such as operational amplifiers. Components other than resistors, capacitors, and coils may also be considered circuit components having circuit constants as long as they can be converted into components consisting of resistors, capacitors, and coils under certain conditions.

[0108] Furthermore, components with physical dimensions have parasitic components such as stray capacitance, residual inductance, or residual resistance. Therefore, the processing unit 12 decomposes a component with parasitic components into components that contain only two or more resistors, capacitors, or coils. Decomposition can be achieved by predicting an equivalent circuit from impedance measurements and determining the circuit constants of the equivalent circuit. This allows even circuits with complex component characteristics to be represented using a graph network. The circuit constants of components with only one characteristic are assigned to the component name in the component name list. Since circuit constants often have a range of 20 or more digits, from 1 pF to 1 G (except in special cases), the circuit constants may be logarithmically scaled. By applying a logarithm to the circuit constants, it is possible to prevent a capacitor with a capacitance of 1 pF, for example, from being overlooked due to calculation errors.

[0109] The processing unit 12 may normalize and / or standardize the function values. For example, normalization may be performed on the results of applying a logarithm to the circuit constants. When a graph network is input to a graph neural network, the activation function in the graph neural network responds to real numbers between 0 and 1. By normalizing the results of applying a logarithm to the circuit constants and performing a bijection on real numbers between 0 and 1, or between 0 and 1, the results of applying a logarithm to the circuit constants can be associated with a real-number activation function.

[0110] The results of applying a logarithm to the circuit constants may be standardized. For example, if the distribution of the results of applying a logarithm to the circuit constants of capacitors used in an electrical circuit contains many capacitors of 100 μF or less, even one capacitor of 100 F may result in a variance in the distribution of the results of applying a logarithm to the circuit constants, resulting in an underestimation of the differences in the results of applying a logarithm to the circuit constants for each capacitor. Therefore, standardization of the results of applying a logarithm to the circuit constants can reduce the variance in the distribution. Furthermore, because the ranges of circuit constants vary for each type of circuit component, different normalization or standardization may be performed for each type of circuit component. For example, a 100 F capacitor is considered large among capacitors, while a 100 Ω resistor is considered small among resistors, resulting in a larger range. Therefore, for example, adjusting the distribution so that 1 μF is the center for capacitors and 100 Ω is the center for resistors reduces rounding errors and improves the accuracy of the estimates of the results of applying a logarithm to the circuit constants.

[0111] Furthermore, the processing unit 12 may perform normalization after normalization of the results of applying logarithms to the circuit constants, or may perform normalization after normalization. By combining normalization and standardization in this way, the effects of both can be obtained.

[0112] Circuit components that do not have circuit constants are not considered information when they are assigned the same numerical value, such as "0" or "1," as an identification number. For this reason, the feature list created with additional information can be expressed as a matrix. For example, capacitors or coils can be classified by their circuit constants, and because they have two terminals, there is no information degradation when converting from a graph network to an electrical circuit. On the other hand, if a single electrical circuit contains two or more semiconductors, and two or more semiconductors have the same model number, information degradation occurs when converting from a graph network to an electrical circuit. For this reason, additional information indicating that the semiconductors are different components can be added to the component name list for the semiconductors.

[0113] For example, a real number greater than 0 and equal to or less than 1 is divided by the number of semiconductors, and a different real number is assigned to each semiconductor as additional information. If there are two semiconductors with the same model number in an electrical circuit, one semiconductor is assigned a different real number, such as 0.3, and the other semiconductor is assigned a different real number, such as 0.6. Also, if all that is known is that the components in an electrical circuit are semiconductors, and the electrical circuit is a circuit made up of 10 semiconductors, then additional information may be assigned values ​​from 0.1 to 1.0 in increments of 0.1. Note that the additional information only needs to have different numerical values, and real numbers may be assigned in any order.

[0114] If identification numbers are not used, the processing unit 12 may output the part name list and combination list as list information without replacing the part names with identification numbers.

[0115] Variation 1. In the information processing device 1 according to Variation 1, the processing unit 12 uses a graph network to train a graph neural network, with the component name list as the nodes in the graph network, the wiring name list as the edges in the graph network, and the combination list as the adjacency matrix in the graph network. The training of the graph neural network is unsupervised when the training data set contains only nodes and edges. On the other hand, when correct answer data is obtained through circuit simulation or experimentation, the processing unit 12 trains the graph neural network using the nodes, edges, and correct answer data as the training data set. The processing unit 12 also trains the graph neural network using edge attribute information (edge ​​attribute), such as edge frequency characteristics. Furthermore, the processing unit 12 trains the graph neural network using the component characteristics of each circuit constant or each semiconductor as node attribute information (node ​​attribute).

[0116] 11 is a flowchart showing an example (1) of data input processing into a graph network in the first embodiment. Assuming that the number of electric circuits is n, n netlists, the same number as the number of electric circuits, can be created. Therefore, the processing unit 12 sets the n netlists to be processed (step ST1A). The processing unit 12 also sets "1" as a parameter i (step ST2A).

[0117] The processing unit 12 sets the value of the parameter i in the function g[i]=[[node], [edge]] (step ST3A). The processing unit 12 extracts a component name list and a wiring name list from the i-th netlist acquired by the acquisition unit 11.

[0118] The processing unit 12 reads the component name list extracted from the i-th netlist as nodes of the graph network and the wiring name list as edges of the graph network (step ST4A). The processing unit 12 stores the nodes and edges related to the i-th netlist as one data set, associates them with the function g[i], and stores them in a storage area such as the memory 104 (step ST5A).

[0119] The processing unit 12 determines whether the parameter i is equal to or less than n (step ST6A). If the parameter i is equal to or less than n (step ST6A; YES), the processing unit 12 adds "1" to the parameter i (step ST7A) and returns to the processing of step ST4A. On the other hand, if the processing unit 12 determines that the parameter i is greater than n (step ST6A; NO), the processing unit 12 outputs the data sets associated with g[1] to g[n] (step ST8A).

[0120] The nodes are a matrix of (number of components in each circuit + ground terminal + input terminal + output terminal) x (number of features of the node). For example, in the electrical circuit shown in Figure 6, the nodes are a 7 x 1 matrix. Note that up to this point, electrical circuits with one input terminal and one output terminal have been shown, but it is sufficient if there is one or more terminals, in which case the columns of the matrix will be larger.

[0121] The number of node features may also be input as one-hot. In this case, if the number of node features is M (for example, M = 4 for the component types such as a capacitor, a coil, a first semiconductor, and a second semiconductor, as in the electrical circuit shown in FIG. 6 ), the nodes will be a 7 × M matrix. The edges will be a 2 × (number of edges) matrix. Here, the "2" multiplied by the (number of edges) represents any two components in the component name list, and the edges represent a matrix indicating the number of connections between these two components. Note that a directed graph may also be used if the direction of current flow is known. In a directed graph, if the order of component current flow in the combination list is expressed as (1, 2), for example, this means, by definition, from 1 to 2 or from 2 to 1. Bidirectional edges may exist, as in an undirected graph. In this case, simply add (2, 1) to (1, 2). Considering bidirectional edges, if an undirected graph is a 2×(number of edges) matrix, then a directed graph will be a maximum 4×(number of edges) matrix.

[0122] In the case of the electrical circuit shown in Figure 6, the combination list contains nine combinations: (8,1), (1,2), (2,3), (3,4), (4,2), (4,9), (7,1), (7,2), and (7,3), so the nodes are a 2x9 matrix. The elements of this matrix are the identification numbers contained in the component name list that form the nodes. This means that components included in one circuit do not form edges with components included in other circuits.

[0123] In a graph neural network, individual circuits can be processed sequentially, but parallelization is possible using dedicated hardware such as a GPU. In particular, when the number of circuits becomes large, exceeding several thousand, it is more desirable in terms of computation speed and efficiency to process them all at once rather than calculating each circuit sequentially. Therefore, all or all combinations of nodes and edges that can be stored in memory at once are input together. In this example, unsupervised learning is performed because there is no correct answer data.

[0124] 12 is a flowchart showing an example (2) of data input processing to a graph network in the first embodiment. Assuming that the number of electric circuits is n, n netlists, the same as the number of electric circuits, can be created. Therefore, the processing unit 12 sets the n netlists to be processed (step ST1B). The processing unit 12 sets "1" as the parameter i (step ST2B).

[0125] The processing unit 12 sets the value of the parameter i to the function g[i] = [[node], [edge], [correct data]] (step ST3B). The processing unit 12 extracts a component name list and a wiring name list from the i-th netlist acquired by the acquisition unit 11, and acquires the correct data calculated in advance.

[0126] The processing unit 12 reads the component name list extracted from the i-th netlist as nodes of the graph network, reads the wiring name list as edges of the graph network, and further reads the correct answer data (step ST4B). The processing unit 12 stores the nodes, edges, and correct answer data related to the i-th netlist as a single data set, associates it with the function g[i], and stores it in a storage area such as the memory 104 (step ST5B).

[0127] The processing unit 12 determines whether the parameter i is equal to or less than n (step ST6B). If the parameter i is equal to or less than n (step ST6B; YES), the processing unit 12 adds "1" to the parameter i (step ST7B) and returns to the processing of step ST4B. On the other hand, if the processing unit 12 determines that the parameter i is greater than n (step ST6B; NO), the processing unit 12 outputs the data sets associated with g[1] to g[n] (step ST8B).

[0128] 13 is a flowchart showing an example (3) of data input processing to a graph network in the first embodiment. Assuming that the number of electric circuits is n, n netlists, the same as the number of electric circuits, can be created. Therefore, the processing unit 12 sets the n netlists to be processed (step ST1C). The processing unit 12 sets "1" as the parameter i (step ST2C).

[0129] The processing unit 12 sets the value of the parameter i to the function g[i] = [[node], [edge], [edge attribute], [correct data]] (step ST3C). The processing unit 12 extracts a component name list and a wiring name list from the i-th netlist acquired by the acquisition unit 11, and acquires the edge attributes and correct data that have been calculated in advance.

[0130] The processing unit 12 reads the component name list extracted from the i-th netlist as nodes of the graph network, reads the wiring name list as edges of the graph network, and further reads the edge attributes and correct answer data (step ST4C). The processing unit 12 stores the nodes, edges, edge attributes, and correct answer data related to the i-th netlist as a single data set, associates it with the function g[i], and stores it in a storage area such as the memory 104 (step ST5C).

[0131] The processing unit 12 determines whether the parameter i is equal to or less than n (step ST6C). If the parameter i is equal to or less than n (step ST6C; YES), the processing unit 12 adds "1" to the parameter i (step ST7C) and returns to the processing of step ST4C. On the other hand, if the processing unit 12 determines that the parameter i is greater than n (step ST6C; NO), the processing unit 12 outputs the data sets associated with g[1] to g[n] (step ST8C).

[0132] The data set obtained as described above can be used for self-supervised learning, which is one of clustering, autoencoder, and contrastive learning. Clustering can be used to classify node types or edge types. Autoencoder is a graph neural network learning method that aims to obtain output data that is the same as the input data after passing it through a graph neural network. Autoencoder can abstract and retain multiple circuits. Self-supervised learning is similar to clustering, but can, for example, classify each input data and classify similar circuits into any number of sets. These are just some examples, and multiple techniques can be combined to predict the presence or absence of an edge between nodes or the presence or absence of a node.

[0133] There are many known neural networks that handle data of electrical circuits in the form of graph networks, including graph neural networks, graph convolutional neural networks, graph attention networks, etc. Any neural network can be used depending on the characteristics of the data or the characteristics of the correct answer data, such as those that are suitable for large-scale models or those that are good at handling sparse adjacency matrices created using edges.

[0134] The processing unit 12 uses the circuit diagram types as training data, taking the correct answer data, and uses, as training data, for example, 3,362 sample circuit types handled by the circuit simulator, to train the graph neural network. The sample circuits include nine types of circuits for operating semiconductors: switch circuits (89), reference circuits (59), ADC circuits (27), DAC circuits (29), comparator circuits (40), filter circuits (25), power supply circuits (2,272), and operational amplifier circuits (665).

[0135] The processing unit 12 trains a graph neural network for classifying electrical circuits using a data set combining a graph network and circuit classification data assigned to each of a plurality of electrical circuits as training data, and classifies the electrical circuits by inputting graph networks not used in the training to the graph neural network. For example, training is performed on a graph neural network that solves a classification problem of classifying electrical circuits into the above nine types. Here, 2,300 randomly acquired pieces of data are used as training data, and the remaining 897 pieces of data are used as test data not used in training. The graph neural network resulting from the training randomly classifies the data so that the distribution of classification problems between the training data and the test data is similar. Furthermore, the same training data and test data are used in all graph neural network calculations shown in the embodiments.

[0136] Note that under the above conditions, no nodes for component constants or component model numbers were used, and each node only had the identification number for each type of component, such as semiconductor, capacitor, or coil. This was done to prevent circuit classification problems from being predicted from connection information between circuit components, as entering component model numbers into the data would allow circuits to be classified from the model number. Furthermore, only information connecting each identification number was entered for the edges. In this case, an undirected graph was used, which does not take into account the direction of current, so the adjacency matrix was symmetric.

[0137] 14 is a graph showing an example (1) of the calculation results of inference accuracy by the information processing device 1 according to embodiment 1. In FIG. 11, the horizontal axis represents the number of iterations (epochs) when training a graph neural network using training data and updating the parameters of the graph neural network. The vertical axis represents the inference accuracy of the trained graph neural network for test data not used in training. As shown in FIG. 11, as the number of iterations increases, the inference accuracy for the test data improves, with the maximum inference accuracy reaching 96.26% at 4,000 iterations.

[0138] The graph neural network used to calculate the inference results shown in FIG. 14 has a combination of six hidden layers and a Relu (Rectified Linear Unit), and the features obtained by the graph neural network and Relu are classified into one of nine types of outputs by two fully connected layers.

[0139] Additionally, cross-entropy was used as the loss function, and Adam (Adaptive Moment Estimation) was used as the optimization function. The batch size was set to 500, and the graph neural network was trained to bring the loss function closer to 0. In this way, by training the graph neural network based only on the component types and the connection relationships between each component, the inference accuracy of the trained graph neural network was approximately 90%. Furthermore, when the circuits shown in the test data were classified using the graph network without the preconceived notion that 77% of humans classify them as power supply circuits, the inference accuracy by humans was approximately 50%. These results demonstrate that the inference accuracy based on this method is significantly higher than that of humans.

[0140] 15 is a graph showing an example (2) of the calculation result of inference accuracy by the information processing device 1 according to the first embodiment, and shows the result of training a graph neural network using, as training data, passive elements that are nodes used when calculating the inference result of FIG. 14 and have component constants assigned to them. The passive elements are, for example, resistors, capacitors, or coils. Because the dynamic range that passive element values ​​can take is large, the logarithm to base 10 of the identification number corresponding to the type of passive element is taken, normalized to be between 0 and 1, and input as a real number.

[0141] For example, if the node information is (C1, 0.33 uF) and (L2, 10 uH), and the identification number of C1 is 1 and the identification number of L2 is 2, the processing unit 12 converts it to (1, -6.48) and (2, -5.00). After all conversions are complete, the processing unit 12 performs normalization using the maximum and minimum values ​​and inputs the result as node information into the graph neural network. Information on the type of active element (semiconductor) (such as for a power supply circuit or an operational amplifier circuit) was not entered because it would be the same as the correct answer data, and the component information for the active element was set to 0. However, the component information for the active circuit does not have to be 0; appropriate information can be selected. In addition, GND, IN, and OUT were also set to 0, just like the active element. When performing inference calculations without changing any other conditions from those used when calculating Figure 14, it was confirmed that the inference accuracy for the test data was 98.90% with the same number of iterations.

[0142] By training the graph neural network using the processing unit 12, it is possible to classify the circuit type based on link information alone. A common identification number was assigned to each semiconductor element. If the type of semiconductor element is used as an identification number, it will match the type of circuit, improving inference accuracy without the need to train link information. For this reason, information held by the semiconductor element was discarded, and information other than that of the semiconductor element was not included. The processing unit 12 updates the part names in the part name list and combination list using the identification number assigned to each part name in this way.

[0143] Variation 2. The processing unit 12 may simultaneously train the generative network and the discriminative network in the generative adversarial network using a data set that combines a graph network and ground truth data for the characteristics of a plurality of electric circuits as training data, and input data showing characteristics similar to the ground truth data to the generative network, thereby generating a new graph network. By combining the generative adversarial network with the graph neural network, it is possible to generate a circuit diagram from circuit specifications such as a desired output signal waveform.

[0144] The processing unit 12 simultaneously trains a generator network, which is a neural network that generates circuits (generator), and a discriminator network, which is a neural network that judges circuits (discriminator) in the generative adversarial network. The processing unit 12 then trains the graph neural network to improve the performance of the generator and reduce the difference between the circuit or circuit output that serves as training data and the circuit or circuit output on the generator side. This allows input data to be generated from the correct answer data. In other words, when the requested design requirements are taken as the correct answer data, it is possible to generate input data, i.e., a combination of nodes and edges, that satisfies the correct answer data.

[0145] Furthermore, the generative adversarial network can be trained using multiple data, such as not only output signals but also heat generation or component costs, as ground truth data. In this case, it is possible to generate a circuit that simultaneously optimizes the signal waveform flowing through each edge, the heat generation at each node, the power consumption at each node, and the overall circuit cost. Furthermore, because the circuit can be designed in a short time, it is possible to review the required specifications or the cost at an early stage of design.

[0146] To generate a specific waveform using a node that is a circuit component, a node with unknown characteristics or type may be given, and the characteristics or type of the component may be predicted to optimize the waveform. Prediction of component characteristics can be achieved by generating node attributes in a graph neural network using a generative adversarial network. Prediction of component types can be achieved using technology for classifying nodes in a graph neural network. Alternatively, some of the node types, which are the correct answer data for training data, may be treated as black boxes, and the graph neural network may be trained to predict node types using self-supervised learning. This also makes it possible to predict node types using a trained graph neural network. The information processing device 1 may also train a graph neural network using data for which calculations have been completed for a large-scale circuit diagram, and use the trained graph neural network to predict the voltage or voltage frequency characteristics applied to the component. This can be achieved using existing technology that generates attribute information for nodes in a graph neural network using a generative adversarial network. However, because Kirchhoff's law, which is a physical constraint, must not be violated, this can be achieved using a constrained generative adversarial network. Alternatively, a portion of the voltage or voltage frequency characteristics, which is the correct data of the learning data, is treated as a black box, and the graph neural network is trained to predict the voltage or voltage frequency characteristics through self-supervised learning. This also makes it possible to predict the voltage or voltage frequency characteristics using the trained graph neural network. Furthermore, the information processing device 1 can create a circuit according to the design purpose by predicting connections between existing nodes to create specific waveforms for edges that become wiring within the circuit. This corresponds to edge prediction (link prediction) in a graph neural network, and after creating a graph network based on this embodiment, prediction can be made using existing technology using the graph neural network.Alternatively, a portion of the training data, which is the correct data for determining whether an edge exists between nodes, can be treated as a black box, and the graph neural network can be trained to predict the presence or absence of an edge between nodes through self-supervised learning. This also makes it possible to predict the presence or absence of an edge between nodes in an unknown circuit (graph network) using a trained graph neural network.

[0147] For example, a graph neural network trained using pre-calculated results for a large-scale circuit diagram that is difficult to simulate can be used to predict the current and current frequency characteristics applied to a component. Specifically, similar to the case of generating node attributes using a generative adversarial network, the processing unit 12 assigns a dataset to nodes as training data, combining a graph network with ground truth data, which is a matrix in which feature quantities obtained by assigning voltage or voltage frequency characteristics to each node in the graph network are used as node attribute elements. A generative adversarial network for predicting voltage or voltage frequency characteristics may then train the relationship between the graph network generated from the circuit diagram and the voltage or voltage frequency characteristics using the graph neural network, and use the graph neural network to predict the voltage or voltage frequency characteristics of some or all nodes in a graph network not used in the training. The generative adversarial network is composed of a generation network that predicts voltage or voltage frequency characteristics while hiding pre-calculated results, which are training data, and a discrimination network that identifies the accuracy of the generated prediction. In a generative adversarial network, the generative network and the discriminative network are trained simultaneously so that the difference between the discrimination result and the calculated result, which is the training data, is small. Alternatively, a portion of the current and current frequency characteristics, which are the correct data of the training data, is treated as a black box, and a graph neural network is trained to predict the current and current frequency characteristics using self-supervised learning. This also makes it possible to predict the current and current frequency characteristics of an unknown circuit (graph network) using a trained graph neural network.

[0148] Furthermore, the processing unit 12 may train a graph neural network for predicting the type of parts using a data set that combines a graph network and data including the types of parts corresponding to each node in the graph network as training data, and use the graph neural network to predict the types of parts that are part of some or all of the nodes in the graph network that were not used for training. This involves creating a graph network in which input data for the graph neural network is created from a circuit diagram, and training data in which output data is the type of parts corresponding to the nodes, and performing supervised learning using this training data as training data. This makes it possible to predict the types of parts used in any graph network using the trained graph neural network.

[0149] Furthermore, the processing unit 12 may train a graph neural network for predicting the current or current frequency characteristics at edges using a data set combining a graph network and ground truth data, which is a matrix whose elements are features indicating the current or current frequency characteristics at each edge of the graph network, as training data, and use the graph neural network to predict the current or current frequency characteristics at some or all edges of the graph network not used for training. This involves creating a graph network created from a circuit as input data for the graph neural network, and training data in which the output data is the current or current frequency characteristics corresponding to the edges, and performing supervised learning using this training data as training data. This makes it possible to predict the current or current frequency characteristics in any graph network using the trained graph neural network. Furthermore, if there is sufficient training data, the current or current frequency characteristics in any graph network can be predicted using a generative adversarial network or self-supervised learning, as in the case of generating the node attributes described above using a generative adversarial network. Predicting the current or current frequency characteristics in any graph network can be achieved using methods such as supervised learning, a generative adversarial network, or self-supervised learning. Here, supervised learning is effective when the dataset has few labeling errors and the bias and variance of the entire dataset are small. Generative adversarial networks are effective when the dataset is large and a solution is required as a solution to an inverse problem, such as when optimizing the entire circuit. Self-supervised learning is effective when labeling is difficult due to the large computational cost, when there are many labeling errors, or when abundant computational resources are available. Furthermore, the results of a graph neural network obtained by self-supervised learning, i.e., the weight matrix obtained by learning, can be used in combination with supervised learning for problems with insufficient datasets, for example, by transfer learning or fine-tuning.In this way, the information processing device 1 may change the structure or learning method of the graph neural network, the way in which training data is provided, etc., depending on given conditions or desired results.

[0150] Furthermore, the processing unit 12 may train a graph neural network for predicting power or power frequency characteristics of at least one of the nodes or edges using, as training data, a dataset combining a graph network and ground truth data, which is a matrix whose elements are features indicating power or power frequency characteristics of at least one of some or all of the nodes or edges of the graph network, and use the graph neural network to predict power or power frequency characteristics of at least one of some or all of the nodes or edges of a graph network not used in training. Even in this case, supervised training of the graph neural network is performed, with the graph network as the input and the power or power frequency characteristics as the output. Power or power frequency characteristics can be inferred from unknown inputs of the trained graph neural network obtained in this way. Alternatively, the graph network is used as the input, power or power frequency characteristics are predicted from a generation network, and the graph neural network is trained so as to reduce the difference between the prediction result and ground truth data using a discrimination network. Power or power frequency characteristics can be inferred from unknown inputs of the trained graph neural network obtained in this way. Furthermore, we perform self-supervised learning of a graph neural network, which uses a graph network as input and hides part of the power or power frequency characteristics as output, and learns to predict the hidden value. This makes it possible to infer power or power frequency characteristics from unknown inputs of the trained graph neural network obtained.

[0151] Even for predictive calculations that have traditionally taken a long time, using inference with a graph neural network allows for real-time output prediction without going through a circuit simulator. For example, by performing rough inference using a graph neural network and then interpolating the prediction using calculations with a circuit simulator, the number of times the circuit simulator is used, which requires time and computational costs for predictive calculations, can be reduced. Furthermore, the results of calculations using a circuit simulator or actual measurements can be reused as training data.

[0152] Modification 3. In Modification 3, it will be explained that the wiring can be given a current direction, that a voltage of a specific frequency or a voltage frequency characteristic can be given to the component name list, and that a current of a specific frequency or a current frequency characteristic can be given to the combination list. In terms of current direction, the following combination list can be obtained from the net list of the electric circuit shown in FIG. 6. (1); (IN, A) (2); (A, B) (3); (B, C), (C, D), (D, B) (4); (D, OUT) G-A; (GND, A) G-B; (GND, B) G-C; (GND, C)

[0153] For example, when writing (IN, A), taking into consideration the order in which it is written, if you write (IN, A), you can define the direction of the current from the IN terminal to the A terminal. If you apply graph theory to the component name list and the wiring name list, the component name list is a node, and the wiring name list is an edge. If the direction of the current is not taken into consideration, the graph network becomes an undirected graph. On the other hand, by defining the order in which it is written, the graph network can be thought of as a directed graph. Note that in the case of circuits that include alternating current, the direction of the current cannot be correctly defined from the circuit diagram alone.

[0154] In the case of a directed graph, it is possible to determine the direction of the current from the arrival time difference by putting the circuit into operation through circuit simulation or actual measurement, superimposing a pulse-like signal that does not affect this operation, and simultaneously observing multiple points on the wiring to be measured with a voltage probe or current probe. However, in circuit simulation, detection is difficult because no time difference occurs on the wiring.

[0155] In this case, the processing unit 12 virtually places a small inductance on the wiring, approximately the same as the residual inductance of the wiring (approximately 1 nH / mm), and can infer the direction of the current from the time difference between the voltage across the inductance or the change in current. Furthermore, signals may flow bidirectionally in communications. In such cases, by including (B, A) in addition to (A, B) in the combination list, processing can be performed assuming that signals flow bidirectionally.

[0156] In graph theory, a combination list can be defined as an adjacency matrix. To create an adjacency matrix, a square matrix with the same number of rows and columns as the maximum value of the elements in the combination list is prepared, and the rows and columns of the square matrix are made to correspond to the combination list, with a value of 1 entered in the corresponding locations and a value of 0 entered in all other locations. For example, if (5, 3) is in the combination list, an adjacency matrix can be created by entering a value of 1 in row 5, column 3. If the flow of current in an electrical circuit is not taken into consideration, this adjacency matrix will be a symmetric matrix, so if the above (5, 3) is in the combination list, a value of 1 will be entered in row 5, column 3 and row 3, column 5.

[0157] On the other hand, when the direction of current in the circuit is taken into consideration, either the 5th row, 3rd column or the 3rd row, 5th column is set to 1, and the other is set to 0. As a result, when the direction of current is not taken into consideration, the matrix becomes symmetric, whereas when the direction of current is taken into consideration, the matrix becomes asymmetric. In both cases, the adjacency matrix becomes an upper triangular matrix or a lower triangular matrix. In particular, in the second embodiment described below, since there is no self-loop, the adjacency matrix becomes an upper triangular matrix whose diagonal elements are 0 or a lower triangular matrix whose diagonal elements are 0. However, if there is at least one bidirectional signal in the circuit, that is, a signal that is both received and transmitted through a single wiring, such as an antenna or a communication signal, the matrix will not be an upper triangular matrix or a lower triangular matrix, but will be an asymmetric matrix.

[0158] Furthermore, in the component name list, it is possible to set a voltage or a voltage frequency characteristic at a specific frequency in an electrical circuit, similar to a component constant. When setting a frequency characteristic in the component name list, it is necessary to convert the frequency characteristic into a discrete value and input the signal as an amplitude at a discrete frequency. For example, if a frequency characteristic from 1 MHz to 10 MHz is desired, it is sufficient to set 10 elements associated with each component in 1 MHz increments. In this case, it is set as a matrix with the same number of rows as the number of components and the same number of columns as the frequency increments (10 columns in 1 MHz increments from 1 MHz to 10 MHz). However, the frequency band or increment must be the same for all circuit diagrams used in processing and all components within the circuit diagrams.

[0159] Although the frequency intervals are shown in 1 MHz increments from 1 MHz to 10 MHz, as long as they are common to all components, the intervals of the frequency increments may be any, such as logarithmic, and do not have to be uniform. Furthermore, the order of the frequencies may be different, and the component name list may be configured as a single matrix by combining the identification numbers defined by the component type or model number and the frequency characteristics in different columns.

[0160] Furthermore, a specific frequency current or current frequency characteristics can be assigned to the combination list. This can be considered similar to the frequency characteristics of voltage. If the same frequency band and frequency increments are used for all circuit diagrams and all wiring, the combination list can be input as a matrix with a vertical axis having as many rows as the number of combinations in the combination list and a horizontal axis having as many columns as the frequency increments (10 columns in 1 MHz increments from 1 MHz to 10 MHz). However, since the combinations themselves are meaningful in a combination list, it is not desirable to assign current information to the combination list as is the case with a component name list. Therefore, it is desirable to define these frequency characteristics as a separate matrix and assign them to the combination list as wiring attribute information (edge ​​attribute in graph theory).

[0161] Since the combination list has as many rows as there are combinations, it can also be used for directed graphs, and even if the frequency characteristics of the outgoing current and the incoming current are different, they can be treated as different. Furthermore, the combination list may be entered into the above-mentioned single matrix with information other than the current or the frequency characteristics of the current, such as the length or thickness of the wiring, as information in different columns.

[0162] As described above, the information processing device 1 according to the first embodiment includes an acquisition unit 11 that acquires a netlist of an electric circuit, and a processing unit 12 that extracts a component name list and a wiring name list from the netlist, updates the component name list by adding component names indicating ground terminals, input terminals, and output terminals, updates the wiring name list by removing wiring names indicating ground wiring, input wiring, and output wiring, and extracts component names corresponding to wiring names in the updated wiring name list from the component names in the updated component name list, creates a combination list including the extracted component names, and outputs the updated component name list and combination list. This enables the information processing device 1 to provide list information that can suppress information degradation that occurs when an electric circuit is converted into a graph network.

[0163] The information processing device 1 according to the first embodiment includes an acquisition unit 11 that acquires a netlist of an electric circuit; a processing unit 12 that extracts a component name list and a wiring name list from the netlist, updates the component name list by adding component names indicating ground terminals, input terminals, and output terminals, updates the wiring name list by removing wiring names indicating ground wiring, input wiring, and output wiring, and extracts component names corresponding to wiring names in the updated wiring name list from the component names in the updated component name list, creates a combination list including the extracted component names and their corresponding wiring names, and outputs the updated component name list and combination list. This allows the information processing device 1 to provide list information that can suppress information degradation that occurs when converting an electric circuit into a graph network. Furthermore, because the information processing device 1 can suppress an increase in the number of component combinations, it can reduce the amount of calculation and increase in calculation time required for processing a graph neural network using list information including the combination list.

[0164] In the information processing device 1 according to the first embodiment, the processing unit 12 outputs an updated part name list and combination list in which part names are replaced with unique identification numbers for each part feature. This allows the information processing device 1 to reduce the amount of information by expressing the list information as numerical values, thereby preventing information degradation that occurs when list information is converted into a graph network. This is because, when the definition in which part features are converted into numerical values ​​is used in reverse, the part features can be determined from the numerical values, i.e., the part features and numerical values ​​are bijective.

[0165] In the information processing device 1 according to the first embodiment, the processing unit 12 defines a unique identification number for each type of part. This allows the information processing device 1 to reduce the amount of information by expressing list information as numerical values, and prevents information degradation that occurs when list information is converted into a graph network. This is because, when the definition in which the type of part is converted into a numerical value is used in reverse, the type of part can be determined from the numerical value, i.e., the type of part and the numerical value are bijective.

[0166] In the information processing device 1 according to the first embodiment, the processing unit 12 defines a unique identification number for each part model number. This allows the information processing device 1 to reduce the amount of information by expressing list information as numerical values, and prevents information degradation that occurs when list information is converted into a graph network. This is because, when the definition in which the part model number is converted into a numerical value is used in reverse, the part model number can be determined from the numerical value, i.e., the part type and the numerical value are bijective.

[0167] In the information processing device 1 according to the first embodiment, the processing unit 12 replaces the part names in the part name list with rows or columns of a feature matrix obtained by one-hot-representing the features of the parts. This enables the information processing device 1 to perform matrix calculations on the part names in the part name list and the features of the parts. This is because, by using the definition obtained by converting the features of the parts into one-hot representation in reverse, the features of the parts can be determined from the one-hot representation.

[0168] In the information processing device 1 according to the first embodiment, when an electric circuit includes two or more semiconductors, the processing unit 12 changes the elements corresponding to the semiconductors in the feature matrix to different values ​​for each semiconductor. This allows the information processing device 1 to prevent information degradation that occurs when converting list information into a graph network. This is because, by using the definition in which semiconductors are converted into elements corresponding to each semiconductor in reverse, it is possible to determine the semiconductor from the elements corresponding to the semiconductor.

[0169] In the information processing device 1 according to the first embodiment, the processing unit 12 replaces elements corresponding to passive circuits in the feature matrix with function values ​​calculated by substituting the circuit constants of the components into a function including a logarithm. This allows the information processing device 1 to reduce the amount of information by expressing the list information as numerical values, thereby preventing information degradation that occurs when converting list information to a graph network. This is because the circuit constants are real numbers greater than 0 and have a bijective relationship with the function including a logarithm, so the numerical values ​​of the original circuit constants can be calculated from the numerical values ​​obtained after applying the function including a logarithm.

[0170] In the information processing device 1 according to the first embodiment, the processing unit 12 performs normalization and / or standardization on the function values. This allows the information processing device 1 to reduce the amount of information by expressing the list information as numerical values, and prevents information degradation that occurs when converting list information to a graph network. This is because, even in normalization or standardization, the values ​​before and after normalization or standardization are bijective, allowing conversion in both directions.

[0171] In the information processing device 1 according to the first embodiment, when there are three or more combinations of component names corresponding to one wiring name in the combination list, the processing unit 12 breaks each combination into two combinations, thereby enabling the information processing device 1 to easily create an adjacency matrix of a graph network from the combination list.

[0172] In the information processing device 1 according to the first embodiment, when a combination list has three or more component names, the processing unit 12 separates each combination list into lists each having two component names. This allows the information processing device 1 to prevent information degradation that occurs when list information is converted into a graph network.

[0173] In the information processing device 1 according to the first embodiment, the acquisition unit 11 acquires netlists for two or more electric circuits. The processing unit 12 extracts component name lists from each netlist, combines the extracted component name lists into a single component name list, and removes duplicate component names from the combined component name list. This allows the information processing device 1 to prevent an increase in the amount of information in the component name list.

[0174] In the information processing device 1 according to the first embodiment, the component name list is a node in the graph network, the wiring name list is an edge in the graph network, and the combination list is an adjacency matrix in the graph network. This allows the information processing device 1 to use the list information as a graph network.

[0175] In the information processing device 1 according to the first embodiment, the processing unit 12 refers to a database containing semiconductors that are noise sources and their terminal numbers, and performs a search process in which, starting from a terminal corresponding to the terminal number in the electric circuit, the search continuously searches for adjacent components under the condition that the same component is not passed through more than once, and extracts a current loop representing the semiconductor, thereby completing the search process. This enables the information processing device 1 to search for a loop path consisting of the semiconductor, capacitor, coil, ground, and semiconductor.

[0176] In the information processing device 1 according to the first embodiment, the processing unit 12 determines whether or not a component indicating a noise filter is present in a current loop, thereby enabling the information processing device 1 to extract a noise filter provided in the current loop, which is a path through which a current flows.

[0177] In the information processing device 1 according to the first embodiment, the processing unit 12 extracts features of a semiconductor to be searched for and features of a current loop indicating the semiconductor from one or more electric circuits including one or more semiconductors, and searches for semiconductors similar to the semiconductor to be searched for using the extracted features of the semiconductor and the current loop. This enables the information processing device 1 to search for similar circuits.

[0178] In the information processing device 1 according to the first embodiment, the processing unit 12 extracts a combination list according to the direction of current flow and generates an asymmetric adjacency matrix from the extracted combination list. This allows the information processing device 1 to suppress information degradation even in circuits where the direction of current flow is known.

[0179] In the information processing device 1 according to the first embodiment, the processing unit 12 sets the amplitude of the current between mutually connected components in the adjacency matrix to a real number, and sets the amplitude of the current between unconnected wires to 0. This allows the information processing device 1 to suppress the occurrence of information degradation even in circuits where the direction of current flow is known.

[0180] In the information processing device 1 according to the first embodiment, the processing unit 12 sets a combination of nodes and edges as input data for the graph neural network, thereby enabling the information processing device 1 to learn the graph neural network using the graph network.

[0181] In the information processing device 1 according to the first embodiment, the processing unit 12 trains a graph neural network for classifying electric circuits using, as training data, a data set that combines a graph network and circuit classification data assigned to each of a plurality of electric circuits, and classifies the electric circuits by inputting graph networks that have not been used in the training to the graph neural network. This enables the information processing device 1 to classify the electric circuits.

[0182] In the information processing device 1 according to the first embodiment, the processing unit 12 simultaneously trains the generative network and the discriminative network in the generative adversarial network using, as training data, a data set that combines a graph network and ground truth data on the characteristics of a plurality of electric circuits assigned to each of the electric circuits, and generates a new graph network by inputting data that exhibits characteristics similar to the ground truth data into the generative network. This enables the information processing device 1 to automatically design an electric circuit corresponding to the new graph network.

[0183] In the information processing device 1 according to the first embodiment, the processing unit 12 uses, as training data, a data set that combines a graph network with ground truth data, which is a matrix whose elements are feature quantities obtained by assigning voltages or voltage frequency characteristics to each node in the graph network, to train a graph neural network for predicting the voltages or voltage frequency characteristics to be assigned to nodes, and uses the graph neural network to predict the voltages or voltage frequency characteristics at some or all nodes in the graph network that are not used in the training. This allows the information processing device 1 to predict the output voltage or output voltage frequency characteristics of an unknown circuit without performing a circuit simulation.

[0184] In the information processing device 1 according to the first embodiment, the processing unit 12 trains a graph neural network for predicting the type of part using as training data a data set that combines a graph network with data including the type of part corresponding to each node in the graph network, and predicts the type of part that is a part of some or all of the nodes in the graph network that were not used for training, using the graph neural network. This enables the information processing device 1 to predict the type of part.

[0185] In the information processing device 1 according to the first embodiment, the processing unit 12 uses, as training data, a data set that combines a graph network with ground truth data, which is a matrix whose elements are feature quantities that indicate the current or frequency characteristics of the current at each edge of the graph network, to train a graph neural network for predicting the current or frequency characteristics of the current at the edges, and predicts the current or frequency characteristics of the current at some or all edges of the graph network that are not used for training using the graph neural network. This enables the information processing device 1 to predict the output current or frequency characteristics of the output current of an unknown circuit without performing a circuit simulation.

[0186] In the information processing device 1 according to the first embodiment, the processing unit 12 uses, as training data, a data set that combines a graph network with ground truth data, which is a matrix whose elements are features that indicate the power or frequency characteristics of power in at least one of the nodes or edges of the graph network, and trains a graph neural network for predicting the power or frequency characteristics of power in at least one of the nodes or edges, and predicts the power or frequency characteristics of power in at least one of the nodes or edges of the graph network that are not used for training, using the graph neural network. This enables the information processing device 1 to predict the output power or frequency characteristics of output power of an unknown circuit without performing a circuit simulation.

[0187] In the information processing device 1 according to the first embodiment, the processing unit 12 uses a graph network as training data to train a graph neural network for predicting the presence or absence of an edge between nodes in the graph network, and predicts the presence or absence of an edge between nodes in a graph network that is not used for training using the graph neural network. This enables the information processing device 1 to predict the presence or absence of an edge between nodes in a graph network that is not used for training.

[0188] In the information processing device 1 according to the first embodiment, the processing unit 12 uses a graph network as training data to train a graph neural network for clustering electrical circuits into a finite number of clusters according to their characteristics, and uses the graph neural network to cluster graph networks not used in the training, thereby classifying the electrical circuits into groups of similar electrical circuits. This enables the information processing device 1 to classify groups of similar electrical circuits.

[0189] In the information processing method according to the first embodiment, an information processing device 1 executes the steps of acquiring a netlist of an electric circuit, extracting a component name list and a wiring name list from the netlist, creating an updated component name list by adding component names indicating ground terminals, input terminals, and output terminals, creating an updated wiring name list by removing wiring names indicating ground wiring, input wiring, and output wiring, and extracting, from the component names in the updated component name list, component names corresponding to wiring names in the updated wiring name list and creating a combination list including the extracted component names. This makes it possible to provide list information that can suppress information degradation that occurs when an electric circuit is converted into a graph network.

[0190] In the information processing method according to the first embodiment, an information processing device 1 executes the following steps: acquiring a netlist of an electric circuit; extracting a component name list and a wiring name list from the netlist; creating an updated component name list by adding component names indicating ground terminals, input terminals, and output terminals; creating an updated wiring name list by removing wiring names indicating ground wiring, input wiring, and output wiring; extracting component names corresponding to wiring names in the updated wiring name list from the component names in the updated component name list and creating a combination list including the extracted component names and their corresponding wiring names; and outputting the updated component name list and combination list. This makes it possible to provide list information that can suppress information degradation that occurs when converting an electric circuit into a graph network. Furthermore, because an increase in the number of component combinations can be suppressed, the increase in the amount of calculation and the increase in calculation time required for graph neural network processing using list information including the combination list can be reduced.

[0191] Second Embodiment. Fig. 16 is a block diagram showing an example configuration of an information processing device 1A according to a second embodiment. In Fig. 16, the information processing device 1A acquires a netlist of an electric circuit and uses the acquired netlist to provide list information capable of suppressing information degradation that occurs when the electric circuit is converted into a graph network. The graph network of an electric circuit is information that represents the electric circuit using nodes representing components and edges representing wiring. The graph network also includes information indicating the feature amounts of the nodes and the feature amounts of the edges.

[0192] As shown in FIG. 16 , the information processing device 1A includes an acquisition unit 11 and a processing unit 12A. The acquisition unit 11 executes a first process of acquiring a netlist of an electric circuit. For example, the information processing device 1 is connected to a computer equipped with a circuit design CAD, and the acquisition unit 11 acquires a netlist created using the circuit design CAD from the computer. The acquisition unit 11 may also acquire a circuit diagram model of the electric circuit that operates on a circuit simulator and convert the circuit diagram represented by this circuit diagram model into a netlist. In other words, acquiring a netlist by the acquisition unit 11 also includes converting a circuit diagram to acquire a netlist.

[0193] The processing unit 12A uses the component name list updated by adding component names indicating the ground terminal, input terminal, and output terminal and the wiring name list updated by removing wiring names indicating the ground wiring, input wiring, and output wiring, to treat components connected to three or more wirings as two-terminal components with the same number of wirings, and adds component names indicating the two-terminal components to the updated component name list, removes component names indicating the components before they were treated as two-terminal components from the updated component name list, connects three or more wirings to one terminal of each two-terminal component, connects the other terminals of the two-terminal components with new wirings, adds wiring names indicating the new wirings to the updated wiring name list, extracts component names corresponding to the wiring names in the updated wiring name list from the updated component name list, creates a combination list including the extracted component names, and outputs the updated component name list and combination list.The processing unit 12A may also output the updated component name list and combination list in which component names have been replaced with identification numbers.

[0194] The information processing device 1A is, for example, a computer connected to an information network. The computer may be a server or client that can connect to a cloud or the like via the information network, or may be a standalone computer that is not connected to an information network. It may also be a computer used in a closed network environment within a factory, known as edge computing. The information processing device 1A may also be a smartphone, a tablet terminal, a PC, or a microcomputer.

[0195] 17 is a flowchart showing an information processing method according to the second embodiment, illustrating a series of operations performed by the information processing device 1A. The acquisition unit 11 acquires a netlist (step ST1D). The processing unit 12A extracts a component name list from the netlist (step ST2D-1) and extracts a wiring name list from the netlist (step ST2D-2). For example, the processing unit 12A stores all component names included in the netlist in the component name list, and stores all wiring names included in the netlist in the wiring name list. Note that the processing of step ST2D-1 and the processing of step ST2D-2 may be performed either first, or may be performed simultaneously.

[0196] The processing unit 12A adds the ground wiring, input wiring, and output wiring included in the netlist to the component name list as ground terminals, input terminals, and output terminals (step ST3D-1). The processing unit 12A removes the ground wiring, input wiring, and output wiring from the wiring name list (step ST3D-2). This leaves information indicating the ground terminals, input terminals, and output terminals as component information in the component name list, thereby suppressing information degradation when converting an electrical circuit into a graph network using list information including the component name list. Note that the processing of step ST3D-1 and the processing of step ST3D-2 may be performed first, or may be performed simultaneously.

[0197] The processing unit 12A uses the component name list and the wiring name list to determine whether there are any components connected to three or more wirings (step ST4D). If there are no components connected to three or more wirings (step ST4D; NO), the processing proceeds to step ST5D. In Fig. 17, the processes of steps ST5D, ST6D, ST7D, ST12D, ST13D, and ST14D are the same as steps ST4, ST5, ST6, ST7, ST8, and ST9 in Fig. 5, and therefore will not be described here.

[0198] If there is a component connected to three or more wires (step ST4D; YES), the processing unit 12A regards the components connected to three or more wires as two-terminal components with the same number of wires (step ST8D). The processing unit 12A then assigns new component names to the two-terminal components (step ST9D). The processing unit 12A then connects three or more wires to one terminal of each two-terminal component, and adds new wires to connect the other terminals of each two-terminal component (step ST10D). The processing unit 12A adds the wire names assigned to the new wires to the wire name list (step ST11D).

[0199] In this way, the processing unit 12A connects each of the two-terminal components disassembled from a single component and assigns new wiring names to the wires used for each connection. Since the other terminals of each two-terminal component have the same number of wires as the three or more wires, the processing unit 12A connects each of the terminals to the wires. This conversion prevents self-loops or multiple edges, and prevents information degradation when converting from an electrical circuit to a graph network and from a graph network to an electrical circuit.

[0200] For example, a self-loop occurs when wiring from a terminal of a semiconductor to a different terminal of the same semiconductor without passing through a circuit component, and such wiring may be necessary to define the operation of the semiconductor, and occurs in such cases. In the first embodiment, such conditions are discarded, resulting in information degradation, but by dividing into two-terminal components as in the second embodiment, it is possible to convert to a graph network while retaining such information.

[0201] Furthermore, multiple edges occur when bus wiring is performed from one semiconductor to another when there are multiple input terminals to ensure current capacity for a power supply, etc. In this case, in the first embodiment, such conditions are discarded, resulting in information degradation. However, by dividing into two-terminal components as in the second embodiment, it is possible to convert to a graph network while retaining such information.

[0202] In step ST11D, the component names held by each wiring name are extracted from the updated wiring name list, as in embodiment 1, and a component name combination list is extracted. As in embodiment 1, if one wiring name holds three or more component names, the combination list is broken down into combinations of two components per wiring. Furthermore, an identification number is assigned to each component name using the updated component name list, and these identification numbers are used to replace the component names with the identification numbers corresponding to each component name in the combination list. Furthermore, the component name list is replaced with the identification numbers, and the component name list replaced with these identification numbers and the combination list replaced with the identification numbers are output, completing the process.

[0203] FIG. 18 is a circuit diagram showing an example of an electric circuit (4). FIG. 19 is a circuit diagram showing an example of an electric circuit (5). In FIG. 18, component A has three wires connected: (1) between the input terminal "IN" and component A, (2) between component B and component A, and (3) between GND and component A. Component A is disassembled into three two-terminal components, each of which is named, for example, A1, A2, and A3. One terminal of each disassembled component is connected to the terminal of the other disassembled component, resulting in connections between A1 and A2, A2 and A3, and A3 and A1, respectively. These connections are named, for example, A1-A2, A1-A3, and A2-A3. The connection between A3 and GND is also named G-A3. Component B is disassembled in the same manner, and the disassembled components and the wires between them are named, resulting in the electric circuit structure shown in FIG. 18.

[0204] The same applies to Fig. 19, and since the components holding three or more wires in Fig. 18 are components A and E, each component is disassembled and names are assigned to the wires between the disassembled components. Note that, for simplicity of explanation, a circuit diagram is used as the processing target, but similar processing is also possible for a netlist.

[0205] The netlist shown in the first embodiment is shown below. When component A is searched for in the # wiring in the netlist, it is found to be held by wiring (1), (2), and GND. Therefore, it can be determined that three wirings are connected to component A, and it can be broken down into a two-terminal component. #Component A B C D #Wiring (1); IN, A (2); A, B (3); B, C, D (4); D, OUT GND; A, B, C

[0206] 18, by breaking down the components into two-terminal components, the component name list becomes "A1, A2, A3, B1, B2, B3, C, D, GND, IN, OUT," and the wiring name list becomes "(1), (2), (3), (4), A1-A2, A2-A3, A1-A3, B1-B2, B2-B3, B1-B3, G-A3, G-B3, GC." As in the first embodiment, the processing unit 12A adds "IN," "OUT," and "GND" to the component name list and removes "IN," "OUT," and "GND" from the wiring name list.

[0207] Similarly, by breaking down the components into two-terminal components as shown in Figure 19, the component name list becomes "A1, A2, A3, C, D, E1, E2, E3, F, GND, IN, OUT", and the wiring name list becomes "(1A), (2A), (3A), (4A), (5A), A1-A2, A2-A3, A1-A3, E1-E2, E2-E3, E1-E3, G-A3, G-E3, G-C".

[0208] For components with three or more terminals, the combination list for the electric circuit shown in Figure 18 is as follows, based on the combination list created from the updated wiring name list and the combination list for two-terminal components: (1) to (4), G-C, G-A3, and G-B3 are created from the netlist, and A1-A2, A1-A3, A1-A3, B1-B2, B2-B3, and B1-B3 are combination lists created from the updated wiring name list. (1); IN, A1 (2); A2, B1 (3); B2, C, D (4); D, OUT A1-A2; A1, A2 A2-A3; A2, A3 A1-A3; A1, A3 B1-B2; B1, B2 B2-B3; B2, B3 B1-B3; B1, B3 G-A3; GND, A3 G-B3; GND, B3 GC; GND, C

[0209] Similarly, the following combination list can be extracted for the circuit diagram shown in Figure 19: (1A); IN, A1 (2A); A2, D (3A); D, C, E1 (4A); E2, F (5A); F, OUT A1-A2; A1, A2 A2-A3; A2, A3 A1-A3; A1, A3 E1-E2; E1, E2 E2-E3; E2, E3 E1-E3; E1, E3 G-A3; GND, A3 G-E3; GND, E3 G-C; GND, C

[0210] After circuit components with three or more terminals are disassembled in this manner, the process is the same as in embodiment 1. The component name list for the circuit shown in Figure 18 is "A1, A2, A3, B1, B2, B3, C, D, GND, IN, OUT," and the component name list for the circuit shown in Figure 19 is "A1, A2, A3, C, D, E1, E2, E3, F, GND, IN, OUT." Combining these two lists and removing duplicates results in "A1, A2, A3, B1, B2, B3, C, D, E1, E2, E3, F, GND, IN, OUT." If a different identification number is assigned to each component name, the combined list may look like the following, for example: A1 → 1 A2 → 2 A3 → 3 B1 → 4 B2 → 5 B3 → 6 C → 7 D → 8 E1 → 9 E2 → 10 E3 → 11 F → 12 GND → 13 IN → 14 OUT → 15

[0211] If identification numbers are used, the component name list for the circuit shown in Fig. 18 will be "1, 2, 3, 4, 5, 6, 7, 8, 13, 14, 15," and the component name list for the circuit shown in Fig. 19 will be "1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 15." Also, in the combination list, components with three or more component names are divided into two and each component name is replaced with an identification number, resulting in the combination list for the circuit shown in Fig. 18 as follows: (1); (14,1) (2); (2,4) (3); (5,7), (7,8), (8,5) (4); (8,15) A1-A2; (1,2) A2-A3; (2,3) A1-A3; (1,3) B1-B2; (4,5) B2-B3; (5,6) B1-B3; (4,6) G-A3; (13,3) G-B3; (13,3) GC; (13,7)

[0212] The combination list for the circuit shown in Figure 19 is as follows: (1A); (15,1) (2A); (2,8) (3A); (8,7) (8,9), (7,9) (4A); (10,12) (5A); (12,15) A1-A2; (1,2) A2-A3; (2,3) A1-A3; (1,3) E1-E2; (9,10) E2-E3; (10,11) E1-E3; (9,11) G-A3; (13,3) G-E3; (13,11) G-C; (13,7)

[0213] As an output result of the processing unit 12A, the component name list for the circuit shown in FIG. 18 is "1, 2, 3, 4, 5, 6, 7, 8, 13, 14, 15," and the combination list is "(14, 1) (2, 4) (5, 7) (7, 8) (8, 5) (8, 15) (1, 2) (2, 3) (1, 3) (4, 5) (5, 6) (4, 6) (13, 3) (13, 3) (13, 7)." Furthermore, the component name list for the circuit shown in FIG. 19 is "1, 2, 3, 7, 8, 9, 10, 11, 12, 13, 14, 15," and the combination list is "(15, 1) (2, 8) (8, 7) (8, 9), (7, 9) (10, 12) (12, 15) (1, 2) (2, 3) (1, 3) (9, 10) (10, 11) (9, 11) (13, 3) (13, 11) (13, 7)."

[0214] In circuit components, particularly semiconductors, operation can be controlled by shorting one terminal of a semiconductor with a wire between a different terminal of the same semiconductor. An electrical circuit with this structure has a self-loop, where the wire originates from itself and returns to itself. However, while it is possible to create a combination list from a netlist related to an electrical circuit with a self-loop, it is not possible to convert the combination list with the self-loop back to the original netlist. This is because information degradation occurs when converting from a netlist to a combination list. In contrast, by decomposing into components with three or more elements as described above, it is possible to eliminate wiring that becomes a self-loop. Therefore, the information processing device 1A according to the second embodiment can use a netlist related to an electrical circuit with a self-loop to create a combination list related to an electrical circuit without a self-loop. As a result, the combination list can be converted to a netlist without information degradation.

[0215] For example, in an electrical circuit connected to a power supply with a large current, wiring connected to the same power supply may be connected to multiple terminals of a semiconductor to distribute the current. Also, there are electrical circuits that have semiconductors with pull-up power supplies or control signals connected to multiple terminals. These connection relationships result in multiple edges. Therefore, if multiple edges are included in the combination list, as with self-loops, the information for each edge is lost, and the combination list cannot be restored to a netlist. This is considered to have caused information degradation. In contrast, the information processing device 1A according to the second embodiment can restore the combination list to the original netlist even for an electrical circuit with multiple edges. Therefore, a netlist can be converted to a combination list and the combination list can be converted back to a netlist without causing information degradation.

[0216] FIG. 20 is a schematic diagram showing an example (1) of an electric circuit and graph network according to the second embodiment. The electric circuit shown in FIG. 20 includes a switching power supply U1. When a voltage is applied between the input terminal and ground GND, a different voltage is output between the output terminal and ground GND. The result of extracting a component list and a combination list from a netlist related to this electric circuit is called a graph. In the electric circuit shown in FIG. 20, the graph cannot be converted into a circuit diagram. In particular, because information about the wiring shown in gray in the circuit diagram at the top of FIG. 20 is missing, it is considered that information degradation occurred when the graph was converted.

[0217] Figure 21 is a schematic diagram showing an example (2) of an electric circuit and graph network according to the second embodiment. The graph shown in Figure 21 is constructed by adding input terminals, output terminals, and ground terminals to a component name list, as described in the first embodiment. It can be seen that the resulting circuit diagram has a similar structure to that of Figure 20. However, the line between "IN" and "U1" in the graph in the lower diagram of Figure 21 has multiple edges. Furthermore, among the lines from "U1" to "OUT," some lines pass through L1 and some do not. This means that the circuit diagram and the graph are not identical. In many cases where graphs are used, some degradation of information is acceptable, so the method of the first embodiment is more effective than conventional methods. However, the conversion from a graph to a circuit diagram is not completely reversible.

[0218] Fig. 22 is a schematic diagram showing an example (3) of an electric circuit and a graph network according to the second embodiment. By the processing unit 12A decomposing components with three or more terminals in the electric circuit into two-terminal components, the electric circuit has a structure in which two-terminal components are connected to individual wires, as shown in Fig. 22. In other words, since the electric circuit has a structure in which all two-terminal components are connected, it becomes possible to reversibly convert between a graph and a circuit diagram.

[0219] While the decomposition of components as described above has the advantage of enabling reversible conversion between a graph and a circuit diagram, it is necessary to consider the wiring connecting the decomposed components. In other words, the increase in the number of wiring connecting the decomposed components increases the required information or the amount of calculation, so this is not necessarily better than the first embodiment. For this reason, it is desirable to select and use the information processing method according to the first embodiment or the information processing method according to the second embodiment depending on the inference accuracy required for the graph neural network or the allowable amount of calculation.

[0220] In the second embodiment, the processing unit 12A may also remove the decomposed node and the wiring connected to the node, as long as it does not cause a self-loop or multiple edges. For example, if it is determined that there is no information in the multiple edges or self-loop itself, the node and the wiring connected to the node may be removed. This removal not only speeds up the processing, but also improves the inference accuracy of the graph neural network because unnecessary information is not included.

[0221] 23 is a graph showing an example of the calculation results of inference accuracy by the information processing device 1A according to the second embodiment, showing the results when a component with three or more terminals is disassembled. To compare with the results shown in FIG. 15 , which shows the highest inference accuracy, only the component identification numbers were assigned to the nodes, and only the connection information between the identification numbers was input to the edges. The correct answer data was a classification problem in which nine circuits were classified by type, as in FIG. 15 .

[0222] The same graph neural network that produced the results shown in Figure 15 was trained, including circuit constants, and the trained graph neural network was used to infer the above classification. As a result, the inference accuracy was 95.32%, a 3.58% decrease compared to the results shown in Figure 15. This is presumably because the training included the relationships between two-terminal components obtained by decomposition, and there was insufficient training data to determine these unknowns. As such, the information processing method of embodiment 2 is suitable when highly reversible conversion between a netlist and a graph is required, but there are also cases where the information processing method of embodiment 1 is superior.

[0223] On the other hand, if correct information can be obtained in advance by circuit simulation or the like, the calculated edge weights may not be learned during graph neural network training, and updates may be stopped. In this case, the inference accuracy of the graph neural network can be improved even if a process of decomposing components with three or more terminals into two-terminal components is performed. In this way, it is desirable to selectively use the information processing method according to the first embodiment and the information processing method according to the second embodiment depending on the available data or the purpose.

[0224] In the above example, the correct answer data was the type of circuit. However, the training data could also be the output waveform or frequency characteristics of the output waveform obtained by a circuit simulator. In this case, by utilizing a circuit simulator, it is possible to create as much training data as needed for training. Furthermore, by changing the correct answer data, it is possible to freely train the graph neural network according to the purpose, not limited to the output waveform, by predicting the signal waveform of a specific wiring in the circuit, the area of ​​the eye pattern of the signal waveform, the heat generation of a specific part of the circuit, the cost of the components required to construct the circuit, or the frequency characteristics of the electromagnetic noise that appears at the input terminal.

[0225] Furthermore, by creating and using attribute information data of edges in combination with circuit simulation, it is possible to perform calculations similar to those described above even for directed graphs that include current directionality.

[0226] It is also possible to assign voltage frequency characteristics to nodes or current frequency characteristics to edges. However, as shown in Variation 3, if frequency data is input one frequency at a time into the column of attribute information for nodes or edges of a graph neural network, a large matrix will result, requiring a lot of calculation time and computational effort for learning. In such cases, a high-performance computer with a large memory may be used for learning. However, for example, by learning information in which the frequency characteristics are converted into vector quantities using graph embedding, the amount of calculation can be reduced even for input data with a large matrix containing frequency characteristics in a large-scale circuit, making it possible to learn a graph neural network without using a high-performance computer.

[0227] Furthermore, for an electric circuit having multiple components connected in parallel to a single wiring, the number of component combinations increases even when using the information processing method according to the second embodiment. That is, when an electric circuit has multiple components connected in parallel to a single wiring, the number of corresponding component combinations in the combination list increases approximately in proportion to the square of the number of components connected in parallel to the wiring. As a result, the amount of calculation required to search for a current loop increases exponentially, and the search time also increases.

[0228] Therefore, the information processing device 1A may create a combination list including wiring names and component names so as to suppress an increase in the number of combinations of component names for a large-scale circuit in which multiple components are connected in parallel to a single wiring. For example, as in the first embodiment, the processing unit 12A creates an updated component name list by adding component names indicating ground terminals, input terminals, and output terminals, and creates an updated wiring name list by removing wiring names indicating ground wiring, input wiring, and output wiring. Then, as described above, the processing unit 12A considers components connected to three or more wirings as two-terminal components with the same number of wirings, adds component names indicating the two-terminal components to the updated component name list, and removes component names indicating the components before they were considered two-terminal components from the updated component name list. Furthermore, the processing unit 12A defines a connection relationship in which three or more wirings are connected to one terminal of each two-terminal component and a new wiring connects the other terminals of the two-terminal components, and adds the wiring names indicating the new wiring to the updated wiring name list. After this, the processing unit 12A extracts from the updated component name list component names that correspond to the wiring names in the updated wiring name list, creates a combination list including the extracted component names and their corresponding wiring names, and outputs the updated component name list and combination list. That is, the combination list includes component names that correspond to the wiring names in the updated wiring name list and their corresponding wiring names. A graph network converted from list information including this combination list has the feature that component names and wiring names are represented by nodes, and as shown in FIG. 10 , a node adjacent to a node with any component name becomes a node with the wiring name. This allows the number of combinations to be proportional to the first power of the number of components.

[0229] As described above, in the information processing device 1A according to the second embodiment, the processing unit 12A uses the component name list updated by adding component names indicating ground terminals, input terminals, and output terminals and the wiring name list updated by removing wiring names indicating ground wiring, input wiring, and output wiring, to treat components connected to three or more wirings as two-terminal components with the same number of wirings, and add component names indicating the two-terminal components to the updated component name list, remove component names indicating the components before they were treated as two-terminal components from the updated component name list, connect three or more wirings to one terminal of the two-terminal component, connect the other terminals of the two-terminal component with new wirings, add wiring names indicating the new wirings to the updated wiring name list, extract from the updated component name list component names corresponding to the wiring names in the updated wiring name list, create a combination list including the extracted component names, and output the updated component name list and combination list. This enables the information processing device 1A to provide list information that can suppress information degradation that occurs when converting an electric circuit into a graph network. Furthermore, by defining two-terminal components, it is possible to prevent self-loops or multiple edges, and to suppress the degradation of information that occurs when converting from an electrical circuit to a graph network and from a graph network to an electrical circuit.

[0230] In the information processing device 1A according to the second embodiment, the processing unit 12A creates an updated component name list by adding component names indicating ground terminals, input terminals, and output terminals, and an updated wiring name list by removing wiring names indicating ground wiring, input wiring, and output wiring. The processing unit 12A treats components connected to three or more wirings as two-terminal components with the same number of wirings, and adds component names indicating the two-terminal components to the updated component name list. The processing unit 12A removes component names indicating the components before they were treated as two-terminal components from the updated component name list. The processing unit 12A defines a connection relationship in which three or more wirings are connected to one terminal of each two-terminal component and a new wiring connects the other terminals of the two-terminal component. The processing unit 12A adds wiring names indicating the new wirings to the updated wiring name list. The processing unit 12A extracts component names corresponding to the wiring names in the updated wiring name list from the updated component name list. The processing unit 12A creates a combination list including the extracted component names and their corresponding wiring names. The processing unit 12A outputs the updated component name list and the combination list. This enables the information processing device 1A to provide list information that can suppress information degradation that occurs when converting an electrical circuit into a graph network. Furthermore, the information processing device 1A can suppress an increase in the number of combinations of parts, thereby reducing the amount and time of calculations required for processing a graph neural network using list information including the combination list.

[0231] In the information processing device 1A according to the second embodiment, the processing unit 12A outputs an updated part name list and combination list in which the part names are replaced with unique identification numbers for each feature of the part. This enables the information processing device 1A to reduce the amount of information by expressing the list information as numerical values, and to prevent information degradation that occurs when the list information is converted into a graph network.

[0232] In an information processing method according to a second embodiment, an information processing device 1A performs the following steps: consider a component connected to three or more wires as two-terminal components with the same number of wires, and add component names indicating the two-terminal components to an updated component name list; remove from the updated component name list component names indicating the components before they were considered two-terminal components; connect three or more wires to one terminal of each of the two-terminal components, connect the other terminals of the two-terminal components with new wires, and add wire names indicating the new wires to the updated wire name list; extract, from the updated component name list, component names corresponding to the wire names in the updated wire name list and create a combination list including the extracted component names; and output the updated component name list and combination list. By defining two-terminal components, it is possible to prevent self-loops or multiple edges, and to prevent information degradation during conversion from an electrical circuit to a graph network and from a graph network to an electrical circuit.

[0233] In the information processing device 1A according to the second embodiment, the processing unit 12A removes nodes from two-terminal components as long as the wiring connecting the two-terminal components does not cause a self-loop or multiple edges. This enables the information processing device 1A to provide list information that can suppress information degradation when graph information of an electric circuit is created.

[0234] In an information processing method according to a second embodiment, an information processing device 1A executes the following steps: creating an updated component name list by adding component names indicating ground terminals, input terminals, and output terminals, and an updated wiring name list by removing wiring names indicating ground wiring, input wiring, and output wiring, treating components connected to three or more wirings as two-terminal components with the same number of wirings, and adding component names indicating the two-terminal components to the updated component name list; removing component names indicating the components before they were treated as two-terminal components from the updated component name list; connecting three or more wirings to one terminal of each of the two-terminal components, connecting the other terminals of the two-terminal components with new wirings, and adding wiring names indicating the new wirings to the updated wiring name list; extracting component names corresponding to wiring names in the updated wiring name list from the component names in the updated component name list, creating a combination list including the extracted component names; and outputting the updated component name list and the combination list. This makes it possible to provide list information that can suppress information degradation that occurs when converting an electric circuit into a graph network. Furthermore, by defining two-terminal components, it is possible to prevent self-loops or multiple edges, and to suppress information degradation that occurs when converting from an electrical circuit to a graph network and from a graph network to an electrical circuit.

[0235] In the information processing method according to the second embodiment, the information processing device 1A executes the steps of: extracting, from the component names in the updated component name list, component names that correspond to the wiring names in the updated wiring name list; creating a combination list including the extracted component names and their corresponding wiring names; and outputting the updated component name list and combination list. This makes it possible to provide list information that can suppress information degradation that occurs when converting an electric circuit into a graph network. Furthermore, because an increase in the number of component combinations can be suppressed, the increase in the amount of calculation and the increase in calculation time required for processing a graph neural network using list information including the combination list can be reduced.

[0236] It is possible to combine the embodiments, modify any of the components of the embodiments, or omit any of the components of the embodiments.

[0237] The information processing device according to the present disclosure can be used, for example, for designing a circuit using a circuit design CAD and a board design CAD.

[0238] 1, 1A Information processing device, 11 Acquisition unit, 12, 12A Processing unit, 100 Input interface, 101 Output interface, 102 Processing circuit, 103 Processor, 104 Memory

Claims

1. An acquisition unit that acquires a netlist of an electric circuit; a processing unit that extracts a component name list and a wiring name list from the netlist, updates the component name list by adding component names indicating ground terminals, input terminals, and output terminals, updates the wiring name list by removing wiring names indicating ground wiring, input wiring, and output wiring, extracts component names corresponding to wiring names in the updated wiring name list from component names in the updated component name list, creates a combination list including the extracted component names, and outputs the updated component name list and the combination list.

23. An information processing apparatus comprising:

2. The processing unit includes: A component connected to three or more wirings is regarded as a two-terminal component having the same number of terminals as the number of wirings, and a component name indicating the two-terminal component is added to the updated component name list; removing from the updated part name list a part name indicating a part before it was regarded as a two-terminal part; The three or more wirings are connected to one terminal of the two-terminal component, A new wiring is connected between the other terminals of the two-terminal component, Add a wiring name indicating the new wiring to the updated wiring name list; extracting, from the updated part name list, part names corresponding to wiring names in the updated wiring name list; A combination list including the extracted part names is created, and the updated part name list and combination list are output.

2. The information processing apparatus according to claim 1,

3. An acquisition unit that acquires a netlist of an electric circuit; a processing unit that extracts a component name list and a wiring name list from the netlist, updates the component name list by adding component names indicating ground terminals, input terminals, and output terminals, updates the wiring name list by removing wiring names indicating ground wiring, input wiring, and output wiring, extracts component names corresponding to wiring names in the updated wiring name list from component names in the updated component name list, creates a combination list including the extracted component names and the corresponding wiring names, and outputs the updated component name list and the combination list.

23. An information processing apparatus comprising:

4. The processing unit includes: A component connected to three or more wirings is regarded as a two-terminal component having the same number of terminals as the number of wirings, and a component name indicating the two-terminal component is added to the updated component name list; removing from the updated part name list a part name indicating a part before it was regarded as a two-terminal part; The three or more wirings are connected to one terminal of the two-terminal component, A new wiring is connected between the other terminals of the two-terminal component, Add a wiring name indicating the new wiring to the updated wiring name list; extracting, from the updated part name list, part names corresponding to wiring names in the updated wiring name list; A combination list including the extracted part names and the corresponding wiring names is created, and the updated part name list and combination list are output.

4. The information processing apparatus according to claim 3.

5. The processing unit outputs the updated part name list and the combination list in which part names are replaced with unique identification numbers common to each feature of the parts.

5. The information processing device according to claim 1, wherein the information processing device is a computer.

6. The processing unit defines the unique identification number common to each type of part.

6. The information processing apparatus according to claim 5,

7. The processing unit defines the unique identification number common to each model number of the part.

6. The information processing apparatus according to claim 5,

8. The processing unit replaces the part names in the updated part name list with rows or columns of a feature quantity matrix obtained by one-hot expressing the features of the parts.

6. The information processing apparatus according to claim 5,

9. The processing unit replaces elements corresponding to passive circuits in the feature matrix with function values ​​calculated by substituting circuit constants of components into a function including a logarithm.

9. The information processing apparatus according to claim 8,

10. The processing unit performs normalization and / or standardization on the function values.

10. The information processing apparatus according to claim 9,

11. The processing unit removes a node from the two-terminal component as long as a self-loop or multiple edges are not generated in a wiring connecting the two-terminal components.

3. The information processing apparatus according to claim 2.

12. the part name list is a node in a graph network; the list of wiring names is an edge in the graph network; The combination list is an adjacency matrix in the graph network.

5. The information processing device according to claim 1, wherein the information processing device is a computer.

13. The processing unit sets the combination of nodes and edges as input data for a graph neural network.

13. The information processing apparatus according to claim 12.

14. An information processing device, obtaining a netlist of an electrical circuit; extracting a component name list and a wiring name list from the netlist; creating an updated part name list by adding part names indicating ground terminals, input terminals, and output terminals; creating an updated wiring name list by removing wiring names indicating ground wiring, input wiring, and output wiring; extracting, from the part names in the updated part name list, part names corresponding to wiring names in the updated wiring name list, and creating a combination list including the extracted part names; and outputting the updated part name list and the combination list.

23. An information processing method comprising: