Substrate for semiconductor device

Abstract

A substrate for a semiconductor device according to the present invention comprises: a silicon nitride ceramic substrate that has a first surface and a second surface; brazing material layers that are positioned on the first surface and the second surface; and a copper plate that is positioned on a bonding layer, wherein there is a region in which the hardness decreases along the thickness direction of the copper plate from the interface between the bonding layer and the copper plate.

Description

Substrate for semiconductor device

[0001] The present invention relates to a substrate for a semiconductor device.

[0002] BACKGROUND ART As a substrate for a semiconductor device used in a power transistor module or the like, a substrate in which a copper plate is provided on the surface of a silicon nitride ceramic substrate via a bonding agent is known (for example, Patent Document 1).

[0003] Japanese Patent Application Laid-Open No. 2022-173209

[0004] However, durability under thermal cycling has been an issue for substrates for semiconductor devices, and there has been a demand for a substrate for semiconductor devices that can prevent peeling of the copper plate even under such an environment. The present invention has been made to solve this problem, and an object of the present invention is to provide a substrate for semiconductor devices that can prevent peeling of the copper plate even under thermal cycling.

[0005] Item 1. A substrate for a semiconductor device comprising: a ceramic substrate having a first surface and a second surface; a brazing filler metal layer disposed on the first surface and the second surface; and a copper plate disposed on the bonding layer, wherein the copper plate has a thickness of 0.3 mm or more, and the copper plate has a region of reduced hardness along the thickness direction of the copper plate between the interface between the bonding layer and the copper plate and a position spaced 100 μm in the thickness direction from the interface.

[0006] Item 2. The substrate for a semiconductor device according to Item 1, wherein at least one of the copper plates is patterned.

[0007] Item 3. The substrate for a semiconductor device according to Item 1 or 2, wherein the copper plate has a nanoindentation hardness of 1.2 GPa to 2.3 GPa at a first position 10 μm away from the interface in the thickness direction, and the nanoindentation hardness at a position farther away from the interface than the first position is lower than the nanoindentation hardness at the first position.

[0008] Item 4. The substrate for a semiconductor device according to any one of Items 1 to 3, wherein the copper plate has a nanoindentation hardness of 0.7 GPa to 1.3 GPa at a second position 30 μm away from the interface in the thickness direction, and the nanoindentation hardness at a position farther away from the interface than the second position is lower than the nanoindentation hardness at the second position.

[0009] Item 5. The substrate for a semiconductor device according to any one of Items 1 to 4, wherein the copper plate has a nanoindentation hardness of 0.5 GPa to 1.1 GPa at a third position 100 μm away from the interface in the thickness direction, and the nanoindentation hardness at a position farther away from the interface than the third position is lower than the nanoindentation hardness at the third position.

[0010] According to the substrate for a semiconductor device of the present invention, a bonded substrate having high durability against thermal cycles can be obtained, and peeling of the copper plate due to temperature changes can be suppressed.

[0011] 1 is a cross-sectional view showing an embodiment of a semiconductor device having a substrate for a semiconductor device according to the present invention; FIG. 1 is a cross-sectional view showing the interface between a copper plate and a bonding layer; FIG. 2 is a flowchart showing a method for manufacturing a substrate for a semiconductor device; FIG. 3 is a cross-sectional view showing the manufacturing process of a substrate for a semiconductor device; FIG. 4 is a cross-sectional view showing the manufacturing process of a substrate for a semiconductor device; FIG. 5 is a cross-sectional view showing the manufacturing process of a substrate for a semiconductor device; FIG. 6 is a temperature profile in the manufacturing process of a substrate for a semiconductor device; FIG. 7 is a graph showing a general tendency showing the relationship between stress when a force is applied in a direction to peel the plate from the bonding layer and the distance in a planar direction from an end of a circuit pattern; and FIG. 8 is a cross-sectional view explaining the horizontal axis of FIG.

[0012] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a substrate for a semiconductor device according to the present invention will now be described with reference to the accompanying drawings. Fig. 1 is a cross-sectional view of an example of a semiconductor device having a substrate for a semiconductor device according to this embodiment.

[0013] <1. Overview of Semiconductor Device> The semiconductor device according to this embodiment is used as a power module in various electronic devices such as smartphones, personal computers, large home appliances, railways, electric vehicles, power generation (wind power generation, solar power generation, fuel cells, etc.), air conditioners, industrial robots, commercial elevators, home microwave ovens, induction electric rice cookers, and UPS (uninterruptible power supplies).

[0014] As shown in FIG. 1, the semiconductor device 1 according to this embodiment includes a substrate 2 for a semiconductor device, a first bonding material 5, a second bonding material 5', a semiconductor chip 6, bonding wires 7, and a heat sink 8.

[0015] The substrate 2 for a semiconductor device includes a plate-shaped ceramic substrate 3 which is an insulator, a first copper plate 4 bonded to the upper surface (first surface) of the ceramic substrate 3 via a bonding layer 9, and a second copper plate 4′ bonded to the lower surface (second surface) via a bonding layer 9. The ceramic substrate 3 may be, for example, an aluminum oxide substrate, an aluminum nitride substrate, or a silicon nitride substrate.

[0016] The bonding layer 9 may contain an active metal. The active metal may be, for example, at least one active metal selected from the group consisting of titanium and zirconium. Alternatively, the bonding layer 9 may contain a metal other than the active metal. The metal other than the active metal contained in the bonding layer 9 may be, for example, at least one metal selected from the group consisting of silver, copper, indium, and tin. The bonding layer 9 may also contain nitrogen and / or silicon supplied from the ceramic substrate 3, and the supplied nitrogen and / or silicon may form a compound with the active metal. Furthermore, the bonding layer 13 may contain copper supplied from the copper plate 12.

[0017] The first copper plate 4 is patterned to form a transmission circuit, while the second copper plate 4' is formed in a flat plate shape.

[0018] A semiconductor chip 6 is bonded to the upper surface of the semiconductor device substrate 2, i.e., to a part of the upper surface of the first copper plate 4, via a first bonding material 5. The semiconductor chip 6 and the first copper plate 4 are also connected by bonding wires 7.

[0019] On the other hand, a heat sink 8 is bonded to the lower surface of the semiconductor device substrate 2, i.e., the lower surface of the second copper plate 4′, via a second bonding material 5′. The heat sink 8 is a known material and can be made of a metal such as copper.

[0020] The thicknesses of the ceramic substrate 3, copper plates 4, 4', and bonding layer 9 are not particularly limited, but for example, the thickness of the ceramic substrate is preferably 0.2 to 0.65 mm. The thickness of the copper plate is 0.3 mm or more, preferably 0.5 mm or more, and more preferably 0.8 mm or more. A thicker copper plate improves heat dissipation. The upper limit of the copper plate thickness is not particularly limited, but may be, for example, 2.0 mm or less. The thickness of the bonding layer is preferably 0.1 to 20 μm.

[0021] 2. Characteristics of the Substrate for a Semiconductor Device The substrate 2 for a semiconductor device according to this embodiment is characterized in that the hardness decreases along the thickness direction of each of the copper plates 4, 4′ in the range between the interface between the bonding layer 9 and each of the copper plates 4, 4′ and a position at least 100 μm away from this interface, as shown in FIG. 2. The specific hardness profile is not particularly limited, but is preferably configured as follows, for example.

[0022] (1) In the copper plates 4, 4', the nanoindentation hardness at a first position 10 μm away in the thickness direction from the interface with the bonding layer 9 is 1.2 GPa to 2.3 GPa. (2) In the copper plates 4, 4', the nanoindentation hardness at a second position 30 μm away in the thickness direction from the interface with the bonding layer 9 is 0.7 GPa to 1.3 GPa. (3) In the copper plates 4, 4', the nanoindentation hardness at a third position 100 μm away in the thickness direction from the interface with the bonding layer 9 is 0.5 GPa to 1.1 GPa.

[0023] The above (1) to (3) are merely examples, but it is preferable to satisfy (1), more preferably (1) and (2), and more preferably all of (1) to (3). In this embodiment, the hardness decreases with increasing distance from the interface in at least the region up to 100 μm from the interface (third position). However, for example, when satisfying (1) above, it is sufficient that the nanoindentation hardness on the third position side of the first position is lower than the nanoindentation hardness at the first position. In other words, the nanoindentation hardness at the second and third positions do not necessarily have to be the nanoindentation hardnesses shown in (2) and (3) above. When satisfying (1) and (2) above, it is sufficient that the nanoindentation hardness on the third position side of the second position is lower than the nanoindentation hardness at the second position. In other words, the nanoindentation hardness at the third position does not necessarily have to be the nanoindentation hardness shown in (3) above.

[0024] The nanoindentation hardness can be measured as follows. First, a region on the surface of the copper plates 4, 4' of the semiconductor device substrate 2 is selected, where a length of 10 mm or more can be ensured. In other words, a region on the copper plates 4, 4' that is not divided by patterning and where a length of 10 mm or more can be ensured is selected. Next, a length of 10 mm is selected, and the semiconductor device substrate 2 is cut so that a cross section including the midpoint of the selected length is exposed. Subsequently, the cut surface is polished by ion milling.

[0025] Next, as shown in Figure 2, three lines sandwiching the midpoint are determined on the cross section after polishing. The first line passes through the midpoint and extends perpendicularly from the interface in the thickness direction. The second line is a line 30 µm away from the first line. The third line is a line 30 µm away from the first line on the opposite side of the second line.

[0026] Next, the nanoindentation hardness is measured on each line at a first position 10 μm away from the interface, a second position 30 μm away from the interface, and a third position 100 μm away from the interface using a nanoindenter. The nanoindentation hardnesses measured at the first, second, and third positions on each line are then averaged to obtain the nanoindentation hardnesses at the first, second, and third positions.

[0027] The above measurement method and measurement results can be applied to both substrates for semiconductor devices in which the copper plates 4, 4' are patterned as shown in FIG. 1, and substrates for semiconductor devices in which no patterning is applied.

[0028] 3. Manufacturing Method of Substrate for Semiconductor Device> Next, a manufacturing method of a substrate for a semiconductor device will be described. Fig. 3 is a flowchart showing the manufacturing method of a substrate for a semiconductor device according to this embodiment. Figs. 4, 5, and 6 are cross-sectional views schematically showing intermediate products obtained during the manufacturing of the substrate for a semiconductor device.

[0029] First, a ceramic substrate 3 is prepared (step S1). Next, as shown in FIG. 4, brazing filler metal layers 9i are formed on the upper and lower surfaces of the ceramic substrate 3 (step S2). At this time, a paste containing an active metal brazing filler metal, a binder, and a solvent is prepared as the brazing filler metal layer 9i. This paste may further contain a dispersant, an antifoaming agent, etc. Next, the prepared paste is screen-printed on the upper and lower surfaces of the ceramic substrate 3. As a result, a screen-printed film is formed on each surface of the ceramic substrate 3. Next, the solvent contained in the formed screen-printed film is volatilized. As a result, the screen-printed film is transformed into the brazing filler metal layer 9i. The brazing filler metal layer 9i contains an active metal brazing filler metal and a binder. However, the brazing filler metal layer 9i may be formed by a method other than this method.

[0030] The active metal brazing material includes a hydrogenation active metal powder and a metal powder. The hydrogenation active metal powder includes a hydride of at least one active metal selected from the group consisting of titanium and zirconium. The metal powder includes silver. The metal powder may include a metal other than silver. The metal other than silver is at least one metal selected from the group consisting of copper, indium, and tin. When at least one metal selected from the group consisting of copper, indium, and tin is included in the active metal brazing material, the melting point of the active metal brazing material decreases.

[0031] The active metal brazing material is preferably made of a powder having an average particle size of 0.1 μm or more and 20 μm or less. The average particle size can be obtained by measuring the particle size distribution using a commercially available laser diffraction particle size distribution measuring device and calculating the D50 (median diameter) from the measured particle size distribution. By using a powder having such a small average particle size for the active metal brazing material, the brazing material layer 9i can be made thin.

[0032] The brazing material layer 9i preferably has a thickness of 0.1 μm or more and 20 μm or less, and more preferably has a thickness of 0.1 μm or more and 5 μm or less.

[0033] 5, the copper plates 4, 4' are placed on the formed brazing material layer 9i (step S3), thereby obtaining an intermediate product 2i including the ceramic substrate 3, the copper plates 4, 4', and the brazing material layer 9i.

[0034] Next, the obtained intermediate product 2i is subjected to a heat and pressure treatment (step S4). This produces a bonding layer 9 as shown in Fig. 6. As a result, a substrate 2 for a semiconductor device is obtained, which includes a ceramic substrate 3, copper plates 4, 4', and a bonding layer 9, as shown in Fig. 6. The copper plates 4, 4' are bonded to the ceramic substrate 3 by the bonding layer 9.

[0035] When the intermediate product 2i is subjected to the heating and pressurizing treatment, the heating is performed according to the temperature profile shown in Fig. 7. As shown in Fig. 7, the temperature inside the furnace is raised in a vacuum atmosphere so that the temperature of the intermediate product 2i reaches a maximum of 800 to 900°C. The temperature rise rate at this time can be set to, for example, 2 to 10°C / min. In this process, during the time period from the bonding layer formation temperature range of approximately 750°C or higher until nitrogen substitution, the vacuum atmosphere inside the furnace is maintained at 10 -2 The pressure is adjusted to be equal to or less than 0.2 Pa. Pressurization is applied to the intermediate product 2i during the temperature increase process and until cooling is completed. At this time, the surface pressure applied to the intermediate product 2i can be adjusted to, for example, 0.2 Pa to 22 MPa. By applying pressure, the ceramic, the bonding layer, and the copper plate can be reliably contacted and reacted with each other, thereby forming a bonding layer.

[0036] Next, the temperature of the intermediate product 2i is maintained at 800 to 900°C for 30 to 60 minutes, and then the intermediate product 2i is cooled. Next, when the temperature of the intermediate product reaches 650 to 800°C, an inert gas such as nitrogen is injected into the furnace, and the temperature is lowered in the inert gas atmosphere. The pressure at this time is preferably equivalent to atmospheric pressure or higher. A bonding layer 9 is formed in a vacuum atmosphere.

[0037] In the process of cooling the intermediate product 2i, it is rapidly cooled from 800-900° C. to 200-300° C. at a rate of approximately 2.8-12° C. / min. After the rapid cooling, it is slowly cooled to room temperature.

[0038] Next, the copper plate 4 and the bonding layer 9 are patterned by etching or the like (step S5). As a result, the copper plate 4 is transformed into the patterned copper plate 4 shown in Fig. 1. The bonding layer 9 is also transformed into the patterned bonding layer 13 shown in Fig. 1.

[0039] <4. Features> As described above, in this embodiment, the hardness decreases along the thickness direction of the copper plates 4, 4′ in the range between the interface between the bonding layer 9 and the copper plates 4, 4′ and a position at least 100 μm away from this interface. That is, in the vicinity of the interface between the bonding layer 9 and the copper plates 4, 4′, the hardness decreases with increasing distance from the interface in the thickness direction, thereby preventing peeling of the copper plates 4, 4′. This point will be described with reference to FIGS. 8 and 9 .

[0040] FIG. 8 shows the stress distribution at the bonding interface during thermal cycling. FIG. 9 illustrates the horizontal axis of FIG. 8 . During thermal cycling, high stress is generated at the bonding interface due to the difference in thermal expansion between the copper 4, 4' and the ceramic substrate 3. As shown in FIG. 8 , if the copper plates 4, 4' have a gradient that reduces the hardness of the copper, the force is dispersed, and the peak value of the stress at the interface is reduced. Therefore, the peak value of stress near the edges of the copper plates 4, 4' (especially in the region close to X = 0 in FIGS. 8 and 9 ) is reduced below the threshold at which peeling occurs, thereby preventing peeling of the edges of the copper plates 4, 4'.

[0041] Furthermore, while a thicker copper plate 4, 4' improves heat dissipation, it also increases the likelihood of peeling of the copper plate 4, 4' during thermal cycling. However, in this embodiment, because the copper plate 4, 4 has the hardness gradient described above, peeling due to thermal cycling can be effectively suppressed even when the copper plate 4, 4' is thick.

[0042] Examples of the present invention will be described below, but the present invention is not limited to the following examples.

[0043] 1. Fabrication of a Substrate for a Semiconductor Device A silicon nitride ceramic substrate having a thickness of 0.32 mm and a copper plate having a thickness of 0.8 mm were prepared. A brazing filler metal having a thickness of 0.1 μm to 20 μm and containing an active metal brazing filler metal containing 40 wt % to 95 wt % silver and titanium hydride was also prepared. This brazing filler metal was then applied to the top and bottom surfaces of the silicon nitride ceramic substrate by screen printing, and a copper plate was placed on top to form an intermediate product.

[0044] Next, this intermediate product was placed in a furnace and heated according to the temperature profile shown in Figure 7. In the temperature-raising process, the temperature was raised to approximately 850°C at approximately 5°C / min, and when it exceeded 750°C, a pressure of approximately 20 MPa was applied. Thereafter, cooling was carried out at the cooling rates shown in Tables 2 to 5, and when it had dropped to approximately 250°C, it was slowly cooled to room temperature. In this way, substrates for semiconductor devices according to Examples 1 to 9 and Comparative Example 1 were completed. That is, in this example, three substrates for semiconductor devices were produced at one cooling rate. Note that copper plate patterning was not performed on these semiconductor substrates.

[0045] <2. Evaluation> The nanoindentation hardness was measured at the first to third positions described above for the substrates for semiconductor devices according to Examples 1 to 9 and Comparative Example 1. The measurement conditions were as shown in Table 1, and the results were as shown in Table 2.

[0046] Next, a thermal cycle test was conducted on the semiconductor device substrates according to Examples 1 to 9 and Comparative Example 1. That is, after 3,000 cycles of temperature increase and decrease between -40°C and 175°C, an ultrasonic flaw detection test was conducted to check for peeling at the edge of the copper plate. The ultrasonic flaw detection test was conducted using a Hitachi Power Solutions ultrasonic flaw detection device FSesIII, using the reflection method. The results are as follows: those in which no peeling was confirmed were rated as OK, and those in which no peeling was confirmed were rated as NO. In the images obtained by the ultrasonic flaw detection test, gaps are generated between the copper plate and the bonding layer in the areas where peeling has occurred, and these gaps appear white, allowing the peeling to be confirmed.

[0047] The results in Table 6 confirm that a copper plate having a hardness gradient in which the nanoindentation hardness decreases from the first position to the third position does not peel off in the thermal cycle test. On the other hand, in Comparative Example 1, which does not have such a hardness gradient, peeling of the copper plate occurred. Therefore, it was found that if the copper plate has the above-mentioned hardness gradient, peeling of the copper plate can be suppressed.

[0048] 2... Substrate for semiconductor device 3... Ceramic substrate 4, 4'... Copper plate 9... Bonding layer

Claims

1. A substrate for a semiconductor device comprising: a ceramic substrate having a first surface and a second surface; a bonding layer disposed on the first surface and the second surface; and a copper plate disposed on the bonding layer, wherein the copper plate has a thickness of 0.3 mm or more, and the copper plate has a region of reduced hardness along the thickness direction of the copper plate between the interface between the bonding layer and the copper plate and a position 100 μm away in the thickness direction.

2. The substrate for a semiconductor device according to claim 1, wherein at least one of said copper plates is patterned.

3. A substrate for a semiconductor device as described in claim 1 or 2, wherein the copper plate has a nanoindentation hardness of 1.2 GPa to 2.3 GPa at a first position 10 μm away from the interface in the thickness direction, and the nanoindentation hardness at a position farther away from the interface than the first position is lower than the nanoindentation hardness at the first position.

4. A substrate for a semiconductor device as described in claim 3, wherein the nanoindentation hardness at a second position in the copper plate that is 30 μm away from the interface in the thickness direction is 0.7 GPa to 1.3 GPa, and the nanoindentation hardness at a position that is farther away from the interface than the second position is lower than the nanoindentation hardness at the second position.

5. A substrate for a semiconductor device as described in claim 4, wherein the nanoindentation hardness at a third position in the copper plate that is 100 μm away from the interface in the thickness direction is 0.5 GPa to 1.1 GPa, and the nanoindentation hardness at a position that is farther away from the interface than the third position is lower than the nanoindentation hardness at the third position.

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