Switching element drive circuit and power conversion device

Abstract

The present invention increases the voltage across a first capacitor. In a switching element drive circuit (2), a first bootstrap circuit (71) includes a first capacitor (C1) and a first diode (D11) connected to the first capacitor (C1). A second bootstrap circuit (72) includes a second capacitor (C2) and a second diode (D12) connected thereto. A third bootstrap circuit (73) includes a third capacitor (C3) and a third diode (D13) connected thereto. A power supply unit (9) is connected in parallel to a fourth gate driver (64). The anode of the third diode (D13) is connected to the power supply unit (9). The anode of the second diode (D12) is connected to the cathode of the third diode (D13). The anode of the first diode (D11) is connected to the cathode of the third diode (D13) without passing through the second diode (D12).

Description

Switching element drive circuit and power conversion device

[0001] The present disclosure relates to a switching element drive circuit and a power conversion device, and more particularly to a switching element drive circuit that drives four switching elements of a diode-clamped three-level inverter, and a power conversion device including the switching element drive circuit.

[0002] Japanese Patent Application Laid-Open No. 2006-129999 (Patent Document 1) discloses a switching element drive circuit for a three-level neutral point clamped inverter, which includes first, second, third, and fourth switching elements connected in series between the positive and negative terminals of a DC power supply. The switching element drive circuit includes an element drive power supply with the negative terminal as a potential reference, a fourth element drive unit (fourth gate driver), a third diode, a third element drive unit (third gate driver), a third capacitor, a second diode, a second element drive unit (second gate driver), a second capacitor, a first diode, a first element drive unit (first gate driver), and a first capacitor. The fourth element drive unit is connected between the positive and negative terminals of the element drive power supply and drives the fourth switching element. The third diode has an anode connected to the positive terminal of the element drive power supply. The third element drive unit is connected between the cathode of the third diode and a common connection point of the third and fourth switching elements and drives the third switching element. The third capacitor is connected in parallel to the third element driving unit. The second diode has an anode connected to the cathode of the third diode. The second element driving unit is connected between the cathode of the second diode and a common connection point of the second and third switching elements, and drives the second switching element. The second capacitor is connected in parallel to the second element driving unit. The first diode has an anode connected to the cathode of the second diode. The first element driving unit is connected between the cathode of the first diode and a common connection point of the first and second switching elements, and drives the first switching element. The first capacitor is connected in parallel to the first element driving unit.

[0003] Japanese Patent Application Laid-Open No. 2018-133876

[0004] In the switching element drive circuit disclosed in Patent Document 1, the voltage across the first capacitor may drop significantly below the voltage across the second capacitor and the voltage across the third capacitor.

[0005] An object of the present disclosure is to provide a switching element drive circuit and a power conversion device that can increase the voltage across the first capacitor.

[0006] A switching element drive circuit according to one aspect of the present disclosure drives a diode-clamped three-level inverter. The diode-clamped three-level inverter has a first switching element, a second switching element, a third switching element, and a fourth switching element connected in series between a positive electrode and a negative electrode of a DC power supply unit. The switching element drive circuit includes a first gate driver, a second gate driver, a third gate driver, a fourth gate driver, a first bootstrap circuit, a second bootstrap circuit, a third bootstrap circuit, and a power supply unit. The first gate driver drives the first switching element. The second gate driver drives the second switching element. The third gate driver drives the third switching element. The fourth gate driver drives the fourth switching element. The first bootstrap circuit includes a first capacitor connected in parallel to the first gate driver and a first diode having a cathode connected to the first capacitor. The second bootstrap circuit includes a second capacitor connected in parallel to the second gate driver and a second diode having a cathode connected to the second capacitor. The third bootstrap circuit includes a third capacitor connected in parallel to the third gate driver and a third diode having a cathode connected to the third capacitor. The power supply unit is connected in parallel to the fourth gate driver. The anode of the third diode is connected to the power supply unit. The anode of the second diode is connected to the cathode of the third diode. The anode of the first diode is connected to the cathode of the third diode without passing through the second diode.

[0007] A power conversion device according to one aspect of the present disclosure includes the switching element drive circuit of the above aspect, the diode clamped three-level inverter, and a control unit, wherein the control unit controls the switching element drive circuit.

[0008] The switching element drive circuit and power conversion device of the present disclosure have the advantage of being able to further increase the voltage across the first capacitor.

[0009] FIG. 1 is a circuit diagram of a power conversion device including a switching element drive circuit according to the present disclosure. FIG. 2 is an explanatory diagram of a current path when a switching circuit in the power conversion device of embodiment 1 is in a first switching state. FIG. 3 is an explanatory diagram of a switching circuit in the power conversion device of embodiment 1 when in the first switching state. FIG. 4 is an explanatory diagram of a current path when a switching circuit in the power conversion device of embodiment 1 is in a second switching state. FIG. 5 is an explanatory diagram of a charging path when a switching circuit in the power conversion device of embodiment 1 is in the second switching state. FIG. 6 is an explanatory diagram of a current path when a switching circuit in the power conversion device of embodiment 1 is in a third switching state. FIG. 7 is an explanatory diagram of a charging path when a switching circuit in the power conversion device of embodiment 1 is in the third switching state. FIG. 8 is a waveform diagram of an output current in the power conversion device of embodiment 1. FIG. 9 is an explanatory diagram of voltage command values ​​for each phase in the power conversion device of embodiment 1. FIG. 10 is an explanatory diagram of a group of voltage vectors related to the power conversion device of embodiment 1. FIG. 11 is a more detailed explanatory diagram of a group of voltage vectors related to the power conversion device of embodiment 1. FIG. 12 is a vector diagram for explaining the operation of the control unit in the power conversion device of embodiment 1. FIG. 13 is a diagram showing a time chart of the switching states of each phase of the power conversion device of embodiment 1. FIG. 14 is a diagram showing a time chart of the on / off states of the first to fourth switching elements of the power conversion device of embodiment 1. FIG. 15 is an operational waveform diagram of the power conversion device of embodiment 1. FIG. 16 is an explanatory diagram of a current path when the switching circuit is in a fourth switching state in the power conversion device of embodiment 2. FIG. 17 is an explanatory diagram of a charging path when the switching circuit is in the fourth switching state in the power conversion device of embodiment 2. FIG. 18 is an explanatory diagram of the operation of the power conversion device of embodiment 2. FIG. 19 is an operational waveform diagram of the power conversion device of embodiment 2. FIG. 20 is an operational waveform diagram of the power conversion device of embodiment 2. FIG. 21 is an explanatory diagram of the operation of the power conversion device of embodiment 3. FIG. 22 is a circuit diagram of a power conversion device of embodiment 4.

[0010] First Embodiment A power conversion device 100 including a switching element drive circuit according to a first embodiment will be described below with reference to FIGS.

[0011] (1) Switching Element Drive Circuit A switching element drive circuit 2 according to the first embodiment will be described with reference to the drawings.

[0012] FIG. 1 is a circuit diagram of a power conversion device 100 including a switching element drive circuit 2 according to the present disclosure. As shown in FIG. 1 , the switching element drive circuit 2 according to the first embodiment is a circuit that drives a diode-clamped three-level inverter 1 (hereinafter also referred to as inverter circuit 1). The inverter circuit 1 includes a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4 that are connected in series between a positive electrode P1 and a negative electrode N1 of a DC power supply unit 3. The switching element drive circuit 2 includes a first gate driver 61, a second gate driver 62, a third gate driver 63, a fourth gate driver 64, a first bootstrap circuit 71, a second bootstrap circuit 72, a third bootstrap circuit 73, and a power supply unit 9. The first gate driver 61 drives the first switching element Q1. The second gate driver 62 drives the second switching element Q2. The third gate driver 63 drives the third switching element Q3. The fourth gate driver 64 drives the fourth switching element Q4.

[0013] (2) Circuit Configuration of Switching Element Drive Circuit and Power Conversion Apparatus Hereinafter, the circuit configuration of the switching element drive circuit 2 and the power conversion apparatus 100 according to the first embodiment will be described with reference to the drawings.

[0014] (2.1) Circuit Configuration of the Power Conversion Device As shown in FIG. 1 , for example, the power conversion device 100 includes a DC power supply unit 3, a plurality of (three in the example of FIG. 1 ) inverter circuits 1, and a control device 6 having a plurality of switching element drive circuits 2 (hereinafter also referred to as drive circuits 2). The DC power supply unit 3 has a positive electrode P1, a negative electrode N1, and an intermediate potential point M1. The plurality of inverter circuits 1 are connected between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The control device 6 controls the plurality of inverter circuits 1. The "intermediate potential point M1" is a point at an intermediate potential between the potential of the positive electrode P1 and the potential of the negative electrode N1 of the DC power supply unit 3.

[0015] The power conversion device 100 is a diode-clamped three-level three-phase inverter. In the power conversion device 100, a plurality of inverter circuits 1 each have an output terminal 41. In the power conversion device 100, an AC load RA1 is connected to a plurality of (three in the example of FIG. 1 ) output terminals 41.

[0016] The AC load RA1 is, for example, a three-phase servo motor. In the power conversion device 100, one of the multiple inverter circuits 1 is an inverter circuit 1U that outputs a U-phase voltage, another is an inverter circuit 1V that outputs a V-phase voltage, and the remaining is an inverter circuit 1W that outputs a W-phase voltage.

[0017] Each of the inverter circuits 1 includes a switching circuit 10, a first clamp diode D5, and a second clamp diode D6. In the power conversion device 100, the potential of the intermediate potential point M1 is clamped by the first clamp diode D5 and the second clamp diode D6 of each inverter circuit 1.

[0018] Each switching circuit 10 has a first switching element Q1, a second switching element Q2, a third switching element Q3, and a fourth switching element Q4. In each switching circuit 10, the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are connected in series from the positive electrode P1 side to the negative electrode N1 side of the DC power supply unit 3 in the order of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4.

[0019] Each switching circuit 10 further includes four diodes D1 to D4. Diode D1 is connected in anti-parallel to the first switching element Q1. Diode D2 is connected in anti-parallel to the second switching element Q2. Diode D3 is connected in anti-parallel to the third switching element Q3. Diode D4 is connected in anti-parallel to the fourth switching element Q4. A first clamp diode D5 is connected between a first connection point 11 between the first switching element Q1 and the second switching element Q2 and an intermediate potential point M1. A second clamp diode D6 is connected between a second connection point 12 between the third switching element Q3 and the fourth switching element Q4 and the intermediate potential point M1.

[0020] The control device 6 has a plurality of (three in the example of FIG. 1 ) drive circuits 2 and a control unit 60. The plurality of drive circuits 2 correspond one-to-one to the plurality of (three in the example of FIG. 1 ) inverter circuits 1.

[0021] In each of the plurality of drive circuits 2, the first bootstrap circuit 71 includes a first capacitor C1 connected in parallel to the first gate driver 61 and a first diode D11 connected in series to the first capacitor C1. In each of the plurality of drive circuits 2, the second bootstrap circuit 72 includes a second capacitor C2 connected in parallel to the second gate driver 62 and a second diode D12 connected in series to the second capacitor C2. In each of the plurality of drive circuits 2, the third bootstrap circuit 73 includes a third capacitor C3 connected in parallel to the third gate driver 63 and a third diode D13 connected in series to the third capacitor C3.

[0022] In each of the plurality of drive circuits 2, the power supply unit 9 is connected in parallel to the fourth gate driver 64. In each of the plurality of drive circuits 2, the anode of the third diode D13 is connected to the power supply unit 9. In each of the plurality of drive circuits 2, the anode of the second diode D12 is connected to the cathode of the third diode D13. In each of the plurality of drive circuits 2, the anode of the first diode D11 is connected to the cathode of the third diode D13 without passing through the second diode D12.

[0023] (2.2) Details of the Power Conversion Device The DC power supply unit 3 includes a fourth capacitor C11 and a fifth capacitor C12. In the DC power supply unit 3, the fourth capacitor C11 and the fifth capacitor C12 are connected in series. The DC power supply unit 3 further includes a first DC terminal 31 connected to the positive electrode P1 and a second DC terminal 32 connected to the negative electrode N1. In the DC power supply unit 3, a first end of the fourth capacitor C11 is connected to the first DC terminal 31, a second end of the fourth capacitor C11 is connected to a first end of the fifth capacitor C12, and a second end of the fifth capacitor C12 is connected to the second DC terminal 32. In the DC power supply unit 3, the connection point between the fourth capacitor C11 and the fifth capacitor C12 is an intermediate potential point M1. For example, a DC voltage source E1 is connected between the first DC terminal 31 and the second DC terminal 32. In this case, the output voltage Vdc of the DC voltage source E1 is applied between the positive electrode P1 and the negative electrode N1 of the DC power supply unit 3. The capacitance of the fifth capacitor C12 is the same as the capacitance of the fourth capacitor C11. The phrase "the capacitance of the fifth capacitor C12 is the same as the capacitance of the fourth capacitor C11" does not necessarily mean that the capacitance of the fifth capacitor C12 exactly matches the capacitance of the fourth capacitor C11, but may mean that the capacitance of the fifth capacitor C12 is within a range of 95% to 105% of the capacitance of the fourth capacitor C11.

[0024] Hereinafter, for convenience of explanation, with regard to the multiple switching circuits 10, the switching circuit 10 included in inverter circuit 1U may be referred to as switching circuit 10U, the switching circuit 10 included in inverter circuit 1V may be referred to as switching circuit 10V, and the switching circuit 10 included in inverter circuit 1W may be referred to as switching circuit 10W. Furthermore, of the multiple output terminals 41, the output terminal 41 included in inverter circuit 1U may be referred to as output terminal 41U, the output terminal 41 included in inverter circuit 1V may be referred to as output terminal 41V, and the output terminal included in inverter circuit 1W may be referred to as output terminal 41W.

[0025] The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 have a control terminal, a first main terminal, and a second main terminal. The first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are, for example, insulated gate bipolar transistors (IGBTs). Therefore, the control terminal, the first main terminal, and the second main terminal of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 of each switching circuit 10 are, respectively, a gate terminal, a collector terminal, and an emitter terminal.

[0026] A control terminal of the first switching element Q1 of each switching circuit 10 is connected to a corresponding one of the plurality of first gate drivers 61. A control terminal of the second switching element Q2 of each switching circuit 10 is connected to a corresponding one of the plurality of second gate drivers 62. A control terminal of the third switching element Q3 of each switching circuit 10 is connected to a corresponding one of the plurality of third gate drivers 63. A control terminal of the fourth switching element Q4 of each switching circuit 10 is connected to a corresponding one of the plurality of fourth gate drivers 64.

[0027] In each switching circuit 10, a first main terminal of a first switching element Q1 is connected to a positive electrode P1 of the DC power supply 3, and a second main terminal of the first switching element Q1 is connected to a first main terminal of a second switching element Q2. In each switching circuit 10, a second main terminal of the second switching element Q2 is connected to a first main terminal of a third switching element Q3. In each switching circuit 10, a second main terminal of the third switching element Q3 is connected to a first main terminal of a fourth switching element Q4, and a second main terminal of the fourth switching element Q4 is connected to a negative electrode N1 of the DC power supply 3.

[0028] In the inverter circuit 1U, a third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10U is connected to the output terminal 41U. In the inverter circuit 1V, a third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10V is connected to the output terminal 41V. In the inverter circuit 1W, a third connection point 13 between the second switching element Q2 and the third switching element Q3 in the switching circuit 10W is connected to the output terminal 41W. The third connection point 13 of the inverter circuit 1U is connected to, for example, the U-phase of the AC load RA1 via the output terminal 41U. The third connection point 13 of the inverter circuit 1V is connected to, for example, the V-phase of the AC load RA1 via the output terminal 41V. The third connection point 13 of the inverter circuit 1W is connected to, for example, the W-phase of the AC load RA1 via the output terminal 41W.

[0029] In each switching circuit 10, the anode of diode D1 is connected to the second main terminal (emitter terminal) of the first switching element Q1, and the cathode of diode D1 is connected to the first main terminal (collector terminal) of the first switching element Q1. In each switching circuit 10, the anode of diode D2 is connected to the second main terminal (emitter terminal) of the second switching element Q2, and the cathode of diode D2 is connected to the first main terminal (collector terminal) of the second switching element Q2. In each switching circuit 10, the anode of diode D3 is connected to the second main terminal (emitter terminal) of the third switching element Q3, and the cathode of diode D3 is connected to the first main terminal (collector terminal) of the third switching element Q3. In each switching circuit 10, the anode of the diode D4 is connected to the second main terminal (emitter terminal) of the fourth switching element Q4, and the cathode of the diode D4 is connected to the first main terminal (collector terminal) of the fourth switching element Q4.

[0030] In each switching circuit 10, the diode D1 may be substituted with a parasitic diode of the IGBT that constitutes the first switching element Q1. In each switching circuit 10, the diode D2 may be substituted with a parasitic diode of the IGBT that constitutes the second switching element Q2. In each switching circuit 10, the diode D3 may be substituted with a parasitic diode of the IGBT that constitutes the third switching element Q3. In each switching circuit 10, the diode D4 may be substituted with a parasitic diode of the IGBT that constitutes the fourth switching element Q4.

[0031] In each inverter circuit 1, the cathode of the first clamp diode D5 is connected to a first connection point 11 between the first switching element Q1 and the second switching element Q2. The anode of the first clamp diode D5 is connected to an intermediate potential point M1 of the DC power supply unit 3. In the first embodiment, the intermediate potential point M1 is connected to ground, and therefore the potential of the intermediate potential point M1 is 0 V. In this case, when the voltage across the DC power supply unit 3 is Vdc, the potential of the positive electrode P1 is Vdc / 2, and the potential of the negative electrode N1 is −Vdc / 2.

[0032] The cathode of the second clamp diode D6 is connected to the intermediate potential point M1, and the anode of the second clamp diode D6 is connected to the second connection point 12 between the third switching element Q3 and the fourth switching element Q4.

[0033] The plurality of first gate drivers 61 correspond one-to-one to the plurality of first switching elements Q1. Each of the plurality of first gate drivers 61 is connected to a control terminal of a corresponding first switching element Q1. Each of the plurality of first gate drivers 61 drives a corresponding first switching element Q1. The plurality of first gate drivers 61 are connected to a control unit 60. The control unit 60 outputs a plurality of first control signals S1 (see FIG. 2 ) that correspond one-to-one to the plurality of first gate drivers 61. Each of the plurality of first gate drivers 61 controls the on / off of the first switching element Q1 based on the provided first control signal S1.

[0034] The second gate drivers 62 correspond one-to-one to the second switching elements Q2. Each of the second gate drivers 62 is connected to a control terminal of a corresponding second switching element Q2. Each of the second gate drivers 62 drives a corresponding second switching element Q2. The second gate drivers 62 are connected to a control unit 60. The control unit 60 outputs second control signals S2 (see FIG. 2 ) that correspond one-to-one to the second gate drivers 62. Each of the second gate drivers 62 controls the on / off of the second switching element Q2 based on the second control signal S2 provided thereto.

[0035] The plurality of third gate drivers 63 correspond one-to-one to the plurality of third switching elements Q3. Each of the plurality of third gate drivers 63 is connected to a control terminal of a corresponding third switching element Q3. Each of the plurality of third gate drivers 63 drives a corresponding third switching element Q3. The plurality of third gate drivers 63 are connected to a control unit 60. The control unit 60 outputs a plurality of third control signals S3 (see FIG. 2 ) that correspond one-to-one to the plurality of third gate drivers 63. Each of the plurality of third gate drivers 63 controls the on / off of the third switching element Q3 based on the provided third control signal S3.

[0036] The plurality of fourth gate drivers 64 correspond one-to-one to the plurality of fourth switching elements Q4. Each of the plurality of fourth gate drivers 64 is connected to a control terminal of a corresponding fourth switching element Q4. Each of the plurality of fourth gate drivers 64 drives a corresponding fourth switching element Q4. The plurality of fourth gate drivers 64 are connected to a control unit 60. The control unit 60 outputs a plurality of fourth control signals S4 (see FIG. 2 ) that correspond one-to-one to the plurality of fourth gate drivers 64. Each of the plurality of fourth gate drivers 64 controls the on / off of the fourth switching element Q4 based on the received fourth control signal S4.

[0037] Each of the plurality of first bootstrap circuits 71 supplies a voltage to a corresponding one of the plurality of first gate drivers 61. Each of the plurality of first bootstrap circuits 71 includes a first resistor R1 in addition to a first capacitor C1 and a first diode D11.

[0038] In each first bootstrap circuit 71, the anode of the first diode D11 is connected to the positive terminal of the power supply unit 9 via a third diode D13, not via a second diode D12. In each first bootstrap circuit 71, the cathode of the first diode D11 is connected to a first end of a first capacitor C1 via a first resistor R1. The first end of the first capacitor C1 is connected to a high-potential power supply terminal 61H (see FIG. 3 ) of the first gate driver 61. The second end of the first capacitor C1 is connected to a low-potential power supply terminal 61L (see FIG. 3 ) of the first gate driver 61. The first bootstrap circuit 71 supplies the first gate driver 61 with a voltage (a voltage greater than the threshold voltage of the first switching element Q1) required to turn on the first switching element Q1 in the first gate driver 61.

[0039] Each of the second bootstrap circuits 72 supplies a voltage to a corresponding one of the second gate drivers 62. Each of the second bootstrap circuits 72 includes a second resistor R2 in addition to a second capacitor C2 and a second diode D12. In each second bootstrap circuit 72, the anode of the second diode D12 is connected to the positive terminal of the power supply unit 9 via a third diode D13. In each second bootstrap circuit 72, the cathode of the second diode D12 is connected to a first end of the second capacitor C2 via the second resistor R2. The first end of the second capacitor C2 is connected to a high-potential power supply terminal 62H (see FIG. 3 ) of the second gate driver 62. The second end of the second capacitor C2 is connected to a low-potential power supply terminal 62L (see FIG. 3 ) of the second gate driver 62. The second bootstrap circuit 72 supplies the second gate driver 62 with a voltage (a voltage greater than the threshold voltage of the second switching element Q2) required to turn on the second switching element Q2 in the second gate driver 62.

[0040] Each of the multiple third bootstrap circuits 73 supplies a voltage to a corresponding one of the multiple third gate drivers 63. Each of the multiple third bootstrap circuits 73 includes a third resistor R3 in addition to a third capacitor C3 and a third diode D13. In each third bootstrap circuit 73, the anode of the third diode D13 is connected to the positive terminal of the power supply unit 9. In each third bootstrap circuit 73, the cathode of the third diode D13 is connected to a first end of a third capacitor C3 via the third resistor R3. The first end of the third capacitor C3 is connected to a high-potential power supply terminal 63H (see FIG. 3 ) of the third gate driver 63. The second end of the third capacitor C3 is connected to a low-potential power supply terminal 63L (see FIG. 3 ) of the third gate driver 63. The third bootstrap circuit 73 supplies the third gate driver 63 with a voltage (a voltage greater than the threshold voltage of the third switching element Q3) required to turn on the third switching element Q3 in the third gate driver 63.

[0041] Each of the multiple power supply units 9 is, for example, a DC power supply including an isolated DC-DC converter 91. In each of the multiple drive circuits 2, the positive terminal of the power supply unit 9 is connected to the high-potential power supply terminal 64H (see FIG. 3) of the fourth gate driver 64. The positive terminal of the power supply unit 9 is also connected to the first end of the third capacitor C3 via the third diode D13 and the third resistor R3. The positive terminal of the power supply unit 9 is also connected to the first end of the second capacitor C2 via the third diode D13, the second diode D12, and the second resistor R2. The positive terminal of the power supply unit 9 is also connected to the first end of the first capacitor C1 via the third diode D13, the first diode D11, and the first resistor R1. The negative terminal of the power supply unit 9 is connected to the low-potential power supply terminal 64L (see FIG. 3) of the fourth gate driver 64. The negative terminal of the power supply unit 9 is also connected to the negative pole N1 of the DC power supply unit 3.

[0042] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64. Thus, the control unit 60 controls a plurality of first switching elements Q1, a plurality of second switching elements Q2, a plurality of third switching elements Q3, and a plurality of fourth switching elements Q4. The execution entity of the control unit 60 includes a computer system. The computer system has one or more computers. The computer system is primarily composed of a processor and memory as hardware. The processor executes a program stored in the memory of the computer system, thereby realizing the function of the control unit 60 as the execution entity in the present disclosure. The program may be pre-stored in the memory of the computer system, provided via a telecommunications line, or provided by being recorded on a non-transitory recording medium such as a memory card, optical disk, or hard disk drive (magnetic disk) readable by the computer system. The processor of the computer system is composed of one or more electronic circuits including a semiconductor integrated circuit (IC) or a large-scale integrated circuit (LSI). The multiple electronic circuits may be integrated into a single chip or distributed across multiple chips. The plurality of chips may be integrated into one device, or may be distributed among a plurality of devices.

[0043] FIG. 2 is an explanatory diagram of current paths when the switching circuit 10 in the power conversion device 100 of the first embodiment is in a first switching state. The control unit 60 outputs a plurality (three) of first control signals S1 (see FIG. 2 ) for controlling a plurality (three) of first switching elements Q1. The control unit 60 also outputs a plurality (three) of second control signals S2 (see FIG. 2 ) for controlling a plurality (three) of second switching elements Q2. The control unit 60 also outputs a plurality (three) of third control signals S3 (see FIG. 2 ) for controlling a plurality of third switching elements Q3. The control unit 60 also outputs a plurality (three) of fourth control signals S4 for controlling a plurality (three) of fourth switching elements Q4. Note that FIG. 2 illustrates only one of the three inverter circuits 1 (see FIG. 1 ), and the remaining two inverter circuits 1 are not illustrated. 2 does not show the plurality of first gate drivers 61, the plurality of second gate drivers 62, the plurality of third gate drivers 63, the plurality of fourth gate drivers 64, the plurality of first bootstrap circuits 71, the plurality of second bootstrap circuits 72, the plurality of third bootstrap circuits 73, and the plurality of power supply units 9 shown in FIG. 1.

[0044] Fig. 3 is an explanatory diagram of the power conversion device 100 of the first embodiment when the switching circuit 10 is in the first switching state. Fig. 3 illustrates only one of the three inverter circuits 1 (see Fig. 1 ), and omits the illustration of the remaining two inverter circuits 1. Furthermore, Fig. 3 omits the illustration of the two first gate drivers 61, two second gate drivers 62, two third gate drivers 63, two fourth gate drivers 64, two first bootstrap circuits 71, two second bootstrap circuits 72, two third bootstrap circuits 73, and two power supply units 9 shown in Fig. 1 .

[0045] The three first control signals S1 include a first control signal S1U that controls the first switching element Q1 of the switching circuit 10U, a first control signal S1V that controls the first switching element Q1 of the switching circuit 10V, and a first control signal S1W that controls the first switching element Q1 of the switching circuit 10W.

[0046] The three second control signals S2 include a second control signal S2U that controls the second switching element Q2 of the switching circuit 10U, a second control signal S2V that controls the second switching element Q2 of the switching circuit 10V, and a second control signal S2W that controls the second switching element Q2 of the switching circuit 10W.

[0047] The three third control signals S3 include a third control signal S3U that controls the third switching element Q3 of the switching circuit 10U, a third control signal S3V that controls the third switching element Q3 of the switching circuit 10V, and a third control signal S3W that controls the third switching element Q3 of the switching circuit 10W.

[0048] The three fourth control signals S4 include a fourth control signal S4U that controls the fourth switching element Q4 of the switching circuit 10U, a fourth control signal S4V that controls the fourth switching element Q4 of the switching circuit 10V, and a fourth control signal S4W that controls the fourth switching element Q4 of the switching circuit 10W.

[0049] Each of the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3 and the plurality of fourth control signals S4 is, for example, a signal whose potential level changes between a first potential level (hereinafter also referred to as a low level) and a second potential level (hereinafter also referred to as a high level) that is higher than the first potential level.

[0050] The first potential level is, for example, 0 V, and the second potential level is a potential level greater than the gate threshold voltage of the IGBT. That is, for each of the plurality of control signals (the plurality of first control signals S1, the plurality of second control signals S2, the plurality of third control signals S3, and the plurality of fourth control signals S4), the first potential level is a potential level for turning off the switching element corresponding to that control signal, and the second potential level is a potential level for turning on the switching element corresponding to that control signal.

[0051] Each of the plurality of first switching elements Q1 is turned on when the corresponding first control signal S1 is at a high level and turned off when it is at a low level. Each of the plurality of second switching elements Q2 is turned on when the corresponding second control signal S2 is at a high level and turned off when it is at a low level. Each of the plurality of third switching elements Q3 is turned on when the corresponding third control signal S3 is at a high level and turned off when it is at a low level. Each of the plurality of fourth switching elements Q4 is turned on when the corresponding fourth control signal S4 is at a high level and turned off when it is at a low level.

[0052] (3) Operation of the Power Conversion Device In the power conversion device 100, each of the multiple inverter circuits 1 is controlled to a first switching state, a second switching state, or a third switching state. That is, in the power conversion device 100, the switching state of the switching circuit 10 in each of the three inverter circuits 1U, 1V, and 1W is controlled to one of a first switching state, a second switching state, and a third switching state. The first switching state, the second switching state, and the third switching state differ in the combination of the on / off states of the first to fourth switching elements Q1 to Q4. In each of the multiple inverter circuits 1, the output voltage in the first switching state, the output voltage in the second switching state, and the output voltage in the third switching state are different from one another. That is, in each of the multiple inverter circuits 1, the potential level of the output voltage changes between three levels depending on the states of the first to fourth switching elements Q1 to Q4. Regarding the output voltages of the multiple inverter circuits 1, the output voltage of the U-phase inverter circuit 1U, the output voltage of the V-phase inverter circuit 1V, and the output voltage of the W-phase inverter circuit 1W are out of phase with each other.

[0053] The first switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the ON state and both the third switching element Q3 and the fourth switching element Q4 are in the OFF state. When controlled to the first switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the positive electrode P1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the first switching state, the potential of the third connection point 13 becomes the potential level of the positive electrode P1 of the DC power supply unit 3 (e.g., Vdc / 2).

[0054] The second switching state is a combination in which both the first switching element Q1 and the fourth switching element Q4 are in the off state and both the second switching element Q2 and the third switching element Q3 are in the on state. When controlled to the second switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3. In each of the multiple inverter circuits 1 in the second switching state, the potential of the third connection point 13 becomes the potential level of the intermediate potential point M1 (e.g., 0).

[0055] The third switching state is a combination in which both the first switching element Q1 and the second switching element Q2 are in the OFF state and both the third switching element Q3 and the fourth switching element Q4 are in the ON state. When controlled to the third switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the negative electrode N1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the third switching state, the potential of the third connection point 13 becomes the potential level of the negative electrode N1 of the DC power supply unit 3 (e.g., −Vdc / 2).

[0056] When the switching circuit 10 of the inverter circuit 1 is in the first switching state, as shown in FIG. 2, a current I1 flows through the path of the positive electrode P1 of the DC power supply unit 3, the first switching element Q1, the second switching element Q2, the third connection point 13, and the output terminal 41, and the voltage value of the output voltage to the AC load RA1 (see FIG. 1) becomes approximately Vdc / 2.

[0057] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, a voltage required for the first gate driver 61 to turn on the first switching element Q1 is supplied from the first capacitor C1 of the first bootstrap circuit 71 to the first gate driver 61. Therefore, the charge of the first capacitor C1 of the first bootstrap circuit 71 is discharged through a first discharge path. The first discharge path is a path from the first capacitor C1 to the high-potential power supply terminal 61H (see FIG. 3) of the first gate driver 61 to the low-potential power supply terminal 61L (see FIG. 3) of the first gate driver 61 to the first capacitor C1. As the charge of the first capacitor C1 is discharged, the voltage VC1 across the first capacitor C1 in the first bootstrap circuit 71 decreases over time.

[0058] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the first switching state, the second capacitor C2 of the second bootstrap circuit 72 supplies to the second gate driver 62 a voltage necessary for the second gate driver 62 to turn on the second switching element Q2. Therefore, the charge in the second capacitor C2 is discharged through a second discharge path. The second discharge path is a path from the second capacitor C2 to the high-potential power supply terminal 62H of the second gate driver 62 to the low-potential power supply terminal 62L of the second gate driver 62 to the second capacitor C2. As the charge in the second capacitor C2 is discharged, the voltage VC2 across the second capacitor C2 in the second bootstrap circuit 72 decreases over time.

[0059] When the switching circuit 10 of the inverter circuit 1 is in the first switching state, none of the first capacitor C1, the second capacitor C2, and the third capacitor C3 is charged.

[0060] 4 is an explanatory diagram of a current path when the switching circuit 10 is in the second switching state in the power conversion device 100 of embodiment 1. When the switching circuit 10 of the inverter circuit 1 is in the second switching state and the polarity of the output current (see FIG. 8) is positive, as shown by the thick solid arrow in FIG. 4, current I1 flows through a path from the intermediate potential point M1 of the DC power supply unit 3 to the first clamp diode D5 to the second switching element Q2 to the third connection point 13 to the output terminal 41, and the voltage value of the output voltage to the AC load RA1 becomes 0. More specifically, when the switching circuits 10U, 10V, and 10W are in the second switching state, the third switching state, and the third switching state, respectively, current I1 flows through a path from the intermediate potential point M1 of the DC power supply unit 3 to the first clamp diode D5 of the inverter circuit 1U to the second switching element Q2 of the switching circuit 10U to the third connection point 13 to the output terminal 41.

[0061] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state and the polarity of the output current (see FIG. 8) is negative, as shown by the thick dashed arrow in FIG. 4, a current I1 flows through the path of the output terminal 41-third node 13-third switching element Q3-second node 12-second clamp diode D6, and the voltage value of the output voltage to the AC load RA1 becomes 0. More specifically, when the switching circuits 10U, 10V, and 10W are in the second switching state, the second switching state, and the first switching state, respectively, in the inverter circuit 1U, a current I1 flows through the path of the output terminal 41-third node 13-third switching element Q3-second node 12-second clamp diode D6, and the voltage value of the output voltage to the AC load RA1 becomes 0.

[0062] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, the second capacitor C2 of the second bootstrap circuit 72 supplies to the second gate driver 62 a voltage required for the second gate driver 62 to turn on the second switching element Q2. Therefore, the charge in the second capacitor C2 is discharged through a second discharge path. The second discharge path is the second capacitor C2--the high-potential power supply terminal 62H (see FIG. 5) of the second gate driver 62--the low-potential power supply terminal 62L (see FIG. 5) of the second gate driver 62--the second capacitor C2. As the charge in the second capacitor C2 is discharged, the voltage VC2 across the second capacitor C2 in the second bootstrap circuit 72 decreases over time.

[0063] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the second switching state, a voltage required for the third gate driver 63 to turn on the third switching element Q3 is supplied from the third capacitor C3 of the third bootstrap circuit 73 to the third gate driver 63. Therefore, the charge in the third capacitor C3 is discharged through a third discharge path. The third discharge path is a path from the third capacitor C3 to the high-potential power supply terminal 63H of the third gate driver 63 to the low-potential power supply terminal 63L of the third gate driver 63 and back to the third capacitor C3. As the charge in the third capacitor C3 is discharged, the voltage VC3 across the third capacitor C3 in the third bootstrap circuit 73 decreases over time.

[0064] 5 is an explanatory diagram of a charging path when the switching circuit 10 is in the second switching state in the power conversion device 100 of embodiment 1. When the switching circuit 10 of the inverter circuit 1 is in the second switching state, the second capacitor C2 is charged by the third capacitor C3, and the first capacitor C1 is charged by the third capacitor C3. As shown in FIG. 5, the charging path Ru32 that charges the second capacitor C2 by the third capacitor C3 is a path from the third capacitor C3 to the third resistor R3, the second diode D12, the second resistor R2, the second capacitor C2, the third node 13, the third switching element Q3, and the third capacitor C3. As shown in FIG. 5, a charging path Ru31 through which the first capacitor C1 is charged by the third capacitor C3 is a path from the third capacitor C3 to the third resistor R3, the first diode D11, the first resistor R1, the first capacitor C1, the first connection point 11, the second switching element Q2, the third connection point 13, the third switching element Q3, and the third capacitor C3.

[0065] FIG. 6 is an explanatory diagram of a current path when the switching circuit 10 in the power conversion device 100 of embodiment 1 is in the third switching state. When the switching circuit 10 of the inverter circuit 1 is in the third switching state, as shown in FIG. 6, current I1 flows through the path from the output terminal 41 to the third connection point 13, the third switching element Q3, the fourth switching element Q4, and the negative pole N1 of the DC power supply unit 3, resulting in an output voltage of −Vdc / 2 to the AC load RA1. Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, the third capacitor C3 charges the second capacitor C2 of the second bootstrap circuit 72 (see FIG. 1). Therefore, the voltage VC2 across the second capacitor C2 increases over time, and the second capacitor C2 is fully charged. Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the third switching state, the third capacitor C3 of the third bootstrap circuit 73 supplies the third gate driver 63 with the voltage required to turn on the third switching element Q3. Therefore, the charge in the third capacitor C3 is discharged through a third discharge path, which is the path from the third capacitor C3 to the high-potential power supply terminal 63H of the third gate driver 63 to the low-potential power supply terminal 63L of the third gate driver 63 and back to the third capacitor C3.

[0066] 7 is an explanatory diagram of a charging path when the switching circuit 10 is in the third switching state in the power conversion device 100 of embodiment 1. When the switching circuit 10 of the inverter circuit 1 is in the third switching state, the third capacitor C3 is charged by the power supply unit 9. As shown in FIG. 7, the charging path Ru93 along which the third capacitor C3 is charged by the power supply unit 9 is a path from the positive terminal of the power supply unit 9 to the third diode D13, the third resistor R3, the third capacitor C3, the second connection point 12, the fourth switching element Q4, and the negative terminal of the power supply unit 9.

[0067] The control unit 60 generates first to fourth control signals S1 to S4 (S1U to S4U) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1U based on a voltage command Vu (see FIG. 9) related to the output voltage of the inverter circuit 1U. The control unit 60 also generates first to fourth control signals S1 to S4 (S1V to S4V) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1V based on a voltage command Vv (see FIG. 9) related to the output voltage of the inverter circuit 1V. The control unit 60 also generates first to fourth control signals S1 to S4 (S1W to S4W) for the first to fourth switching elements Q1 to Q4 of the inverter circuit 1W based on a voltage command Vw (see FIG. 9) related to the output voltage of the inverter circuit 1W.

[0068] FIG. 9 is an explanatory diagram of voltage command values ​​for each phase in the power conversion device 100 of the first embodiment. As shown in FIG. 9 , the voltage command Vu and the voltage command Vv are sinusoidal signals, for example, with a phase difference of 120° from each other, and their values ​​(voltage command values) change over time. The voltage command Vu, the voltage command Vv, and the voltage command Vw have the same duration per cycle. The control unit 60 may perform proportional integral (PI) control of the voltage commands Vu, Vv, and Vw based on information output from a detection unit 8 that detects the state of the AC load RA1. If the AC load RA1 is a three-phase servo motor, the information output from the detection unit 8 may include, for example, at least one of information on the detection results of multiple current sensors that detect the output currents flowing through the U, V, and W phases of the AC load RA1 and information on the detection results of an encoder that detects the rotation speed, rotation angle, etc. of the three-phase servo motor.

[0069] Below, we will explain the operation of one of the three inverter circuits 1 (for example, the U-phase inverter circuit 1U). The operation of the V-phase inverter circuit 1V and the W-phase inverter circuit 1W is similar to the operation of the U-phase inverter circuit 1U. The output voltages of the U-phase inverter circuit 1U, the V-phase inverter circuit 1V, and the W-phase inverter circuit 1W are out of phase with each other.

[0070] The control unit 60 controls a plurality of first gate drivers 61, a plurality of second gate drivers 62, a plurality of third gate drivers 63, and a plurality of fourth gate drivers 64 by performing voltage vector control.

[0071] The voltage vector control by the control unit 60 will be described in more detail below.

[0072] The control unit 60 stores a group of voltage vectors in advance. Each of the group of voltage vectors is determined by a combination of potential levels at a connection point (third connection point 13) between the second switching element Q2 and the third switching element Q3 of the multiple inverter circuits 1. In other words, the group of voltage vectors is determined by the switching state of the switching circuit 10U corresponding to the U phase, the switching state of the switching circuit 10V corresponding to the V phase, and the switching state of the switching circuit 10W corresponding to the W phase. The number of voltage vectors included in the group of voltage vectors is 33 = 27.

[0073] 10 is an explanatory diagram of a group of voltage vectors related to the power conversion device 100 of the first embodiment. As shown in FIG. 10 , the group of voltage vectors includes three zero vectors V0p, V0n, and V0o, each of which has a magnitude of zero. The group of voltage vectors also includes six voltage vectors V1, V2, V3, V4, V5, and V6, each of which has a magnitude of (2 / 3)½·2 Vdc and is oriented in different directions. The group of voltage vectors also includes 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n, each of which has a magnitude of (2 / 3)½·Vdc. The group of voltage vectors includes six voltage vectors V13, V14, V15, V16, V17, and V18, each having a magnitude of (2 / 3)1 / 2·31 / 2·Vdc and pointing in different directions. In Figure 10, the angle between any two adjacent voltage vectors among the six voltage vectors V1, V2, V3, V4, V5, and V6 is 60 degrees. The angle between any two adjacent voltage vectors among the six voltage vectors V13, V14, V15, V16, V17, and V18 is also 60 degrees. Figure 10 is a vector diagram illustrating the group of voltage vectors on an orthogonal d-q coordinate system.

[0074] A group of voltage vectors can be expressed as shown in FIG. 11 by representing the first switching state, the second switching state, and the third switching state with the symbols "P," "0," and "N," respectively, and notating the U phase, V phase, and W phase in that order.

[0075] FIG. 11 is a more detailed explanatory diagram of a group of voltage vectors related to the power conversion device 100 of the first embodiment. As shown in FIG. 11 , three zero vectors V0p, V0n, and V0o can be expressed as V0p[PPP], V0n[NNN], and V0o

[000] , respectively. For example, V0p[PPP] indicates that, with respect to the zero vector V0p, the switching state of the U-phase switching circuit 10U is "P," the switching state of the V-phase switching circuit 10V is "P," and the switching state of the W-phase switching circuit 10W is "P." For example, a voltage vector with a "p" appended, such as V10p, includes "P" but does not include "N." This applies hereinafter. Furthermore, a voltage vector with a "n" appended, such as V10n, includes the switching state "N" but does not include the switching state "P." This applies hereinafter. Furthermore, voltage vectors with "o" appended, such as V10o, include "0" but do not include "P" or "N." When the switching state of the switching circuit 10 is "P," the potential of the third connection point 13 in the switching circuit 10 becomes the potential of the positive electrode P1 of the DC power supply unit 3. When the switching state of the switching circuit 10 is "N," the potential of the third connection point 13 in the switching circuit 10 becomes the potential of the negative electrode N1 of the DC power supply unit 3. When the switching state of the switching circuit 10 is "0," the potential of the third connection point 13 in the switching circuit 10 becomes the potential of the intermediate potential point M1 of the DC power supply unit 3.

[0076] Furthermore, the six voltage vectors V1, V2, V3, V4, V5, and V6 can be expressed as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], respectively. Voltage vectors that do not have "p," "n," or "o" added after the number added to "V," such as V1[PNN], V2[PPN], V3[NPN], V4[NPP], V5[NNP], and V6[PNP], include "P" and "N" as the switching states of the three phases.

[0077] Furthermore, the 12 voltage vectors V7p, V7n, V8p, V8n, V9p, V9n, V10p, V10n, V11p, V11n, V12p, and V12n can be expressed as V7p[P00], V7n[0NN], V8p[PP0], V8n[00N], V9p[0P0], V9n[N0N], V10p[0PP], V10n[N00], V11p[00P], V11n[NN0], V12p[P0P], and V12n[0N0], respectively.

[0078] Furthermore, the six voltage vectors V13, V14, V15, V16, V17, and V18 can be expressed as V13[P0N], V14[0PN], V15[NP0], V16[NOP], V17[0NP], and V18[PN0], respectively.

[0079] FIG. 12 is a vector diagram illustrating the operation of the control unit 60 in the power conversion device 100 of the first embodiment. FIG. 13 is a diagram illustrating a time chart of the switching states of each phase of the power conversion device 100 of the first embodiment. FIG. 14 is a diagram illustrating a time chart of the on / off states of the first to fourth switching elements (Q1 to Q4) of the power conversion device 100 of the first embodiment. The control unit 60 converts instantaneous values ​​of command voltages related to the output voltages of the multiple inverter circuits 1 into command voltage vectors V* (see FIG. 12 ). When the d-axis component of the command voltage vector V* on the orthogonal d-q coordinate system is Vd and the q-axis component of the command voltage vector V* on the orthogonal d-q coordinate system is Vq, the command voltage vector V* can be calculated using equation (1).

[0080]

[0081] The control unit 60 selects a plurality of (e.g., five) voltage vectors that are adjacent to the command voltage vector V* from the group of voltage vectors. In the example of Fig. 12, the plurality of voltage vectors are V8p[PP0], V8n[00N], V13[P0N], V7p[P00], and V7n[0NN].

[0082] The angle formed between the voltage vector closest to the command voltage vector V* (hereinafter also referred to as voltage vector VV1) and the command voltage vector V* is smaller than 30 degrees.

[0083] The control unit 60 causes the composite vector of the vectors at the vertices of an equilateral triangle surrounding the command voltage vector V* to coincide with the command voltage vector V* within a predetermined control period Ts. That is, the control unit 60 causes the composite vector of the voltage vector VV1 (V8p[PP0] and V8n[00N] in the example of FIG. 12), the voltage vector V13[P0N], and the voltage vectors V7p[P00] and V7n[0NN] to coincide with the command voltage vector V*. The control period Ts is one period of the carrier signal. In the control period Ts, the control unit 60 changes the switching state of only one of the U, V, and W phases in two voltage vectors arranged in time series between "P" and "0" or between "0" and "N," and outputs the same voltage vector twice. 13, the voltage vectors are output in the following order: voltage vector V8n[00N] → voltage vector V13[P0N] → voltage vector V7p[P00] → voltage vector V8p[PP0] → voltage vector V8p[PP0] → voltage vector V7p[P00] → voltage vector V13[P0N] → voltage vector V8n[00N]. FIG. 13 illustrates an example in which, for a control period Ts, the allocation time of voltage vectors V8p and V8n is T0, the allocation time of voltage vector V13 is T1, and the allocation time of voltage vectors V7p and V7n is T2. Regarding T0, T1, and T2, when the voltage vectors at the vertices of an equilateral triangle surrounding the command voltage vector V* are Va, Vb, and Vc, and the magnitude and angle of the command voltage vector V* are V and θ, respectively, T0, T1, and T2 are determined so as to satisfy equations (2) and (3). 12, for example, the voltage vector Va is the voltage vector V8p[PP0] and V8n[00N], the voltage vector Vb is the voltage vector V13[P0N], and the voltage vector Vc is the voltage vector V7p[P00] and V7n[0NN].

[0084]

[0085]

[0086] In the example of FIG. 13, the on / off states of the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 are as shown in FIG. 14 within the control period Ts.

[0087] Even if the command voltage vector V* is the same as that in FIG. 12, the order of the voltage vectors within the control period Ts may differ depending on the initial value of the carrier signal at the start of the control period Ts.

[0088] Fig. 15 is a diagram showing waveforms of the output current of the U-phase inverter circuit 1 of the power conversion device 100 according to embodiment 1, and the voltage VC1 across the first capacitor C1, the voltage VC2 across the second capacitor C2, and the voltage VC3 across the third capacitor C3 of the drive circuit 2 corresponding to the U-phase inverter circuit 1. Note that Fig. 15 shows an example in which the capacitance of each of the first capacitor C1, the second capacitor C2, and the third capacitor C3 is set to 1 µF, the switching frequency is set to 20 kHz, and the frequency of the output current (current I1) is set to 50 Hz.

[0089] 15, A1 indicates the waveform of the voltage VC1 across the first capacitor C1 in the drive circuit 2 according to embodiment 1, A2 indicates the waveform of the voltage VC2 across the second capacitor C2, and A3 indicates the waveform of the voltage VC3 across the third capacitor C3. Also in Fig. 15, B1 indicates the waveform of the voltage across the first capacitor in a switching element drive circuit of the comparative example in which the anode of the first diode is connected to the cathode of the third diode via the second diode, B2 indicates the waveform of the voltage across the second capacitor, and B3 indicates the waveform of the voltage across the third capacitor.

[0090] 15 shows that in the drive circuit 2 according to the first embodiment, the voltage VC1 across the first capacitor C1 when the first capacitor C1 is charged is greater than the voltage across the first capacitor C1 in the comparative example. The difference between the maximum value of the voltage VC1 across the first capacitor C1 in the first embodiment and the maximum value of the voltage across the first capacitor C1 in the comparative example is approximately the same as the value of the forward voltage drop of the second diode D12.

[0091] 8 is a waveform diagram of the output current (current I1) in the power conversion device 100 of embodiment 1. In the inverter circuit 1, when the polarity of the output current (current I1) flowing through the output terminal 41 is defined as positive when flowing from the third connection point 13 to the output terminal 41 and negative when flowing from the output terminal 41 to the third connection point 13, the waveform of the output current becomes a sinusoidal waveform, for example, as shown in FIGS. 8 and 15 . Note that the U-phase output current, the V-phase output current, and the W-phase output current are sinusoidal currents that are, for example, 120° out of phase with each other.

[0092] The waveforms of the output current of the V-phase inverter circuit 1, the voltage VC1 across the first capacitor C1 of the drive circuit 2 corresponding to the V-phase inverter circuit 1, the voltage VC2 across the second capacitor C2, and the voltage VC3 across the third capacitor C3 are the same as those in Figure 15.

[0093] In addition, the waveforms of the output current of the W-phase inverter circuit 1, the voltage VC1 across the first capacitor C1 of the drive circuit 2 corresponding to the W-phase inverter circuit 1, the voltage VC2 across the second capacitor C2, and the voltage VC3 across the third capacitor C3 are the same as those in Figure 15.

[0094] (4) Advantages In the switching element drive circuit 2 according to the first embodiment, the anode of the first diode D11 of the first bootstrap circuit 71 is connected to the cathode of the third diode D13 without passing through the second diode D12.

[0095] According to the above configuration, the voltage VC1 across the first capacitor C1 can be increased.

[0096] The power conversion device 100 according to the first embodiment also includes a plurality of switching element drive circuits 2, a plurality of diode-clamped three-level inverters 1, and a control unit 60 that controls the plurality of switching element drive circuits 2.

[0097] The above configuration can increase the voltage VC1 across the first capacitor C1 of each of the multiple drive circuits 2. Therefore, in the power conversion device 100 according to the first embodiment, the difference between the gate voltage (gate-emitter voltage) applied to the first switching element Q1 in each diode-clamped three-level inverter 1 and the threshold voltage (e.g., 5.8 V) of the first switching element Q1 can be increased, and the switching loss of the first switching element Q1 can be reduced.

[0098] Second Embodiment A power conversion device 100 according to a second embodiment will be described with reference to FIG. 1 and FIGS. 16 to 20. FIG.

[0099] (1) Configuration The circuit configuration of the power conversion device 100 according to the second embodiment is the same as the circuit configuration of the power conversion device 100 according to the first embodiment (see FIG. 1).

[0100] (2) Operation of the Power Conversion Device In the power conversion device 100 according to the second embodiment, in each of the three inverter circuits 1U, 1V, and 1W, the switching state of the switching circuit 10 is controlled to one of a first switching state, a second switching state, a third switching state, and a fourth switching state. The first switching state, the second switching state, the third switching state, and the fourth switching state differ in the combination of the on / off states of the first to fourth switching elements Q1 to Q4. The first switching state, the second switching state, and the third switching state are as described in the first embodiment, and therefore will not be described again.

[0101] The fourth switching state is a combination in which both the second switching element Q2 and the fourth switching element Q4 are in the ON state and both the first switching element Q1 and the third switching element Q3 are in the OFF state. When controlled to the fourth switching state, each of the multiple inverter circuits 1 can output an output voltage at the potential level of the intermediate potential point M1 of the DC power supply unit 3. In each of the multiple inverter circuits 1, in the fourth switching state, the potential of the third connection point 13 becomes the potential level of the intermediate potential point M1 (e.g., 0).

[0102] 16 is an explanatory diagram of a current path when the switching circuit 10 is in the fourth switching state in the power conversion device 100 according to embodiment 2. When the switching circuit 10 of the inverter circuit 1 is in the fourth switching state, as shown in Fig. 16, a current I1 flows through a path from the intermediate potential point M1 of the DC power supply unit 3 to the first clamp diode D5, the second switching element Q2, the third connection point 13, and the output terminal 41, and the voltage value of the output voltage to the AC load RA1 becomes zero.

[0103] Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the fourth switching state, a voltage required for turning on the second switching element Q2 is supplied from the second capacitor C2 of the second bootstrap circuit 72 to the second gate driver 62 by the second gate driver 62. Therefore, the charge in the second capacitor C2 of the second bootstrap circuit 72 is discharged through a discharge path of the second capacitor C2--the high-potential power supply terminal 62H (see FIG. 17) of the second gate driver 62--the low-potential power supply terminal 62L (see FIG. 17) of the second gate driver 62--the second capacitor C2. Furthermore, when the switching circuit 10 of the inverter circuit 1 is in the fourth switching state, a voltage required for turning on the fourth switching element Q4 is supplied from the power supply unit 9 to the fourth gate driver 64 by the fourth gate driver 64.

[0104] 17 is an explanatory diagram of a charging path when the switching circuit 10 is in the fourth switching state in the power conversion device 100 of embodiment 2. When the switching circuit 10 of the inverter circuit 1 is in the fourth switching state, the third capacitor C3 of the third bootstrap circuit 73 is charged by the power supply unit 9. As shown in FIG. 17 , the charging path Ru93 along which the third capacitor C3 is charged by the power supply unit 9 is a path from the positive terminal of the power supply unit 9 to the third diode D13, the third resistor R3, the third capacitor C3, the second connection point 12, the fourth switching element Q4, and the negative terminal of the power supply unit 9.

[0105] In the power conversion device 100 according to the second embodiment, the control unit 60 has a first control mode, a second control mode, and a third control mode.

[0106] In the first control mode, the control unit 60 turns on the first switching element Q1, turns on the second switching element Q2, turns off the third switching element Q3, and turns off the fourth switching element Q4. More specifically, in the first control mode, the control unit 60 controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 so that the switching circuit 10 is in the first switching state.

[0107] In the second control mode, the control unit 60 turns off the first switching element Q1, turns on the second switching element Q2, turns on the third switching element Q3, and turns off the fourth switching element Q4. More specifically, in the second control mode, the control unit 60 controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 so that the switching circuit 10 is in the second switching state.

[0108] In the third control mode, the control unit 60 turns off the first switching element Q1, turns on the second switching element Q2, turns off the third switching element Q3, and turns on the fourth switching element Q4. More specifically, in the third control mode, the control unit 60 controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 so that the switching circuit 10 is in a fourth switching state.

[0109] FIG. 18 is an explanatory diagram of the operation of the power conversion device 100 of the second embodiment. When the polarity of the current flowing through the output terminal 41 is positive, the control unit 60 alternates between the first control mode and the second control mode. Here, as shown in FIG. 18 , when transitioning from the first control mode to the second control mode, the control unit 60 performs control in the third control mode between the first control mode and the second control mode. Therefore, immediately after the third control mode, the control unit 60 transitions to the first control mode via the second control mode. Note that in FIG. 18 , with regard to the potential levels of the first control signal S1, the second control signal S2, the third control signal S3, and the fourth control signal S4, a low level is represented as "L" and a high level is represented as "H."

[0110] The control unit 60 also sets a dead time period Td between the period when the potential level of the control signal S4 is high and the period when the potential level of the control signal S3 is high so that the on-period of the fourth switching element Q4 does not overlap with the on-period of the third switching element Q3. The control unit 60 also sets a dead time period Td between the period when the potential level of the control signal S1 is high and the period when the potential level of the control signal S4 is high so that the on-period of the first switching element Q1 does not overlap with the on-period of the fourth switching element Q4. The control unit 60 also sets a dead time period Td between the period when the potential level of the control signal S3 is high and the period when the potential level of the control signal S1 is high so that the on-period of the third switching element Q3 does not overlap with the on-period of the first switching element Q1. The length of the dead time period Td may be zero. Furthermore, in the power conversion device 100 according to the second embodiment, in the third control mode, the control unit 60 sets the length T4 of the on-period of the fourth switching element Q4 to be equal to or greater than 90% and equal to or less than 110% of the CR time constant of the third bootstrap circuit 73 that supplies a voltage to the third gate driver 63. In the power conversion device 100 according to the second embodiment, the CR time constant of the third bootstrap circuit 73 is determined by the capacitance of the third capacitor C3 and the resistance value of the third resistor R3 of the third bootstrap circuit 73.

[0111] The control unit 60 also has a fourth control mode. In the fourth control mode, the control unit 60 turns off the first switching element Q1, turns off the second switching element Q2, turns on the third switching element Q3, and turns on the fourth switching element Q4. More specifically, in the fourth control mode, the control unit 60 controls the first switching element Q1, the second switching element Q2, the third switching element Q3, and the fourth switching element Q4 so that the switching circuit 10 is in a third switching state.

[0112] When the polarity of the output current (current I1) flowing through the output terminal 41 is negative, the control unit 60 alternates between the second control mode and the fourth control mode.

[0113] Fig. 19 is a diagram showing waveforms of the output current of the U-phase inverter circuit 1 of the power conversion device 100 according to embodiment 2, and the voltage VC1 across the first capacitor C1, the voltage VC2 across the second capacitor C2, and the voltage VC3 across the third capacitor C3 of the drive circuit 2 corresponding to the U-phase inverter circuit 1. Note that Fig. 19 shows an example in which the capacitance of each of the first capacitor C1, the second capacitor C2, and the third capacitor C3 is set to 1 µF, the switching frequency is set to 20 kHz, and the frequency of the output current (current I1) is set to 50 Hz.

[0114] 19, A1 indicates the waveform of the voltage VC1 across the first capacitor C1 in the drive circuit 2 according to embodiment 2, A2 indicates the waveform of the voltage VC2 across the second capacitor C2, and A3 indicates the waveform of the voltage VC3 across the third capacitor C3. Also in Fig. 19, B1 indicates the waveform of the voltage across the first capacitor in a switching element drive circuit of the comparative example in which the anode of the first diode is connected to the cathode of the third diode via the second diode, B2 indicates the waveform of the voltage across the second capacitor, and B3 indicates the waveform of the voltage across the third capacitor.

[0115] 19 shows that in the drive circuit 2 according to the second embodiment, the voltage VC1 across the first capacitor C1 when the first capacitor C1 is charged is greater than the voltage across the first capacitor C1 in the comparative example. The difference between the maximum value of the voltage VC1 across the first capacitor C1 in the second embodiment and the maximum value of the voltage across the first capacitor C1 in the comparative example is substantially equal to the value of the forward voltage drop of the second diode D12. Note that FIG. 20 enlarges the waveform A1 of the voltage VC1 across the first capacitor C1 in the second embodiment and the waveform B1 of the voltage across the first capacitor C1 in the comparative example for a portion of the period in FIG. 19 during which the polarity of the output current is positive, showing their relationship to the switching state of the switching circuit 10.

[0116] The waveforms of the output current of the V-phase inverter circuit 1, the voltage VC1 across the first capacitor C1 of the drive circuit 2 corresponding to the V-phase inverter circuit 1, the voltage VC2 across the second capacitor C2, and the voltage VC3 across the third capacitor C3 are the same as those in Figure 19.

[0117] In addition, the waveforms of the output current of the W-phase inverter circuit 1, the voltage VC1 across the first capacitor C1 of the drive circuit 2 corresponding to the W-phase inverter circuit 1, the voltage VC2 across the second capacitor C2, and the voltage VC3 across the third capacitor C3 are the same as those in Figure 19.

[0118] It can be seen from FIG. 20 that when the control unit 60 performs control in the third control mode and is in the fourth switching state, the voltage drop of the first capacitor C1 can be suppressed.

[0119] From Figure 19, it can be seen that in embodiment 2, compared to the comparative example, the voltage VC1 across the first capacitor C1 can be made larger during the period when the polarity of the output current is positive (during the entire half cycle when the polarity of the output current is positive), and a decrease in the voltage of the first capacitor C1 can be suppressed.

[0120] (3) Advantages In the power conversion device 100 according to the second embodiment, similarly to the power conversion device 100 according to the first embodiment, in each of the plurality of switching element drive circuits 2, the anode of the first diode D11 of the first bootstrap circuit 71 is connected to the cathode of the third diode D13 without passing through the second diode D12, and therefore the voltage VC1 across each of the plurality of first capacitors C1 (see FIG. 3 ) can be increased.

[0121] Furthermore, in the power conversion device 100 according to the second embodiment, the control unit 60 has a first control mode, a second control mode, and a third control mode, and when the polarity of the current flowing through the output terminal 41 is positive, immediately after the third control mode, the control unit 60 transitions to the second control mode and then to the first control mode.

[0122] According to the above configuration, it is possible to further suppress the decrease in the voltage VC1 across the first capacitor C1 of each of the plurality of drive circuits 2.

[0123] Third Embodiment A power conversion device 100 according to a third embodiment will be described with reference to FIGS. 1 and 21. FIG.

[0124] (1) Configuration The circuit configuration of the power conversion device 100 according to the third embodiment is the same as the circuit configuration of the power conversion device 100 according to the first embodiment (see FIG. 1).

[0125] (2) Operation of the Power Conversion Device The power conversion device 100 according to the third embodiment differs from the power conversion device 100 according to the first embodiment in that the control unit 60 performs PWM control instead of voltage vector control.

[0126] FIG. 21 is an explanatory diagram illustrating the operation of the power conversion device 100 according to the third embodiment. For each diode-clamped three-level inverter 1, the control unit 60 compares the output voltage command value Vout at the output terminal 41 with a triangular-wave first carrier wave CA1 to generate a first control signal S1 consisting of a PWM signal, as shown in FIG. 21 . The control unit 60 also generates a third control signal S3 consisting of a PWM signal obtained by inverting the PWM signal constituting the first control signal S1. Therefore, in the inverter circuit 1, the first switching element Q1 and the third switching element Q3 operate complementarily. The control unit 60 also compares the output voltage command value Vout at the output terminal 41 with a triangular-wave second carrier wave CA2 to generate a second control signal S2 consisting of a PWM signal, as shown in FIG. 21 . The control unit 60 also generates a fourth control signal S4 consisting of a PWM signal obtained by inverting the PWM signal constituting the second control signal S2. Therefore, in the inverter circuit 1, the second switching element Q2 and the fourth switching element Q4 operate complementarily.

[0127] (3) Advantages In the power conversion device 100 according to the third embodiment, similarly to the power conversion device 100 according to the first embodiment, in each of the plurality of switching element drive circuits 2, the anode of the first diode D11 of the first bootstrap circuit 71 is connected to the cathode of the third diode D13 without passing through the second diode D12, and therefore the voltage VC1 across each of the plurality of first capacitors C1 (see FIG. 3 ) can be increased.

[0128] (Fourth embodiment) A power conversion device 100A according to a fourth embodiment will be described with reference to Fig. 22. Regarding the power conversion device 100A according to the fourth embodiment, components similar to those of the power conversion device 100 according to the first embodiment (see Fig. 1) are denoted by the same reference numerals, and description thereof will be omitted.

[0129] (1) Configuration Fig. 22 is a circuit diagram of a power conversion device 100A according to embodiment 4. In the power conversion device 100A according to embodiment 4, a power supply unit 9 is shared by multiple (three in the example of Fig. 1) switching element drive circuits 2. Therefore, the power conversion device 100A according to embodiment 4 is configured to include only one power supply unit 9, rather than multiple power supply units 9 as in the power conversion device 100 according to embodiment 1. The power supply unit 9 is, for example, a DC power supply including an isolated DC-DC converter 91.

[0130] In the power conversion device 100A, the power supply unit 9 is connected in parallel to the multiple fourth gate drivers 64. In the multiple first bootstrap circuits 71, the anode of the first diode D11 is connected to the positive terminal of the power supply unit 9 via a third diode D13, not via a second diode D12. In the multiple second bootstrap circuits 72, the anode of the second diode D12 is connected to the positive terminal of the power supply unit 9 via the third diode D13. In the multiple third bootstrap circuits 73, the anode of the third diode D13 is connected to the positive terminal of the power supply unit 9.

[0131] (2) Advantages In the power conversion device 100A according to the fourth embodiment, similarly to the power conversion device 100 according to the first embodiment, in each of the plurality of switching element drive circuits 2, the anode of the first diode D11 of the first bootstrap circuit 71 is connected to the cathode of the third diode D13 without passing through the second diode D12, and therefore the voltage VC1 across each of the plurality of first capacitors C1 (see FIG. 3 ) can be increased.

[0132] Furthermore, the power conversion device 100A according to the fourth embodiment has a common power supply unit 9 for multiple (three in the example of Figure 1) switching element drive circuits 2, and therefore can be made smaller than the power conversion device 100 according to the first embodiment, which has multiple (three) power supply units 9.

[0133] (Modifications) The above-described first to fourth embodiments are merely examples of various embodiments of the present disclosure. The above-described first to fourth embodiments can be modified in various ways depending on the design, etc., as long as the object of the present disclosure can be achieved.

[0134] Furthermore, each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, and the fourth switching elements Q4 is not limited to an IGBT but may be a MOSFET. In this case, the control terminal, the first main terminal, and the second main terminal of each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, and the fourth switching elements Q4 are a gate terminal, a drain terminal, and a source terminal, respectively. In each switching circuit 10, the MOSFETs constituting each of the first switching elements Q1, the second switching elements Q2, the third switching elements Q3, and the fourth switching elements Q4 are, for example, normally-off n-channel MOSFETs. Note that although the MOSFETs are Si-based MOSFETs, they are not limited to Si-based MOSFETs and may be, for example, SiC-based MOSFETs.

[0135] The first bootstrap circuit 71 may further include a first Zener diode connected in parallel to the first capacitor C1. In this case, the cathode of the first Zener diode is connected to the first end of the first capacitor C1, and the anode of the first Zener diode is connected to the second end of the first capacitor C1. The second bootstrap circuit 72 may further include a second Zener diode connected in parallel to the second capacitor C2. In this case, the cathode of the second Zener diode is connected to the first end of the second capacitor C2, and the anode of the second Zener diode is connected to the second end of the second capacitor C2. The third bootstrap circuit 73 may further include a third Zener diode connected in parallel to the third capacitor C3. In this case, the cathode of the third Zener diode is connected to the first end of the third capacitor C3, and the anode of the third Zener diode is connected to the second end of the third capacitor C3.

[0136] The first bootstrap circuit 71 may include a first resistor R1 but may not include the first resistor R1, and the cathode of the first diode D11 may be connected to the first end of the first capacitor C1. The second bootstrap circuit 72 may include a second resistor R2 but may not include the second resistor R2, and the cathode of the second diode D12 may be connected to the first end of the second capacitor C2. The third bootstrap circuit 73 may include a third resistor R3 but may not include the third resistor R3, and the cathode of the third diode D13 may be connected to the first end of the third capacitor C3.

[0137] Furthermore, the power conversion device 100 is not limited to a configuration including a plurality of switching circuits 10, and may be a configuration including a single switching circuit 10. When the power conversion device 100 is configured to include a single switching circuit 10 instead of a plurality of switching circuits 10, there is also one each of the first gate driver 61, the second gate driver 62, the third gate driver 63, and the fourth gate driver 64, and there is also one each of the first bootstrap circuit 71, the second bootstrap circuit 72, and the third bootstrap circuit 73.

[0138] (Aspects) The following aspects are disclosed in this specification.

[0139] A switching element drive circuit (2) according to a first aspect drives a diode-clamped three-level inverter (1). The diode-clamped three-level inverter (1) has a first switching element (Q1), a second switching element (Q2), a third switching element (Q3), and a fourth switching element (Q4) connected in series between a positive electrode (P1) and a negative electrode (P2) of a DC power supply unit (3). The switching element drive circuit includes a first gate driver (61), a second gate driver (62), a third gate driver (63), a fourth gate driver (64), a first bootstrap circuit (71), a second bootstrap circuit (72), a third bootstrap circuit (73), and a power supply unit (9). The first gate driver (61) drives the first switching element (Q1). The second gate driver (62) drives the second switching element (Q2). The third gate driver (63) drives the third switching element (Q3). The fourth gate driver (64) drives the fourth switching element (Q4). The first bootstrap circuit (71) includes a first capacitor (C1) connected in parallel to the first gate driver (61) and a first diode (D11) having a cathode connected to the first capacitor (C1). The second bootstrap circuit (72) includes a second capacitor (C2) connected in parallel to the second gate driver (62) and a second diode (D12) having a cathode connected to the second capacitor (C2). The third bootstrap circuit (73) includes a third capacitor (C3) connected in parallel to the third gate driver (63) and a third diode (D13) having a cathode connected to the third capacitor (C3). The power supply unit (9) is connected in parallel to the fourth gate driver (64). The anode of the third diode (D13) is connected to the power supply unit (9). The anode of the second diode (D12) is connected to the cathode of the third diode (D13), and the anode of the first diode (D11) is connected to the cathode of the third diode (D13) without passing through the second diode (D12).

[0140] According to this aspect, it is possible to further increase the voltage (VC1) across the first capacitor (C1).

[0141] In the switching element drive circuit (2) according to the second aspect, in the first aspect, the first bootstrap circuit (71) further includes a first resistor (R1). The first resistor (R1) is connected between the first diode (D11) and the first capacitor (C1). The second bootstrap circuit (72) further includes a second resistor (R2). The second resistor (R2) is connected between the second diode (D12) and the second capacitor (C2). The third bootstrap circuit (73) further includes a third resistor (R3). The third resistor (R3) is connected between the third diode (D13) and the third capacitor (C3).

[0142] In the switching element drive circuit (2) according to the third aspect, in the first or second aspect, the power supply section (9) includes a DC-DC converter (91).

[0143] A power conversion device (100; 100A) according to a fourth aspect is the power conversion device according to any one of the first to third aspects, and includes a switching element drive circuit (2), a diode-clamped three-level inverter (1), and a control unit (60). The control unit (60) controls the switching element drive circuit (2).

[0144] According to this aspect, it is possible to further increase the voltage (VC1) across the first capacitor (C1).

[0145] In the power conversion device (100; 100A) according to the fifth aspect, in the fourth aspect, the control unit (60) controls the first gate driver (61), the second gate driver (62), the third gate driver (63), and the fourth gate driver (64) by performing voltage vector control.

[0146] In a power conversion device (100; 100A) according to a sixth aspect, in the fifth aspect, the diode-clamped three-level inverter (1) is connected to a connection point (third connection point 13) between the second switching element (Q2) and the third switching element (Q3), and has an output terminal (41) connected to an AC load (RA1). The control unit (60) has a first control mode, a second control mode, and a third control mode. In the first control mode, the control unit (60) turns on the first switching element (Q1), turns on the second switching element (Q2), turns off the third switching element (Q3), and turns off the fourth switching element (Q4). In the second control mode, the control unit (60) turns off the first switching element (Q1), turns on the second switching element (Q2), turns on the third switching element (Q3), and turns off the fourth switching element (Q4). In the third control mode, the control unit (60) turns off the first switching element (Q1), turns on the second switching element (Q2), turns off the third switching element (Q3), and turns on the fourth switching element (Q4). When the polarity of the current flowing through the output terminal (41) is positive, the control unit (60) transitions from the third control mode to the first control mode via the second control mode.

[0147] According to this aspect, it is possible to further suppress the decrease in the voltage (VC1) across the first capacitor (C1).

[0148] In the power conversion device (100; 100A) according to the seventh aspect, in the fourth aspect, the control unit (60) controls the first gate driver (61), the second gate driver (62), the third gate driver (63), and the fourth gate driver (64) by performing PWM control.

[0149] In the power conversion device (100; 100A) according to the eighth aspect, in any one of the fourth to seventh aspects, each of the first switching element (Q1), the second switching element (Q2), the third switching element (Q3), and the fourth switching element (Q4) is an IGBT or a MOSFET.

[0150] A power conversion device (100; 100A) according to a ninth aspect is any one of the fourth to eighth aspects, and includes three diode-clamped three-level inverters (1) and three switching element drive circuits (2). The three switching element drive circuits (2) share a power supply unit (9).

[0151] According to this aspect, it is possible to achieve miniaturization.

[0152] A power conversion device (100A) according to a tenth aspect is the ninth aspect, in which the power supply unit (9) is common to the three switching element drive circuits (2).

[0153] According to this aspect, further miniaturization can be achieved.

[0154] The switching element drive circuit and power conversion device of the present disclosure can increase the voltage across the first capacitor. Thus, the switching element drive circuit and power conversion device of the present disclosure are industrially useful.

[0155] 1 Diode clamp type three-level inverter 2 Switching element drive circuit 3 DC power supply unit 6 Control device 60 Control unit 61 First gate driver 62 Second gate driver 63 Third gate driver 64 Fourth gate driver 9 Power supply unit 91 DC-DC converter 13 Third connection point 71 First bootstrap circuit 72 Second bootstrap circuit 73 Third bootstrap circuit 100, 100A Power conversion device C1 First capacitor C2 Second capacitor C3 Third capacitor D5 First clamp diode D6 Second clamp diode D11 First diode D12 Second diode D13 Third diode P1 Positive pole Q1 First switching element Q2 Second switching element Q3 Third switching element Q4 Fourth switching element M1 Midpoint potential point N1 Negative pole R1 First resistor R2 Second resistor R3 Third resistor VC1 Voltage across both ends

Claims

1. A switching element drive circuit for driving a diode clamp type three-level inverter having a first switching element, a second switching element, a third switching element, and a fourth switching element connected in series between the positive and negative terminals of a DC power supply unit, The aforementioned switching element drive circuit is A first gate driver that drives the first switching element, A second gate driver that drives the second switching element, A third gate driver that drives the third switching element, A fourth gate driver that drives the fourth switching element, A first bootstrap circuit including a first capacitor connected in parallel to the first gate driver and a first diode whose cathode is connected to the first capacitor, A second bootstrap circuit including a second capacitor connected in parallel to the second gate driver and a second diode whose cathode is connected to the second capacitor, A third bootstrap circuit including a third capacitor connected in parallel to the third gate driver and a third diode whose cathode is connected to the third capacitor, The system comprises a power supply unit connected in parallel to the fourth gate driver, The anode of the third diode is connected to the power supply unit. The anode of the second diode is connected to the cathode of the third diode. The anode of the first diode is connected to the cathode of the third diode without going through the second diode. Switching element drive circuit.

2. The first bootstrap circuit further includes a first resistor connected between the first diode and the first capacitor, The second bootstrap circuit further includes a second resistor connected between the second diode and the second capacitor, The third bootstrap circuit further includes a third resistor connected between the third diode and the third capacitor. The switching element driving circuit according to claim 1.

3. The aforementioned power supply unit is Including a DC-DC converter, A switching element driving circuit according to claim 1 or 2.

4. A switching element driving circuit according to claim 1 or 2, The diode clamp type three-level inverter, The system includes a control unit for controlling the switching element drive circuit, Power converter.

5. The control unit controls the first gate driver, the second gate driver, the third gate driver, and the fourth gate driver by performing voltage vector control. The power conversion device according to claim 4.

6. The diode clamp type three-level inverter is connected to the connection point between the second switching element and the third switching element, and has an output terminal that is connected to an AC load. The control unit, A first control mode in which the first switching element is turned on, the second switching element is turned on, the third switching element is turned off, and the fourth switching element is turned off, A second control mode in which the first switching element is turned off, the second switching element is turned on, the third switching element is turned on, and the fourth switching element is turned off, It has a third control mode in which the first switching element is turned off, the second switching element is turned on, the third switching element is turned off, and the fourth switching element is turned on. The control unit, when the polarity of the current flowing to the output terminal is positive, Immediately after the third control mode, the system transitions to the first control mode via the second control mode. The power conversion device according to claim 5.

7. The control unit controls the first gate driver, the second gate driver, the third gate driver, and the fourth gate driver by performing PWM control. The power conversion device according to claim 4.

8. Each of the first switching element, the second switching element, the third switching element, and the fourth switching element is an IGBT or a MOSFET. The power conversion device according to claim 4.

9. The system includes three diode clamp type three-level inverters, The circuit comprises three of the aforementioned switching element drive circuits. The power conversion device according to claim 4.

10. The power supply unit is common to the three switching element drive circuits mentioned above. The power conversion device according to claim 9.